JPH10171749A - Memory access controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory access controller in which the high performance of data transfer can be ensured by a simple controlling processing. SOLUTION: This memory access controller is provided with a memory device 7 including memories 5 and 6 which store data, data bus 1 to which the data of the memories 5 and 6 are outputted, bus transceivers 2 and 3 for controlling the direction of data between this data bus 1 and the memories 5 and 6, and control circuit 4 for controlling access in the memories 5 and 6 and the bus transceivers 2 and 3. The bus transceivers 2 and 3 substituted for a conventional bus transceiver with a register having plural control transmission lines for input are controlled through two control transmission lines by the control circuit 4. The bus transceivers 2 and 3 are operated corresponding to the switching of the signal direction of a data signal, the output selection of the data signal, or the setting of high impedance or the like by a control signal from the control circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory access control device for controlling access to a memory, which is a main storage device of a computer, such as address, data, and refresh.

[0002]

2. Description of the Related Art Conventionally, as a technique related to access control in this kind of memory, for example, Japanese Patent Application Laid-Open No. 5-539
Japanese Patent Laid-Open No. 05-2005 discloses a shared memory access method and apparatus.

FIG. 4 is a block diagram showing a basic configuration of the shared memory access device (memory access control device). The shared memory access device includes a first MPU 14 and a second MPU for accessing data having different data widths.
U15, a memory device 7 including a plurality of shared memories 5 and 6 accessed by the second MPU 15, a data bus 1 connected to the first MPU 14, and a plurality of registers connecting the plurality of memories 5, 6 and the data bus 1. Bus transceivers 9, 10 and a control circuit 11 for controlling access to the memory device 7 and the bus transceivers 9, 10 with registers.

In this shared memory access device, for example, when n data of width W are continuously read from the memory device 7 and read into the first MPU 14 via the bus transceivers 9 and 10 with registers, the data of width W To n
And at the same time read out from the memory device 7 and hold them in the (n-1) bus transceivers with registers.
The bus transceivers 10 with registers are set to the through state, thereby reading data from the bus transceivers 10 with the registers in the through state. Is being read.

FIG. 5 is a simplified block diagram showing a specific configuration of the shared memory access device. The shared memory access device has two memories 5 and 5 storing data.
6, a data bus 1 to which data of the memories 5 and 6 are outputted, and two register-equipped bus transceivers 9 for controlling the direction of data between the data bus 1 and the memories 5 and 6. , 10 and memory 5,
6 and a control circuit 11 for controlling access in the bus transceivers with registers 9 and 10. The bus transceivers with registers 9 and 10 are controlled by the control circuit 11 via six control transmission lines, respectively. ing.

FIG. 6 is a circuit diagram showing a main configuration of bus transceivers with registers 9 and 10 provided in the memory access control device of FIG.

The register-equipped bus transceivers 9, 10
Has a control circuit 12 for switching and controlling the signal directions of the data signal A1 and the data signal B1 according to the direction signal DIR from the control circuit 11, and the control circuit 12 converts the data signal A1 to the data signal B1.
Or the signal direction can be switched from the data signal B1 to the data signal A1. Further, the control circuit 12 can control whether the data signal A1 or the data signal B1 is output or the impedance is high by the enable signal G from the control circuit 11. However, here, in order to hold the input data, the data input as the data signals A1 and B1 are held at the falling edge of the CBA signal. Switching between the through mode and the register output mode is performed by SAB and SBA, respectively. It should be noted that a plurality of such control circuits 12 are usually mounted for each of the register-equipped bus transceivers 9 and 10.

The operation of the memory access control device will be described below with reference to a timing chart shown in FIG.

Here, the control device 11 controls the memory device 7
Bus transceivers with registers 9 and 10 for reading data from memories 5 and 6 and outputting the data to data bus 1.
Of the memories 5 and 6 in the direction of the data bus 1 from the memory device 7 is set.

[0010] That is, for example, an address _5, RAS _5, CAS ₅ with respect to the memory 5, data ₅ is in the relation as shown, when to output the first data ₅ in the memory 5 (D0) to the data bus 1, register with bus enable signal G bar ₁₀ of the transceiver 10 controlled by the output in a high impedance state, the enable signal G bar ₉ regarding register with bus transceiver 9, the direction signal DI
Controlling the R ₉ and CAB signals ₉ and controlling the CBA signal ₉ and the SBA signal ₉ through the operation of the SAB signal ₉ to put the output into a through state and put the memories 5 and 6 into a reading state to output data. Thus, data ₅ (D0) of the memory 5 is output to the data bus 1.

Next, regarding the memory 6, the address ₆ , RA
S ₆ , CAS ₆ , and data ₆ have a relationship as shown in the figure, and the first data ₆ (D 1) of the memory 6 is transferred to the data bus 1.
Case of output controls the enable signal G bar ₉ of register with Bus Transceivers 9 the output in a high impedance state, the enable signal G bar ₁₀ about the register with bus transceiver 10, the direction signal DIR _10, and C
After controlling the AB signal ₁₀ and operating the SAB signal ₁₀ , C
By controlling the BA signal ₁₀ and the SBA signal ₁₀ , the output is set to the through state, and the memories 5 and 6 are set to the read state and the data is output, so that the data ₆ (D
1) is output to the data bus 1.

Subsequently, similarly, the next data in the memory 5
_{5 When} (D2) is output to the data bus 1, the enable signal G bar ₁₀ of the bus transceiver with register ₁₀ is controlled to bring the output into a high impedance state, and the enable signals G bar ₉ ,
Direction signal DIR _9, and the control of the CAB signals _9, and S
Through the operation of the AB signal ₉ , the CBA signal ₉ and the SBA signal ₉
, The output is set to the through state, and the memories 5, 6
To read data and output data,
Data ₅ (D2) of the memory 5 is output to the data bus 1.

Further, similarly, the next data ₆ (D
If to output 3) to the data bus 1, by controlling the enable signal G bar ₉ of register with Bus Transceivers 9 the output in a high impedance state, the enable signal G bar ₁₀ about the register with bus transceiver 10, the direction signal DIR _10, By controlling the CBA signal ₁₀ and the SBA signal ₁₀ through the control of the CAB signal ₁₀ and the operation of the SAB signal ₁₀ , the output is set to the through state, and the memories 5 and 6 are set to the read state and the data is output, so that the memory is output. The data ₆ (D3) of No. ₆ is output to the data bus 1.

FIG. 8 is a simplified block diagram showing a basic configuration of a memory access control device according to another conventional example. In this shared memory access device, a bus transceiver with a register is not used, and two memories 5 and 5 storing data are used.
6, a data bus 1 to which data of the memories 5 and 6 are output, and a control circuit 13 for controlling access to the data bus 1 and the memories 5 and 6. , 6 are directly connected.

The operation of the memory access control device will be described below with reference to a timing chart shown in FIG.

Here, the control device 13 controls the memory device 7.
In order to read data from the memories 5 and 6 and output the data to the data bus 1, settings are made so that the data in the memories 5 and 6 flows from the memory device 7 toward the data bus 1.

[0017] That is, for example, an address _5, RAS _5, CAS ₅ with respect to the memory 5, data ₅ is in the relation as shown, when to output the first data ₅ in the memory 5 (D0) to the data bus 1, memory 5 in a read state to output data,
₅ (D0) is output to the data bus 1. Thereafter, the data in the memory 5 is set to a high impedance state in order to avoid a bus collision in the data bus 1.

Next, regarding the memory 6, the address ₆ , RA
S ₆ , CAS ₆ , and data ₆ have a relationship as shown in the figure, and the first data ₆ (D 1) of the memory 6 is transferred to the data bus 1.
In this case, the memory 6 is set to the read state and the data is output, so that the data ₆ (D
1) is output to the data bus 1. Here, after that, the data in the memory 6 is set to the high impedance state.

Subsequently, similarly, the next data in the memory 5
_{5 When} (D2) is output to the data bus 1, the memory 5
To read data and output data,
Data ₅ (D2) of the memory 5 is output to the data bus 1. Here, after that, the data in the memory 5 is set to the high impedance state.

Further, similarly, the next data ₆ (D
When 3) is output to the data bus 1, the data ₆ (D3) of the memory 6 is output to the data bus 1 by setting the memory 6 to the read state and outputting the data. Here, after that, the data in the memory 6 is set to the high impedance state.

Incidentally, as a well-known technique related to a main storage device of a general computer, for example, Japanese Patent Laid-Open No. 5-53 is known.
905 and the like.

[0022]

In the case of the above-mentioned shared memory access device (memory access control device), the first M
Although a registered bus transceiver is used to connect the data bus to which the PU is connected to the memory in the memory device, one registered bus transceiver requires six control transmission lines for controlling the same. Since the control circuit needs n × 6 control signals in proportion to the number n of the register-equipped bus transceivers, control processing becomes complicated if such a large number of control signals are required, and the control circuit In addition, it is difficult to reduce the size of the circuit board to an LSI, and it is difficult to reduce the size of the circuit board because of the large area occupied by the circuit board.

In particular, the control circuit has n × n as shown in FIG.
When the six control signals are required, high performance is required for the data transfer, and the processing operation becomes complicated, which causes a cost increase. When the bus transceiver with the register is not used as shown in FIGS. 8 and 9, the control is simplified. However, since the data transfer performance is deteriorated, there is a problem in reliability.

The present invention has been made in order to solve such problems, and a technical problem of the present invention is to provide a memory access control device capable of ensuring high data transfer performance with a simple control process. is there.

[0025]

According to the present invention, there is provided a memory device including a plurality of memories storing data, a data bus to which data of the plurality of memories is output, and a data bus between the data bus and the plurality of memories. A memory access control device including a plurality of bus transceivers for controlling the direction of data, a plurality of memories, and a control circuit for controlling access in the plurality of bus transceivers is obtained.

According to the present invention, in the above memory access control device, the plurality of bus transceivers control switching of the signal direction of a data signal including any one of the plurality of memories by a control signal from a control circuit. And a memory access control device including a plurality of control circuits for selecting the output of the data signal or setting the high impedance state.

Further, according to the present invention, in any of the above memory access control devices, a memory access control device in which a plurality of bus transceivers are controlled from a control circuit via two control transmission lines, respectively, is obtained. .

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a simplified block diagram showing a basic configuration of a memory access control device according to one embodiment of the present invention.

The memory access control device includes a memory device 7 including a plurality of (here, two) memories 5 and 6 storing data, a data bus 1 to which data of the memories 5 and 6 are output, A plurality (here, 2) for controlling the direction of data between the bus 1 and the memories 5, 6
Bus transceivers 2 and 3 and a control circuit 4 for controlling accesses to the memories 5 and 6 and the bus transceivers 2 and 3.

That is, in this memory access control device,
The bus transceivers 2 and 3 are connected to the data bus 1, and these bus transceivers 2 and 3 are connected to memories 5 and 6 respectively.
Are connected, and the memories 5 and 6 and the bus transceivers 2 and 3 are controlled by the control circuit 4. However, the bus transceivers 2 and 3 are controlled by the control circuit 4 via two control transmission lines, respectively.

FIG. 2 is a circuit diagram showing a main configuration of bus transceivers 2 and 3 provided in the memory access control device of FIG.

Each of the bus transceivers 2 and 3 has a control circuit 8 for switching and controlling the signal direction of the data signal A1 or the data signal B1 according to the direction signal DIR from the control circuit 4. The control circuit 8 controls the data signal A1. To the data signal B1, or the signal direction can be switched from the data signal B1 to the data signal A1. Further, the control circuit 8 can control whether the data signal A1 or the data signal B1 is output or the impedance is high by the enable signal OE from the control circuit 4. That is, the control circuit 8 controls the switching of the signal direction of the data signal including any one of the memories 5 and 6 by the control signal from the control circuit 4 and selects the output of the data signal or the high impedance. Set the status.
It should be noted that a plurality of such control circuits 8 are usually mounted for each of the bus transceivers 2 and 3.

The operation of the memory access control device will be described below with reference to the timing chart shown in FIG.

Here, the direction signal DI of the bus transceivers 2 and 3 is read by the control circuit 4 in order to read data from the memories 5 and 6 of the memory device 7 and output the data to the data bus 1.
R is controlled so that data in the memories 5 and 6 flows from the memory device 7 in the direction of the data bus 1.

That is, for example, when the address ₅ , RAS ₅ , CAS ₅ and data ₅ are in the relationship shown in the figure with respect to the memory 5 and the first data ₅ (D0) of the memory 5 is output to the data bus 1, By controlling the enable signal OE of the transceiver 3 to set the output to a high impedance state, controlling the direction signal DIR of the bus transceiver 2 to set the output to a through state and reading the memories 5 and 6 to output data, , Data ₅ (D0) of the memory 5 is output to the data bus 1.

Next, regarding the memory 6, addresses ₆ , RA
S ₆ , CAS ₆ , and data ₆ have a relationship as shown in the figure, and the first data 6 (D 1) of the memory 6 is transferred to the data bus 1.
, The enable signal OE of the bus transceiver 2 is controlled to make the output a high impedance state, the enable signal OE of the bus transceiver 3 is controlled, and the direction signal DIR is controlled to make the output a through state. By causing the memories 5 and 6 to be in the read state and outputting data, the data ₆ (D1) of the memory 6 is output to the data bus 1.

Subsequently, similarly, the next data in the memory 5
_{5 When} (D2) is output to the data bus 1, the enable signal OE of the bus transceiver 3 is controlled so that the output is in a high impedance state, and the direction signal DIR of the bus transceiver 2 is controlled so that the output is in a through state. Data ₅ (D 2) of the memory 5 is output to the data bus 1 by causing the data 5 and 6 to be in the read state and outputting the data.

Further, similarly, the next data ₆ (D
When 3) is output to the data bus 1, the enable signal OE of the bus transceiver 2 is controlled to put the output into a high impedance state, the enable signal OE of the bus transceiver 3 is controlled, and the direction signal DIR is controlled. The data ₆ (D3) of the memory 6 is output to the data bus 1 by setting the output to the through state and setting the memories 5 and 6 to the read state and outputting the data.

[0040]

As described above, according to the memory access control device of the present invention, a bus having a small number of input control transmission lines can be used instead of the conventional bus transceiver with registers having a large number of input control transmission lines. Provide a transceiver,
The bus transceiver switches the signal direction of the data signal, selects the output of the data signal, or sets the high impedance according to various control signals from the control circuit. Can be secured. As a result, a simple control process using a small number of control signals is sufficient, so that the control circuit can be easily integrated into an LSI, and the area occupied on the circuit board is reduced, so that the scale can be easily reduced. Because it can be operated, it can be provided at low cost for these reasons.

[Brief description of the drawings]

FIG. 1 is a simplified block diagram showing a basic configuration of a memory access control device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main configuration of a bus transceiver provided in the memory access control device of FIG. 1;

FIG. 3 is a timing chart showing waveforms of processing signals in respective units of the memory access control device shown in FIG.

FIG. 4 is a block diagram showing a basic configuration of a shared memory access device (memory access control device) according to a conventional example.

FIG. 5 is a simplified block diagram showing a specific configuration of the memory access control device shown in FIG.

6 is a circuit diagram showing a main configuration of a bus transceiver with a register provided in the memory access control device of FIG. 5;

7 is a timing chart showing waveforms of processing signals in respective units of the memory access control device shown in FIG.

FIG. 8 is a simplified block diagram showing a basic configuration of a memory access control device according to another conventional example.

9 is a timing chart showing the waveform of a processing signal in each section of the memory access control device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data bus 2, 3 Bus transceiver 4, 11, 13 Control circuit 5, 6 Memory 7 Memory device 8, 12, Control circuit 9, 10, Bus transceiver with register 14, 15 MPU

Claims (3)

[Claims] 1. A memory device including a plurality of memories storing data, a data bus to which data of the plurality of memories is output, and a direction of data between the data bus and the plurality of memories. A plurality of bus transceivers, and a control circuit for controlling access to the plurality of memories and the plurality of bus transceivers. 2. The memory access control device according to claim 1, wherein the plurality of bus transceivers switch a signal direction of a data signal including any one of the plurality of memories according to a control signal from the control circuit. A memory access control device comprising a plurality of control circuits for performing control and for selecting the output of the data signal or setting a high impedance state. 3. The memory access control device according to claim 1, wherein the plurality of bus transceivers are controlled by the control circuit via two control transmission lines, respectively. Memory access control device.