JPS61264463A - Bus controlling system - Google Patents

Abstract

PURPOSE:To increase processing speed by always giving a bus occupation permitting signal to a specified processor regardless of the presence or the absence of an access request to the bus of the specific processor as long as no bus occupation request is given from another processor. CONSTITUTION:A bus controller 1 transmits a bus occupation permitting signal BPRNi to a central processing unit 2 if no bus occupation request signal is delivered from an arithmetic processor 3, etc. Thus the unit 2 monitors the bus occupation declaration signals of a bus 6 regardless of the presence or the absence of an access request to the bus 6. Then the unit 2 occupies the bus 6 synchronously with the trailing of the next bus clock BCLK and delivers the bus occupation declaration signal BBUSY after the occupation of the bus 6 is released synchronously with the trailing of the clock BLLK given from the processor 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control method used in a system including a main memory device using a microprocessor, an input/output device, and the like.

[Conventional technology]

Conventionally, as this type of bus control system, there is Intel's multipath system, which will be explained using FIGS. 3 and 4.

FIG. 3 is a block diagram showing a bus control method in an information processing system. In FIG. 1, 1 is a bus control device, 2 is a central processing unit, and 3 is an arithmetic processing unit.

4 is a main storage device, 5 is an input/output device, and 6 is a bus connecting these devices.

Next, the operation will be explained. In the configuration shown in FIG. 3, when the central processing unit 2 (priority = i) occupies the bus 6, the arithmetic processing unit 3 (priority =
j) sends a bus occupancy request signal BREQj to the bus control device 1.
When (i<j) is output, in the conventional control system, the bus 6 is controlled according to the sequence shown in FIG. Note that the numbers 0 to (g in FIG. 4 correspond to numbers 1 to 2 in the following explanation. However, in FIG. 4, the numbers 0 to (g) are missing.

(When accessing the bus 6, the central processing unit 2 outputs the bus occupancy request signal BREQi corresponding to the priority to the bus control unit 1 in synchronization with the falling edge of the bus clock BCLK).

The Q rebus control device 1 identifies and selects the device with the highest priority at that time, which in this embodiment is the central processing device 2.

(5) Devices identified and selected by the above-mentioned operation Q In this embodiment, the bus control device 1 sends a bus occupancy permission signal BPRNl to the central processing unit 2.

@Central processing unit 2 that received bus occupancy permission signal BPRNi
If the bus occupancy declaration signal BBIJSY is not output to the bus 6, it outputs the bus occupancy declaration signal BBtJsY in synchronization with the falling edge of the bus clock BCLK to declare the occupancy of the bus 6.

(8) When the central processing unit 2 occupies the bus 6, the arithmetic processing unit 3 with a higher priority tries to access the bus 6 and outputs the bus occupancy request signal BREQ in synchronization with the fall of the bus clock BCLKO. Suppose we output the following.

When the bus controller 1 receives the bus occupancy request signal BREQj in the above operation, it stops the bus occupancy permission signal BPRNi that was being output to the central processing unit 2 and sends the bus occupancy permission signal BPRNj to the arithmetic processing unit 3. give.

(The above operation causes the bus occupancy permission signal BPRNj to
The arithmetic processing unit 3 receives the bus occupancy declaration signal B of the bus 6.
BUSY is monitored, and when the central processing unit 2 releases the occupancy of the bus 6 in synchronization with the falling edge of the bus clock BCLK, the arithmetic processing unit 3 is released in synchronization with the falling edge of the primary bus clock BCLK. Bus occupancy declaration signal BBUS
Output Y.

When the access request to the bus 6 from the arithmetic processing device 3 is completed, the bus control device 1 stops the bus occupancy permission signal BPRNj that has been output to the arithmetic processing device 3. At the same time, if there is no bus occupancy request from another processing unit and the bus occupancy request signal BREQ l is output from the central processing unit 2, then
The bus control device 1 sends a bus occupancy permission signal B to the central processing unit 2.
Give PRNi.

(By the above-mentioned operations, the bus occupancy permission signal BPRNi is
The central processing unit 2 that received the bus 6 monitors the bus occupancy declaration signal of the bus 6, and when the occupancy of the bus 6 is released by the arithmetic processing unit 3 in synchronization with the falling edge of the bus clock BCLK, the primary bus clock BCLK is released. Central processing unit 2 synchronizes with the falling edge of
occupies the bus 6 and outputs a bus occupancy declaration signal BBUSY.

Note that the broken lines in FIG. 4 indicate that the signals change in synchronization with the falling edge of the bus clock, and the dotted lines indicate mutually contradictory signals and indicate changing points.

[Problem that the invention seeks to solve]

This conventional bus control method performs control as described above, and therefore has the following problems.

(1) When each processing device connected to the bus accesses the bus, it takes a delay time after outputting the bus occupancy request signal, receiving the bus occupancy permission signal, and outputting the bus occupancy declaration signal. . Therefore, it takes time after the bus occupancy request is output to the bus to output address, command, data (at the time of write) signals, etc. to the bus, and therefore processing time of the processing device is required.

(21) All processing devices must issue a bus occupancy request signal when accessing the bus.

This invention was made to solve the above-mentioned problems, and when a specific processing device accesses the bus, it minimizes the overhead up to outputting the bus occupancy declaration signal, and It is an object of the present invention to provide a bus control method that does not require special circuits and control signals to request access.

[Means for solving problems]

In the bus control method according to the present invention, unless a specific processing device among a plurality of processing devices receives a bus occupancy request from another processing device, the specific processing device always receives an access request to the bus. figure.

A bus occupancy permission signal is applied, and while the bus occupancy permission signal is applied, the specific processing device continues to output a bus occupancy declaration signal.

[Effect]

According to the bus control method of the present invention, when a specific processing device accesses, there is no need to determine whether the access is to the bus, and the bus occupancy declaration signal is output before accessing the bus. Therefore, signals such as addresses, commands, and data (when writing) can be quickly sent to the bus.

〔Example〕

Hereinafter, a bus control method in an embodiment of the present invention will be explained. FIG. 1 is a block diagram showing the bus control system of this embodiment, and numerals 1 to 6 are the same as or correspond to those in FIG. 3 described above.

In the configuration shown in FIG. 1, in the bus control method of this embodiment, the bus 6 is controlled according to the sequence shown in FIG. Note that the numbers σ~(su) in FIG. 2 correspond to the numbers σsu~(su~(su) in the following explanation.

(In FIG. 1, the bus control device 1 is the arithmetic processing device 3.
If the bus occupancy request signal is not outputted from the processing unit 2, the bus occupancy permission signal BPRNi is sent to the central processing unit 2.

(If the bus occupancy declaration signal BBUSY is not output, the central processing unit 2 that receives the rebus occupancy permission signal BPRNi occupies the bus in synchronization with the falling edge of the bus clock BCLK, regardless of whether there is an access to the bus 6 or not.) A declaration signal BBUSY is output to the bus 6 to declare that the bus 6 is occupied.

■When the central processing unit 2 occupies the bus 6, for example, if the arithmetic processing unit 3 attempts to access the bus 6, it outputs the bus occupancy request signal BREQjt in synchronization with the falling edge of the bus clock BCLK. do.

When the bus controller 1 receives the bus occupancy request signal BREQjt in the operation described above, it stops the bus occupancy permission signal BPRNi that was being output to the central processing unit 2 and sends the bus occupancy permission signal BPRNj to the arithmetic processing unit 3. give.

(αThe arithmetic processing unit 3 that receives the bus occupancy permission signal BPRNj by the above @ operation receives the bus occupancy declaration signal B of the bus 6.
BUSY is monitored, the processing of the central processing unit 2 is completed, and the bus 6 is occupied by the bus clock BCLK from the central processing unit 2.
When released in synchronization with the falling edge of B, the next bus clock B
In synchronization with the falling edge of CLK, the arithmetic processing unit 3 occupies the bus 6 and outputs a bus occupancy declaration signal BBUSY.

(When the arithmetic processing unit 3 completes its access request to the bus, the bus control unit 1 stops the bus occupancy permission signal BPRNj that has been output to the arithmetic processing unit 3. At the same time, if there is no bus occupancy request from another processing unit, , bus control device 1
gives a bus occupancy permission signal BPRNi to the central processing unit 2.

(By the above 6 operations, the bus occupancy permission signal BPRNi is
The central processing unit 2 that receives the bus 6 monitors the bus occupancy declaration signal of the bus 6, regardless of whether there is an access request to the bus 6, and determines that the occupancy of the bus 6 is synchronized with the falling edge of the bus clock BCLK from the arithmetic processing unit 3. When the bus 6 is released, the central processing unit 2 occupies the bus 6 in synchronization with the fall of the primary bus clock BCLKO and outputs the bus occupancy declaration signal BBUSYe.

The above embodiment describes a case where the bus access frequency is high and the bus is mainly occupied by a central processing unit and other arithmetic processing units. However, even in a mutually equal multiprocessor system, bus occupancy requests If the bus occupancy permission signal is always given to a specific processing device, the same effect as in the above embodiment can be obtained.

Furthermore, in the above embodiment, if a bus occupancy request does not come from another processing device, a bus occupancy permission signal is given to the central processing unit, so the central processing unit describes a case where the bus occupancy request circuit and signal are not required. However, if the priority level of the central processing unit is set to the lowest level and the bus occupation request signal is always output to the bus regardless of whether there is an access request to the bus from the central processing unit, the same effect as in the above embodiment can be obtained. Play.

〔Effect of the invention〕

As described above, according to the present invention, if there is no bus occupancy request from another processing device, a bus occupancy permission signal is always given to the specific processing device regardless of whether there is an access request to the bus of the specific processing device, Since the specific processing device can occupy the bus, there is no delay time between outputting the bus occupation request signal and outputting the bus occupation declaration signal, and there is no delay time between outputting the bus occupation request signal and outputting the bus occupation declaration signal. ) Signals etc. can be sent out quickly, processing speed is increased and performance is improved, and a bus access request circuit and signal for requesting access to the bus are not required for a specific processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a bus control method according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing a bus control sequence of the bus control method according to an embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram showing the bus control sequence of the conventional bus control method. In the figure, 1 is a bus control unit, 2 is a central processing unit, and 3 is a bus control unit.
is an arithmetic processing unit, 4 is a main storage device, 5 is an input/output device, 6
is a bass, and BCLK is a bass glock. BBUSY is a bus occupancy declaration signal, BREQi-1 is a bus occupancy request signal, and BPRNI-1 is a bus occupancy permission signal. In the drawings, the same reference numerals indicate the same or common parts.

Claims (1)

[Claims] If there is no bus access request from another processing device to a specific processing device among a plurality of processing devices that access the bus in a time-sharing manner, regardless of whether there is a bus access request from the specific processing device, A bus control method in which a bus occupancy permission signal is always given to the specific processing device, and the specific processing device continues to occupy the bus while the bus occupancy permission signal is being given to the specific processing device.