JPH03204786A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To suppress the operation which cannot be foreknown due to a runaway, etc., of a system to the minimum by executing the output control of an output state by an input signal from the outside irrespective of an internal operation by which the output control of the output port is executed by a CPU. CONSTITUTION:A second output control circuit 6 becomes effective at the time when an input level of an output control input terminal 7 provided on the outside of a microcomputer is a high level. Accordingly, when the output control input terminal 7 is a low level input, data of a data signal A is outputted from an output terminal, but in the case a CPU runs away, when the level of the output control input terminal 7 becomes a high level, an input level of an output data input terminal 8 inputted from the outside is outputted irrespective of the data signal A from an internal circuit and the level of an internal output control signal 5. In such a way, when a program becomes a runaway state, its output can be controlled from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip microcomputer.

[Conventional technology]

Conventionally, in this type of single-chip microcomputer, the output of the output boat is controlled and output using various control signals from the internal CPU.For example, when performing high-level output to the output boat, the output latch of the output boat is The output was determined by setting high-level data by the CPU.

[Problem to be solved by the invention]

In the conventional single-chip microcomputer described above, if the program goes out of control, the single-chip microcomputer is in an abnormal operating state, so there is a possibility that abnormal output control will be performed by rewriting the output latch, etc. Moreover, even if a fatal defect occurs in the internal circuit that can prevent the operation of the CPU, such as a partial short circuit or disconnection, normal output control according to the user program cannot be performed.

In particular, in devices that require high reliability using single-chip microcomputers, such as robot control, NC control, and automobile electrical equipment, the above-mentioned failures can cause unpredictable abnormalities because the output boat cannot obtain the expected output. There is a drawback that it moves.

The purpose of the present invention is to prevent the program from running out of control.
The object of the present invention is to provide a single-chip microcomputer whose output can be controlled externally.

[Means to solve the problem]

The single-chip microcomputer of the present invention is a single-chip microcomputer having an output terminal, and has means for controlling the level of the output terminal by an input signal from the outside, regardless of the internal operation of the CPU controlling the output. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Data outputted to the output terminal 1 is generated by being transmitted to the gate of the MOS transistor of the CMO3 output buffer 4 via the output control circuit 3 in accordance with the data signal A from the internal circuit. The first output control circuit 3 is controlled by an internal output control signal 5 from an internal circuit, and during normal operation, when this signal is low level, the output becomes 1 enable (high or low level output) 1, and when it is low level, the output is is disabled (high impedance output).

On the other hand, the second output control circuit 6 is a circuit that becomes effective when the input level of the output control input terminal 7 provided outside the microcomputer is at a high level. The level input from the data input terminal 8 becomes the data signal B, and the second
It is transmitted to the CMO3 output buffer 4 via the output control circuit 6 of 6, and the output is determined.6 At the same time, the internal output circuit control signal 10 becomes high level, so the internal output control signal 5 is controlled and the output is determined by the first output control circuit. 3 is invalid.

Therefore, when the output control input terminal 7 is a low level input, the data of the data signal A is output from the output terminal 1, but if the CPU goes out of control, the level of the output control input terminal 7 is set to a high level. As a result, the input level of the output data input terminal 8 input from the outside can be output regardless of the levels of the data signal A and the internal output control signal 5 from the internal circuit.

FIG. 2 is a block diagram showing a second embodiment of the invention. The basic configuration of this embodiment is the same as that of the first embodiment, but the configuration for supplying the data signal B is such that when the output control input terminal 7 is input at a high level, a predetermined pulse is sent from one output terminal to the CP.
It is distinctive in that it is designed to be output regardless of the operation of U. That is, n-bit down counter 1
Reference numeral 1 denotes a timer that counts down based on the tarock input from an external clock input terminal 12, and outputs U and F (mander follow) signals 13 when the count ends. Further, the initial value of this counter is a value preset in the m-bit register 14 (02m) and is loaded into the n-bit down counter 11 by a trigger applied to the external trigger input terminal 15. .

This m-bit register 14 is fixedly set at the time of manufacture by a mask.

When a rising etch input is applied to the external trigger input terminal 14, the F/F 16 (SR, flip-flop) is set and the data signal B is output at a high level.

When the down count ends and U and F13 occur,
The F/F 16 is reset and the data signal B is output at a low level.

Therefore, a predetermined (m bits×clock period) pulse synchronized with the external clock can be output from the output terminal 1, regardless of the operation of the CPU.

〔Effect of the invention〕

As explained above, the present invention uses a single-chip microcomputer by allowing the CPU to control the output state of the output board using external input signals, regardless of the internal operation that controls the output of the output board. Especially in systems that require high reliability, it is possible to design the system so that it operates on the safe side even if the microcomputer operates abnormally, which has the effect of minimizing unpredictable operations such as runaway system. .

[Brief explanation of drawings]

The first section is a block diagram showing the first embodiment of the present invention, and the second section is a block diagram showing the first embodiment of the present invention.
The figure is a block diagram showing a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Output terminal, 3... First output control circuit, 4.
... CMOS output buffer, 5... Internal output control signal, 6... Second output control circuit B, 7... Output control input terminal, 8... Output data input terminal, 10... Internal Output circuit control signal, 11...n-bit down counter, 12...external clock input terminal, 13...U,
F (underflow signal), 14... m-bit register, 15... external trigger input terminal, 16... F/
F (set-reset, flip-flop).

Claims (1)

[Claims] A single-chip microcomputer having an output terminal, characterized in that the single-chip microcomputer has means for output-controlling the level of the output terminal by an input signal from the outside, regardless of the internal operation in which the CPU performs output control. .