JP2001203324A - Integrated circuit and method for controlling its operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a low power consumption of order of several microamperes. SOLUTION: In an integrated circuit 1, a main circuit 2 and a sub-circuit 10 are constituted so that a power can be turned on and off independently from each other. When the circuit 2 is turned off, a substantial area of the circuit 1 becomes an area of the circuit 10. Accordingly, a leakage current can be suppressed, and the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which a plurality of circuits are mounted on one chip.

[0002]

BACKGROUND OF THE INVENTION An increase in the number of circuits constituting an electronic device;
Power consumption is increasing in accordance with the complexity of circuits. In order to realize low power consumption, for example, the clock frequency of the microcomputer is reduced or stopped, or the power supply of the microcomputer is monitored. When the power supply is reduced, a low power consumption mode is set. Thus, it is very important to minimize power.

As the LSI (large scale integration) becomes larger, a microcomputer and its peripheral circuits are also mounted on one chip. Even in such a case, the power consumption can be suppressed to some extent by lowering or stopping the clock frequency of the microcomputer, but if the problem is to reduce the power consumption by several microamperes, the leakage current is ignored. You can't do that.

[0004] Even if the LSI chip area becomes large, CM
In the case of OS (complementary metal oxide semiconductor), leak current does not flow theoretically, but actually leak current flows according to the chip area due to lattice deficiency,
It cannot be ignored.

[0005]

DISCLOSURE OF THE INVENTION An object of the present invention is to suppress leakage current and reduce power consumption on the order of several microamperes.

The present invention relates to an integrated circuit having a plurality of circuits mounted on a single chip.
And a second circuit section including a second circuit and connected to the first circuit section, wherein the first circuit section, the second circuit section, Can be controlled independently on and off.

[0007] The present invention also provides a method suitable for the above integrated circuit. That is, in this method, a plurality of circuits
In an integrated circuit mounted on a chip, a first circuit portion including a first circuit and a second circuit portion including a second circuit and connected to the first circuit portion are provided. That is, the first circuit unit and the second circuit unit are independently turned on and off.

According to the present invention, the circuit is divided into the first circuit and the second circuit. The first circuit unit and the second circuit unit are configured to be able to be independently controlled on and off. By turning off one of the first circuit unit and the second circuit unit, the substantial area of the integrated circuit is reduced. Leakage current can be suppressed. Either the first circuit unit or the second circuit unit can be turned on, so that the processing can be realized within a range executable by either one of the circuit units.

Preferably, when the second circuit section is off, a signal supplied from the first circuit section to the second circuit section is cut off. In this case, for example, the second circuit section is turned off after the signal given from the second circuit section to the first circuit section is cut off.

[0010] The signal supplied from the second circuit section to the first circuit section may be cut off when the second circuit section is off. To prevent a signal from being erroneously input from the second circuit unit to the first circuit unit when the second circuit unit is off, thereby preventing the first circuit unit from malfunctioning. Can be.

[0011] The first circuit section may further include a circuit for controlling on / off of the second circuit section.

A monitoring circuit for monitoring an operating voltage of the second circuit; and a second circuit for detecting the second circuit being inoperable by the operating voltage monitoring circuit. May be further provided with a circuit for turning off the circuit section. Automation of the off control of the second circuit unit can be realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention and is a block diagram showing an electrical configuration of an integrated circuit 1.

The integrated circuit 1 is composed of a main circuit 2 and a sub-circuit 10 each of which can be independently turned on and off (whether or not power is supplied).

The main circuit 2 includes a CPU, a DRAM, a signal processing circuit, and the like. The main circuit 2 is supplied with a power supply voltage from outside the integrated circuit 10.

The sub-circuit 10 includes a first AND gate 11 and a second AND gate 12, and a calendar circuit 13. The sub-circuit 10 is supplied with an operation control signal, a sub-circuit reset signal and a sub-circuit power supply voltage from outside the integrated circuit 10. The operation control signal includes a first AND
Gate 11 and one input terminal of second AND gate 12 are provided.

The main circuit 2 and the sub circuit 10 are connected.
The main circuit 2 outputs a signal for rewriting the data of the calendar circuit 13. This rewrite signal is input to the other input terminal of the first AND gate 11. Therefore, when the operation control signal is given to the sub-circuit 10, the rewrite signal output from the main circuit 2 passes through the first AND gate 11 and is input to the calendar circuit 13. The data of the calendar circuit 13 will be rewritten.

The output data of the calendar circuit 13 is input to the other input terminal of the second AND gate 12. When the operation control signal is input to the second AND gate 12, the output data of the calendar circuit 13 passes through the second AND gate 12, and is input to the main circuit 2. The main circuit 2 allows the date and the like indicated by the calendar circuit 13 to be displayed.

FIG. 2 is a time chart showing the operation of integrated circuit 1 shown in FIG.

At time T1, a power supply voltage is applied to sub-circuit 10. Thus, the operation of the sub circuit 10 starts. Subsequently, at time T2, a reset signal is supplied to the sub-circuit 10 to be reset once. Thereafter, at time T3, the power supply voltage is applied to the main circuit 2, and the operation starts.
Further, at time T4, the operation control signal is input to the sub-circuit 10, and the sub-circuit 10 of the signal from the main circuit 2 as described above.
The input to the calendar circuit 13 and the output data from the calendar circuit 13 to the main circuit 2 can be performed. That is, the data of the calendar circuit 13 in the sub-circuit 10 can be changed and the data can be read.

Thereafter, when the operation control signal stops at time T5, the input of the output signal from the main circuit 2 to the calendar circuit 13 and the input of the output data from the calendar circuit 13 to the main circuit 2 are cut off as described above. Can be Time T6
The supply of the operation power to the main circuit 2 is stopped at
The operation of the main circuit 2 stops.

The sub-circuit 10 operates regardless of whether the main circuit 2 is on or off. When the main circuit 2 is turned off, the substantial area of the integrated circuit 1 becomes the area of the sub-circuit 10. Integrated circuit 1
Is substantially small, so that the leakage current can be suppressed. It is possible to realize low power consumption in units of micro-amps.

When the main circuit 2 is off, the output of the signal from the main circuit 2 to the sub circuit 10 and the output of the signal from the sub circuit 10 to the main circuit 2 are cut off. An erroneous signal can be prevented from being input to the circuit 10 and the sub-circuit 10 can be prevented from malfunctioning.

FIG. 3 shows another embodiment, and is a block diagram showing an electrical configuration of the integrated circuit 1A.

In this figure, the same circuits as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The sub-circuit 10A includes a power supply control circuit 20. The power supply control circuit 20 controls supply of a power supply voltage to the main circuit 2. The power supply control circuit 20 includes a NAND gate 21, a NOR gate 22, and a flip-flop 23. The output terminal of the NAND gate 21 is connected to the set terminal of the flip-flop 22. The output terminal of the NOR gate 22 is connected to the reset terminal of the flip-flop 23.

A power supply 31 for supplying power to the main circuit 2 is included. A voltage monitoring circuit 32 for checking the voltage of the power supply 31 is connected to the power supply 31. When the voltage of the power supply 31 is equal to or higher than a predetermined threshold, the power supply monitoring circuit 32
It outputs a level signal, and outputs an L level signal if it is less than the threshold value. The output signal of the power supply monitoring circuit 32 is applied to the non-inverting input terminal of the NAND gate 21 and the inverting input terminal of the NOR gate 22 described above. The voltage from the power supply 31 is supplied to the main circuit 2 and the reset circuit 36 via the switch circuit 35. The reset signal output from the reset circuit 36 is also input to the main circuit 2. Switch circuit
Reference numeral 35 is turned on and off by the output signal of the flip-flop 22.

Further, a command switch 33 for starting the supply of power to the main circuit 2 is included. Command switch
A signal indicating the depression of 33 is supplied to the inverting input terminal of the NAND gate 21. The main circuit 2 also outputs a command signal for turning off the main circuit 2. This command signal is transmitted to the NOR gate 22
To the non-inverting input terminal.

Therefore, when the voltage of the power supply 31 is equal to or higher than the predetermined threshold voltage and the command switch 33 is on, a signal is output from the NAND gate 21 and applied to the set input terminal of the flip-flop 22. It will be. Also, an off command is given from the main circuit 2 or the power supply 31
Is lower than a predetermined threshold voltage, a signal is output from the NOR gate 22 and applied to the reset input terminal of the flip-flop 23.

FIG. 4 is a time chart showing the operation of the circuit shown in FIG. In this figure, an operation different from the operation shown in FIG. 2 will be described.

At time T11, voltage monitoring of the power supply 31 starts. If the voltage of the power supply 31 is equal to or higher than the threshold, an H level signal is output. When the command switch 33 is turned on at time T12, the switch circuit 35 is turned on at time T13, and the voltage of the power supply 31 is supplied to the main circuit 2 (time T3).

When the power supply voltage applied to the main circuit 2 exceeds a predetermined value, the reset circuit 36 outputs a reset release signal. The reset release signal is supplied to the main circuit 2, and the reset of the main circuit 2 is released at time T15.

At time t16, when the voltage of the power supply 31 decreases, the output of the voltage monitoring circuit 32 goes from H level to L level at time T17. Then, at time T18, the output of the power supply control circuit 20 turns off, and the switch circuit 35 turns off. The power supply to the main circuit 2 is stopped. When the power supply voltage of the main circuit 2 falls below a certain voltage, a reset signal is output from the reset circuit 36, and the main circuit 2 is reset.

When the voltage of the power supply 31 decreases, the power supply to the main circuit 2 can be stopped.

At time T17, if an OFF command is output from main circuit 2 to power supply control circuit 20, power supply control circuit 20
Outputs a switch control signal to the switch circuit 35. Then, the switch circuit 35 is turned off, and the time T
At 16, the supply of the voltage to the main circuit 2 is stopped.

In the circuit shown in FIG. 3, the power supply voltage of the main circuit 2 is monitored, and when the power supply voltage falls below a predetermined threshold voltage, the supply of power to the main circuit 2 can be stopped. Further, the supply of power to the main circuit 2 can be stopped by the main circuit 2 itself.

In the circuit shown in FIG. 3, the voltage monitoring circuit 32, the command switch 33, the switch circuit 35, the reset circuit 36, etc. are not mounted on the integrated circuit 1A, but all or a part of those circuits are integrated. Needless to say, it may be mounted on the circuit 1A.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an integrated circuit.

FIG. 2 is a time chart showing an operation of the integrated circuit shown in FIG.

FIG. 3 is a block diagram showing another embodiment and showing an electric configuration of an integrated circuit.

FIG. 4 is a time chart illustrating an operation of the integrated circuit illustrated in FIG. 3;

[Explanation of symbols]

 1,1A integrated circuit 2 main circuit 10,10A sub circuit 11,12 AND gate 13 calendar circuit 20 power supply control circuit 31 power supply 32 voltage monitoring circuit 33 command switch 35 switch circuit 36 reset circuit

Continued on the front page F-term (reference)

Claims (7)

[Claims] 1. An integrated circuit having a plurality of circuits mounted on one chip, comprising: a first circuit section including a first circuit; and a second circuit.
And a second circuit unit connected to the first circuit unit, wherein the first circuit unit and the second circuit unit are independently turned on,
An off-controlled integrated circuit. 2. A signal supplied from the first circuit section to the second circuit section and a signal supplied from the second circuit section to the first circuit section when the second circuit section is off. 2. The integrated circuit according to claim 1, further comprising a cutoff circuit that cuts off at least one of the received signals. 3. The method according to claim 1, further comprising the step of: turning on said first circuit after turning on said second circuit.
3. The integrated circuit according to claim 2, further comprising a cutoff release circuit for releasing said cutoff of a signal supplied from said circuit portion to said second circuit portion. 4. The integrated circuit according to claim 2, further comprising an off control circuit for turning off said second circuit unit after said interruption of a signal supplied from said second circuit unit to said first circuit unit. . 5. The integrated circuit according to claim 1, wherein said first circuit unit further comprises a circuit for controlling on / off of said second circuit unit. 6. A monitoring circuit for monitoring an operation voltage of the second circuit, and the second circuit is responsive to the operation voltage monitoring circuit detecting that the second circuit has become inoperable. 2. The integrated circuit according to claim 1, further comprising a circuit for turning off the circuit unit. 7. An integrated circuit having a plurality of circuits mounted on one chip, comprising: a first circuit portion including a first circuit; and a second circuit;
And a second circuit unit connected to the first circuit unit, and the first circuit unit and the second circuit unit are independently turned on.
An operation control method for an integrated circuit, which is turned off.