JP2846203B2 - Parallel multiple inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel multiplex inverter device in which inverter output terminals are connected in parallel in order to increase the capacity of the inverter device. And a parallel multiplex inverter device.

[0002]

2. Description of the Related Art Generally, in order to increase the capacity of an inverter device, a parallel multiplexing system in which output terminals of a plurality of unit inverters are connected in parallel via a reactor is employed. FIG. 11 is a circuit diagram showing a configuration of a conventional parallel multiplex inverter device, in which 1 is a DC power supply, 2a,
2b is a unit inverter, 3a to 3f are half bridges,
4a, 4b, 4c are reactors with an intermediate tap, X is an intermediate potential point of the DC power supply 1, 5a to 5f are half bridges 3a.
Output terminals U, V, and W are the output terminals of the parallel multiplex inverter device. 12 and 13 are circuit diagrams showing the configuration of the half bridges 3a to 3f. FIG. 12 shows a two-level inverter capable of outputting two values of E and 0 of the voltage of the DC power supply 1 to the output terminal 5. In FIG.
Reference numerals a and 6b denote self-extinguishing semiconductor devices, 7a and 7b denote freewheeling diodes, and 5 denotes a half-bridge output terminal. FIG. 13 shows a three-level inverter which can output three values of E, E / 2 and 0 of the voltage of the DC power supply 1 to the output terminal 5. In FIG. Semiconductor elements, 7c to 7f are freewheel diodes, 8a and 8b are clamp diodes, 5 is an output terminal of a half bridge, and X is a terminal connected to the intermediate potential point X of the DC power supply 1. When the unit inverters 2a and 2b are operated in the same phase in such a parallel multiplex inverter device, variations in switching characteristics of the self-extinguishing semiconductor elements 6a to 6f constituting the unit inverters 2a and 2b,
Due to variations in inductance values of the reactors 4a, 4b, 4c, a circulating current flows between the unit inverters 2a, 2b via the reactors 4a, 4b, 4c. FIG. 14 is a circuit diagram showing a circulating current path in the three-level inverter of FIG.
This may break the load sharing of 2b.

A method for driving such a parallel multiplex inverter device while suppressing such a circulating current is disclosed in Japanese Unexamined Patent Publication No. 1-1100.
As disclosed in Japanese Patent Publication No. 62-62, it is known that the circulating current is suppressed by adjusting the timing of the ON / OFF signal of the self-extinguishing type semiconductor element constituting each unit inverter.

Japanese Patent Application Laid-Open No. 63-287371 discloses a circulating current for each phase which is detected and fed back to correct a voltage command value for each phase relating to pulse width modulation (hereinafter referred to as PWM). There is known a method for suppressing the circulating current.

Further, Japanese Patent Application Laid-Open No. 3-253293 discloses that when an AC motor is driven by using a parallel multiplex inverter device, an added value (phase output current) is calculated based on the output current detection value of each unit inverter. And a subtraction value (circulating current) are calculated, and the circulating current is suppressed while suppressing the phase output current by feeding back to the output current control circuit of each unit inverter with different gains. .

[0006]

SUMMARY OF THE INVENTION Conventional Japanese Patent Laid-Open No. 1-11 / 1999
In the parallel multiplex inverter device disclosed in Japanese Patent Application Publication No. 0062, a point-extinguishing timing adjuster must be added to the point-extinguishing signal generation circuits of all the self-extinguishing type semiconductor elements constituting the unit inverter. When using a three-level inverter as a unit inverter as shown in FIG.
As shown in FIG. 5, there is a problem that the configuration of the point extinguishing timing controller becomes complicated because there are four types of point extinguishing patterns of the self-extinguishing type semiconductor element for each phase.

[0007] Further, in a parallel multiplex inverter device capable of suppressing a circulating current disclosed in JP-A-63-287371 and JP-A-3-253293,
An AC voltage command signal is created for each phase of each unit inverter. In other words, the PWM circuit is based on a so-called triangular wave comparison PWM method in which a triangular wave carrier is compared with an AC voltage command signal to generate a switching signal for the self-extinguishing type semiconductor element. Therefore, the output voltage of the inverter is represented by a voltage vector, for example, a voltage vector is selected such that the primary interlinkage magnetic flux vector of the AC motor draws a circular locus, and the switching state of the self-extinguishing type semiconductor element corresponding to the voltage vector is determined. There is a problem that the method cannot be applied to a so-called voltage vector PWM method (also called a space voltage vector PWM method) to be selected. The reason will be described below.

FIG. 16 is a circuit diagram showing a configuration of a parallel multiplex inverter. The voltage vector PWM method will be described with reference to FIG. In this figure, if the zero potential is set so that the zero-phase component of the voltage becomes zero, that is, the equation (1),

[0009] _{v a + v b + v c} = 0 ‥‥‥‥‥‥ (1)

[0010] phase of the output voltage instantaneous value v _a, v _b, v _c can be represented by two variables, i.e. voltage vector. When this is represented by an instantaneous voltage vector, the following equation (2) is obtained.

[0011]

(Equation 1)

Considering the voltage vector of the output voltage of the inverter under this definition, S _a (or S _b , S _c ) = 1 when the self-extinguishing type semiconductor element of the upper arm is turned on in the circuit of FIG. , S _a (or S _b , S _c ) = 0 when the self-extinguishing type semiconductor element of the lower arm is turned on, and the voltage vector v _k is _a function of S _a , S _b , S _c , and v
_{When represented by k} (S _a , S _b , S _c ), the result is as shown in FIG.
For example, equation (3)

[0013]

(Equation 2)

## EQU1 ## Since the output of v ₀ (000), (111) is short-circuited, it becomes a zero voltage vector as shown in FIG. The number of vectors is eight in total, and the position where the voltage vector exists is seven. Here, each of the eight vectors is referred to as a voltage vector. FIG.
In the case of the three-level inverter shown in FIG. 13, this concept is extended, and in the circuit of FIG.
There the case of on-S _a (or _{S b, S c) = 1} , the case where the self-extinguishing type semiconductor device 6d, 6e are turned on S _a (or _{S b, S c) = 1} /2, self-extinguishing Type semiconductor element 6
e, 6f are turned on, S _a (or S _b , S _c ) =
0, and the voltage vector is _a function of S _a , S _b , S _c ,
When represented by v _k (S _a , S _b , S _c ), as shown in FIG. 18, there are 19 voltage vector positions and 27 voltage vector positions.

[0015] For example, when 17 and 18 of the voltage voltage as shown in the vector diagram command V ^* is given, three selected voltage vectors adjacent to the voltage command V ^*, to output a voltage command V ^* The PWM period T is allocated as the duration of the three voltage vectors. Here, if an equilateral triangle formed by connecting the vertices of three voltage vectors is referred to as a region, the voltage vector is defined as PWM for each region.
The voltage command V ^* can be output by previously determining the output order within the period T and switching the switching state of the self-extinguishing type semiconductor element forming the inverter according to the output order and duration of the voltage vector. This inverter control method is called a voltage vector PWM method.

The reason why the voltage vector PWM method cannot be applied to the conventional driving method of the parallel multiplex inverter device for suppressing the circulating current is as follows. First, when the parallel multiplex inverter device has three phases, the voltage vector has two variables according to the equations (1) and (2). In order to suppress the circulating current, three independent variables are required. is necessary. As described above, since the circulating current flows due to the variation in the switching characteristics of the self-extinguishing type semiconductor element constituting the unit inverter and the variation in the inductance value of the reactor, the magnitude of the circulating current in each phase is determined by three phases. Does not exist, that is, equation (1) does not hold for the output voltage of each unit inverter.

This does not depend on the configuration of the unit inverter.
Second, using a three-level inverter as the unit inverter,
When a voltage command is created for each unit inverter and the voltage command is made to follow the voltage command, an area where the voltage command exists is always determined by the voltage vector PWM method. Therefore, as shown in the voltage vector diagram of FIG. 18, for example, different areas are output depending on the voltage commands V ₁ ^* and V ₂ ^* given to each unit inverter.

FIG. 19A is an output voltage waveform diagram in accordance with the output sequence of the voltage vector of the unit inverter following the voltage command V ₁ ^* , and FIG. 19B is a unit following the voltage command V ₂ ^*. FIG. 4 is an output voltage waveform diagram according to an output order of voltage vectors of an inverter. Comparing these two figures, the two unit inverters are driven according to different voltage vector output orders and durations, and there is a PWM cycle T in which the circulating current cannot be suppressed. Therefore, the conventional parallel multiplex inverter has a problem that the circulating current cannot be suppressed in a balanced manner by the voltage vector PWM method .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and is intended to be applied to a case where the driving is performed by a voltage vector PWM method without adding a point extinguishing timing adjuster or the like of a switching element of a unit inverter. Another object of the present invention is to provide a parallel multiplex inverter device that suppresses a circulating current and follows a voltage command.

According to a second aspect of the present invention, the load current is feedback-controlled without adding a point extinguishing timing adjuster or the like of the switching element of the unit inverter, and the circulating current is suppressed when driven by the voltage vector PWM method. It is another object of the present invention to obtain a parallel multiplex inverter device that equalizes a load current and follows a voltage command.

According to a third aspect of the present invention, the load current is feedback-controlled without adding a point extinguishing timing adjuster or the like for the switching element of the unit inverter, and the circulating current is suppressed when driven by the voltage vector PWM method. It is another object of the present invention to provide a parallel multiplex inverter device that equalizes the load current, follows the voltage command, and further reduces the circulating current suppression processing time.

According to a fourth aspect of the present invention, when a plurality of unit inverters are connected in parallel and driven by a voltage vector PWM method, a circulating current is suppressed, a load current is made uniform, and a voltage multiplex inverter is followed. The aim is to obtain a device.

[0023]

According to a first aspect of the present invention, there is provided a parallel multiple inverter device comprising at least three voltage vectors forming each vertex of a region formed by connecting three adjacent vertices of a voltage vector. Select PWM
Voltage vector selecting means for determining an output order within a cycle, voltage command generating means for outputting a voltage command in the form of a voltage vector, and area determining means for determining an area where the voltage command is located for each PWM cycle. A duration calculating means for calculating a duration of the voltage vector within the PWM cycle so that the output voltage matches the voltage command;
Duration correction means for correcting the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of each unit inverter; and output of the unit inverter based on the output from the duration correction means or the duration calculation means. A switching signal generating unit for generating a control signal for controlling the switching element; and the voltage vector selecting unit includes an output unit for outputting a voltage vector based on an output from the duration correcting unit and the area determining unit. .

According to a second aspect of the present invention, there is provided a parallel multiplex inverter device, wherein at least three voltage vectors forming each vertex of a region formed by connecting three adjacent vertices of the voltage vector are selected, and a PWM cycle is selected. A voltage vector selecting means for determining an output order within the circuit, a current command generating means for outputting a current command signal, and a voltage command for outputting a voltage command in the form of a voltage vector based on the current command and the output current of the parallel multiplex inverter device. Generating means, area determining means for determining an area in which the voltage command is located for each PWM cycle, and calculating the duration of the voltage vector within the PWM cycle so that the output voltage matches the voltage command. And calculating the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of each unit inverter. The voltage vector selecting means, comprising: a duration correction means for correcting; and a switching signal generating means for generating a control signal for controlling a switching element of the unit inverter based on outputs from the duration correcting means and the area determining means. An output means for outputting a voltage vector to the unit inverter based on the output from the duration correction means and the area determination means.

According to a third aspect of the present invention, in the parallel multiplex inverter device, one of the voltage vector selecting means outputs a voltage vector to one of the unit inverters based on the output from the duration correcting means and the area judging means. The other of the voltage vector selecting means includes output means for outputting a voltage vector to the other of the unit inverters based on the output from the duration calculating means and the area determining means.

According to a fourth aspect of the present invention, there is provided a parallel multiplex inverter device in which a plurality of unit inverters are connected in parallel, and the output current of one main unit inverter and the output current of another subordinate unit inverter are set as a reference. And a duration correction means for correcting the duration of the voltage vector so as to reduce the deviation current from the deviation current detection means.

[0027]

According to a first aspect of the present invention, there is provided a parallel multiplex inverter device comprising: a region determined from a voltage command by a region determining unit; a voltage vector output unit selected by a voltage vector selecting unit; and a voltage vector obtained by a duration correcting unit. Driven based on duration. Therefore, when driven by the voltage vector PWM method, the circulating current flowing between the unit inverters is suppressed and the voltage command is followed.

In the parallel multiplex inverter device according to the second aspect of the present invention, the area determined from the voltage command by the area determining means, the voltage vector output order selected by the current command generating means and the voltage vector selecting means, and the duration correcting means are used. It is driven based on the obtained voltage vector duration. Therefore, when the load current is feedback-controlled and driven by the voltage vector PWM method,
The circulating current flowing between the unit inverters is suppressed, and the load current is made equal to follow the voltage command.

In the parallel multiplex inverter device according to the third aspect of the present invention, only the duration correction means is provided in one of the unit inverters, and the calculation time required to suppress the circulating current can be reduced.

According to a fourth aspect of the present invention, a plurality of unit inverters which are maintained in parallel are selected by a current generating means and a voltage vector selecting means from a region determined from a voltage command by a region determining means. It is driven based on the output order of the voltage vector and the voltage vector duration obtained by the duration correction means. Therefore, when the load current is feedback-controlled and driven by the voltage vector PWM method, the circulating current flowing between the unit inverters is suppressed, and the load current is equally shared to follow the voltage command.

[0031]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a parallel multiplex inverter device according to an embodiment of the present invention.
FIG. 2 is a configuration diagram showing a main circuit of the parallel multiplex inverter device of FIG.

In FIG. 1, reference numeral 10 denotes voltage command generating means of the parallel multiplex inverter device, 11 denotes area determining means, 12 denotes voltage vector duration calculating means, 13a, 13b, 1
3c is based on the circulating current Δi of each phase from the unit inverters 2a and 2
voltage error calculating means for calculating an output voltage error between b, 14
a and 14b are duration correction means for correcting the duration of the voltage vector in accordance with the computation results of the duration error computing means 13a, 13b and 13c based on the computation result of the duration computation means 12;
5a and 15b are voltage vector selection means, 16a and 16b
Reference numeral denotes switching signal generating means for generating a switching signal for turning on / off the self-extinguishing type semiconductor elements constituting the unit inverters 2a and 2b. The signals of the switching inverters 16a and 16b are used to generate the unit inverter 2
a and 2b are driven. In addition, unit inverters 2a and 2b
Is a three-level inverter shown in FIG. 13 for the purpose of simultaneously solving the two problems of the above-described conventional technology.

Referring to FIG. 2, 9a in FIG.
Reference numerals 9f to 9f denote current detecting means for detecting all output currents of the unit inverters, and the arrows in the drawing indicate the positive direction of the current.
Further, the same reference numerals as those of the conventional example have the same configuration as the conventional example.

Next, the operation will be described. First, a method of driving a parallel multiple inverter device while suppressing a circulating current using a voltage vector PWM method will be described.

The voltage command generating means 10 outputs a voltage command vector V ^* . And the voltage command vector V ^* Each unit inverter 2a, and not with respect to 2b, is for the parallel multi-inverter system, amplitude k, that is, using an angle θ from the axis, i.e. v ₄ of the U-phase in Fig. 3 vector It shall be displayed. Here, it is assumed that voltage command vector V ^* rotates at angular frequency ω.

Next, the region determining means 11 determines in which region the voltage command vector V ^* exists in the voltage vector diagram of FIG. Therefore, the voltage vector to be selected here is also determined. Hereinafter, as shown in FIG. 3, the voltage command vector V ^* becomes three voltage vectors v ₄ ′ [= (1 /
2,0,0) or (1,1 / 2,1 / 2)], v ₆ ′
[= (1/2, 1/2, 0) or (1, 1, 1 /
2)] and v ₄₆ [= (1, 1/2, 0)] will be described as an example. On the basis of the voltage command vector V ^* , the duration calculating means 12 calculates the arc trajectory drawn by the voltage command vector V ^* in a certain PWM cycle T and the trajectory drawn by the composite vector output using the voltage vector to be selected. The condition for equality is expressed by equation (4).

[0037]

(Equation 3)

The condition and the condition that the sum of the durations of the three voltage vectors is equal to the PWM period T is expressed by the following equation (5).

T ₄ ′ + t ₆ ′ + t ₄₆ = T ‥‥‥‥‥‥ (5)

When the durations of these three voltage vectors are obtained, the equation (6) is obtained.

T ₄ ′ = T (1-2 k sin θ) t ₆ ′ = T {1-2 k sin [(π / 3) −θ]} t ₄₆ = T {2 k sin [θ + (π / 3)] − 1} ‥‥‥‥‥ (6)

Here, t ₄ ′, t ₆ ′ and t ₄₆ are the durations of the voltage vectors v ₄ ′, v ₆ ′ and v ₄₆ respectively. Similarly, when the voltage command vector V ^* exists in another area, it is possible to obtain the duration of three selected voltage vectors.

Next, a method of calculating the circulating current Δi will be described. Looking at the U-phase, in FIG.
a, 9 a d of each unit inverter U-phase output currents i _u1,
i _u2 is detected. Assuming that the circulating current Δi _u and the U-phase output current i _u are flowing in the direction of the arrow in the figure, the phase output currents i _u1 and i _u2 are expressed by Equation (7).

I _u1 = (i _u / 2) + Δi _u i _u2 = (i _u / 2) −Δi _u ‥‥‥‥‥‥‥‥ (7)

From the phase currents i _u1 and i _{u2 in} equation (7), the circulating current Δi _u is represented by equation (8).

Δi _u = (i _u1 −i _u2 ) / 2 ‥‥‥‥‥‥‥‥ (8)

[0047] Thus, the circulating current .DELTA.i _u by subtractor (not shown) to detect a current detector 9a, 9 U-phase output currents i _u1, i _u2 of each unit inverter by d can be easily obtained. The circulating current of other phases in the same manner .DELTA.i _v, delta
i _w can also be determined. Next, the voltage error calculating means 13
a, 13b, 13c, the unit inverter 2b with respect to the unit inverter 2a required to flow the circulating current Δi
Output voltage error Delta] v _u of, Delta] v _v, seek Delta] v _w, the output voltage error Δv _u, Δv _v, the voltage value of the half from Delta] v _w of the DC power source 1 E / 2, PWM frequency f a (= 1 / T) calculating correction amount of time Delta] t _u duration of the voltage vector for the PWM period T, Δt _v, a Delta] t _w using. The correction time amounts Δt _u , Δt _v , Δt _w are calculated by the voltage error calculating means 13.
a, 13b, and 13c are output.

Next, the voltage error calculating means 13a, 13b, 1
3c, the correction time amounts Δt _u , Δt _v , Δt
_{A method} of using _w to correct the voltage vector duration obtained by the duration calculation means 12 in the duration correction means 14a and 14b so as to suppress the circulating current Δi flowing through each phase will be described. Here, FIG. 3 is given as the voltage command vector V ^* , and the duration calculation means 1 in that case is given.
2, the distribution of the voltage vector duration to the PWM cycle T is shown in FIG.
The voltage vectors selected at the beginning and end in the same position are the same, but different elements are selected.

When the voltage vector is selected in this manner, PW
In the M period T, the output voltage level always fluctuates in all three phases. For convenience v ₄ a 'duration t ₄ of' it is evenly distributed but reduce the ripple of the output current, or be distributed arbitrarily for the purpose of ensuring a minimum pulse width, a voltage that is uniformly distributed There is no problem as long as the sum of the durations of the vectors is the same.

FIG. 4A shows an output voltage waveform of each phase (normalized by the voltage E of the DC power supply 1) when the output is performed in accordance with the output order of the selected voltage vector. If attention is paid to the PWM cycle T on the left side of the figure, v ₄ ′ is maintained for a period from time t ₀ to t _{1, that} is, T ₄ ′ / 2,
From time t ₁ t ₂ i.e. T ₆ 'period of v _6' persisting the period from time t ₂ t ₃ i.e. T ₄₆ causes sustain v _46, t ₄ ie T ₄ from the time t ₃ '/ 2 the period 'and persisting the, T _4' v ₄ sum of T ₆ 'and T ₄₆ indicates that a PWM period T. As shown in FIG. 5, the three-phase circulating current Δi is assumed to be positive in the U phase, positive in the V phase, and negative in the W phase.

However, the direction from the unit inverter 2a to the unit inverter 2b is positive. Therefore, when the circulating current Δi flows in a positive direction for a certain phase, the unit inverter 2a has a positive polarity and the unit inverter 2b has a negative polarity as an output voltage error of the phase. In this case, the unit inverter 2a becomes a negative electrode and the unit inverter 2b becomes a positive electrode.

In the PWM cycle T on the left side of FIG. 4A, the voltage level of the V phase changes from 0 to で は at time t ₁ , and the voltage level of the U phase changes from か ら to 0 at time t _2. At time t ₃ , the W-phase voltage level is changed from 0 to １ ／.
Has changed.

Therefore, at time t ₁ , only the V-phase output voltage can be changed by shifting to the right or left by the correction time Δt _v output from the voltage error calculating means 13a.

[0054] If you find that the circulating current Δi _v now V-phase is positive, the right shift of Δt _v is the unit inverter 2a, the unit inverters 2b be carried out to the left shift of Δt _v, circulating current Δi _v Is to flow in the negative polarity, so that the circulating current flowing in the positive polarity is suppressed. As for the time t ₂ can be changed by the output voltage of the U-phase if only the right or left shifted correction amount of time Delta] t _u. Knowing that the circulating current .DELTA.i _u of U-phase is positive, the unit inverters 2a to right shift Delta] t _u,
So that may be carried out to the left shift of Δt _u in the unit inverter 2b.

At time t ₃ , the correction time Δt
_By shifting right or left by _w, only the W-phase output voltage can be changed. Knowing that circulating current .DELTA.i _w of W-phase is negative, the unit inverters 2a Delta] t _w
The left shift, so that may be carried out a right shift of Δt _w in the unit inverter 2b.

The PWM of the left half of FIGS. 4B and 4C
The period T indicates the above processing operation. FIG.
4B shows the distribution of the voltage vector duration for the unit inverter 2a after the correction by the duration correction means 14a, and FIG. 4C shows the distribution of the voltage vector duration to the unit inverter 2b after the correction by the duration correction means 14b.
Considering the PWM cycle T in the right half of FIG. 4A similarly, the PWM cycle T in the right half of FIGS. 4B and 4C is considered.
become.

Here, considering the average of FIGS. 4B and 4C, that is, the output as a parallel multiplex inverter device,
FIG. 6 shows that the average voltage output in the PWM cycle T is the same as that in FIG. That is, the duration correction means 14
The correction of the voltage vector duration performed at a and 14b has no adverse effect on the output of the parallel multiplex inverter device.

Further, even when the voltage command vector V ^* is in another area, the voltage change of each phase (change of rising like the left half or change of falling like the right half of FIG. 4A) If the information of the phase having the voltage fluctuation is known in advance at the time of switching the voltage vector, the above-described voltage vector duration correction for suppressing the circulating current Δi of each phase can be performed.

Next, voltage vector selecting means 15a, 15b
In the above, voltage vectors are selected and output in a predetermined order based on the area obtained by the area determination means 11 and the voltage vector duration obtained by the duration correction means 14a and 14b. Further, in accordance with the voltage vectors selected by the voltage vector selection units 15a and 15b, the switching signal generation units 16a and 16b output switching signals for turning on and off the self-extinguishing type semiconductor elements constituting the unit inverters 2a and 2b, respectively. Drive the unit inverters 2a and 2b.

Embodiment 2 FIG. FIG. 7 is a circuit diagram showing a configuration of a parallel multiplex inverter device according to one embodiment of the second aspect of the present invention. The main circuit configuration of the parallel multiplex inverter device of the present invention is the same as that of the first embodiment. In the figure, reference numeral 17 denotes a current command generating means of the parallel multiplex inverter device, 18a, 18b,
Reference numeral 18c denotes a subtractor for calculating a deviation between each phase current command and each phase output current, and 19 denotes a voltage command generating means for outputting a voltage command of the parallel multiplex inverter device in the form of a vector from the outputs of the subtracters 18a, 18b, 18c. The same reference numerals as those of the first embodiment denote the same components as those of the first embodiment.

Next, the operation will be described. First, a method of calculating each phase output current i will be described. As for the U-phase by a current detector 9a, 9 d in FIG. 2 for detecting the U-phase output currents i _u1, i _u2 of each unit inverter. Assuming that the circulating current Δi _u and the U-phase output current i _u are flowing in the direction of the arrow in the figure, the phase output currents i _u1 and i _u2 are expressed by Expression (9).

I _u1 = (i _u / 2) + Δi _u i _u2 = (i _u / 2) −Δi _u ‥‥‥‥‥‥‥ (9)

From the phase output currents i _u1 and i _{u2 in} equation (9), the U-phase output current i _u is expressed by equation (10).

I _u = i _u1 + i _u2 ‥‥‥‥‥‥‥ (10)

[0065] Thus, U-phase output currents i _u by an adder (not shown) to detect a current detector 9a, 9 by d of each unit inverter U-phase output currents i _u1, i _u2 can is easily determined. The output current i _v of other phases in the same manner, i _w can be determined.

Next, each phase current command and each phase output current are input to the subtracters 18a, 18b and 18c, and a current deviation is obtained as an output. This deviation is input to the voltage command generation means 19, and a voltage command is output from the voltage command generation means 19 so that the deviation becomes zero, that is, the output current matches the current command. The output form of the voltage command generating means 19 can be the same as the output form of the voltage command generating means 10 of the first embodiment which outputs the voltage command in the form of a vector.
That is, the output current i _u , i _v , i _w of each phase of the parallel multiplex inverter shown in FIG.

[0067] _{i u + i v + i w} = 0 ‥‥‥‥‥ (11)

This is because the following holds. Therefore, Example 1
In the same manner as described above, the parallel multiplex inverter device can be driven. Here, when creating the voltage command, since the equation (11) is satisfied with respect to the phase output voltage, only the values of two phases of each phase output current may be used.

Further, when the average of the output voltages of the unit inverters 2a and 2b, that is, the output of the parallel multiplex inverter device is considered, it is exactly the same as the first embodiment . That is, it has been found that the correction of the voltage vector duration performed by the duration correcting means 14a and 14b does not have any adverse effect on the output of the parallel multiplex inverter device. This means that the current control response of the output current controller of the parallel multiplex inverter device inside the voltage command generator 19 (not shown) and the circulating current controller inside the voltage error calculators 13a, 13b and 13c (not shown). This means that the current control response can be designed independently. Therefore, even when the current control response of the output current controller of the parallel multiple inverter device is designed to be high, it is possible to suppress the circulating current flowing through each phase.

Embodiment 3 FIG. FIG. 8 is a circuit diagram showing a configuration of a parallel multiplex inverter device according to one embodiment of the third invention. The main circuit configuration of the parallel multiplex inverter device of the present invention is the same as that of the first embodiment. First, portions different from FIG. 7 in FIG. 8 will be described. The unit inverter 2a outputs the voltage vector selected by the voltage vector selecting unit 15a according to the output of the duration calculating unit 12 and the area determining unit 11, and the unit inverter 2b outputs the voltage vector of the duration correcting unit 1.
The voltage vector selected by the voltage vector selection unit 15b is output according to the output of the voltage vector selection unit 11 and the output of the area determination unit 11.
That is, the difference is that a duration correction means for suppressing the circulating current Δi is provided for one of the unit inverters. However, the method of suppressing the circulating current Δi using the unit inverter 2b is the same as in the first embodiment.

Therefore, unit inverter 2a follows the voltage command generated from voltage command generating means 19, and unit inverter 2b outputs a voltage to suppress circulating current Δi to zero, as in the first embodiment. If the circulating current Δi can be suppressed, the unit inverter 2b will eventually become
9 will follow the voltage command generated. That is, the two unit inverters have a master-slave relationship with respect to the voltage command generated from the voltage command generating means 19.

Further, when the average of the output voltages of the unit inverters 2a and 2b, that is, the output of the parallel multiplex inverter device is considered, the result is exactly the same. Are not the same when considering the average of the output voltages of the unit inverters 2a and 2b, that is, the output of the parallel multiplex inverter device.

However, the parallel multiplex inverter shown in FIG. 8 feeds back the output current, and the voltage command generation means 19 outputs the voltage command so that the output current matches the current command of the current command generation means 17. Has become. Therefore, the output of the parallel multiplex inverter device is not adversely affected.

More effectively, although not shown, the current control response of the output current controller of the parallel multiplex inverter device inside the voltage command generating means 19 is applied to the inside of the voltage error calculating means 13a, 13b, 13c not shown. It is preferable to design the current control response of a circulating current controller to be low.

Embodiment 4 FIG. FIG. 9 is a main circuit showing an embodiment of a parallel multiplex inverter device according to an embodiment of the fourth aspect of the present invention, and FIG. 10 is a configuration diagram including its control. Here, the number of unit inverters connected in parallel is N, k is an integer from 1 to N, and the unit inverter of N = k is INV
(K), and the output current of each phase is i _uk , i _vk , i
_wk .

Next, the operation will be described. The unit inverter used as a reference is set to INV (1), and is called a main unit inverter. Other unit inverters are referred to as subordinate unit inverters. First, the U-phase output current i _{uk of} each unit inverter
And a deviation Δi _uk between the U-phase output current value i _u1 of the main unit inverter INV (1) and the U-phase output current value i _uk of the slave unit inverters excluding the unit inverter INV (1) is not shown. Calculate all by means.

The U-phase output current i _u of the parallel multiplex inverter device is obtained by Δi _uk . The phase current and the deviation current can be similarly obtained for the other V phases and W phases. This deviation current is essentially the same as the circulating current, but when a plurality of unit inverters are connected in parallel, it is extremely difficult to specify the return path of the circulating current. It is replaced by the deviation current from the current.

Here, the parallel multiplexed inverter device has the same voltage as that of the second and third embodiments so that the deviation between each phase output current and each phase current command becomes zero, that is, the output current matches the current command. A voltage command is output from the command generating means 19.

When the deviation current approaches zero using the method described in the third embodiment, the phase output currents of all the slave unit inverters become equal to those of the reference main unit inverter.
At that time, when the sum of the output currents of the respective phases of the unit inverters matches the respective phase current commands, each unit inverter equally shares the load current. By using this method, even when the number of unit inverters connected in parallel is arbitrarily selected, the load current can be controlled without breaking the load sharing of each unit inverter.

Embodiment 5 FIG. Although the output form of the current command generating means 17 of the parallel multiplex inverter device in the above-described second, third, and fourth embodiments is a three-phase current command,
When the AC motor is driven, a torque current command and an excitation current command may be used. In this case, a torque converter and an excitation current are calculated from the three-phase output current of the parallel multiplex inverter device using a coordinate converter, and a deviation of each current is obtained by a subtractor. Will do.

Embodiment 6 FIG. Further, when an AC motor having two sets of polyphase windings is driven by the parallel multiplex inverter device in the above-described embodiment, mutual inductance is generated due to magnetic coupling between the polyphase windings, so that two unit inverters are used. No reactor is required to connect. In this case, an unbalanced current flows instead of the circulating current. Since the unbalanced current can be handled in the same manner as the circulating current in the above-described embodiment, the unbalanced current is suppressed, and the AC having the multi-phase winding is provided. It is possible to balance the current flowing through each phase winding of the motor.

Embodiment 7 FIG. Although the three-level inverter shown in FIG. 13 is used as the half bridge constituting the unit inverter in the above-described embodiment, the present invention is not limited to this configuration. Can be applied as it is. It is not necessary to limit the unit inverter to the two-level inverter and the three-level inverter shown in FIGS. 12 and 13, and it is needless to say that a multi-level inverter can be applied.
The reactors shown in FIGS. 2 and 10 are coupled reactors.
A tor or an air-core reactor may be used.

[0083]

As described above, according to the first aspect of the present invention, at least three voltage vectors forming each vertex of a region formed by connecting three adjacent vertices of the voltage vector are selected. , A voltage vector selecting means for determining an output order within a PWM cycle, a voltage command generating means for outputting a voltage command in the form of a voltage vector,
Area determination means for determining an area where the voltage command is located for each cycle; and duration calculation means for calculating the duration of the voltage vector within the PWM cycle so that the output voltage matches the voltage command. A duration correction means for correcting the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of each unit inverter; and the unit inverter based on an output from the duration correction means or the duration calculation means. Switching signal generating means for generating a control signal for controlling the switching element, and wherein the voltage vector selecting means has an output means for outputting a voltage vector based on the output from the duration correcting means and the area determining means. Therefore, when driven by the voltage vector PWM method, the circulating current flowing between the unit inverters Can be suppressed, downsizing of the reactor for connecting the unit inverters, the apparatus can be downsized. Further, there is an effect that a loss of the reactor due to the circulating current can be reduced, and a parallel multiple inverter device that can achieve high efficiency of the device can be obtained.

According to the second aspect of the present invention, at least three voltage vectors forming each vertex of a region formed by connecting three adjacent vertexes of the voltage vector are selected, and the output within the PWM cycle is selected. Voltage vector selecting means for determining the order, current command generating means for outputting a current command signal, voltage command generating means for outputting a voltage command in the form of a voltage vector based on the current command and the output current of the parallel multiplex inverter device, Area determining means for determining an area where the voltage command is located for each PWM cycle; and duration calculation for calculating the duration of the voltage vector within the PWM cycle so that the output voltage matches the voltage command. Means for correcting the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of each unit inverter. And a switching signal generating means for generating a control signal for controlling a switching element of the unit inverter based on outputs from the duration correcting means and the area determining means, wherein the voltage vector selecting means includes the duration correcting means and the area. Since the output means for outputting a voltage vector to the unit inverter based on the output from the determination means is provided, the circulating current flowing between the unit inverters when the load current is feedback-controlled and driven by the voltage vector PWM method. Therefore, the size of the reactor connected to the unit inverter can be reduced, the loss of the reactor due to the circulating current can be reduced, and the efficiency of the device can be improved. Further, the load sharing of the unit inverters can be equalized, and there is an effect that a parallel multiplex inverter device capable of downsizing the device can be obtained.

According to the third aspect of the present invention, one of the voltage vector selecting means outputs a voltage vector to one of the unit inverters based on the output from the duration correcting means and the area judging means. Since the other of the selection units has an output unit that outputs a voltage vector to the other of the unit inverters based on the output from the duration calculation unit and the area determination unit,
Further, there is an effect that a parallel multiple inverter device capable of shortening the operation time required for suppressing the circulating current can be obtained.

According to the fourth aspect of the present invention, the area determined from the voltage command by the area determining means and the voltage vector selected by the current generating means and the voltage vector selecting means for a plurality of unit inverters connected in parallel. Since the configuration is driven based on the output sequence and the voltage vector duration obtained by the duration correction means, the load current is feedback-controlled and the circulating current flowing between the unit inverters when driven by the voltage vector PWM method. And the load current can be shared equally to follow the voltage command. Accordingly, there is an effect that a parallel multiplex inverter device capable of easily increasing the output current capacity can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a parallel multiplex inverter device according to an embodiment of the present invention.

FIG. 2 is a main circuit configuration diagram of a parallel multiplex inverter device applied to the embodiment of FIG. 1;

FIG. 3 is a diagram showing a voltage command vector of the parallel multiplex inverter device of FIG. 1;

FIG. 4 is a diagram showing distribution of voltage vector durations and an output voltage waveform of the parallel multiplex inverter device of FIG. 1;

FIG. 5 is a diagram showing a circulating current vector of the parallel multiplex inverter device of FIG. 1;

FIG. 6 is a diagram showing an output voltage waveform of the parallel multiplex inverter device of FIG. 1;

FIG. 7 is a configuration diagram of a parallel multiplex inverter device according to one embodiment of the second invention.

FIG. 8 is a configuration diagram of a parallel multiplex inverter device according to an embodiment of the third invention.

FIG. 9 is a block diagram of a parallel multiplex inverter device according to an embodiment of the present invention.

FIG. 10 is a main circuit configuration diagram of a parallel multiplex inverter device applied to an embodiment of the present invention.

FIG. 11 is a main circuit configuration diagram of a conventional parallel multiplex inverter device.

FIG. 12 is a configuration diagram of a two-level inverter.

FIG. 13 is a configuration diagram of a three-level inverter.

FIG. 14 is a diagram showing a path through which a circulating current of the parallel multiple inverter flows.

FIG. 15 is a diagram showing a point extinguishing pattern of a self-extinguishing type semiconductor element constituting a three-level inverter.

FIG. 16 is a main circuit configuration diagram of a three-phase two-level inverter.

FIG. 17 is a diagram showing a voltage vector of a two-level inverter.

FIG. 18 is a diagram showing a voltage vector of a three-level inverter.

FIG. 19 is a diagram showing an output voltage waveform for each unit inverter.

[Explanation of symbols]

2a, 2b Unit inverter 10 Voltage command generation means (voltage command generation means) 11 Area determination means 12 Duration calculation means 13a, 13b, 13c Voltage error calculation means (output means) 14a, 14b Duration correction means 15a, 15b Voltage vector Selection means 16a, 16b Switching signal creation means 17 Current command generation means

Claims (4)

(57) [Claims] 1. In a parallel multiple inverter device obtained by connecting two unit inverters in parallel, each vertex of a region formed by connecting three adjacent vertexes of a voltage vector according to a switching state of the parallel multiple inverter device. A voltage vector selecting means for selecting at least three of said voltage vectors forming the following and determining an output order within a PWM cycle, and a voltage command for outputting a voltage command in the form of a voltage vector based on an output from said voltage vector selecting means. Generating means, area determining means for determining an area in which the voltage command is located for each PWM cycle by the voltage command, such that the output voltage matches the voltage command in the area determined by the area determining means. A duration calculating means for calculating a duration of the voltage vector within the PWM cycle; A duration correction means for correcting the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of the inverter; and a switching element of the unit inverter based on an output from the duration correction means or the duration calculation means. Switching signal generating means for generating a control signal to be controlled, wherein the voltage vector selecting means includes an output means for outputting a voltage vector to the unit inverter by an output from the duration correcting means and the area determining means. Inverter device. 2. In a parallel multiplex inverter device obtained by connecting two unit inverters in parallel, each vertex of a region formed by connecting three adjacent vertexes of a voltage vector according to a switching state of the parallel multiplex inverter device. A voltage vector selecting means for selecting at least three of said voltage vectors forming an output order within a PWM cycle, a current command generating means for outputting a current command signal for said parallel multiplex inverter device, and said current command Voltage command generating means for outputting a voltage command in the form of a voltage vector based on a current command from the generating means and an output current of the parallel multiplex inverter device;
Area determining means for determining an area in which the voltage command is located for each cycle; and the voltage vector in the PWM cycle such that the output voltage matches the voltage command in the area determined by the area determining means. Duration calculation means for calculating a duration, duration correction means for correcting the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of each unit inverter, and the duration correction means and area. Switching signal generating means for generating a control signal for controlling a switching element of the unit inverter based on an output from the determining means, wherein the voltage vector selecting means converts a voltage vector by an output from the duration correcting means and the area determining means. A parallel multiplex inverter device comprising output means for outputting to the unit inverter. 3. In a parallel multiplex inverter device obtained by connecting two unit inverters in parallel, each vertex of a region formed by connecting three adjacent vertexes of a voltage vector according to a switching state of the parallel multiplex inverter device. A voltage vector selecting means for selecting at least three of said voltage vectors forming an output order within a PWM cycle, a current command generating means for outputting a current command signal for said parallel multiplex inverter device, and said current command Voltage command generating means for outputting a voltage command in the form of a voltage vector based on a current command from the generating means and an output current of the parallel multiplex inverter device;
Area determining means for determining an area in which the voltage command is located for each cycle; and the voltage vector in the PWM cycle such that the output voltage matches the voltage command in the area determined by the area determining means. Duration calculation means for calculating a duration, duration correction means for correcting the duration of the voltage vector so as to reduce the deviation of the output current of the same phase of each unit inverter, and the duration correction means or the duration. Switching signal generating means for generating a control signal for controlling the switching element of the unit inverter based on outputs from the time calculating means and the area determining means, wherein one of the voltage vector selecting means is the duration correcting means and the area determining means A voltage vector is output to one of the unit inverters by an output from
A parallel multiplex inverter device comprising an output means for outputting a voltage vector to the other of the unit inverters based on an output from the duration calculating means and an area determining means. 4. In a parallel multiplex inverter device obtained by connecting a plurality of unit inverters in parallel, each vertex of a region formed by connecting three adjacent vertexes of a voltage vector according to a switching state of the parallel multiplex inverter device. A voltage vector selecting means for selecting at least three of said voltage vectors forming an output order within a PWM cycle, a current command generating means for outputting a current command signal for said parallel multiplex inverter device, and said current command Voltage command generating means for outputting a voltage command in the form of a voltage vector based on a current command from the generating means and an output current of the parallel multiplex inverter device;
Area determining means for determining an area in which the voltage command is located for each cycle; and the voltage vector in the PWM cycle such that the output voltage matches the voltage command in the area determined by the area determining means. Duration calculation means for calculating the duration, deviation current detection means for respectively detecting the deviation current between the output current of one main unit inverter as a reference and the output current of another slave unit inverter, and the deviation current detection A duration correction means for correcting the duration of the voltage vector so as to reduce the deviation current from the means, and a switching element of the unit inverter based on an output from the duration correction means or the duration calculation means and the area determination means. Switching signal generation means for generating a control signal to be controlled, wherein the voltage vector selection means of the main unit inverter is The voltage vector is output to the main unit inverter by the output from the duration calculating means and the area determining means, and the voltage vector selecting means of the dependent inverter is configured to convert the voltage vector by the output from the duration correcting means and the area determining means. A parallel multiplex inverter device having output means for outputting to a dependent unit inverter.