DE102007063434A1 - Inverter system and control method - Google Patents

Abstract

The application relates to an inverter arrangement with a DC voltage terminal to which a DC voltage can be applied, a load terminal for connecting a load, a plurality of inverters connected in parallel, whose inputs are coupled together with the DC voltage terminal and its outputs via one or more inductors together with the load terminal, and a control device for controlling the inverters in dependence on a default vector of a higher-level control or regulation unit. The control device is designed to control the inverters in such a way that the output voltage at the load connection assumes a specific state from a number of different states depending on the default vector of a higher-level control or regulation unit, wherein at least some states of the output voltage are determined by a number of different combinations of operating states Inverters can be achieved and the controller selects for each state of the output voltage that combination of operating states of the inverter from the number of different combinations, in which a desired criterion is met as optimally as possible.

Description

The The invention relates to a PWM (Pulse Width Modulation) control method for parallel-connected self-commutated voltage source inverters, which can also be operated as a rectifier or active filter. In this case, the voltage source inverter can different topologies such. B. 2-level or 3-level NPC (Neutral Point Clamped). The coupling of the voltage source inverter via inductive components such. As reactors, transformers or winding strands of electrical machines.

The Achieving high output in the range of electrical Drives or filters can be done through different approaches be achieved.

Here are many variations of Multilevel power converters used. There are topologies such as "Series Connected H-Bridge", 3-level NPC, FLC and hybrid methods, as described in "Multilevel Inverter by Cascading Industrial VSI", Remus Teodorescu, Frede Blaabjerg, et al., IEEE Transactions on Industrial Electronics, 08/2002 and Krug, D. Malinowski, M. Bernet, S., Industry Applications Conference, 2004. 39th IAS Annual Meeting., Conference Record 2004 IEEE. "Design and Comparison of Medium Voltage Multi-Level Converters for Industry Applications" are described. Basically, by series connection of cells or components with respect to the rated voltage of the components increased output voltage and thus achieved performance.

In "Multilevel Inverter by Cascading Industrial VSI", Remus Teodorescu, Frede Blaabjerg, et al., IEEE Transactions on Industrial Electronics, 08/2002 . "Optimal Pulse-Width Modulation for Three-Level Inverters", Thomas Bruckner, Donald Grahame Holmes, IEEE Transactions on Power Electronics 01/2005 . Pulsewidth Modulation for Electronic Power Conversion ", Joachim Holtz, Proceeding of the IEEE, Vol. 82, 08/1994 and "Pulse Width Modulation for Power Converters: Principles and Practice", Holmes, DG Lipo, TA, IEEE Press Series on Power Engineering, Wiley-IEEE Press, 2003 carrier-based modulation methods and also space-vector modulation methods as well as their implementation possibilities for these topologies are described.

Next the aforementioned methods, which are based on series circuit concepts, is the parallel connection of individual inverters, below Also called inverter or voltage inverter, in different Publications described.

The basic structure of such a parallel connection is in 1 demonstrated.

A DC intermediate circuit (ZK) feeds two voltage inverters (WR1 and WR2) whose outputs are in each case connected to the equivalent phase of the other inverter via inductors (L _{U, 1} ; L _{V, 1} ; L _{W, 1} , L _{U, 2} ; L _{V, 2} , L _{W, 2} ) are connected. The midpoints between the chokes (U, V, W) are connected to the load.

Each inverter consists of 3 half-bridges, hereafter also called bridge branches or phase leg. Each half bridge, as in 12 is composed of 2 self-extinguishing semiconductor switches (S1, S2), hereinafter also called switch. Insulated gate bipolar transistors (IGBT), metal oxide semiconductor field effect transistors (MOSFET), gate turn-off thyristors (GTO), integrated gate commutated thyristors (IGCT) and bipolar transistors are used. Freewheeling diodes (D1, D2), also referred to below as inverse diodes, are connected in parallel with the semiconductor switches.

On Reason for the different switching behavior of the individual semiconductor switches and the impedance differences in the branches occurs during operation to the current flow between the half-bridges of the individual inverters. This is referred to below as a circular current or as a cross-flow designated. The circulating current generates increased losses and does not contribute to the load current.

In DE 41 11 734 C1 a method is described which solves these problems. A control unit specifies potential adjustment commands, also referred to as switching vectors or switching states, to both inverters. An independent circulating current limitation causes the potential setting commands for a bridge branch to be output inverted when the circulating current has exceeded a limit value. Only when the circulating current has fallen below a reduced limit, the actual potential adjustment command is issued again. This regulation is independent of the actual control unit, which specifies the potential adjustment commands. In this application, both parallel inverters are always supplied with the same setpoint.

In DE 38 16 444 C2 a method is described, which solves the Kreisstromproblematik such that a correction signal for each individual inverter is added to a common phase total voltage setpoint, so that the circulating current is reduced.

In EP 0 813 292 A2 describes a configuration of 3 or n parallel inverters, in which the 3 or n inverters are connected via inductors. A PWM generator outputs a PWM signal for each phase. Depending on the circulating current, the change of the level of the PWM signal is delayed. Thus, a balancing of the cross-flow can be achieved. A conscious generation of a multilevel output voltage is not performed here.

In DE 43 41 868 C2 describes a parallel connection of 2 inverters, which can be implemented as 2-level or 3-level NPC. Here, a space-vector-based modulation method is used. A duration calculation unit calculates the duration of the switching states, which are the same for both inverters. Depending on the size of the circulating currents, a time-duration correction device changes the setpoint times for each individual inverter in such a way that the deviation of the output currents from one another is reduced. Only the circulating currents occurring due to different switching behavior and different impedances are reduced. A multilevel output voltage should not be generated.

The range of such solutions, as in DE 41 11 734 C1 . EP 0 813 292 A2 and DE 43 41 868 C2 are described, shows the first occurring carrier tape at the switching frequency.

Of the Use of parallel-connected inverters offers the possibility to improve the output spectrum, not by both inverters spend the same tension at any time but consciously different be controlled. However, this increases the problem the Kreisstromentstehung.

This is z. In JP 60098875 shown. In a configuration with n inverters connected in parallel, it is proposed here to shift the carrier signals of the modulators of the individual alternating funnels by a factor of 360 ° / n in each case and thus to virtually increase the switching frequency by the factor n. The problem of the circulating currents is not considered here.

In "An Interleaved Active Power Filter with Reduced Size of Passive Components", L. Asiminoaei, et al., IEEE 2006 shows the parallel connection of 2 voltage source inverters for an active filter in which the carrier signals are shifted by 180 °. To reduce the circulating currents, the use of common mode chokes is proposed.

In EP 0 600 635 B1 A method of modulating a parallel inverter arrangement is shown in which the carrier signals for each individual inverter are changed in dependence on the polarity of the setpoint signal (phase setpoint voltage). A method for minimizing the circulating currents in connection with the illustrated modulation method is not specified.

In EP 0 697 763 B1 A method based on 2-level space vector modulation is presented. The 2-level space-demodulator calculates the corresponding switching times for a given nominal voltage vector and selects the switching vectors to be used. A "vector exchange unit" outputs the switching vectors in different order to the PWM units of the individual inverters, the first inverter receives the vectors in order (V _i , V _j , V ₇ , V _j , V _i , V ₀ ), the second one Inverters in the order (V ₀ , V _i , V _j , V ₇ , V _j , V _i ) .This ensures that the switching states of the two inverters are temporarily different and thus creates an additional level in the output voltage Output spectrum is better than with synchronous operation of the two inverters However, in this method, the distortion of the output voltage by harmonics of the fundamental wave is greater than in a 3-level inverter with 3-level space vector modulator, since the latter can be ensured that only switching states of an adjacent area to respective setpoint voltage vector is used to represent this setpoint voltage vector (within a short period of time) sections, the phase-phase output voltage changes between three voltage levels). To limit the circulating currents, the order of the switching vectors, in which they are given to the PWM units of the inverters, can be reversed, so as to counteract the circulating currents.

The object of the invention is to provide a method and a circuit arrangement which makes it possible to operate parallel inverters in such a way that the output voltage spectrum is significantly improved compared to the methods of the prior art and at the same time the circulating currents are regulated, wherein an increase in the switching frequency, which would cause additional losses is waived. The improved output spectrum makes it possible to reduce the passive filtering effort (chokes, capacitors, transformers). In connection with the application in the field of electric drives (motors, generators) the reduced harmonic content of the voltage leads to lower current ripple and thus to lower torque ripple, which is characterized by a lower load and lower losses in the machine.

in the Application of the grid feed, z. B. of wind turbines or Active front-ends of industrial converters, the Network standards with respect to the harmonic content with significant reduced filter effort can be achieved.

simultaneously the method can be used for high-speed drives, where systemically high output fundamental frequencies needed become. By means of the new process can also at low Switching frequencies of individual inverters and high output frequency low THD (Total Harmonic Distortion) values are achieved.

It a method is given which allows n-parallel switched self-commutated inverters with a multilevel modulation or control methods and thus the advantages of these multilevel methods exploits, as there would be, for example, an optimized output spectrum and a lower THD, (so modulate that, on the one hand, the output voltage a multilevel characteristic and thus an optimized spectrum and at the same time both the currents of the individual To invert inverters as well as the occurring circulating currents to limit or minimize.

there If the inverters connected in parallel are not individually modulated, but it becomes a common multilevel modulator or multilevel controller, hereinafter referred to as modulator used. Downstream of this is a switching state selector which is as desired Criteria (current balancing, circulating current minimization, maximum current) from the possible redundant switching states who chooses the optimization criteria best fulfilled. Furthermore, the selection of the redundant switching states are carried out in such a way that a desired distribution of the switching losses is achieved.

According to the invention This object is achieved by an inverter arrangement of the aforementioned type with several parallel connected, of one or more inverter half-bridges formed inverters, wherein the inverter half-bridges each having two or more switching elements, with which DC pulses with the timing of the discrete switching states the switching elements dependent polarity, pulse width and possibly amplitude to an output of an inverter half-bridge to switch. Here are the corresponding outputs the inverter via one or more inductors connected with each other. The inverter assembly also has a modulator for determining pulse widths, polarities and possibly amplitudes of the DC voltage pulses for approximation to an output AC voltage desired, especially sinusoidal Form, and a switch state selector least mediate Driving the switching elements, which is designed such that he under different regarding the approach to one desired output AC voltage for a possible date and with respect to the current output voltage equivalent switching state combinations of Switching the one switching state combination determines at an optimizing criterion is optimally fulfilled.

A possible inverter arrangement is characterized from that the modulator is a pulse width modulator, which after the Sine-triangular method works. In this case, there is the inverter arrangement, for example from 2-level inverters, where a number of n 2-level inverters are switched in parallel GE and the inverter arrangement as (n + 1) level Pulse width modulator in sine-triangular method with a number of n triangular carrier signals works.

In another preferred embodiment of the invention the modulator is a pulse width modulator that is designed to perform a multi-level space vector modulation. there For example, the inverter arrangement is also made 2-level inverters, again with a number of n inverters are connected in parallel and the inverter arrangement as (n + 1) level Pulse width modulator operates in Mehrlevelraumzeigermodulationsverfahren.

The Switching elements of the inverter arrangement are preferably insulated gate Bipolar transistors or integrated gate commutated thyristors.

Preferably the switching state selector comprises current measuring devices for the measurement currents at the outputs of the inverters up and is trained, the selection of operating conditions depending on the measured values of the currents at the outputs of the inverters. Furthermore is the switching state selector is formed, depending on the combination operating currents of the inverters adjusting circulating currents, Phase currents or phase and phase currents between to predict individual inverters.

In another preferred embodiment of the invention the switching state selector determines the selection of the operating states depending on a system model calculated Values of the currents at the outputs of the inverters.

Of Furthermore, the switching state selector is designed as an optimization criterion to perform a minimization of the phase currents. In this case, the switching state selector preferably has one for each phase Unit for assigning the phase output state to the phase switching state the respective phase and is formed by means of a determined the current measuring devices and to the unit for assignment of the phase output state to the phase switching state of the respective one Phase output control value actual value vector to perform a minimization of the phase currents.

In a further preferred embodiment of the invention the switching state selector is designed to minimize the Circulating currents as an optimization criterion. In this case, the switching state selector preferably has one for each phase Calculation unit for calculating one for a circulating current control suitable control value actual value vector and a unit associated with the output of the calculation unit for assignment of the phase output state to the phase switching state of the respective phase on and is formed by means of one of the current measuring devices determined and output to the calculation unit first Regelungsgrößenistwertvektors and one from the calculation unit to the unit for assignment of the phase output state to the phase switching state of the respective one Phase output calculated second control value actual value vector to perform a minimization of the circulating currents.

In another preferred embodiment of the invention the switching state selector is designed, a common mode current control as an optimization criterion. It has the Switching state selector per phase preferably a calculation unit to calculate one suitable for common mode current control Control value actual value vector and one with the Output of the calculation unit connected unit for assignment of the phase output state to the phase switching state of the respective one Phase up and is formed by means of one of the current measuring devices determined and output to the calculation unit first Regelungsgrößenistwertvektors and one from the calculation unit to the unit for assignment of the phase output state to the phase switching state of the respective one Phase output calculated second control value actual value vector to perform a common mode current control.

In Yet another preferred embodiment of the invention the switching state selector is designed to select a selection of switching state combinations on the basis of several optimization criteria such as a minimization of the phase currents, a minimization of the circulating currents and a common mode current control perform.

there For example, the switching state selector preferably has one calculation unit per phase for calculating a suitable for a circulating current control Control quantity actual value vector, a calculation unit for Calculation of one suitable for common mode current control Control value actual value vector, a unit for Setting the weighting of the individual optimization criteria such as Minimization of the phase currents, minimization of the circulating currents and common mode current control, a calculation unit for calculation the weighted sum of all control value actual value vectors and a phase output state allocation unit Phase switching state of the respective phase.

The current measuring devices of the switching state selector are connected to the inputs of all calculation units. The unit for adjusting the sensitivity of the individual optimization criteria and the outputs of the calculation unit for calculating a Kreisstromregelung suitable Regelungsististwertvektors and the calculation unit for calculating a suitable for a common mode current control Regelgrößenistwertvektors are connected to the input of the calculation unit for calculating the weighted sum of all Regelgrößenbestwertvektoren. The output of the weighted sum calculation unit of all control value actual value vectors is in turn connected to the unit for assigning the phase output state to the phase switching state of the respective phase.

Of the Switching state selector is preferably formed by means of one of the current measuring devices determined and to all calculation units output Stromwertwertvektor and one of the calculation unit for calculating the weighted sum of all control value actual value vectors to the unit for assigning the phase output state to the phase switching state of the respective phase, calculated weighted control value actual value vector a selection of switching state combinations based on the above Perform optimization criteria.

Of Furthermore, the switching state selector is preferably formed, a limit monitor for one or more Perform optimization criteria. In this case, the switching state selector compared to the aforementioned embodiments each Phase preferably additionally a unit for the determination the magnitude value of the to the unit for the assignment of the phase output state control value actual value vector outputted to the phase switching state of each phase, one with the unit for determining the absolute value of the control value actual value vector associated limit comparator for comparing the Amount value of the control value actual value vector with a limit value output to the limit comparator and a phase switching state change comparator connected to the limit comparator for the comparison of the magnitude value of the control value actual value vector if the limit is exceeded with one of a multi-level modulator obtained phase switching state change value and for the output of a phase switching state change signal if the limit value is exceeded, the unit is assigned of the phase output state to the phase switching state of the respective one Phase up.

Of the Switching state selector is designed, a limit value monitoring for one or more optimization criteria and when the limit value is exceeded by means of the unit for Assignment of the phase output state to the phase switching state the respective phase to make a new phase switching state calculation and as a result output a phase switching state change.

Preferably the inverter arrangement is characterized in that the Modulator is formed, a carrier-based pulse width modulation method such carry out that a number of according to the number the parallel-connected inverter of carrier signals be linked to a reference signal (setpoint), that the number of possible initial states each phase is 1 greater than the number of parallel switched inverter multiplied by the reduced by 1 Number of levels of the individual inverters.

at an alternative embodiment, the modulator is designed to process precalculated pulse patterns, the number of possible output states per phase by 1 greater can be the number of inverters connected in parallel multiplied by the reduced by 1 number of levels of individual inverters.

In a still further preferred embodiment of the invention the inverter arrangement is characterized in that the Inverter arrangement two or more inverters with multilevel topology having a common modulator.

The Invention will now be more apparent with reference to the accompanying drawings be explained. The drawings show in:

1 : Basic circuit of a basic structure of a parallel connection of two inverters,

2 : general structure of an inverter arrangement according to the invention,

2a alternative structure of an inverter arrangement according to the invention

3 : general arrangement of n parallel-connected inverters,

4 : Block diagram of an arrangement of n parallel-connected inverters,

5 : Chokes as inductive coupling units at the bridge outputs 4 .

6 : Common mode chokes as inductive coupling units at the bridge outputs 4 .

7 : Series connection of choke and common mode choke as inductive coupling units at the bridge outputs 4 .

8th : Chokes located on a common core as inductive coupling units at the bridge outputs 4 .

8a an equivalent arrangement of current-compensated 2-phase chokes for throttle arrangement in 8th

9 : basic design of an inductive coupling unit according to 8th .

9a another design of an inductive coupling unit after 8th

9b an improved design of an inductive coupling unit after 8th

10 : Circuit diagram of a 2-level bridge branch (half bridge),

11 : For example, representation of the output spectrum and some output variables of an arrangement with 4 parallel 2-level inverters with a 2-level sine-delta modulato (prior art),

12 : For example, representation of the output spectrum and some output sizes of an arrangement with 4 parallel 2-level inverters with a 2-level sine-delta-modulator with phase-shifted carrier signals (prior art),

13 : Block diagram of a 3-level bridge branch in NPC topology,

14 : Block diagram of four parallel-connected 2-level inverters as a 5-level modulator for three phases,

15 : Table of phase switching states of a 5-level modulator after 14 .

16a : Representation of the possible switching states of a bridge branch of a 2-level inverter,

16b : Example of a switching state of a 3-phase 2-level inverter,

16c : Example of a switching state of four parallel-connected 3-phase 2-level inverters,

17a : Representation of the phase state 0 of a 5-level pulse width modulator, which consists of four parallel 2-level inverters,

17b : Representation of the phase state 1 of a 5-level pulse width modulator, which consists of four parallel 2-level inverters,

17c : Representation of the phase state 2 of a 5-level pulse width modulator, which consists of four parallel 2-level inverters,

17d : Representation of the phase state 3 of a 5-level pulse width modulator, which consists of four parallel 2-level inverters,

17e : Representation of the phase state 4 of a 5-level pulse width modulator, which consists of four parallel 2-level inverters,

18 : Representation of the output voltage of a phase as a space vector in a space vector hexagon of a 5-level pulse width modulator after the 14 and 15 operating according to the space vector modulation method,

19 : Example of a 5-level pulse width modulator consisting of four parallel-connected 2-level inverters that works according to the sine-triangular method,

20 : Representation of the current flow in a 5-level pulse width modulator 19 .

21 1 is a block diagram of a switching state selector with phase current limiting control;

22 1 is a block diagram of a switching state selector with circulating current control,

23 Exemplary illustration of the output spectra of a phase of a 5-level pulse width modulator operating according to the space vector modulation method with a circulating current control according to FIG 22 .

24 1 is a block diagram of a switching state selector with common mode current regulation;

25 1 is a block diagram of a switching state selector with simultaneous circulating current regulation, phase current limiting regulation and circulating current regulation;

26 : Block diagram of a switching state selector with limit value monitoring and simultaneous circulating current control,

27 Exemplary representation of the output spectra of a phase of a 5-level pulse width modulator operating according to the space vector modulation method with limit value monitoring and simultaneous circulating current control according to FIG 26 .

28 : Basic circuit of a two-phase topology with a 3-level modulator.

In 2 shows the general structure of the drive of the inverter according to the invention.

From a superimposed control or control becomes a desired voltage vector U, consisting of magnitude and phase or α, β coordinates specified. The k-level modulator M generates output signals for each of the 3 phases. These output signals correspond to discrete phase center voltages with k levels and are processed by a switching state selector SZS. The k-level modulator M gives a discrete desired voltage, which k levels, for each of the 3 phases to the switching state selector in front. In this case, the modulator M is constructed as a multilevel modulator. The output states are chosen such that the target voltage vector to be achieved as accurately as possible is shown.

Of the Switching state selector SZS gets from the current measuring devices SM1 to SMn are the measured values of the output currents of the individual m-level inverter. Depending on the measured Streaming he chooses for the desired Voltage state that redundant switching state, the / the met the desired optimization criteria.

In order to is achieved that the output voltage of the predetermined by the modulator M. Stress follows and at the same time the existing degrees of freedom (redun dante Switching states) to achieve the optimization criterion be used. Thus, the circulating current can be regulated without that changes the output voltage for it.

In 2a the general structure of the control of the inverter is shown according to the invention, when the higher-level control instead of a desired voltage vector, a k-level switching state vector specifies. In this structure no additional modulator is needed and the k-level switching states are processed directly by the switching state selector.

A general arrangement of n parallel connected inverters is in 3 shown. A number of n inverters (n ≥ 2) WR 1 to WR n are connected on the input side to a common intermediate circuit (C1 .. C4). This DC link represents a voltage source and can consist of any combination of capacities. The output of each inverter is in each case connected to an inductive coupling unit (L ₁ ... L _n ). The parallel connection of the outputs of the coupling units (L ₁ ... L _n ) merges the currents of the individual power converters and forwards them to the load.

The system concerning the invention is in 4 shown. A number of n changes as well Richter (n ≥ 2) WR 1 to WR n is connected on the input side to a common DC link (C1 .. C4). This DC link represents a voltage source and can consist of any combination of capacities. It is irrelevant for the method whether it is a distributed to the individual inverters or a central DC link. An inductive coupling unit L combines the currents of the individual power converters and forwards them to the load (load).

The Output voltage of a bridge branch may be in relation to the center of the intermediate circuit a number m of discrete States. From the combination of n parallel Inverters result k = n * (m-1) + 1 different output voltage levels relative to the DC link center. These output voltage levels can be different Combinations of the switching states of the individual bridge branches be achieved. So there is an output voltage level different redundant switching states. Designated here Switching states the totality of all states of the switches involved in the inverters.

In the 4 illustrated inductive coupling unit L can, for. B. as in the 5 . 6 . 7 and 8th be executed. All implementation options have the common feature that the currents of one phase of the n parallel-connected inverters can be combined and passed on as a summation current to the load.

In 5 In each case an inductance L _i (i = 1 ... n) is connected to the bridge outputs of the inverters. They act both to limit the increase of the circular current and to smooth the output current. It thus damps symmetric as well as asymmetrical disturbances. The inductance can be designed as 3 single-phase chokes or as a three-phase choke per inverter.

In 6 behind each of the n inverters a common mode choke is switched. It is characterized in that it only acts for asymmetric interference currents, to which the circulating current occurring belongs. It can be designed as a toroidal core choke, which is wound with 3 coils in the same direction.

In 7 is the combination of throttles, that of the 5 and 6 correspond, shown. Here, the circulating currents are damped by both throttle types.

In 8th an inductive coupling unit is shown which consists of 3 subunits (L _U , L _V , L _W ) in which the currents of one phase of all n inverters are coupled by a choke. It acts as a differential mode throttle and thus only damps the circulating currents. This has the advantage that at the throttle no voltage drop is generated by the load current. The core of the choke must also only carry the magnetic flux generated by the circulating current.

In 8b is an equivalent in their effect arrangement for inductive coupling unit in 8th shown, in which in the output phases of the n inverters each 2-phase current-compensated reactors are connected, the compensation windings of the chokes of each phase are connected so that an output current compensation is achieved and the inductance of the chokes only acts on the circulating current components of the output current of the inverter ,

In 9 is a possible embodiment of throttles according to 8th for 4 inverters connected in parallel.

In 9a is another embodiment of throttles according to 8th for 4 inverters connected in parallel.

In 9b is an improved embodiment of throttles according to 8th for 4 inverters connected in parallel, in which the symmetrical structure of the inductor causes an equal coupling of the individual windings to one another. For a general arrangement with n inverters connected in parallel, the inductor with n windings is symmetrically star-shaped.

Instead of The reactors can also be used to couple the transformers individual inverters are used.

In 10 is a well-known to those skilled 2-level bridge branch (half bridge) shown. Two semiconductor switches (IGBT, IGCT, MOFET, bipolar transistor) are connected in series and connected to a voltage U _DC . Antiparallel to the semiconductor switches is in each case an inverse diode (D1, D2). The one with Telepoint between the two semiconductor switches is the output (A) of the bridge branches In 11 output current, voltage, phase and circulating current as well as voltage spectrum of a parallel connection of 4 inverters which are controlled by a 2-level sine-delta modulator. These are 3-phase inverters.

In 12 the same sizes are shown, except that 2-level sine-wave modulators with mutually shifted carrier signals were used to control the inverters.

In 13 is a well-known 3-level bridge branch of the well-known NPC topology shown. Between the positive DC voltage connection (+ U _DC / 2) and the output (A), two semiconductor switches S1 and S2 are arranged, in each case parallel to the switch S1, the diode D1 in anti-parallel and parallel to the switch S2, the diode D2 are connected in anti-parallel. Between the negative DC voltage connection (-U _DC / 2) and the output (A), the switches S3 and S4 are connected in series. In each case parallel to the switch S3, the diode D3 is antiparallel, and parallel to the switch S4, the diode D4 is connected in anti-parallel. The midpoint (M) between the positive and negative DC terminals is connected to the anode of diode D5 (NPC diode) with its cathode connected between the two switches S1 and S2. The cathode of diode D6 is connected to the anode of diode D5. The cathode of D6 is connected between switches S3 and S4.

The Method will now be based on the example of four parallel-connected 3-phase 2-level inverters, their initial state using a 5-level Modulators is determined.

In 14 the considered configuration is shown. Four inverters WR1 to WR4 are connected to a common _DC link (-U _DC / 2, M, + U _DC / 2). The inverters each consist of 3 bridge branches according to 10 , The current measuring devices SM1 to SM4 measure the current in each phase of the respective inverter. Each bridge output is followed by the inductors L1.U, L1.V and L1.W. The outputs of the inductors L1.U are connected together and form the output U. The outputs of the inductors L1.V are connected together and form the output V. The outputs of the inductors L1.W are connected together and form the output W. An Outputs U, V and W are connected to a three-phase load (eg motor, generator). In 15 By way of example, two 5-level output states as produced by a 5-level modulator are shown with the respective redundant switching states for the 4 2-level inverters.

As in 16a Each bridge branch of the 2-level inverter can assume the bridge switching states 0 and 1. The switches shown symbolize the self-turn-off semiconductor switches used, the z. B. can be configured as IGBT, IGCT, MOSFET or bipolar transistor. In bridge switching state 0, the lower switch is always switched on and the upper switch open. The output voltage in this case is -U _dc / 2. In bridge switching state 1, the upper switch is on and the lower switch is open. The output voltage is then + U _dc / 2.

In 16b an inverter is shown in single inverter switching state 011. This means that the first bridge branch (U) has the bridge switching state 0, the second bridge branch has the bridge switching state 1 and the third bridge branch likewise has the bridge switching state 1.

In 16c the four inverters WR1 to WR4 connected in parallel are shown in an example switching state.

In the 17a to 17e For example, the possible output voltages U _XM for the configuration with four parallel-connected 2-level bridge branches of the inverters WR 1 to WR 4 are shown in idle phase X. The specified voltages apply to idling or to the configuration of an inductive coupling unit according to 8th , The following output voltages U _XM are shown:

17a : Level state 0

In all inverters WR 1 to WR 4, all lower switches are switched on and all upper switches are switched off. This results in: U XM = -U dc / 2

17b : Phase switching state 1

In the inverters WR 1 to WR 3, the lower switches are switched on and the upper switches are switched off. In the inverter WR 4, the upper switch is turned on and the lower switch is turned off. This results in: U XM = -U dc / 4

17c : Phase switching state 2

In the inverters WR 1 and WR 2, the upper switches are switched off and the lower switches are switched on. In inverters WR 3 and WR 4, the upper switches are switched on and the lower switches are switched off. This results in: U XM = 0V

17d : Phase switching state 3

In the inverters WR 2 to WR 4, the upper switches are switched on and the lower switches are switched off. In the inverter WR 1, the upper switch is turned off and the lower switch is turned on. This results in: U XM = + U dc / 4

17e : Phase switching state 4

In all inverters WR 1 to WR 4, all upper switches are switched on and all lower switches are switched off. This results in: U XM = + U dc / 2

In contrast to the parallel connection of 2-level voltage inverters with equally controlled switches, where only 2 output voltage levels U _XM (-U _dc / 2, + U _dc / 2) are possible, as shown in the table below 15 can be taken, 5 voltage levels are generated.

The to the 2 to 17e Facts explained so far form the basis for the use of a multilevel modulator. Each phase may assume voltage states, the phase output states, with respect to the common DC link center 5.

To achieve an optimal output spectrum, the 5-level space vector modulation method is used as a possible method. In 18 is one to the 14 and 15 associated space vector hexagon of the output voltage shown. The intersections of the lines of the hexagon represent the states that the output voltage of the four inverters WR1 to WR4 connected in parallel can assume. The states of the 3 phases for reaching the respective output voltage vector are indicated in the intersections (output voltage triplet). All triples that are at an intersection output the same output voltage of the 4 inverters. The selection of a meaningful triple can according to known methods such. B. minimizing the common-mode voltage or minimize the switching operations.

The target voltage vector to be imaged is generated by outputting the 3 adjacent switching vectors. This ensures that the chained voltage (eg U _UV ) only jumps by the amount ΔU = 2 · U _dc / 8 during a switching period duration. This has a positive effect on the output spectrum. To illustrate the advantage of this method, the output spectrum of such a 5-level modulator is as a result in 23 shown. Compared to the prior art, shown in the 11 and 12 , it can be seen that the voltage jumps ΔU, as in 23 shown, compared to the prior art are only half as large and thus the harmonic content is lower.

Another way to generate an output voltage triplet is to use a sine-triangle method. An example variant is in 19 shown.

It become four carrier signals (triangle or sawtooth), also called carrier, used. Shown is the reference signal for a phase. According to the prior art For each of inverters WR 1 to WR 4, a carrier signal is generated used, which shows the switching states of the respective inverter sets.

There but only the number of inverters, which one switched on upper switch or lower switch, for the phase output voltage decide is to be evaluated only how many carrier signals are smaller than the reference signal.

Lies the reference signal among all carrier signals is the state "0" to choose, it lies above a carrier signal if the state "1" is to be selected, it is over 2 is to select the state "2." This can be up to continue to the nth level.

The Modulation is performed equivalently for each phase. Only the reference signals are shifted by 120 ° or 240 °. This means that this procedure has one for each phase Switching state between 0 and 4 and a total switching triplet like in the space vector modulation supplies.

In 19 For the period T0, the phase output state of a phase is shown. The value of the sinusoidal reference signal is over 3 carrier signals during this time. This means that the phase output state is 3. This means that in three of the four bridge arms of the considered phase U the upper switch is switched on (bridge switching state 1) and in one of the four bridge branches the lower switch is switched on (bridge switching state 0).

For phase output state 3, there are four different phase switching states (1110, 1101, 1011, 0111). In this case, the phase switching state is 0111 in 19 shown. The four phase switching states all give the same output voltages. However, they differ in the _{circulating current change} di _xk / dt occurring. The current flow diagram for this example is in 20 shown, where the phase X represents the phase U here.

An additional possibility of modulation is to calculate a pulse pattern offline, that is, not in real time during operation of the inverters, according to desired optimization criteria. Here as well, an output voltage triplet with the phase output states 0 to 4 is generated as a result. The resulting output voltages are in the 17a to 17e shown.

The different possibilities for the change of the circulating current can from the 17a to 17e are derived and are shown in Table 1 below. Table 1: Current increases as a function of the phase switching state Phase output state U _XM Phase switching state di _{xk, 1} / dt di _{xk, 2} / dt di _{xk, 3} / dt di _{xk, 4} / dt 0 -U _dc / 2 0000 0 0 0 0 1 -U _dc / 4 1000 3/4 U _dc / L -1/4 U _dc / L -1/4 U _dc / L -1/4 U _dc / L 0100 -1/4 U _dc / L 3/4 U _dc / L -1/4 U _dc / L -1/4 U _dc / L 0010 -1/4 U _dc / L -1/4 U _dc / L 3/4 U _dc / L -1/4 U _dc / L 0001 -1/4 U _dc / L -1/4 U _dc / L 1/4 U _dc / L 3/4 U _dc / L 2 0V 1100 1/2 U _dc / L 1/2 U _dc / L -1/2 U _dc / L -1/2 U _dc / L 1010 1/2 U _dc / L -1/2 U _dc / L 1/2 U _dc / L -1/2 U _dc / L 1001 1/2 U _dc / L -1/2 U _dc / L -1/2 U _dc / L 1/2 U _dc / L 0110 -1/2 U _dc / L 1/2 U _dc / L 1/2 U _dc / L -1/2 U _dc / L 0101 -1/2 U _dc / L 1/2 U _dc / L -1/2 U _dc / L 1/2 U _dC / L 0011 -1/2 U _dc / L -1/2 U _dc / L 1/2 U _dc / L 1/2 U _dc / L 3 + U _dc / 4 0111 -3/4 U _dc / L 1/4 U _dc / L 1/4 U _dc / L 1/4 U _dc / L 1011 1/4 U _dc / L -3/4 U _dc / L 1/4 U _dc / L 1/4 U _dc / L 1101 1/4 U _dc / L 1/4 U _dc / L -3/4 U _dc / L 1/4 U _dc / L 1110 1/4 U _dc / L 1/4 U _dc / L 1/4 U _dc / L -3/4 U _dc / L 4 + U _dc / 2 1111 0 0 0 0

It may be in the case of the phase output states 1, 2 and 3 Phase switching state under different phase switching states to get voted. Through the targeted choice of phase switching states can thus be targeted to the circulating current components of the individual output currents be acted.

Embodiments of the switching state selector for four parallel-connected 2-level inverters WR1 to WR4 according to FIGS 21 to 27 , as in 14 shown, described. A higher-level control provides a setpoint voltage vector at the input of a 5-level modulator. From this setpoint voltage, the modulator generates time resolved output states for phases U, V and W. There are five possible output voltage levels per phase for inverter configurations as described in US Pat 17a to 17e are shown: + U _dc / 2, + U _dc / 4, 0V, -U _dc / 4, -U _dc / 2. These phase output levels correspond to the phase output states 4, 3, 2, 1, 0 according to table in FIG 15 and Table 1. The switching states of the bridge branches are according to 16a with 1 for + U _dc and 0 for -U _dc . The sum of the values of the switching states of the inverters for one phase must be equal to the value of the output state of this phase.

Of the Switching state selector sets the phase output states into the phase switching states of the four 2-level inverters WR1 to WR4. The result of redundant phase switching states resulting degree of freedom is in the switching state selector to minimize the amount used a control variable. In the following Embodiments become the switching states only recalculated for the phases in which also the Initial state changes. The phase switching states the phases where there is no change in phase output state, stay unchanged. The individual phase currents are measured by the current measuring devices SM1 to SM4 or predicted using the system model.

In the following embodiments, the phases U, V, W are treated equally; for the sake of clarity are in the 21 . 22 . 24 . 25 and 26 only the phase U is shown.

An embodiment of a switching state selector according to 21 FIG. 12 illustrates a phase current limiting control of the phase currents of the individual inverters WR1 to WR4. The switching state selector consists of a phase output state assignment unit to the phase switching state of a phase ZA. This unit for assigning the phase output state to the phase switching state ei The phase ZA has as input the control value actual value vector RI, consisting of the control value actual values for the four inverters WR1 to WR4. In the exemplary embodiment, the regulation value actual value vector RI is the phase current of the four inverters in each case in the phases U, V, W; in phase U, the phase currents i _{1, U} ... i _{4, U} , in phase V, the phase currents i _{1, V} ... i _{4, V} and in phase W, the phase currents i _{1, W} ... i _{4, W} , hereinafter referred to as Stromistwertvektor the phase U, V or W. The unit ZA selects the phase switching state according to Table 1 so that high phase currents are reduced and low phase currents are increased.

is after a change in the phase output state, the phase output state in one phase changed to 0 or 4, the bridge switching states of the four inverters WR1 to WR4 corresponding to the same phase all set to 0 or 1; it is not a direct influence of Unit for assigning the phase output state to the phase switching state a phase ZA possible. Is the phase output state on 1, the bridge switching state of the inverter with the smallest phase current in the phase affected by the change to 1 and the bridge switching states of the inverters with a larger control value actual value vector RI set to 0. If the phase output state has changed to 2, become the bridge switching states of the inverter with the two smallest phase currents in the change affected phase to 1 and those with the two largest Control value actual value vector RI is set to 0. When the phase output state changes to 3, the bridge switching states become with the three smallest phase currents in the transition affected phase to 1 and the one with the largest Control value actual value vector RI is set to 0. According to Table 1 increases for the phase output states 1,2 and 3, due to the circulating current, the phase current in the Inverters with the bridge switching state 1. In the Inverters, however, with bridge switching state 0 drops the phase current.

An embodiment of a switching state selector with circulating current control is in 22 shown. The switching state selector regulates the circulating current in one phase. The switching state selector consists of a unit for the assignment of the phase output state to the phase switching state of a phase ZA, as already in the exemplary embodiment 21 executed, and a calculation block BR for the Regelgrößenistwertvektor RI. In the calculation block BR, the control value actual value vector RI is obtained from the phase currents i _{1, U} ... i _{4, U} for phase U, from the phase currents i _{1, V} ... i _{4, V} for phase V and from the phase currents i _{1, W} ... i _4, W calculated for phase W. In the embodiment, the control amount actual value vector RI is the deviation of the phase currents of the same phase of the four inverters WR1 to WR4 from the average of the phase current of the same phase of the inverters. This corresponds to the circulating current component of the phase current of an inverter. The unit for the assignment of the Pha senausgangszustands to the phase switching state of a phase ZA determines the phase switching state, as already in the embodiment to 21 executed.

The output spectrum as a result of the realization according to 22 with a space vector based multilevel modulation is in 23 demonstrated. It can be seen a circular current, which reaches a peak of 500A.

An exemplary embodiment of a switching state selector with common-mode current regulation is shown in FIG 24 shown. The switching state selector controls the common mode current of the four inverters WR1 to WR4. The switching state selector consists of a unit for the assignment of the phase output state to the phase switching state of a phase ZA, as already in the exemplary embodiment 21 executed, and a calculation block BR for the Regelgrößenistwertvektor RI. In the calculation block BR, the control value _actual value vector RI is calculated from the phase currents i _{1, U} ... i _{4, U} , i _{1, V} ... i _{4, V} and i _{1, W} ... i _{4, W.} In the exemplary embodiment, the control value actual value vector RI is the sum of the phase currents of an inverter. The unit for assigning the phase output state to the phase switching state of a phase ZA determines the phase switching state, as already in the exemplary embodiment 21 executed.

An embodiment of a switching state selector is in 25 shown. The switching state selector controls a composite control variable. The switching state selector consists of a unit for the assignment of the phase output state to the phase switching state of a phase ZA, as already in the exemplary embodiment 21 executed, a calculation block BR2, as already in the embodiment too 22 executed, and a calculation block BR3, as already in the embodiment too 24 executed. The two output vectors of the calculation blocks are added together with a control value actual value vector RI, as already in the exemplary embodiment 21 executed, as inputs for an additional calculation block KG used. This forms the weighted sum of the squares of the individual input vector elements taking into account all relevant signs: RI n, P = SIGN (RI1 n, P ) · G1 · RI1 n, P 2 + SIGN (RI2 n, P ) · G2 · RI2 n, P 2 + SIGN (RI3 n, P ) · G3 · RI3 n, P 2

about the unit "weights" becomes the sensitivity of the switching state selector determined for the individual control variables. The squaring can also be done by another mathematical function be replaced. The output of the additional computation block KG supplies the control value actual value vector RI for the unit for assigning the phase output state to the phase switching state of a phase ZA.

An exemplary embodiment of a switching state selector with limit value monitoring is shown in FIG 26 shown. The switching state selector regulates the circulating current in one phase, as already in the exemplary embodiment 22 executed. The switching state selector consists of a unit for the assignment of the phase output state to the phase switching state of a phase ZA, as already in the exemplary embodiment 21 executed, and a calculation block BR, as already in the embodiment too 22 executed. In addition, the amounts of the elements of the control quantity actual value vector RI for the phases U, V, W are monitored by a limit comparator GK. When an element of the control amount actual value vector RI exceeds a threshold output to the threshold comparator GK, or the modulator outputs a phase switching state change signal, a phase switching state change signal is output to the phase output state allocation unit. The logical OR operation takes place in the unit v. The phase output state assignment unit, in turn, calculates a new phase switching state for the limit override phase and outputs this new phase switching state.

The output spectrum as a result of the realization according to 26 is in 27 shown. Unlike the procedure according to 22 the circulating current is limited here to 200A. It can be seen from the curve that, when reaching 200 A, a switching state is selected which reduces the circulating current. Due to the additional switching process for limiting the circulating current, additional switching losses occur. An exemplary embodiment of a two-phase topology, as in 28 uses a switching state selector, as in the embodiments of the 21 or 22 is described. A carrier-based multi-level modulator, in the exemplary embodiment a 3-level modulator, generates the phase output states corresponding to the reference signals of the target voltage specification of the respective phase. The in the embodiments of the 21 and 22 described switching state selectors determine the phase switching state only with the aid of the phase currents of the same phase. Thus, these switching state selectors can also be transferred to single, dual or multi-phase systems. A limit value monitoring as in the embodiment too 26 is also possible.

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

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Claims (23)

Inverter arrangement with a DC voltage terminal to which a DC voltage can be applied, a load terminal for connecting a load, a plurality of parallel inverters whose inputs are coupled together with the DC voltage terminal and its outputs via one or more inductors together with the load terminal, and a controller for controlling the inverter in response to a default vector of a higher-level control or regulating unit, characterized in that the control device is designed to control the inverter such that the output voltage at the load terminal in dependence on the default vector of a higher-level control unit a certain state of a number of different states wherein at least some states of the output voltage are provided by a number of different combinations of operating states of the inverters For each state of the output voltage, the control device selects that combination of operating states of the inverters from the number of different combinations in which a desired criterion is fulfilled as optimally as possible. Inverter arrangement according to claim 1, characterized characterized in that the default vector of a parent Control unit respectively the instantaneous value of a Designated voltage. Inverter arrangement according to Claim 1 or 2, thereby characterized in that the parallel-connected inverters of one or more inverter half bridges formed are, wherein the inverter half bridges each two or more switching elements, with which DC pulses with the timing of the discrete switching states the switching elements dependent polarity, pulse width and possibly amplitude to an output of an inverter half-bridge to switch the corresponding outputs the inverter via one or more inductors connected to each other, and wherein the control device one Modulator for determining pulse widths, polarities and possibly amplitudes of the DC voltage pulses to approach to an output AC voltage desired, especially sinusoidal Form, and a switching state selector least mediate Driving the switching elements, which is designed such that he under different in terms of approach to a desired output AC voltage for a respective time possible and with respect the current output voltage equivalent switching state combinations the switching elements determines that switching state combination, in which an optimization criterion is optimally fulfilled. Inverter arrangement according to claim 3, characterized in that the modulator is a pulse width modulator is that works on the sine triangular method. Inverter arrangement according to claim 4, characterized in that the inverters 2-level inverters where a number of n 2-level inverters are connected in parallel and the inverter arrangement as (n + 1) level pulse width modulator in the sine-triangular method with a number of n triangular Carrier signals works. Inverter arrangement according to claim 3, characterized in that the modulator is a pulse width modulator is configured to perform a multi-level space vector modulation. Inverter arrangement according to claim 6, characterized in that the inverters 2-level inverters are, with a number of n inverters connected in parallel and the inverter arrangement as (n + 1) level pulse width modulator works in multi-level space vector modulation method. Inverter arrangement according to a of claims 3 to 7, characterized in that the switching state selector Current measuring devices for measuring currents at the outputs has the inverter and is adapted to the selection of Operating states depending on the measured values the currents at the outputs of the inverters make. Inverter arrangement according to a of claims 3 to 7, characterized in that the switching state selector is formed, the selection of operating conditions from the using the system parameters calculated currents to the Outputs of the inverters. Inverter arrangement according to a of claims 3 to 9, characterized in that the switching state selector is formed, depending on the combination of operating conditions the inverter adjusting circulating currents between individual To precalculate inverters. Inverter arrangement according to a of claims 3 to 10, characterized in that the switching state selector is designed as a minimization of the optimization criterion Perform phase currents. Inverter arrangement according to claim 11, characterized in that the switching state selector per phase a unit for assigning the phase output state to the phase switching state the respective phase and is formed by means of a determined by the current measuring devices and to the unit for Assignment of the phase output state to the phase switching state The current actual value vector output in each phase minimizes to carry out the phase currents. Inverter arrangement according to a of claims 3 to 10, characterized in that the switching state selector is formed, a minimization of the circulating currents as an optimization criterion perform. Inverter arrangement according to claim 13, characterized in that the switching state selector per phase a calculation unit for calculating one for a circulating current control suitable control value actual value vector and a unit associated with the output of the calculation unit for assignment of the phase output state to the phase switching state of the respective one Phase and is formed by means of one of the current measuring devices determined and output to the calculation unit Stromistwertvektors and one from the calculation unit to the unit for assignment of the phase output state to the phase switching state of the respective one Phase output calculated control value actual value vector to perform a minimization of the circulating currents. Inverter arrangement according to a of claims 3 to 10, characterized in that the switching state selector is designed, a common mode current control as an optimization criterion perform. Inverter arrangement according to claim 15, characterized in that the switching state selector per phase a calculation unit for calculating one for a common mode current control suitable control value actual value vector and a unit associated with the output of the calculation unit for assignment of the phase output state to the phase switching state of the respective one Phase and is formed by means of one of the current measuring devices determined and output to the calculation unit Stromistwertvektors and one from the calculation unit to the unit for assignment of the phase output state to the phase switching state of the respective one Phase output calculated control value actual value vector to perform a common mode current control. Inverter arrangement according to a of claims 3 to 10, characterized in that the switching state selector is formed, a selection of switching state combinations based several optimization criteria according to one of Perform claims 10 to 15. An inverter arrangement according to claim 17, characterized in that the switching state selector per phase comprises a calculation unit for calculating a Kreisstromregelung suitable control value actual value vector, a calculation unit for calculating a suitable for a common mode current control Regelgrößenistwertvektors, a unit for adjusting the sensitivity of the individual optimization criteria such as minimization of the phase currents, minimization the circuit currents and common mode current control, a calculation unit for calculating the weighted sum of all Regelgrößengrößenwertvektoren and a unit for assigning the phase output state to the phase switching state of the respective phase, wherein the current measuring means of the switching state selector with the inputs of all calculation units, the unit for adjusting the sensitivity of each Optimization criteria and the outputs of the calculation unit for calculating ei A control current actual value vector suitable for a circulating current control, and the calculation unit for calculating a common mode current control value actual value vector with the input of the weighted sum calculating unit of all the control value actual value vectors and the output of the weighted sum calculating unit of all the control value actual value vectors with the phase output state allocation unit are connected to the phase switching state of the respective phase, and that the switching state selector is configured to have a calculated weighted control quantity actual value vector outputted from the weighted sum calculating unit of all the control amount actual value vectors to the phase output state allocation unit to the phase switching state of the respective phase by a current actual value vector determined by the current measuring means and outputted to all the calculation units Selection of switching state combinations based on several optimization criteria according to any one of claims 10 to 15 perform. Inverter arrangement according to a of claims 11 to 18, characterized in that the switching state selector is designed, a limit monitoring for to carry out one or more optimization criteria. Inverter arrangement according to claim 19, characterized in that the switching state selector per phase additionally a unit for determining the amount value to the unit for assigning the phase output state to the Phase switching state of the respective phase output Regelungsgrößenistwertvektors, one connected to the unit for determining the magnitude value of the control quantity actual value vector Limit comparator for the comparison of the absolute value of the control value actual value vector with a the limit comparator output limit and one with the Limit comparator connected phase switching state change signal generator for a logical OR operation of the limit comparator signal with a phase switching state change value obtained from a multi-level modulator and for the output of a phase switching state change signal at limit value overrun or phase switching state change of the modulator to the unit for assigning the phase output state to the phase switching state of the respective phase and formed is a limit monitor for one or more To carry out optimization criteria and if the limit value is exceeded or phase switching state change by means of the unit for Assignment of the phase output state to the phase switching state the respective phase to make a new phase switching state calculation and as a result output a phase switching state change. Inverter arrangement according to a of claims 3 to 20, characterized in that the modulator is designed, a carrier-based pulse width modulation method perform such that a number of the corresponding the number of parallel connected inverters of carrier signals be linked to a reference signal (setpoint), that the number of possible initial states 1 greater than the number of parallel connected Inverter multiplied by the number of times decreased by 1 Level of the individual inverters. Inverter arrangement according to claim 21, characterized in that the modulator is formed, process precalculated pulse patterns. Inverter arrangement according to a of claims 1 to 22, characterized in that the inverter arrangement has a multi-phase topology with a multilevel modulator.