CN109120173A

CN109120173A - Multi-level converter topology structure

Info

Publication number: CN109120173A
Application number: CN201710482411.2A
Authority: CN
Inventors: 张永; 高波; 胡晓磊
Original assignee: FENGZHI (SHANGHAI) NEW ENERGY TECHNOLOGY Co Ltd
Current assignee: FENGZHI (SHANGHAI) NEW ENERGY TECHNOLOGY Co Ltd
Priority date: 2017-06-22
Filing date: 2017-06-22
Publication date: 2019-01-01
Anticipated expiration: 2037-06-22
Also published as: CN109120173B

Abstract

The invention mainly relates to multi-level converter topology structure, the upper and lower arms including the composition bridge arm being connected in series between the first and second input terminals for receiving DC input voitage；The first and second control switches being connected in series between the first and second input terminals；Wherein alternating current is exported between the second intermediate node between the first intermediate node between upper and lower arms at interconnection and the first and second control switches at interconnection.There is provided in the topological structure containing inverter circuit can be realized inverter and corresponding inversion scheme of the multilevel at alternating current.

Description

Multi-level converter topology structure

Technical field

Present invention relates generally to inverter technology fields, are to be related to that industrial-frequency alternating current can be exported specifically Multi-level converter topology structure and corresponding inversion scheme.

Background technique

Power electronic technique has passed through the rapid development of nearly half a century since nineteen fifties are born, so far It is widely used in needing the every field of transformation of electrical energy, and with the exhaustion of the chemical industry energy in recent years and to the pollution of environment Become more and more serious, the energy transformation of field of photovoltaic power generation also more and more uses inversion system.In low pressure small-power Use electrical domain, oneself is gradually mature for power electronic technique, and high power density, high efficiency and high-performance variable are at mainstream, and in high pressure Powerful industry and transmission & distribution power technology are just becoming the research emphasis of current power electronic technique.Industry always wants to power electronics Device is capable of handling higher and higher voltage class and capacitance grade.Such as the D.C. high voltage transmission in electric system, with static Synchronous compensator and Active Power Filter-APF etc. are the flexible ac transmission technology of representative, and using high-pressure frequency-conversion as the big electricity of representative Machine driving and large power supply device etc.；Furthermore in order to meet the requirement of harmonic wave of output voltage content, and wish that these are high-power Power electronic equipment can work under high switching frequency, and reduce electromagnetic interference problem to the greatest extent.Power electronic devices is electric power The core of electronic device, in the past few decades in, power electronic devices experienced thyristor, turn-off thyristor, ambipolar High power transistor and fet controller part several stages.In recent years, various New Type Power Devices, integral gate change is brilliant Brake tube IGCT and injection enhancement gate transistor IEGT etc. are again numerous and confused to be occurred.

The resolving ideas and method of a variety of high-power transformation are summed up and are broadly divided into following a few major class: the first, The series-parallel technology of power device, this is a kind of most simple and direct scheme, can be realized with the switching device of smaller power High-power transformation, by devices in series to bear high pressure, by device parallel connection to bear high current, this seems simple method, by In the discreteness of power device parameters, complicated dynamic and static equalizer circuit and euqalizing current circuit are needed.Equalizer circuit can be led The control of cause system is complicated, and loss increases；And device flows, and is phase for the power device largely with negative temperature coefficient When difficult thing.Meanwhile it is series-parallel for device, the requirement of driving circuit also greatly improves, it is desirable that delay time is close to simultaneously It is short as far as possible.In turn off process, due to the difference of restorability, large number of absorbing circuit is also essential but reduces The reliability of system, and this scheme improves no any contribution to harmonic wave of output voltage, thus application range receives Certain limitation.The second, inverter parallel technology is by the inverter parallel of multiple low capacities, the number of shunt chopper It can be determined according to the capacity that system needs.The major advantage of this method is: being easily achieved inverter moduleization can also be with Flexibly expand the capacity of inversion system；It is easy to form N+1 parallel redundant system, improves tieing up for reliability of operation and system Shield property.The difficult point of inverter parallel technology is to need to solve voltage synchronous, stable state and dynamic current equalizing, N+1 from control circuit Redundancy and the big technology of hot-swap three.Third, multiple switch technology in order to use the power device of low capacity realize large capacity power Transformation, also using Multiple techniques.So-called Multiple techniques are exactly with multiple small-power inverters in its input or/and output End is by transformer series or parallel connection, and inverter is with the work of identical frequency out of phase, to reach the high power operation of system The purpose improved with input, output harmonic wave.Multiple techniques not only can be applied to single-phase circuit but also can be applied to three-phase circuit.Multiple skill Art is mainly disadvantageous in that: needing the input and output transformer of special designing, it not only increases the cost of system, reduces The efficiency of system, and when the number of inverter increases, the design of transformer will be extremely difficult.4th, inverter is combined Phase- shifted SPWM technique, basic thought are: in the system that one is made of N grades of modules, all modules use identical modulating wave, But the triangular carrier phase difference alienation of adjacent block.This phase difference makes SPWM pulse caused by each module wrong in phase It opens, the equivalent switching frequency of the SPWM waveform of each module final stack output is increased to original several times, is not improving switch Output harmonic wave is greatly reduced under conditions of frequency.From broadly, related targets combine inverter and a kind of multiple skill Art.And it is different from so-called output voltage multiplex above, here using the multiplex of triangular carrier, simplifies output and become The design of depressor.Related targets combine the advantages of inverter are as follows: the lower high-power switch device of switching frequency is used, realize etc. The high switching frequency output of effect, switching loss is low, and output harmonic wave content is small, reduces the size and capacity of output filter element, letter The design of transformer is changed.The disadvantage is that increasing loss and cost there is still a need for Industrial Frequency Transformer, not reducing power device Voltage stress.5th, multi-electrical level inverter technology multi-electrical level inverter technology is a kind of by improving inverter itself topology knot Structure come realize high-power output novel inverter, it be not necessarily to step transformer and equalizer circuit.Due to output voltage The increase of level number, so that output waveform has better harmonic spectrum, the voltage stress that each switching device is born is smaller.

Multi-electrical level inverter technology have become in power electronics with high-power be transformed to one of research object it is new Research field.Multi-electrical level inverter becomes the hot spot of high-power transformation research, is because it have the advantage that each Power device is subjected only to 1/(N-1) busbar voltage, N is level number, it is possible to realize the big function of high pressure with the device of low pressure resistance Rate output, and it is not necessarily to dynamic voltage-balancing；The increase of level number, improves output voltage waveforms, reduces output voltage waveforms Distortion；Lower switching frequency obtains output voltage waveforms identical with two-level inverter under high switching frequency, thus switchs It is lost small and high-efficient；Without exporting transformer, the volume and loss of system are considerably reduced；Reduce the humorous of input current Wave reduces the pollution to environment；For three-phase induction motor driving when, can higher degree reduce or eliminate neutral point electricity Flat fluctuation；Safety is higher, and the risk of busbar short-circuit substantially reduces；Multi-electrical level inverter technology is as solution high-power The representative and ideal scheme of transformation, receives more and more attention and applies.The basic principle is that by several Level step synthesizes staircase waveform to approach sinewave output voltage, and in general, level number is more, and its resolution ratio is higher, then Mean output voltage waveforms closer to sine wave.In inverse circuit topology structure, multi-electrical level inverter has two common poles Three kinds of Basic Topologicals such as pipe nationality position, striding capacitance, the cascade of H bridge.

An object of the application essentially consists in: the control program for fully considering the multi-electrical level inverter of output alternating current is established, The approach for eliminating existing inverter circuit disadvantage is summarized based on the inversion model derived, these measures are applied to striding capacitance It in the inverter structure of type, inquires into and reduces common mode current, reduce electromagnetic interference and the feasibility of harmonic carcellation distortion, by corresponding The novel inversion topological model disclosed illustrates the mechanism for generating alternating current.The switching switch in inversion system is ensured to greatest extent Voltage stress minimize, lower total harmonic distortion factor, while compact system as far as possible are provided in industrial frequency AC output waveform Electromagnetic interference and reduction loss, provide reliable guarantee for the safe operation of inversion system.

Summary of the invention

In one embodiment, the mostly electric of industrial-frequency alternating current is generated by high frequency switching switch control the present invention discloses a kind of Flat inversion system, comprising: the bridge arm of more level output voltages is generated under the driving of the control signal with first frequency；And Switch the output stage of the voltage reference of more level output voltages under the driving of the control signal with second frequency； Wherein the second frequency is lower than the first frequency；In each period of the alternating current of multi-level inverse conversion system output The bridge arm is switched to using the first current potential as voltage reference and by the bridge by first half period by the output stage Arm generates more level output voltages, is synthesized by a series of more level output voltages change by sine wave rule whereby First half period waveform；And second half of each period of the alternating current in multi-level inverse conversion system output The bridge arm is switched to using the second current potential as voltage reference by the output stage and generates institute by the bridge arm by the period More level output voltages are stated, synthesize second by the variation of sine wave rule by a series of more level output voltages whereby The waveform of half period；Any one complete cycle of the alternating current includes first and second half period.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: described first The waveform of a half period is rendered as positive pulsatile change relative to the first current potential；The waveform of second half period is relative to Two current potentials are rendered as negative sense pulsatile change；And any one complete cycle of the alternating current includes being considered as positive half period First half period and be considered as second half period of negative half period.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: described first Part of the waveform of a half period relative to the first current potential with negative sense pulsatile change and the part with positive pulsatile change；The Part of the waveform of two half periods relative to the second current potential with positive pulsatile change and the part with negative sense pulsatile change； And any one complete cycle of alternating current includes described first that positive pulsating volage is transitioned into from negative sense pulsating volage Half period and include second half period that negative sense pulsating volage is transitioned into from positive pulsating volage.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: the bridge arm Including at least be connected in series in receive DC input voitage the first and second input terminals between first and second groups of switches, by Control signal with first frequency drives first and second groups of switches；Wherein the first input end has the second current potential And second input terminal has the first current potential；And the interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood with One or more capacitor is provided between interconnecting nodes in second group of switch between corresponding a pair of adjacent switch.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: bridge arm is at least Including first group of switch being connected in series between the first and second input terminals for receiving DC input voitage and first group of two pole Pipe；Interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood are adjacent with corresponding a pair in first group of diode One or more capacitor is provided between interconnecting nodes between diode；And/or bridge arm includes at least and is connected in series in reception Second group of diode and second group of switch between first and second input terminals of DC input voitage；Appoint in second group of diode The interconnecting nodes between interconnecting nodes a pair of of adjacent switch corresponding with second group of switch between meaning adjacent pair diode Between be provided with one or more capacitor；Wherein the control signal with first frequency drive first group of switch and/or Second group of switch and the first input end are with the second current potential and second input terminal has the first current potential.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: the output Grade include be connected in series between the first and second input terminals by first and the of the control signal driving with second frequency Two control switches；Wherein the first input end, which is set as with the second current potential, and second input terminal is set as has the first electricity Position；It is used to export the first intermediate node and the first and second of the output stage of more level output voltages in the bridge arm The alternating current is exported between the second intermediate node between control switch at interconnection.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: in the friendship During first half period of the sine wave of galvanic electricity, the first control switch is in an off state and the second control switch is in and connects Logical state, then the second intermediate node of the output stage switches to the second of the reception DC input voitage for being coupled to the bridge arm Input terminal；And during second half period of the sine wave of the alternating current, the first control switch is in an ON state And the second control switch is in an off state, then the second intermediate node of the output stage, which switches to, is coupled to connecing for the bridge arm Receive the first input end of DC input voitage.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: described second Frequency is the power frequency of electric main.

The above-mentioned multi-level inverse conversion system that industrial-frequency alternating current is generated by high frequency switching switch control, in which: the bridge arm The voltage reference of the more level output voltages generated is arranged to using the half period of alternating current sine wave as jump in potential Bound-time node, voltage reference jump one at the end of any one in first and second half periods in each period Secondary, the amplitude of the jump in potential of voltage reference is equal to the value of the DC input voitage of the bridge arm.

In one embodiment, the present invention discloses one kind switches switch by high frequency in multi-level inverse conversion system to control The method that system generates industrial-frequency alternating current, multi-level inverse conversion system have bridge arm and output stage, and method includes: using with the first frequency The control signal of rate drives the bridge arm to generate more level output voltages；Using described in the control signal driving with second frequency Output stage, realization switch the voltage reference of more level output voltages between the first and second current potentials；By described second Frequency strangulation is to power frequency and is lower than the first frequency；A series of more level output voltages that the bridge arm is generated are modulated into The bridge arm is generated using the output stage during this period by the waveform of first half period of sine wave rule variation More level output voltage pressures are switched to using the first current potential as voltage reference；And bridge arm is generated a series of More level output voltages be modulated into the waveform of second half period by the variation of sine wave rule, during this period, using described More level output voltage pressures that output stage generates bridge arm are switched to using the second current potential as voltage reference；Exchange Any one complete cycle of electricity includes first and second half period.

Above-mentioned method, in which: drive the bridge arm using the control signal with first frequency, the institute for exporting bridge arm It states the waveform of sine wave that more level output voltages are modulated into first half period and is rendered as positive arteries and veins relative to the first current potential Dynamic variation；The bridge arm is driven using the control signal with first frequency, makes more level outputs of the bridge arm output Voltage modulated at waveform of the sine wave in second half period be rendered as negative sense pulsatile change relative to the second current potential.

Above-mentioned method, in which: drive the bridge arm using the control signal with first frequency, export the bridge arm Waveform of the sine wave that is modulated into of more level output voltages in first half period had relative to the first current potential The part of negative sense pulsatile change and part with positive pulsatile change, by being transitioned into positive arteries and veins after negative sense pulsating volage zero crossing Dynamic voltage；The bridge arm is driven using the control signal with first frequency, makes more level outputs of the bridge arm output Voltage modulated at waveform of the sine wave in second half period have relative to the second current potential the portion of positive pulsatile change Point and the part with negative sense pulsatile change, by being transitioned into negative sense pulsating volage after positive pulsating volage zero crossing.

Above-mentioned method, in which: the bridge arm, which includes at least, is connected in series in receive DC input voitage first and the First and second groups of switches between two input terminals, the first input end has the second current potential and second input terminal has First current potential；And in the interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood and second group of switch It is provided with one or more capacitor between interconnecting nodes between corresponding a pair of adjacent switch, the bridge arm described whereby forms winged Bridge arm across capacity type inverter；First and second groups of switches are driven using the control signal with first frequency, are used for More level output voltages are generated at the first intermediate node that first and second groups of switches are connected.

Above-mentioned method, in which: the bridge arm, which includes at least, is connected in series in receive DC input voitage first and the First as upper arm group switch between two input terminals and first group of diode as lower arm；Appoint in first group of switch It is mutual between the interconnecting nodes of meaning adjacent pair switch room a pair of of neighboring diode corresponding with first group of diode It even is provided with one or more capacitor between node, constitutes the bridge arm of striding capacitance type inverter whereby；And/or the bridge arm Including at least second as upper arm group two being connected in series between the first and second input terminals for receiving DC input voitage Pole pipe and second group of switch as lower arm；Interconnecting nodes in second group of diode between a pair of diodes of arbitrary neighborhood It is provided with one or more capacitor between interconnecting nodes between a pair of adjacent switch corresponding with second group of switch, The bridge arm of striding capacitance type inverter is constituted whereby；Wherein the first input end has the second current potential and second input terminal With the first current potential；First and/or second group of switch is driven using the control signal with first frequency, for described More level output voltages are generated at the first connected intermediate node of the upper and lower arms of bridge arm.

Above-mentioned method, in which: output stage includes the first and second controls being connected between the first and second input terminals Switch, the first input end is with the second current potential and second input terminal has the first current potential；It is more for exporting in bridge arm Between first intermediate node of level output voltage and the first and second control switches of the output stage at interconnection second among Alternating current is exported between node；First and second control switches are driven using the control signal with second frequency.

Above-mentioned method, in which: during first half period of alternating current sine wave, turn off the first control switch and The second intermediate node for connecting the second control switch then output stage, which switches to, is connected to bridge arm receives DC input voitage second Input terminal；During second half period of alternating current sine wave, connects the first control switch and turn off the second control switch Then the second intermediate node of the output stage, which switches to, is connected to the first input end that the bridge arm receives DC input voitage.

Above-mentioned method, in which: the voltage reference for more level output voltages that bridge arm generates is set as with alternating current The half period of sine wave is the bound-time node of jump in potential, is terminated in each of first and second half period The jump in potential of the moment voltage reference is primary, and the amplitude of jump in potential is equal to the voltage of the DC input voitage of bridge arm Value.

In one embodiment, the present invention discloses a kind of multi-level converter topology structures, comprising: is connected in series in and connects Receive the upper and lower arms between the first and second input terminals of DC input voitage；Be connected in series in the first and second input terminals it Between the first and second control switches；Wherein: the first intermediate node between the upper and lower arms of bridge arm at interconnection and first and Alternating current is exported between the second intermediate node between second control switch at interconnection.

Above-mentioned multi-level converter topology structure, in which: the bridge arm includes being connected in series in receive direct current input electricity First group of switch for being considered as upper arm between first and second input terminals of pressure and second group of switch for being considered as lower arm；And it is described Interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood are adjacent with corresponding a pair in second group of switch One or more capacitor is provided between the interconnecting nodes of switch room.

Above-mentioned multi-level converter topology structure, in which: the bridge arm includes being connected in series in receive direct current input electricity First group of switch for being considered as upper arm between first and second input terminals of pressure and first group of diode for being considered as lower arm；And institute State interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood and corresponding a pair in first group of diode One or more capacitor is provided between interconnecting nodes between neighboring diode.

Above-mentioned multi-level converter topology structure, in which: the bridge arm includes being connected in series in receive direct current input electricity Second group of diode for being considered as upper arm between first and second input terminals of pressure and second group of switch for being considered as lower arm；And institute State the interconnecting nodes and in second group of switch corresponding one in second group of diode between a pair of diodes of arbitrary neighborhood Between being provided with one or more capacitor between the interconnecting nodes adjacent switch.

Above-mentioned multi-level converter topology structure, in which: drive of the bridge arm in the control signal with first frequency The dynamic lower more level output voltages of generation；And first and second control switch is in the drive of the control signal with second frequency The voltage reference of dynamic lower switching more level output voltages；Wherein the second frequency is lower than the first frequency.

Above-mentioned multi-level converter topology structure, in which: in first half period in each period of the alternating current, It is switched to by more level output voltages that first and second control switch generates the bridge arm with the second input terminal The first current potential as voltage reference, whereby by a series of more level output voltages synthesize by sine wave rule become The waveform for first half period changed；And second half period in each period in the alternating current, by first He The second current potential work that more level output voltages that second control switch generates the bridge arm are switched to first input end For voltage reference, second half by the variation of sine wave rule is synthesized by a series of more level output voltages whereby The waveform in period；Any one complete cycle of the alternating current includes first and second half period.

Above-mentioned multi-level converter topology structure, in which: the waveform of first half period is relative to the first current potential It is rendered as positive pulsatile change, the waveform of second half period is rendered as negative sense pulsatile change relative to the second current potential；With And any one complete cycle of the alternating current includes being considered as first half period of positive half period and being considered as negative Half period second half period.

Above-mentioned multi-level converter topology structure, in which: the waveform of first half period is relative to the first current potential Part with negative sense pulsatile change and the part with positive pulsatile change, the waveform of second half period is relative to Two current potentials have the part of positive pulsatile change and the part with negative sense pulsatile change；And any one of the alternating current Complete cycle includes first half period of positive pulsating volage being transitioned into from negative sense pulsating volage and including certainly positive arteries and veins Second half period of the dynamic voltage-transition to negative sense pulsating volage.

Above-mentioned multi-level converter topology structure, in which: during first half period of alternating current sine wave, the One control switch is turned off and the second control switch is switched on, and second intermediate node, which switches to, to be connected to the bridge arm and connect Receive the second input terminal of DC input voitage；And during second half period of alternating current sine wave, the first control is opened Pass is switched on and the second control switch is turned off, and second intermediate node, which switches to, to be connected to the bridge arm to receive direct current defeated Enter the first input end of voltage.

Above-mentioned multi-level converter topology structure, in which: the Voltage Reference base for more level output voltages that bridge arm generates Standard is set as the bound-time node using the half period of the sine wave of alternating current as jump in potential, in the complete of each sine wave The jump in potential of the voltage reference of finish time each of first of complete cycle and second half period is primary；And And the hopping amplitude of voltage reference is equal to the voltage value of the DC input voitage of the bridge arm.

In one embodiment, friendship is generated based on above-mentioned multi-level converter topology structure invention further discloses a kind of The method of galvanic electricity, this method comprises: turning off the first control switch during first half period of alternating current sine wave and connecing Logical second control switch makes second intermediate node switch to the second input terminal for being connected to bridge arm reception DC input voitage, The output voltage of bridge arm generates a series of more level using the first current potential of the second input terminal as voltage reference whereby Output voltage, and synthesize the waveform of first half period by the variation of sine wave rule；At second half of alternating current sine wave During period, connects the first control switch and turn off the second control switch and switch to second intermediate node and be connected to institute The first input end that bridge arm receives DC input voitage is stated, the output voltage of bridge arm is made whereby with the second current potential of first input end A series of more level output voltages are generated for voltage reference, and synthesize second half cycle by the variation of sine wave rule The waveform of phase；Any one complete cycle of alternating current includes first and second half period.

Above-mentioned method, in which: the waveform of modulation first half period makes it be positive relative to the presentation of the first current potential To pulsatile change, the waveform for modulating second half period makes it be rendered as negative sense pulsatile change relative to the second current potential；With And any one complete cycle of the alternating current includes being considered as first half period of positive half period and being considered as negative Half period second half period.

Above-mentioned method, in which: the waveform of modulation first half period makes it relative to the first current potential with negative sense The part of pulsatile change and part with positive pulsatile change, the waveform for modulating second half period make it relative to the Two current potentials have the part of positive pulsatile change and the part with negative sense pulsatile change；And any one of the alternating current Complete cycle includes first half period of positive pulsating volage being transitioned into from negative sense pulsating volage and including certainly positive arteries and veins Second half period of the dynamic voltage-transition to negative sense pulsating volage.

In one embodiment, the present invention discloses a kind of multi-level converter topology structures, comprising: is connected in series in One and the second upper and lower arms between input terminal；And be connected in series between the third and fourth input terminal first and second Control switch；The third current potential that the third input terminal has is different from the second current potential for having of the first input end and described The 4th current potential that 4th input terminal has is different from the first current potential that second input terminal has；Wherein: having in a bridge arm Between the first intermediate node and first and second control switch between the upper and lower arms having at interconnection at interconnection Alternating current is exported between two intermediate nodes.

Above-mentioned multi-level converter topology structure, in which: drive of the bridge arm in the control signal with first frequency The dynamic lower more level output voltages of generation；And first and second control switch is in the drive of the control signal with second frequency The voltage reference of dynamic lower switching more level output voltages；Wherein second frequency is lower than the first frequency.

Above-mentioned multi-level converter topology structure, in which: in first half period in each period of the alternating current, It is switched to by more level output voltages that first and second control switch generates the bridge arm with the 4th voltage ginseng Benchmark is examined, synthesizes the wave of first half period by the variation of sine wave rule by a series of more level output voltages whereby Shape；And second half period in each period in the alternating current, by first and second control switch by the bridge More level output voltages that arm generates are switched to using third current potential as voltage reference, whereby by a series of described The waveform for second half period that more level output voltage synthesis are changed by sine wave rule；Any one of the alternating current is complete Complete cycle includes first and second half period.

Above-mentioned multi-level converter topology structure, in which: the waveform of first half period is relative to the 4th current potential It is rendered as positive pulsatile change, the waveform of second half period is rendered as negative sense pulsatile change relative to third current potential；With And any one complete cycle of the alternating current includes being considered as first half period of positive half period and being considered as negative Half period second half period.

Above-mentioned multi-level converter topology structure, in which: the waveform of first half period is relative to the 4th current potential Part with negative sense pulsatile change and the part with positive pulsatile change, the waveform of second half period is relative to Three current potentials have the part of positive pulsatile change and the part with negative sense pulsatile change；And any one of the alternating current Complete cycle includes first half period of positive pulsating volage being transitioned into from negative sense pulsating volage and including certainly positive arteries and veins Second half period of the dynamic voltage-transition to negative sense pulsating volage.

Above-mentioned multi-level converter topology structure, in which: during first half period of alternating current sine wave, the One control switch is turned off and the second control switch is switched on, and second intermediate node switches to that be connected to the described 4th defeated Enter end；And during second half period of alternating current sine wave, the first control switch is switched on and the second control switch It is turned off, second intermediate node, which switches to, is connected to the third input terminal.

Above-mentioned multi-level converter topology structure, in which: the Voltage Reference base for more level output voltages that bridge arm generates Standard is set as the bound-time node using the half period of the sine wave of alternating current as jump in potential, in the complete of each sine wave The jump in potential of the voltage reference of finish time each of first of complete cycle and second half period is primary；And And the hopping amplitude of voltage reference is equal to the difference of the 4th current potential and third current potential.

In one embodiment, the present invention discloses one kind realized in multi-level inverse conversion system by pulsating volage linking at The method of alternating current, comprising: load the first pulsating volage that multi-electrical level inverter is generated relative to the first current potential in load； The second pulsating volage that multi-electrical level inverter is generated relative to the second current potential is loaded in load；So that: load is in load A series of first and second pulsating volage alternate interval occur, thus by load on continuously apply first and second Pulsating volage is equivalent to be supplied to the alternating voltage of load；And in each complete cycle of the SIN function of the alternating voltage First and second pulsating volage occurred is respectively seen as the pulsating volage of first half period and second half period.

Above-mentioned method, in which: the first pulsating volage is rendered as the positive pulsatile change of alternating current with respect to the first current potential；The Two pulsating volages are rendered as the negative sense pulsatile change of alternating current with respect to the second current potential；Any one complete cycle packet of alternating voltage Second half period of the half period that first half period and definition for including the half period that definition is positive are negative.

Above-mentioned method, in which: the waveform of first half period is rendered as the band of alternating current relative to the first current potential There are the part of negative sense pulsatile change and the part with positive pulsatile change；The waveform of second half period is relative to second The part with positive pulsatile change and the part with negative sense pulsatile change that current potential is rendered as alternating current；And the exchange Electricity any one complete cycle include be transitioned by negative sense pulsating volage positive pulsating volage first half period and Second half period including being transitioned into negative sense pulsating volage from positive pulsating volage.

Above-mentioned method, in which: the DC input voitage for being supplied to multi-electrical level inverter is the second current potential and the first current potential Difference.

Above-mentioned method, in which: any one level in more level output voltages that the multi-electrical level inverter generates High level continue duration and low level continue duration constitute period 1 value；The SIN function, which has, is greater than described the The second week time value of one periodic quantity.

Above-mentioned method, in which: the bridge arm of a flying capacitor type inverter is provided, has and is connected in series in reception direct current Upper and lower arms between first and second input terminals of input voltage；One output stage is provided, has and is connected to first and the The first and second control switches between two input terminals, and the first input end is with the second current potential and second input End has the first current potential；First of the first intermediate node and the output stage between the upper and lower arms of the bridge arm at interconnection Alternating current is provided between second the second intermediate node at interconnection between control switch: wherein: more level of the bridge arm are defeated Voltage, which is switched to generate the first pulsating volage relative to the first current potential and be switched to, out generates the second pulsation relative to the second current potential The switching mode of voltage are as follows: during first half period of alternating current sine wave, processor drives the first control switch to give The second control switch is driven to be connected with shutdown, then second intermediate node is switched to first current potential；? During second half period of alternating current sine wave, locating processor drives the first control switch to be switched on and drive the second control System is turned off, and second intermediate node is switched to second current potential.

Above-mentioned method, in which: with the half period of the SIN function of the alternating voltage be first current potential and institute State the timing node that switching jump is executed between the second current potential, i.e. first and second in each complete cycle of sine wave The jump of the voltage reference of multi-electrical level inverter described in finish time each of half period is primary；And Voltage Reference The jump in potential amplitude of benchmark is equal to the voltage value of the DC input voitage of the multi-electrical level inverter.

In one embodiment, the present invention discloses one kind realized in multi-level inverse conversion system by pulsating volage linking at The method of alternating current, provides the bridge arm of a flying capacitor type inverter and it has to be connected on and receives the of DC input voitage One and the second upper and lower arms between input terminal, and the first and second controls being connected between the first and second input terminals are provided System switchs, to interconnect between the first intermediate node and the first and second control switches between the upper and lower arms of bridge arm at interconnection Alternating current is exported between second intermediate node at place；This method comprises: being closed during first half period of alternating current sine wave Disconnected first control switch and connect the second control switch make second intermediate node switch to be connected to the bridge arm receive it is straight The second input terminal of input voltage is flowed, the output voltage of bridge arm is using the first current potential of the second input terminal as Voltage Reference base whereby Standard generates a series of more level output voltages, and synthesizes the first pulsation electricity by the load of sine wave rule variation in load The waveform of pressure；During second half period of alternating current sine wave, connects the first control switch and turn off the second control and open Closing, which switches to second intermediate node, is connected to the first input end that the bridge arm receives DC input voitage, whereby bridge arm Output voltage a series of more level output voltages are generated using the second current potential of first input end as voltage reference, and The waveform of second pulsating volage of the synthesis by the load of sine wave rule variation in load；So that: load one in load First and second pulsating volages of series, which alternate interval, to be occurred, thus by the first and second pulsation continuously applied in load Voltage is equivalent to be supplied to the alternating voltage of load；And occur in each complete cycle of the SIN function of the alternating voltage First and second pulsating volage be respectively seen as the pulsating volage of first half period and second half period.

In one embodiment, the present invention discloses one kind realized in multi-level inverse conversion system by pulsating volage linking at The method of alternating current, provides the bridge arm of flying capacitor type inverter and it has the first He for being connected on and receiving DC input voitage Upper and lower arms between second input terminal provide the first and second controls being connected between the third and fourth input terminal and open It closes, thus between the first intermediate node and the first and second control switches between the upper and lower arms of bridge arm at interconnection at interconnection Alternating current is exported between second intermediate node；This method comprises: during first half period of alternating current sine wave, shutdown First control switch and connecting the second control switch switches to second intermediate node with the 4th current potential, the bridge described whereby The output voltage of arm generates a series of more level output voltages using the 4th current potential as voltage reference, and by a series of The waveform of first pulsating volage of more level output voltage synthesis by the load of sine wave rule variation in load；In alternating current During second half period of sine wave, connect the first control switch and turning off the second control switch makes second middle node Point is switched to third current potential, and the output voltage of bridge arm is generated a series of using third current potential as voltage reference whereby More level output voltages, and the load by the variation of sine wave rule is synthesized in load by a series of more level output voltages The waveform of second pulsating volage；So that: a series of first and second pulsating volage of the load in load alternates interval Occur, to be equivalent to be supplied to the alternating voltage of load by the first and second pulsating volages continuously applied in load；And First and second pulsating volage occurred in each complete cycle of the SIN function of the alternating voltage is respectively seen as The pulsating volage of one half period and second half period.

Above-mentioned method, in which: first input end is with the second current potential and the second input terminal has the first current potential；Described The 4th current potential that the third current potential that third input terminal has is different from second current potential and the 4th input terminal has Different from first current potential.

Above-mentioned method, in which: the first pulsating volage is rendered as the positive pulsatile change of alternating current with respect to the 4th current potential；The Two pulsating volages are rendered as the negative sense pulsatile change of alternating current with respect to third current potential；Any one complete cycle packet of alternating voltage Second half period of the half period that first half period and definition for including the half period that definition is positive are negative.

Above-mentioned method, in which: the waveform of first half period is rendered as the band of alternating current relative to the 4th current potential There are the part of negative sense pulsatile change and the part with positive pulsatile change；The waveform of second half period is relative to third The part with positive pulsatile change and the part with negative sense pulsatile change that current potential is rendered as alternating current；And the exchange Electricity any one complete cycle include be transitioned by negative sense pulsating volage positive pulsating volage first half period and Second half period including being transitioned into negative sense pulsating volage from positive pulsating volage.

Detailed description of the invention

Read it is described further below and referring to the following drawings after, feature and advantage of the invention will be evident.

Figure 1A to 1B is framework topological used by the multi-electrical level inverter of conventional flying capacitor type.

Fig. 2 is the multi-level inverse conversion system that industrial-frequency alternating current is generated by the control of high frequency switching switch.

Fig. 3 is the example architecture that multi-level inverse conversion system is made of multi-electrical level inverter and output stage.

Fig. 4 A to 4J is the schematic diagram that the output voltage of more level is generated by multi-level inverse conversion system.

Fig. 5 is that the more level generated based on multi-level inverse conversion system are exported to synthesize the example of alternating current.

Fig. 6 is the multi-electrical level inverter with the next diode and output stage composition multi-level inverse conversion system.

Fig. 7 is the multi-electrical level inverter with upper diode and output stage composition multi-level inverse conversion system.

Fig. 8 is more level synthesis alternating current of the multi-electrical level inverter with diode and output stage output.

Fig. 9 A to 9B is that Flying capacitor multilevel inverter and partial pressure type output stage construct inversion system.

Figure 10 is different by the input voltage of lower arm on multi-electrical level inverter and the input voltage of output stage.

Specific embodiment

Below in conjunction with each embodiment, clear and complete elaboration, described implementation are carried out to technical solution of the present invention Example is only the present invention with the embodiment used in illustrating is described herein and not all embodiment, is based on the embodiment, the skill of this field The scheme that art personnel obtain without making creative work belongs to the protection scope of the application.

Referring to shown in Figure 1A, with the rapid development of control theory and power electronic technique, semiconductor technology, cost is found Lower and more efficient inverter realizes that single-phase or many phase alternating current becomes the hot spot of power electronics, wherein flying capacitor type Multi-level inverter circuit causes industry and middle high-power AC motor to adjust the speed the very big concern in field, has small harmonic distortion and low Semiconductor devices stress and the low EMI of inversion system be its many advantages.In transmission line LNA and transmission in figure DC voltage source is provided between line LNB, it is assumed that there is on transmission line LNB current potential VR with current potential VD on transmission line LNA, then it is defeated It is out that VD subtracts VR to the DC voltage of multi-electrical level inverter.First group of switch SA1-SA6 and second group of switch SB1-SB6 are constituted One arm of multi-electrical level inverter, the quantity of every group of switch can be not limited to six but more or fewer here certainly Quantity, wherein each switch SA1-SA6 in first group of switch is connected in series in above-mentioned transmission line LNA and an intermediate node NX Between, corresponding, each switch SB1-SB6 in second group of switch is connected in series in intermediate node NX and above-mentioned transmission line Between LNB.Definition switch has the first and second ends and receives the control terminal of control signal, if control signal control switch connects Be connected between general rule first end and second end or control switch shutdown then first end and second end it is separated.First group is opened Closing the positional relationship respectively switched in SA1-SA6 is, for example: the first end of first switch SA1 is connected to transmission line LNA, and the latter is opened The first end for closing SA2 is connected to the second end of its adjacent previous switch SA1 and the first end of the latter switch SA3 connects Be connected to the second end of its adjacent previous switch SA2, according to the rule can with the rest may be inferred, the first of the latter switch SA5 End is connected to the second end of its adjacent previous switch SA4, and the first end of the switch SA6 at end is connected to the of switch SA5 The second end of two ends and switch SA6 are connected to above-mentioned intermediate node NX.So first switch SA1 in first group of switch SA1-SA6 First end be connected to transmission line LNA and end switch SA6 second end be connected to intermediate node NX, any the latter switch first End is connected to the second end of adjacent previous switch.It is corresponding to it, the positional relationship respectively switched in second group of switch SB1-SB6 E.g.: the second end of first switch SB1 is connected to transmission line LNB, and it is adjacent that the second end of the latter switch SB2 is connected to its The first end of previous switch SB1 and the second end of the latter switch SB3 are connected to its adjacent previous switch SB2's First end, can be with the rest may be inferred according to the rule, and the second end of the latter switch SB5 is connected to its adjacent previous switch The first end of SB4, and the second end of the switch SB6 at end is connected to the first end of the first end of switch SB5 and the switch SB6 at end It is connected to intermediate node NX.So the second end of first switch SB1 is connected to transmission line LNB and end in second group of switch SB1-SB6 The first end of switch SB6 is connected to intermediate node NX, the second end of any the latter switch is connected to adjacent previous switch First end.

Referring to shown in Figure 1A, first group of switch SA1-SA6 sequence is from being connected to the first of transmission line LNA in topological structure Switch SA1 is successively ordered into the switch SA6 for being connected to the end of intermediate node NX, and in multi-level inverse conversion topological structure second group open The sequence for closing SB1-SB6 is then that the end for being connected to intermediate node NX is successively ordered into from the first switch SB1 for being connected to transmission line LNB Switch SB6.The first switch SB1 in first switch SA1 and second group in first group complementary switch each other, in first group Second switch SB2 in second switch SA2 and second group is complementary switch, in the third switch SA3 and second group in first group Third switch SB3 be complementary switch, and there are also the 4th switch SB4 in the 4th switch SA4 and second group in first group Complementation, the 5th switch SB5 in the 5th switch SA5 and second group in first group is complementary each other, so analogizes, until definition the The 6th switch SB6 in the 6th switch SA6 and second group of switch in one group is complementary switch, and complementary switch means complementary One of the two is connected then another one and is turned off.As the multi-electrical level inverter of flying capacitor type, in first group of switch SA1-SA6 Between an interconnecting nodes a pair of of adjacent switch corresponding with second group of switch SB1-SB6 between a pair of switches of arbitrary neighborhood An interconnecting nodes between be arranged/be connected with one or more capacitors, whereby constitute striding capacitance Flying-Capacitor Type multi-electrical level inverter.

Referring to the interconnecting nodes NA1 and second shown in Figure 1A, in first group of switch between adjacent pair switch SA1-SA2 One or more electricity are connected between interconnecting nodes NB1 in group switch between the adjacent switch SB1-SB2 of corresponding a pair Hold C1, in which: the second end of switch SA1 and the first end of switch SA2 are connected to the first of interconnecting nodes NA1 and switch SB1 The second end of end and switch SB2 are connected to interconnecting nodes NB1.

Referring to the interconnecting nodes NA2 and second shown in Figure 1A, in first group of switch between adjacent pair switch SA2-SA3 One or more electricity are connected between interconnecting nodes NB2 in group switch between the adjacent switch SB2-SB3 of corresponding a pair Hold C2, in which: the second end of switch SA2 and the first end of switch SA3 are connected to the first of interconnecting nodes NA2 and switch SB2 The second end of end and switch SB3 are connected to interconnecting nodes NB2.

Referring to the interconnecting nodes NA3 and second shown in Figure 1A, in first group of switch between adjacent pair switch SA3-SA4 One or more electricity are connected between interconnecting nodes NB3 in group switch between the adjacent switch SB3-SB4 of corresponding a pair Hold C3, in which: the second end of switch SA3 and the first end of switch SA4 are connected to the first of interconnecting nodes NA3 and switch SB3 The second end of end and switch SB4 are connected to interconnecting nodes NB3.

Referring to the interconnecting nodes NA4 and second shown in Figure 1A, in first group of switch between adjacent pair switch SA4-SA5 One or more electricity are connected between interconnecting nodes NB4 in group switch between the adjacent switch SB4-SB5 of corresponding a pair Hold C4, in which: the second end of switch SA4 and the first end of switch SA5 are connected to the first of interconnecting nodes NA4 and switch SB4 The second end of end and switch SB5 are connected to interconnecting nodes NB4.

Referring to the interconnecting nodes NA5 and second shown in Figure 1A, in first group of switch between adjacent pair switch SA5-SA6 One or more electricity are connected between interconnecting nodes NB5 in group switch between the adjacent switch SB5-SB6 of corresponding a pair Hold C5, in which: the second end of switch SA5 and the first end of switch SA6 are connected to the first of interconnecting nodes NA5 and switch SB5 The second end of end and switch SB6 are connected to interconnecting nodes NB5.

It is omited referring to the particular implementation of 12/seven level inverter circuit single armeds of switch shown in Figure 1B, shown with Figure 1A Different, Figure 1B uses the adjustable single armed of number of switches, and upper and lower arms switch is all K+1, topological structure tool There is extensive representativeness.Corresponding respectively constituted of upper bridge arm SA_1 to SA_K+1 and lower bridge arm SB_1 to SB_K+1 flies across electricity The first group of switch and second group of switch of the multi-electrical level inverter of appearance formula.Figure 1A is with hexad switch and second group six Switch is used as example, and first and second groups of switches are high-frequency pulsed width modulation signal/controls by being coupled to the control terminal of switch Signal PWM processed carrys out control switch and switches between switching off and on.Actually first group and second group of number of switches does not limit In six, the more or fewer number of switches of the selection of being adapted to property as Figure 1B and also switch can using IGBT, MOSFET or thyristor constant power switch.In fig. ib, in first group of switch arbitrary neighborhood a pair of switches SA_K and SA_K+1 The interconnection section of interconnecting nodes NA_K between the two a pair of of adjacent switch SB_K and SB_K+1 corresponding to second group of switch between the two It is connected with striding capacitance C_K between point NB_K, K is natural number here.Pay attention to a pair of switches SA_K and SA_K+1 and corresponding one In switch SB_K and SB_K+1, the switch SA_K in first group is complementary with the switch SB_K in second group, and, first group In switch SA_K+1 it is complementary with the switch SB_K+1 in second group.Upper bridge arm SA_1 to SA_K+1 and lower bridge arm SB_1 to SB_K + 1 is connected in intermediate node NX described above --- namely arm point, quantity are that the switch of K+1 is respectively applied to upper and lower bridge arm.Ginseng As shown in Figure 1B, the sequence of first group of switch is successively ordered into from the first switch SA_1 for being connected to transmission line LNA in topology It is connected to the switch SA_K+1 at the end of intermediate node NX, and the sequence of second group of switch is then from being connected to transmission line LNB in topology First switch SB_1 be successively ordered into the switch SB_K+1 for being connected to the end of intermediate node NX.DC voltage source is from transmission line It is inputted between LNA and transmission line LNB, more level alternating currents are exported from intermediate node NX, and can also be connected in intermediate node NX Meet the filter inductance LX as Figure 1A.First group and second group of switch are typically considered and constitute the list of multi-electrical level inverter Arm, multiple single armed combinations can be formed by polyphase inverter.Figure 1B due to twice that total single-pole switch quantity is K+1, so The level quantity of K+2 may be implemented.

It is shown in Figure 2, in an alternate embodiment of the invention, discloses and industrial-frequency alternating current is generated by high frequency switching switch control Multi-level inverse conversion system, comprising: the mostly electric of more level output voltages is generated under the driving of the control signal with first frequency Flat inverter 100；More level output voltages are modulated into exchange under the driving of the control signal with second frequency The output stage 101 of electricity.Here multi-electrical level inverter 100 may include the inverter single armed in Figure 1A -1B, multi-electrical level inverter Can export the output voltage of multiple level grades, and the function of output stage 101 here first is that by those multiple level etc. The output voltage of grade is switched to suitable voltage reference, because the output voltage of multiple level grades only has relatively unambiguous voltage Benchmark can just embody the size of voltage level or level grade；The function of output stage 101, which also resides in, will finally generate Directly cross-coupling is realized between alternating current and the direct-current input power supplying of inverter, appropriate can reduce potential direct current Source noise interference and part inhibit the common mode interference problem of multi-electrical level inverter.

Shown in Figure 3, in an alternate embodiment of the invention, multi-electrical level inverter 100 includes being connected in transmission line LNA and middle node First group of switch SA1-SA3 and multi-electrical level inverter 100 between point NX further include being connected to transmission line LNB and intermediate node Second group of switch SB1-SB3 between NX, upper bridge arm SA1-SA3 be connected between transmission line LNA and intermediate node NX and under Bridge arm SB1-SB3 is connected between transmission line LNB and intermediate node NX, can also directly be expressed as first group of switch and second group Switch is connected between transmission line LNA and transmission line LNB.Wherein: a pair of switches SA1-SA2 of arbitrary neighborhood in first group of switch Between interconnecting nodes NA1 a pair of of adjacent switch SB1-SB2 corresponding with second group of switch between interconnecting nodes NB1 between It is provided with the interconnection section in one or more capacitor C11 and first group of switch between a pair of switches SA2-SA3 of arbitrary neighborhood Be provided between interconnecting nodes NB2 between point NA2 a pair of of adjacent switch SB2-SB3 corresponding with second group of switch one or Multiple capacitor C22.Just as explained above, switch SA1-SB1 is complementary, and switch SA2-SB2 is complementary, and switch SA3-SB3 is mutual It mends, constitutes striding capacitance type multi-electrical level inverter whereby.In addition output stage 101 includes being connected in series in transmission line LNA and transmission The first control switch Q1 and the second control switch Q2 between line LNB, if the first end of the first control switch Q1 is connected to transmission line The first end of the second end of LNA and the first control switch Q1 and the second control switch Q2 are connected in intermediate node NY, and second The second end of control switch Q2 is then connected to transmission line LNB.In order to avoid obscuring, we can set the centre of Converting Unit single armed Node NX is the first intermediate node, and the intermediate node NY of output stage is the second intermediate node.It also can be described as first in fact Control switch Q1 is connected between transmission line LNA and intermediate node NY, and the second control switch Q2 is connected in intermediate node NY and transmission line Between LNB.Control switch Q1-Q2 and above first group and second group of switch are all power semiconductor switch, they have the One and second end and receive control signal/modulated signal control terminal, control signal it is suitable if controlling those switch connections Be connected between the first end and second end of switch, or control those and turned off, be equivalent to switch first end and It is disconnected between second end, such as first end and second end can be the drain electrode end and source terminal or on the contrary, for example of field-effect tube It is the collector and emitter or on the contrary, certain anode and cathode or phase that can also be thyristor of insulated gate bipolar transistor Instead, the control terminal switched is grid or gate terminal etc., and switch can also use reverse-blocking tetrode thyristor device etc..The inverter list of Fig. 3 Four level inverse conversions may be implemented in arm topological structure, although the application is to be sent out using four level as example to illustrate in this embodiment Bright spirit, but do not mean that the application shall be limited only to four level.Additionally as the first output end of the output end of output stage Alternating current is generated between OUT1 and second output terminal OUT2, notices that first output end OUT1 is coupled to the intermediate node of single armed NX, corresponding second output terminal OUT2 are coupled to the intermediate node NY of output stage 101, load LD be connected in the first output end OUT1 and Between second output terminal OUT2.About semiconductor power switch, in addition to traditional field effect transistor, other are integrated gate commutated Thyristor, gate turn off thyristor, high power transistor, electron injection enhancement gate transistor etc. can be applied to the present invention In.

Referring to fig. 4 shown in A, if transmission line LNA with current potential VD1 and transmission line LNB that there is current potential VR1 then to input to is mostly electric The DC voltage of flat inverter is that VD1 subtracts VR1, if their difference is equal to U.If again assume that in reference earth potential GND and It is in series with capacitor CS1-CS2 etc. between transmission line LNA, and is in series with capacitor between reference earth potential GND and transmission line LNB CS3-CS4 etc. is equivalent to the DC input voitage U of multi-electrical level inverter being divided into two equal portions, for example, transmission line LNA relative to With reference to the positive U/2 current potential of earth potential GND, negative U/2 current potential of the transmission line LNB relative to reference earth potential GND, but still meet VD1-VR1=U.Assuming that the stage of voltage is established in charging above capacitor C11-C22, capacitor C11 is charged as U/2 and capacitor C22 It is charged as U/4.

Referring to fig. 4 shown in A, switch conduction/shutdown integrated mode of Flying capacitor multilevel inverter single armed are as follows: upper arm SA1 shutdown in first group of switch SA1-SA3 and SA2/SA3 is connected, make lower arm second in the corresponding complementary relationship of upper lower arm SB1 in group switch SB1-SB3 is connected and SB2/SB3 is turned off.Switch conduction/shutdown integrated mode in output stage 101 are as follows: the One control switch Q1 is turned off and the second control switch Q2 is connected, the output under this mode at the intermediate node NX of multi-electrical level inverter Level is about U/2 with respect to NY, and capacitor C11 is electric discharge.This also means that the first output end OUT1 of output stage and U/2 is exported between two output end OUT2.

Referring to fig. 4 shown in B, switch conduction/shutdown integrated mode of Flying capacitor multilevel inverter single armed are as follows: upper arm SA1 in first group of switch SA1-SA3 is connected and SA2/SA3 is turned off, and makes lower arm second in the corresponding complementary relationship of upper lower arm SB1 shutdown and SB2/SB3 connection in group switch SB1-SB3.Switch conduction/shutdown integrated mode in output stage 101 are as follows: the One control switch Q1 is turned off and the second control switch Q2 is connected, the output under this mode at the intermediate node NX of multi-electrical level inverter Level is about U/2 with respect to NY, and capacitor C11 is charging.This also means that the first output end OUT1 of output stage and U/2 is exported between two output end OUT2.

Referring to fig. 4 shown in C, switch conduction/shutdown integrated mode of Flying capacitor multilevel inverter single armed: the of upper arm SA1/SA3 in one group of switch SA1-SA3 is connected and SA2 is turned off, and makes second group of lower arm in the corresponding complementary relationship of upper lower arm SB1/SB3 shutdown and SB2 connection in switch SB1-SB3.Switch conduction/shutdown integrated mode in output stage 101 are as follows: first Control switch Q1 is turned off and the second control switch Q2 is connected, output level at the intermediate node NX of multi-electrical level inverter under this mode Opposite NY is about 3 × U/4, capacitor C11 charging but capacitor C22 electric discharge.This also means that the first output end OUT1 of output stage 3 × U/4 is exported between second output terminal OUT2.

Referring to fig. 4 shown in D, switch conduction/shutdown integrated mode of Flying capacitor multilevel inverter single armed: the of upper arm SA1/SA2 in one group of switch SA1-SA3 is connected and SA3 is turned off, and makes second group of lower arm in the corresponding complementary relationship of upper lower arm SB1/SB3 shutdown and SB3 connection in switch SB1-SB3.Switch conduction/shutdown integrated mode in output stage 101 are as follows: first Control switch Q1 is turned off and the second control switch Q2 is connected, output level at the intermediate node NX of multi-electrical level inverter under this mode Opposite NY is about 3 × U/4, and capacitor C22 is charging.This also means that the output of the first output end OUT1 of output stage and second It holds and exports 3 × U/4 between OUT2.

Referring to fig. 4 shown in E, switch conduction/shutdown integrated mode of flying capacitor type multi-electrical level inverter single armed: upper arm All switch SA1/SA2/SA3 in first group of switch SA1-SA3 are connected, and lower arm the is made in the corresponding complementary relationship of upper lower arm All switch SB1/SB2/SB3 shutdown in two groups of switch SB1-SB3.101 switch conductions of output stage/shutdown integrated mode are as follows: First control switch Q1 is turned off and the second control switch Q2 is connected, and is exported at the intermediate node NX of multi-electrical level inverter under this mode Level is about U with respect to NY, this also means that: U is exported between the first output end OUT1 and second output terminal OUT2 of output stage.

Referring to fig. 4 shown in F, switch conduction/shutdown integrated mode of Flying capacitor multilevel inverter single armed are as follows: upper arm SA1 shutdown in first group of switch SA1-SA3 and SA2/SA3 is connected, make lower arm second in the corresponding complementary relationship of upper lower arm SB1 in group switch SB1-SB3 is connected and SB2/SB3 is turned off.Switch conduction/shutdown integrated mode in output stage 101 are as follows: the One control switch Q1 is connected and the second control switch Q2 is turned off, the output under this mode at the intermediate node NX of multi-electrical level inverter Level is about-U/2 with respect to NY, and capacitor C11 is electric discharge.This also means that the first output end OUT1 of output stage and Negative U/2 is exported between second output terminal OUT2.

Referring to fig. 4 shown in G, switch conduction/shutdown integrated mode of Flying capacitor multilevel inverter single armed: the of upper arm SA1 in one group of switch SA1-SA3 is connected and SA2/SA3 is turned off, and makes second group of lower arm in the corresponding complementary relationship of upper lower arm SB1 shutdown and SB2/SB3 connection in switch SB1-SB3.Switch conduction/shutdown integrated mode in output stage 101 are as follows: first Control switch Q1 is connected and the second control switch Q2 is turned off, the output electricity under this mode at the intermediate node NX of multi-electrical level inverter Flat opposite NY is about-U/2, and capacitor C11 is charging.This also means that the first output end OUT1 of output stage and Negative U/2 is exported between two output end OUT2.

Referring to fig. 4 shown in H, switch conduction/shutdown integrated mode of flying capacitor type multi-electrical level inverter single armed: upper arm SA1/SA3 shutdown in first group of switch SA1-SA3 and SA2 is connected, make lower arm second in the corresponding complementary relationship of upper lower arm SB1/SB3 in group switch SB1-SB3 is connected and SB2 is turned off.Switch conduction/shutdown integrated mode in output stage 101 are as follows: the One control switch Q1 is connected and the second control switch Q2 is turned off, output level at multi-electrical level inverter intermediate node NX under this mode Opposite NY is about -3 × U/4, capacitor C11 electric discharge but capacitor C22 charging.This also means that the first output end of output stage Minus 3 × U/4 is exported between OUT1 and second output terminal OUT2.

Referring to fig. 4 shown in I, switch conduction/shutdown integrated mode of flying capacitor type multi-electrical level inverter single armed: upper arm SA1/SA2 shutdown in first group of switch SA1-SA3 and SA3 is connected, make lower arm second in the corresponding complementary relationship of upper lower arm SB1/SB2 in group switch SB1-SB3 is connected and SB3 is turned off.Switch conduction/shutdown integrated mode in output stage 101 are as follows: the One control switch Q1 is connected and the second control switch Q2 is turned off, output level at multi-electrical level inverter intermediate node NX under this mode Opposite NY is about -3 × U/4, capacitor C11 electric discharge but capacitor C22 charging.This also means that the first output end of output stage Minus 3 × U/4 is exported between OUT1 and second output terminal OUT2.

Referring to fig. 4 shown in J, switch conduction/shutdown integrated mode of flying capacitor type multi-electrical level inverter single armed: upper arm All switch SA1/SA2/SA3 in first group of switch SA1-SA3 are directly turned off, under making in the corresponding complementary relationship of upper lower arm All switch SB1/SB2/SB3 in second group of switch SB1-SB3 of arm are directly connected.Switch conduction/shutdown in output stage 101 Integrated mode are as follows: the first control switch Q1 is connected and the second control switch Q2 is turned off, among the multi-electrical level inverter under this mode Output level is about-U with respect to NY at node NX.This also means that the first output end OUT1 and second output terminal of output stage Negative U is exported between OUT2.

It is worth noting that, in Fig. 4 A-4J the control switch of first group of switch and second group of switch and output stage conducting Or the description of off state are as follows: the switch of the then conducting is connected not by fork fork symbol covering, instead in any one switch Switch of the then shutdown for being off of any one switch by fork fork symbol covering.Based on the timing of Fig. 4 A-4J, single armed is paid attention to The state that turns on and off of first group and second group switch signal or modulated signal are substantially controlled by the output of microprocessor It controls, such as: logical device, the processor of plural number, control device, state machine, controller, chip, software-driven control, door Array and/or other equivalent controllers.It is wherein especially typical with pulse-width signal PWM.

It is shown in Figure 5, curve U1 is observed, substantive curve U1 is the positive half cycle of complete alternating current sine wave.If we Attempt based on the topology in Fig. 3, it is intended to be closed with the more level output voltages exported at the intermediate node NX of single armed At curve U1, then it is contemplated that the timing control scheme of Fig. 4 A-4J.In a subsequent optional but nonessential embodiment In, consider to turn off 101 first control switch Q1 of output stage and be connected with by the second control switch Q2, thus in the first output end The voltage waveform that curve of output U1 is indicated between OUT1 and second output terminal OUT2.

It is shown in Figure 5, it with the amplitudes such as a series of but is differed in time point t0 to the t4 of time shaft T in conjunction with Fig. 4 A-4E The burst pulse of width replaces the local segment of half-sinusoid or half-sinusoid, as industry SPWM waveform --- pulse width is pressed Sinusoidal rule changes and the PWM waveform equivalent with sine wave is modulated like that.First output end OUT1 and second output terminal OUT2 it Between output waveform U1 be that potential VR1 based on intermediate node NX current potential relative to transmission line LNB-U/2 is realized as benchmark More level outputs, in an alternate embodiment of the invention, curve U1 is generated with the value of VR1 or using its absolute value as reference value in Fig. 5 Forward direction pulsation exports mechanism to illustrate more level.

It is shown in Figure 5, it is about U/ in the opposite NY of output level of the time t0 at the intermediate node NX in t1: Fig. 4 A 2, capacitor C11 discharges；Output level in Fig. 4 B at intermediate node NX is about U/2 and capacitor C11 charging with respect to NY；Figure Output level with respect to NY is about 3 × U/4 at intermediate node NX in 4C, capacitor C11 charging but capacitor C22 discharges；In in Fig. 4 D Output level is about 3 × U/4 with respect to NY at intermediate node NX, and capacitor C22 is charging.If button goes intermediate node NX above NY Potential VR1 namely U/2 ground potential, it is about in 0, Fig. 4 B that the intermediate node NX in Fig. 4 A, which is also higher by the additional current potential of NY, It is about U/4 that intermediate node NX, which is also higher by the additional current potential of NY and is also higher by the additional current potential of NY for intermediate node NX in 0, Fig. 4 C, with And being also higher by the additional current potential of NY there are also the intermediate node NX in Fig. 4 D is about U/4.Total reality of the intermediate node NX above NY Border current potential should be the ground potential of any time along with additional current potential.Therefore curve U1 can be equivalent to: first by middle node Ground potential of the point NX above NY, which extracts, is used as reference data current potential, then the additional current potential by intermediate node NX above NY Resultant curve U1 is come with the reference data current potential again.In other words, curve U1 is rendered as relative to the absolute value of VR1 or VR1 The voltage waveform of positive pulsatile change.Specific implementation means, such as time t0 is to the curved portion of t1: correspond to above-mentioned Fig. 4 A-4D Timing generate the more level 0 being made of additional current potential, 0, U/4, U/4, intermediate node NX is higher by these additional current potentials of NY Be considered as more level, by NX be higher by the two values of the 0 and U/4 of NY come high frequency switch to obtain curve U1 be located at time t0 to t1 piece Section；And there are four types of the switching combinings of 0 and U/4, Fig. 4 A is in conjunction with Fig. 4 C or Fig. 4 A is in conjunction with Fig. 4 D, Fig. 4 B in conjunction with Fig. 4 C or Person Fig. 4 B is in conjunction with Fig. 4 D.

Shown in Figure 5, the opposite NY of output level at the intermediate node NX in t1 to t2: Fig. 4 E of time is about U； Output level with respect to NY is about 3 × U/4 at intermediate node NX in known Fig. 4 C, capacitor C11 charging but capacitor C22 discharges；Figure Output level with respect to NY is about 3 × U/4 at intermediate node NX in 4D, and capacitor C22 is charging.If button removes intermediate node NX high For the ground potential of the potential VR1 namely U/2 of NY, it is about U/4 that the intermediate node NX in Fig. 4 C, which is also higher by the additional current potential of NY, The additional current potential that intermediate node NX in Fig. 4 D is also higher by NY is about U/4, and the intermediate node NX in Fig. 4 E is also higher by the additional of NY Current potential is about U/2.Actual potential of the intermediate node NX above NY should be the ground potential of any time along with additional electric Position.Therefore, curve U1 can be still equivalent are as follows: first the ground potential by intermediate node NX above NY, which extracts, is used as reference data Current potential, then the additional current potential by intermediate node NX above NY carrys out resultant curve U1 again with the reference data current potential.In other words It says, so-called curve U1 is substantially the voltage waveform that positive pulsatile change is rendered as relative to the absolute value of VR1 or VR1.Specifically Realization rate, such as the curved portion of time t1 to t2: what the timing corresponding to above-mentioned Fig. 4 C-4E generated is made of additional current potential More level U/4, U/4, U/2, these additional current potentials that intermediate node NX is higher by NY are considered as more level, are higher by by intermediate node NX The two values of the U/4 and U/2 of NY carry out high frequency and switch to obtain curve segment of the curve U1 between time t1 to t2.And U/4 and U/2 Switching combining have: Fig. 4 C- Fig. 4 E combine or Fig. 4 D- Fig. 4 E combine.

Shown in Figure 5, in time t2 to t3: the output level of intermediate node NX is about U with respect to NY in known Fig. 4 E； Output level with respect to NY is about 3 × U/4 at intermediate node NX in Fig. 4 C；In Fig. 4 D at intermediate node NX output level with respect to NY About 3 × U/4.If detaining the ground potential for removing the intermediate node NX potential VR1 above NY namely U/2 above, in Fig. 4 C The additional current potential that intermediate node NX is also higher by NY is about U/4, and the additional current potential that the intermediate node NX in Fig. 4 D is also higher by NY is about The additional current potential that intermediate node NX is also higher by NY in U/4, Fig. 4 E is about U/2.Actual potential of the intermediate node NX above NY is answered This is the ground potential of any time along with additional current potential.Therefore, curve U1 can be still equivalent are as follows: first by intermediate node NX Ground potential above NY, which extracts, is used as reference data current potential, then the additional current potential by intermediate node NX above NY again with The reference data current potential carrys out resultant curve U1.Specific implementation means, such as the curved portion of time t2 to t3: correspond to above-mentioned figure More level U/4, U/4, U/2 for being made of additional current potential that the timing of 4C-4E generates, intermediate node NX be higher by NY these are additional Current potential is considered as more level, is higher by the U/4 and U/2 of NY the two value high frequencies by intermediate node NX and switches to obtain curve U1 and is located at the time Segment between t2 to t3.And the switching combining of U/4 and U/2 has: Fig. 4 C is in conjunction with Fig. 4 E or Fig. 4 D is in conjunction with Fig. 4 E.We can send out More level that the curve segment of t2 to t3 and the curve segment of time t1 to t2 are used between current are almost the same, because time t2 is arrived The curve segment of t3 and the curve segment of time t1 to t2 be it is symmetrical, distinctive points essentially consist in: from time t1 to t2 with when Between to elapse ratio that U/2 is accounted in the switching combining of U/4 and U/2 backward more next more so causing curve U1 voltage waveform in the time T1 to t2 gradually increases, on the contrary, as the time elapses U/4 in the switching combining of U/4 and U/2 backward from time t2 to t3 So curve U1 voltage waveform is caused to gradually reduce in time t2 to t3 more than the ratio accounted for is more next, modulation duty cycle can be passed through Mode realize.

Shown in Figure 5, in time t3 to t4: the opposite NY of intermediate node NX output level in known Fig. 4 A is about U/ 2；Fig. 4 B intermediate node NX output level is about U/2 with respect to NY；Output level is about 3 with respect to NY at Fig. 4 C intermediate node NX ×U/4；Fig. 4 D intermediate node NX output level is about 3 × U/4 with respect to NY.If button removes electricity of the intermediate node NX above NY The ground potential of gesture VR1 namely U/2, the additional current potential that the intermediate node NX of Fig. 4 A is also higher by NY is about 0, Fig. 4 B intermediate node It is the additional current potential that intermediate node NX is also higher by NY in 0, Fig. 4 C is about U/4 that NX, which is also higher by the additional current potential of NY, in Fig. 4 D in The additional current potential that intermediate node NX is also higher by NY is about U/4.Actual potential of the intermediate node NX above NY should be any time Ground potential add additional current potential.Therefore, curve U1 still can be equivalent to: the first base by intermediate node NX above NY Plinth current potential, which extracts, is used as reference data current potential, and then the additional current potential by intermediate node NX above NY is again with reference data electricity Resultant curve U1 is carried out in position.Specific implementation means, such as the curved portion of time t3 to t4: the timing corresponding to above-mentioned Fig. 4 A-4D The more level 0 of generation being made of additional current potential, 0, U/4, U/4, these additional current potentials that intermediate node NX is higher by NY are considered as more Level can be higher by the two values of the 0 and U/4 of NY by NX come high frequency and switch to obtain the segment that curve U1 is located at time t3 to t4； And there are four types of the switching combinings of 0 and U/4, Fig. 4 A in conjunction with Fig. 4 C perhaps Fig. 4 A in conjunction with Fig. 4 D Fig. 4 B in conjunction with Fig. 4 C or Fig. 4 B is in conjunction with Fig. 4 D.We understand the mostly electricity that the curve segment of discovery time t3 to t4 and the curve segment of time t0 to t1 are used Put down it is almost the same because the curve segment of time t3 to t4 and the curve segment of time t0 to t1 are symmetrical, their differences Point essentially consists in: as the time, to elapse the ratio that U/4 is accounted in the switching combining of 0 and U/4 backward more next more from time t0 to t1, Also curve U1 voltage waveform is had led to gradually to increase in time t0 to t1, on the contrary, from time t3 to t4 with the time to The ratio that passage 0 accounts in the switching combining of 0 and U/4 afterwards is more next more so curve U1 voltage waveform is caused to be in time t3 to t4 It gradually reduces.

It is shown in Figure 5, by being exported from time t0 to t4 by the driving to Fig. 3 topology, first in output stage 101 Alternating current voltage wavy curve U1 is produced between the OUT1 and second output terminal OUT2 of end, is specifically produced relative to transmission line The potential VR1 of LNB is rendered as the alternating current positive half cycle of positive pulsation: time t0 to t2 is the first transition of alternating current positive half cycle, Time t2 to t4 is the last transition of alternating current positive half cycle.By being higher by current potential VR1 relatively or being higher by the absolute value of current potential VR1 Level 0, U/4 high frequency switching, synthesize alternating current curve U1 t0-t1 local curve；By being higher by current potential VR1 or being higher by The high frequency of level U/4, U/2 of the absolute value of current potential VR1 switch, and synthesize the local curve of the t1-t2 of alternating current curve U1；And By be higher by current potential VR1 or be higher by current potential VR1 absolute value level U/4, U/2 high frequency switching, synthesize alternating current curve U1 T2-t3 local curve；In addition also by being higher by current potential VR1 or being higher by the high frequency of the level 0 of absolute value of current potential VR1, U/4 Switching, local curve of the synthesis alternating current curve U1 in time period t 3-t4.Therefore it is considered that: in alternating current each period Positive half cycle is switched to by more level output voltages that output stage 101 generates multi-electrical level inverter 100 with supply lines/biography The current potential that defeated line LNB has synthesizes the positive half cycle of the output alternating current generated from output end OUT1-OUT as voltage reference, The positive pulsating volage load that multi-electrical level inverter is generated relative to supply lines/transmission line LNB current potential is on load LD.

It is shown in Figure 5, curve U2 is observed, substantive curve U2 is the negative half period of complete alternating current sine wave.If we Attempt based on the topology in Fig. 3, it is intended to be closed with the more level output voltages exported at the intermediate node NX of single armed At curve U2, then it is contemplated that the timing control scheme of Fig. 4 F-4J.In a subsequent optional but nonessential embodiment In, consider to connect 101 first control switch Q1 of output stage and turn off the second control switch Q2, thus in the first output end The voltage waveform that curve of output U2 is indicated between OUT1 and second output terminal OUT2.

It is shown in Figure 5, it with the amplitudes such as a series of but is differed in time point t4 to the t8 of time shaft T in conjunction with Fig. 4 F-4J The burst pulse of width replaces the local segment of half-sinusoid or half-sinusoid, as industry SPWM waveform --- pulse width is pressed Sinusoidal rule changes and the PWM waveform equivalent with sine wave is modulated like that.First output end OUT1 and second output terminal OUT2 it Between output waveform U2 be that potential VD1 based on intermediate node NX current potential relative to the U/2 of transmission line LNA is realized as benchmark More level outputs, in an alternate embodiment of the invention, curve U2 is generated with the value of VD1 or using its absolute value as reference value in Fig. 5 Negative sense pulsation exports mechanism to illustrate more level.

It is shown in Figure 5, output level at the intermediate node NX in t4 to t5: Fig. 4 F of time with respect to NY is about- U/2, capacitor C11 electric discharge；Output level at Fig. 4 G intermediate node NX is about-U/2 and capacitor C11 charging with respect to NY； Output level is about -3 × U/4, capacitor C11 electric discharge but capacitor C22 charging with respect to NY at Fig. 4 H intermediate node NX；In Fig. 4 I Intermediate node NX at output level with respect to NY be about -3 × U/4 and capacitor C22 electric discharge.If button removes intermediate node NX The ground potential of potential VD1 namely U/2 lower than NY, it is about 0 that the intermediate node NX in Fig. 4 F, which is also less than the additional current potential of NY, It is that intermediate node NX is also less than the additional current potential of NY and is about in 0, Fig. 4 H that intermediate node NX, which is also less than the additional current potential of NY, in Fig. 4 G U/4, and being also less than the additional current potential of NY there are also the intermediate node NX in Fig. 4 I is about U/4.Intermediate node NX is total lower than NY's Actual potential should be the ground potential of any time along with additional current potential.Therefore curve U2 can be equivalent are as follows: first will be intermediate Ground potential of the node NX lower than NY, which extracts, is used as reference data current potential, and intermediate node NX is then lower than the additional current potential of NY again Carry out resultant curve U2 with the reference data current potential.In other words, curve U2 is presented relative to the value of VD1 or the absolute value of VD1 For the voltage waveform of negative sense pulsatile change.Specific implementation means, such as the curved portion of time t4 to t5: corresponding above-mentioned Fig. 4 F- The more level 0 of the timing generation of 4I being made of additional current potential, 0, U/4, U/4, additional current potential of the intermediate node NX lower than NY regard For more level, (0 switches to obtain curve U2 and is located at time t4 to t5 with-U/4) high frequencies for 0 and U/4 by NX lower than NY the two values Segment.And there are four types of the switching combinings of 0 and-U/4, Fig. 4 F is in conjunction with Fig. 4 H or Fig. 4 F is in conjunction with Fig. 4 I, Fig. 4 G and Fig. 4 H In conjunction with or Fig. 4 G in conjunction with Fig. 4 I.

It is shown in Figure 5, output level at the intermediate node NX in t5 to t6: Fig. 4 J of time with respect to NY is about- U；Output level with respect to NY is about -3 × U/4 at intermediate node NX in known Fig. 4 H, capacitor C11 electric discharge but capacitor C22 fills Electricity；Output level with respect to NY is about -3 × U/4 at intermediate node NX in Fig. 4 I, and capacitor C22 is electric discharge.If button goes to centre Node NX is lower than the ground potential of the potential VD1 namely U/2 of NY, and the intermediate node NX in Fig. 4 H is also less than the additional current potential of NY about For U/4, it is about U/4 that the intermediate node NX in Fig. 4 I, which is also less than the additional current potential of NY, and the intermediate node NX in Fig. 4 J is also less than NY Additional current potential be about U/2.Intermediate node NX lower than the NY total actual potential should be the ground potential of any time again In addition additional current potential.Therefore, curve U2 can be still equivalent are as follows: first the ground potential by intermediate node NX lower than NY extracts conduct Reference data current potential, then the additional current potential by intermediate node NX lower than NY carrys out resultant curve U2 again with the reference data current potential. In other words, so-called curve U2 is substantially the voltage wave that negative sense pulsatile change is rendered as relative to the absolute value of VD1 or VD1 Shape.Specific implementation means, such as the curved portion of time t5 to t6: corresponding to above-mentioned Fig. 4 H-4J timing generate by additional These the additional current potentials of more level U/4, U/4, U/2 that current potential is constituted, intermediate node NX lower than NY are considered as more level, by middle node Lower than the U/4 and U/2 of NY the two values, (- U/4 and-U/2) carrys out high frequency and switches to obtain curve U2 to be located at time period t 5 and arrive point NX Curve segment between t6.And the switching combining of-U/4 and-U/2 has: Fig. 4 H combines switching or benefit with the level value of Fig. 4 J Switching is combined with the level value of Fig. 4 J with Fig. 4 I.

Shown in Figure 5, in time t6 to t7: the output level at the intermediate node NX of known Fig. 4 J is about with respect to NY It is-U；Output level with respect to NY is about -3 × U/4 at intermediate node NX in known Fig. 4 H；It is defeated at intermediate node NX in Fig. 4 I Level is about -3 × U/4 with respect to NY out.Intermediate node NX is gone to be lower than potential VD1 namely U/2 that NY has if we first detain Ground potential, it is about U/4 that the intermediate node NX in Fig. 4 H, which is also less than the additional current potential of NY, and the intermediate node NX in Fig. 4 I is also low It is about U/4 in the additional current potential of NY, the additional current potential that the intermediate node NX in Fig. 4 J is also less than NY is about U/2.Intermediate node NX Total actual potential lower than the NY should be the ground potential of any time along with additional current potential.Therefore, curve U2 can be with Still equivalent are as follows: first the ground potential by intermediate node NX lower than intermediate node NY, which extracts, is used as reference data current potential, then will Additional current potential of the intermediate node NX lower than NY carrys out resultant curve U2 again with the reference data current potential.In other words, so-called curve U2 is substantially the voltage waveform that negative sense pulsatile change is rendered as relative to the value of VD1 or the absolute value of opposite VD1.Realization rate, The curved portion of time t6 to t7: the more level U/4, U/4 of the timing generation corresponding to Fig. 4 H-4J being made of additional current potential, U/2, intermediate node NX are considered as more level lower than these additional current potentials of NY, the U/4 and U/2 by intermediate node NX lower than NY this two A value (- U/4 and-U/2) carrys out high frequency and switches to obtain curve U2 to be located at time period t 6 to the segment between t7.Based on explaination above Content, it is known that the switching combining of-U/4 and-U/2 has: Fig. 4 H combines switching with the level value of Fig. 4 J or utilizes Fig. 4 I and figure The level value of 4J switches to combine.The curve segment of discovery time t5 to t6 and the curve segment of time t6 to t7 are used mostly electric Put down it is almost the same because the curve segment of time t5 to t6 and the curve segment of time t6 to t7 be it is symmetrical, difference is: from Time t5 to t6 is more next more so leading with time passage-U/2 is accounted in the switching combining of-U/4 and-U/2 backward ratio Cause curve U2 voltage waveform in time t5 to t6 be it is smaller and smaller, on the contrary with time passage-U/4 backward from time t6 to t7 The ratio accounted in the switching combining of-U/4 and-U/2 is more next more so curve U2 voltage waveform is caused to be in time t6 to t7 It is increasing, it can be realized by modulation duty cycle.

Shown in Figure 5, in time t7 to t8: the output level at intermediate node NX in known Fig. 4 F is about with respect to NY It is-U/2；Output level at Fig. 4 G intermediate node NX is about-U/2 with respect to NY；And it is exported at Fig. 4 H intermediate node NX Level is about -3 × U/4 with respect to NY；Output level counterpart node NY is about -3 × U/ at intermediate node NX in Fig. 4 I 4.If button removes the ground potential of potential VD1 namely U/2 of the intermediate node NX lower than NY, the intermediate node NX in Fig. 4 F is also less than The additional current potential of NY is about that the additional current potential that intermediate node NX is also less than NY in 0, Fig. 4 G is that intermediate node NX is also low in 0, Fig. 4 H It is about U/4 in the additional current potential of NY, and being also less than the additional current potential of NY there are also the intermediate node NX in Fig. 4 I is about U/4.In Total actual potential of the intermediate node NX lower than NY should be the ground potential of any time along with additional current potential.Therefore curve U2 It can be equivalent are as follows: first the ground potential by intermediate node NX lower than NY, which extracts, is used as reference data current potential, then by intermediate node NX Additional current potential lower than NY carrys out resultant curve U2 again with the reference data current potential.In other words, curve U2 is the value relative to VD1 Or the absolute value relative to VD1 is rendered as the voltage waveform of negative sense pulsatile change.Realization rate, such as the curve of time t7 to t8 Part: the more level 0 of the timing generation of corresponding diagram 4F-4I being made of additional current potential, 0, U/4, U/4, intermediate node NX are lower than The additional current potential of NY is considered as more level.Embodiment is: by NX lower than the 0 and U/4 of NY the two values (0 with-U/4) come high frequency Switching obtains the segment that curve U2 is located at time t7 to t8.And there are four types of the switching combinings of 0 and-U/4, Fig. 4 F is in conjunction with Fig. 4 H Or Fig. 4 F, in conjunction with Fig. 4 I, either, Fig. 4 G is in conjunction with Fig. 4 H or Fig. 4 G is in conjunction with Fig. 4 I.The song of discovery time t4 to t5 More level that line segment and the curve segment of time t7 to t8 are used are almost the same, the curve segment and time t7 of time t4 to t5 Curve segment to t8 be it is symmetrical, difference essentially consists in: from time t4 to t5 with the time backward passage-U/4 in-U/4 It is more next more with the ratio that is accounted in 0 switching combining so curve U2 voltage waveform is caused in time t4 to t5 to be smaller and smaller, phase Instead from time t7 to t8 as the time passage-U/4 is accounted in the switching combining of-U/4 and 0 backward ratio the next small so leading Cause curve U2 voltage waveform in time t7 to t8 be it is increasing, can be realized by modulation duty cycle.

It is shown in Figure 5, by being exported from time t4 to t8 by the driving to Fig. 3 topology, first in output stage 101 Alternating current voltage wavy curve U2 is produced between the OUT1 and second output terminal OUT2 of end, is specifically produced relative to transmission line The potential VD1 of LNA is rendered as the alternating current negative half period of negative sense pulsation: time t4 to t6 is the last transition of alternating current negative half period, Time t6 to t8 is the first transition of alternating current negative half period.Absolute value by being relatively lower than current potential VD1 or lower than current potential VD1 Level 0 and-U/4 high frequency switch, synthesize alternating current curve U2 t4-t5 local curve；By lower than current potential VD1 or The high frequency of the level-U/4 and-U/2 of current potential VD1 absolute value switch, and synthesize the local curve of the t5-t6 of alternating current curve U2； And by switching lower than the high frequency of current potential VD1 or the level-U/4 and-U/2 of the absolute value lower than current potential VD1, synthesis exchange The local curve of the t6-t7 of electric curve U2；Pass through the level 0 and-U/4 lower than current potential VD1 or the absolute value lower than current potential VD1 High frequency switching, synthesis alternating current curve U2 time period t 7-t8 local curve.Therefore it is considered that: it is each in alternating current The negative half period in period is switched to by more level output voltages that output stage 101 generates multi-electrical level inverter 100 to power The current potential that line/transmission line LNA has synthesizes the negative of the output alternating current generated from output end OUT1-OUT as voltage reference Half cycle is loading the negative sense pulsating volage load that multi-electrical level inverter is generated relative to supply lines/transmission line LNA current potential On LD.

It is shown in Figure 5, if the first group of switch SA1-SA3 and second group of switch SB1-SB3 of multi-electrical level inverter are having Have under the control signal of first frequency or the driving of modulated signal, generates more level output voltages；And the first control of output stage 101 Making switch Q1 and the second control switch Q2 will be described mostly electric under the driving of the control signal with second frequency or modulated signal Flat output voltage is modulated into alternating current.It can be produced by controlling us by the HF switch to Fig. 3 topology from time t0 to t4 The positive half cycle curve of output U1 of raw industrial-frequency alternating current, namely the positive pulsating volage relative to transmission line LINB potential is generated, it is bent Zero crossing/zero of the line U1 from t0 with respect to VR1, which is stepped up to the alternating current forward direction pulsating volage that moment t2 curve U1 is indicated, to be reached To sine wave maximum value VM, the peak value from t2 with respect to VR1 is stepped down to the zero of the zero crossing of t4.In addition from time t4 to t8 Controlling us also by the HF switch to Fig. 3 topology can produce the negative half period curve of output U2 of industrial-frequency alternating current, that is, generate Relative to the negative sense pulsating volage of transmission line LINA potential, zero crossing/zero of the U2 from the t4 moment with respect to VD1 is gradually reduced then The alternating current negative sense pulsating volage that carving t8 curve U2 indicates reaches sine wave most valley-VM, also the valley from t6 with respect to VD1 by Step increases to the zero of the zero crossing of t8.By the sine wave modulation scheme that the application content above is discussed in detail, then know: The cycle time section of the signal period of complete SIN function waveform Curve1 is t0-t8.Waveform Curve1 by a series of U1 and U2 synthesis, it is just applied to the standard sine alternating current of load from the perspective of load LD: positive pulsation electricity on time shaft T It is negative sense pulsating volage namely curve U2, in other words, negative sense pulsating volage namely curve on time shaft T after pressure namely curve U1 It is positive pulsating volage namely curve U1 after U2, curve U1 and curve U2 are alternately present.It loads a series of on load LD Positive pulsating volage and negative sense pulsating volage alternate interval and occur, to positive be pulsed by what is continuously applied on load LD It is equivalent with negative sense pulsating volage are as follows: to be supplied to the positive half cycle and negative half period of the SIN function Curve1 of the alternating voltage of load LD. Wherein drive the higher frequency of the control signal of single-pole switch the group SA1-SA3 and SB1-SB3 of striding capacitance inverter much high In the work frequency of the control signal of the control switch Q1-Q2 of driving output-stage circuit.In addition to what is illustrated facilitates this The benchmark of curve U1 is specially set as the absolute value of VR1 by application, if substantial transmission line LNB is clamped to lower than zero potential Negative potential, the absolute value of the benchmark VR1 of curve U1 can be substituted for negative value in Fig. 5, i.e., one is added before the absolute value of VR1 Negative sign.Correspondingly, illustrate for convenience and transmission line LNA is defaulted to the positive potential for being above zero potential, curve U2's Benchmark is set as the positive value of VD1.If the current potential that the current potential of transmission line LNB and LNA are positive, the reference data of curve U1 are The reference data of positive value VR1 and curve U2 is positive value VD1, this also means that positive half period is positive on the basis of positive VR1 Pulsation and negative half period are pulsed by benchmark negative sense of positive VD1.What if the current potential of transmission line LNB and LNA were negative Current potential, then curve U1 is using negative value VR1 as reference data and curve U2 using negative value VD1 as reference data, it is meant that positive half A period positive pulsation and negative half period on the basis of negative VR1 are pulsed by benchmark negative sense of negative VD1.

Shown in Figure 6, the Flying capacitor multilevel inverter of figure 3 above introduction changes another topology into: specifically In this embodiment, upper arm still includes first group of switch S11-S13 as Fig. 3, but lower arm is by second group of original switch It is substituted for concatenated a series of diode string.Multi-electrical level inverter 100 include be connected in transmission line LNA and intermediate node NX1 it Between first group of switch S11-S13, and multi-electrical level inverter 100 further includes being connected between transmission line LNB and intermediate node NX1 First group of diode D11-D13, upper bridge arm S11-S13 is connected between transmission line LNA and intermediate node NX1 and lower bridge arm D11-D13 is connected between transmission line LNB and intermediate node NX1, can directly be expressed as first group of switch and first group of two pole Pipe is connected between transmission line LNA and transmission line LNB.In first group of switch between a pair of switches S11-S12 of arbitrary neighborhood Between interconnecting nodes ND11 between interconnecting nodes NS11 a pair of of neighboring diode D11-D12 corresponding with first group of diode It is provided with the interconnecting nodes in one or more capacitor C11 and first group of switch between a pair of switches S12-S13 of arbitrary neighborhood One is provided between interconnecting nodes ND12 between NS12 a pair of of neighboring diode D12-D13 corresponding with first group of diode A or multiple capacitor C22.As explained above, switch S11 is complementary with diode D11, and switch S12 and diode D12 are mutual It mends, switch S13 is complementary with diode D13, constitutes striding capacitance type multi-electrical level inverter whereby.101 part of output stage and Fig. 3's Embodiment can be consistent.Notice that the anode of first diode D11 in first group of diode D11-D13 is connected to transmission line LNB And the cathode of end diode D13 is connected to intermediate node NX1, with any two pole of the latter in first group of diode D11-D13 The mode that the anode of pipe is connected to the cathode of adjacent previous diode is connected.In addition single armed intermediate node NX1 and the first output end It can connect filter inductance LX between OUT1, and can connect filtered electrical between the first and second output end OUT1-OUT2 Hold CO.The control of the upper arm switch of first group of switch S11-S13 and Fig. 3 of the single armed of Fig. 6 or modulation system are substantially similar, but scheme The lower arm diode D11-D13 of 6 single armed is then not necessarily to control off/on.

Refering to what is shown in Fig. 7, the Flying capacitor multilevel inverter of figure 3 above introduction changes another topology into: specifically In this embodiment, lower arm still includes second group of switch S21-S23 as Fig. 3, but upper arm is by first group of original switch It is substituted for concatenated a series of diode string.Multi-electrical level inverter 100 include be connected in transmission line LNB and intermediate node NX2 it Between second group of switch S21-S23, and multi-electrical level inverter 100 further includes being connected between transmission line LNA and intermediate node NX2 Second group of diode D21-D23, upper bridge arm D21-D23 is connected between transmission line LNA and intermediate node NX2 and lower bridge arm S21-S23 is connected between transmission line LNB and intermediate node NX2, can directly be expressed as second group of diode and second group is opened Pass is connected between transmission line LNA and transmission line LNB.In second group of switch between a pair of switches S21-S22 of arbitrary neighborhood Between interconnecting nodes ND21 between interconnecting nodes NS21 a pair of of neighboring diode D21-D22 corresponding with second group of diode It is provided with the interconnecting nodes in one or more capacitor C11 and second group of switch between a pair of switches S22-S23 of arbitrary neighborhood One is provided between interconnecting nodes ND22 between NS22 a pair of of neighboring diode D22-D23 corresponding with second group of diode A or multiple capacitor C22.As explained above, switch S21 is complementary with diode D21, and switch S22 and diode D22 are mutual It mends, switch S23 is complementary with diode D23, constitutes striding capacitance type multi-electrical level inverter single armed.The implementation of output stage 101 and Fig. 3 Example can be consistent.Pay attention to the cathode of first diode D21 in second group of diode D21-D23 be connected to transmission line LNA and The anode of end diode D23 is connected to intermediate node NX2, with any the latter diode in second group of diode D21-D23 The mode that cathode is connected to the anode of adjacent previous diode is connected.In addition single armed intermediate node NX2 and the first output end OUT1 Between can connect filter inductance LX, and can connect filter capacitor CO between the first and second output end OUT1-OUT2. The control of the lower arm switch of second group of switch S21-S23 and Fig. 3 of the single armed of Fig. 7 or modulation system are substantially similar, but the list of Fig. 7 The upper arm diode D21-D23 of arm is then not necessarily to control off/on.Multi-electrical level inverter can be simultaneously in an alternate embodiment of the invention The single armed of single armed and Fig. 7 including Fig. 6, then the two of Fig. 6-7 single armed and the output-stage circuit containing control switch Q1-Q2 join It closes and constitutes multi-level inverse conversion system.

Referring to shown in Fig. 6-7, the joint of the topology of Fig. 6 and/or the topology of Fig. 7 and the two topology also be can produce in Fig. 5 Alternating current positive half period voltage waveform U1 and the negative half-cycle voltage waveform U2, and then generate and positive pulsed by described The alternating current sine wave Curve1 that curve U1 and negative sense pulsation curves U2 is constituted.It must be noted that the switch control that Fig. 4 A-4J is provided Timing is the optional way in plurality of optional control sequential, other switch control time sequences that do not list one by one are applied to figure The disclosed embodiments such as 1A-1B or Fig. 2-3 or Fig. 6-7 are also able to achieve identical function.Furthermore foregoing embodiments be with fly across For capacitor multi-electrical level inverter, the single-pole switch under high frequency control of the multi-electrical level inverter of substantial diode clamp formula Group joins together equally obtain the voltage waveform of alternating current positive half period with the above-mentioned output-stage circuit under industrial frequency control The voltage waveform U2 of the negative half period of U1 and alternating current.In summary: industrial-frequency alternating current is generated by high frequency switching switch control Multi-level inverse conversion system, comprising: generate the more of more level output voltages under the driving of the control signal with first frequency Electrical level inverter 100；Further include multi-electrical level inverter 100 is generated under the driving of the control signal with second frequency it is more Level output voltage is modulated into 101 circuit of output stage of alternating current；The second frequency of approximate power frequency is lower than first frequency.Output stage 101 are modulated into more level output voltages the mode of alternating current: in first half period in alternating current sine wave each period, such as The voltage that inverter generates is switched to by output stage 101 with one of supply lines/such as transmission line LNB by positive half period Current potential more level output voltages are generated as voltage reference, to synthesize the of output alternating current by more level output voltages One half period；And the half period such as negative in second half period in alternating current sine wave each period, it will by output stage 101 The voltage that inverter generates is switched to using the other of supply lines/such as transmission line LNA current potential and generates as voltage reference More level output voltages, so that second half period of output alternating current is synthesized by more level output voltages, first and second A half period constitutes a complete cycle.

It is shown in Figure 8, using the Flying capacitor multilevel inverter of Figure 1A-1B or Fig. 2-3 or Fig. 6-7, or utilize it His any type of multi-electrical level inverter, such as diode clamp multi-electrical level inverter, by the single armed or both arms of multi-electrical level inverter It is sinusoidal in addition to can produce the alternating current that Fig. 5 is shown according to theory described above with 101 electrical combination of output stage Also the alternating current sine wave Curve2 of Fig. 8 can also be generated except wave Curve1.In addition in optional rather than necessary embodiment, Sine wave curve U3 in Fig. 8 can also be obtained using the single armed topology of Fig. 6, while be obtained in Fig. 8 using the single armed topology of Fig. 7 Alternating current sine wave curve U4, i.e. any one complete cycle of alternating current Curve2 are by two different single armed (Fig. 6-Fig. 7 Single armed) half period (U3-U4) that generates respectively is combined into.By above explanation, can learn: such by Fig. 5 The curve U1 and the curve U2 in remaining half period for generating the half period synthesize a cycle, and U1 is positive half week Phase and U2 is negative half period；Curve U3 and the remaining half week in half period can be generated like that by Fig. 8 The curve U4 of phase synthesizes a cycle.It will be apparent that in the embodiment in fig. 8, curve U3 includes whole cycle First a quarter (t0-t2) and the negative wave for being presented as sine wave, curve U3 also include second four points of whole cycle One of (t2-t4) and be presented as the positive waveform of sine wave, curve U4 include first a quarter (t4-t6) of whole cycle simultaneously It is presented as the positive waveform of sine wave and curve U4 also includes second a quarter (t6-t8) of whole cycle and embodiment is positive The negative wave of string wave.In other alternative-embodiments, curve U3 still includes negative pulsating volage and positive pulsating volage, song Line U4 is remained on including positive pulsating volage and negative pulsating volage, and only the negative pulsating volage of curve U3 can not limit It can be not limited to a quarter period in the positive pulsating volage of a quarter period and curve U3, moreover, curve The positive pulsating volage of U4, which can be not limited to a quarter period and the negative pulsating volage of curve U4, to be limited In a quarter period, as long as the negative pulsating volage of time and curve U4 that the negative pulsating volage of curve U3 continues continue Time be added and be equal to the half period time, as long as time that the positive pulsating volage of curve U3 continues and curve U4 The time that positive pulsating volage continues, which is added, is equal to the half period time.

It is shown in Figure 8, if upper arm and second group of switch that first group of switch or series diode define or two poles of concatenation 100 single armed of multi-electrical level inverter that the lower arm that pipe defines is considered as, single armed generate more under the driving of the control signal of first frequency Level output voltage；And the first control switch Q1 and the second control switch Q2 of output stage 101 are in the control with second frequency More level output voltages are modulated into alternating current under the driving of signal or modulated signal.Such as Fig. 8, multi-electrical level inverter pass through from when Between t0 to t4 controlled by HF switch to inverter topology, can produce first half cycle curve of output of industrial-frequency alternating current U3 can produce second half cycle of industrial-frequency alternating current from time t4 to t8 also by the HF switch control to inverter topology Curve of output U4, curve U3-U4 are considered as a complete period of alternating current sinusoidal waveform Curve2.Specific: time t0 arrives T4 is controlled by the HF switch to inverter, and the first control switch Q1 for turning off output stage 101 is opened with the second control is connected Q2 is closed, then the voltage waveform that the curve U3 exported between the first output end OUT1 and second output terminal OUT2 is indicated is relative to biography First half cycle pulsating volage that defeated line LINB potential generates.On the other side, time t4 to t8 passes through the high frequency to inverter Switch control, and synchronous the first control switch Q1 for connecting output stage 101 and shutdown by the second control switch Q2, then first is defeated The voltage waveform that curve of output U4 is indicated between outlet OUT1 and second output terminal OUT2 is produced relative to transmission line LINA potential Second raw half cycle pulsating volage.

Shown in Figure 8, first half cycle pulsating volage also has direct impulse relative to the existing negative-going pulse of VR1: setting Time t0 generates the more level of first set for being lower than current potential VR1 to t1 inverter in intermediate node NX, and the time, t1 to t2 was in middle node The level more than second set for being lower than current potential VR1 is generated at point NX.It is carried out by the width of the more level of the first set being negative to opposite VR1 Modulation, obtains the equivalent U3 waveform containing amplitude and shape required for t0 to t1 period, and the width of pulse presses sinusoidal rule Variation to and the equivalent PWM waveform of alternating current sine wave be also referred to as SPWM waveform, the area of the pulsating volage of output with it is desired Inverter circuit is then adjusted by the frequency and amplitude that change modulating wave in area equation of the sine wave of output in respective bins The frequency and amplitude of output voltage.It is modulated by the width of level more than second set being negative to opposite VR1, obtains t1 to t2 The required equivalent U3 waveform containing amplitude and shape of period.It is opposite to the waveform of t1 period in t0 to be typically due to curve U3 It is more negative in the waveform of t1 to t2 period in curve U3, so at least part level ratio in the more level of first set must be made Level is more negative with respect to VR1 more than second set.

Shown in Figure 8, the curve U3 of first half cycle pulsating volage is negative in t0 to t2 with respect to VR1, with negative curved section Relatively, the curve U3 of first half cycle pulsating volage is positive in t2 to t4 with respect to VR1, i.e., positive curved section.T0 has been described above extremely The negative curved section of the U3 of t2, the positive curved section of the U3 of t2 to t4 are as follows: the width tune of more level is covered by the third being positive to opposite VR1 System, the equivalent U3 waveform containing amplitude and shape of the needs of acquisition t2 to t3 period, passes through the 4th set to be positive to opposite VR1 The width modulated of more level obtains the required equivalent U3 waveform containing amplitude and shape of t3 to t4 period.Due to curve U3 It is corrected relative to curve U3 at t2 to t3 sections at t3 to t4 sections, so usually making at least part level more than the 4th set in level It is bigger with respect to VR1 that more level are covered than third.In some alternative embodiments, by from time t0 to t4 by inverse to more level The HF switch control for becoming device single armed, first half cycle that can produce industrial-frequency alternating current to the control switching of output-stage circuit export Curve U3 generates negative sense and positive pulsating volage relative to transmission line LNB potential, in the exchange that moment t0 curve U3 is indicated The negative voltage of electric first half cycle reaches sine wave most valley-VM, be equivalent to moment t0 curve U3 voltage ratio VR1 or The low VM of VR1 absolute value.In addition reach sine wave in the forward voltage of moment t4 curve U3 first half cycle of alternating current indicated Peak value VM, also that is, moment t4 curve U3 voltage ratio VR1 or the high VM of VR1 absolute value.And as option: can be with Think that each level value chosen more than the 4th set in level takes negative value that the more level of first set can be obtained with respect to VR1, can also recognize Cover each level value in more level for selection third takes negative value that level more than second set can be obtained with respect to VR1.

Shown in Figure 8, second half cycle pulsating volage also has negative-going pulse relative to the existing direct impulse of VD1: setting Time t4 to t5 inverter generates the level more than the 5th set for being higher than current potential VD1 in intermediate node NX, and the time, t5 to t6 was in middle node The level more than the 6th set for being higher than current potential VD1 is generated at point NX.It is carried out by the width for the level more than the 5th set being positive to opposite VD1 Modulation, obtains the equivalent U4 waveform containing amplitude and shape required for t4 to t5 period, and the width of pulse presses sinusoidal rule Variation to and the equivalent PWM waveform of alternating current sine wave be also referred to as SPWM waveform, the area of the pulsating volage of output with it is desired Inverter circuit is then adjusted by the frequency and amplitude that change modulating wave in area equation of the sine wave of output in respective bins The frequency and amplitude of output voltage.It is modulated by the width of level more than the 6th set being positive to opposite VD1, obtains t5 to t6 The required equivalent U4 waveform containing amplitude and shape of period.It is opposite to the waveform of t5 period in t4 to be typically due to curve U4 It is corrected in curve U3 in the waveform of t5 to t6 period, so at least part level ratio more than the 5th set in level must be made Level is bigger with respect to VD1 more than 6th set.

Shown in Figure 8, the curve U4 of second half cycle pulsating volage is positive in t4 to t6 with respect to VD1, with positive curved section Relatively, the curve U4 of second half cycle pulsating volage is negative in t6 to t8 with respect to VD1, i.e., negative curved section.T4 has been described above extremely The positive curved section of the U4 of t6, the negative curved section of the U4 of t6 to t8 are as follows: pass through the width tune of level more than the 7th set being negative to opposite VD1 System, the equivalent U4 waveform containing amplitude and shape of the needs of acquisition t6 to t7 period, passes through the 8th set to be negative to opposite VD1 The width modulated of more level obtains the required equivalent U4 waveform containing amplitude and shape of t7 to t8 period.Due to curve U4 It is more negative at t6 to t7 sections relative to curve U4 at t7 to t8 sections, so usually making at least part level more than the 8th set in level Level is lower with respect to VD1 more than the 7th set.In some alternative embodiments, by from time t4 to t8 by inverse to more level The HF switch control of change device, second half cycle that can produce industrial-frequency alternating current to the control switching of output-stage circuit export song Line U4 generates the positively and negatively pulsating volage relative to transmission line LNA potential, in the alternating current that moment t4 curve U4 is indicated The forward voltage of second half cycle reaches the peak value VM of sine wave, and the voltage ratio VD1 or VD1 being equivalent in moment t4 curve U4 is exhausted VM high to value.In addition also reach sine wave most paddy in the negative voltage of moment t8 curve U4 second half cycle of alternating current indicated Value-VM, also that is, moment t8 curve U4 voltage ratio VR1 or the low VM of VR1 absolute value.And as option: can be with Think that each level value chosen more than the 5th set in level takes negative value that level more than the 8th set can be obtained with respect to VD1, can also recognize Take negative value that level more than the 7th set can be obtained to choose each level value more than the 6th set in level with respect to VD1.

It is shown in Figure 8, if upper arm that the first group of switch or diode group of multi-electrical level inverter define and second group are opened It is defeated to generate more level under the driving of the control signal with first frequency or modulated signal for the lower arm that pass or diode group define Voltage out；And the first control switch Q1 and the second control switch Q2 of output stage 101 with second frequency control signal or More level output voltages are modulated into alternating current under the driving of modulated signal.By from time t0 to t4 by any class The high-frequency drive of type multi-electrical level inverter generates first half cycle curve of output U3 of industrial-frequency alternating current, generates relative to transmission line The negative sense of LNB potential and positive pulsating volage, valley-VM of the curve U3 from t0 with respect to VR1 are stepped up to moment t2 curve U3 The alternating current negative sense pulsating volage of expression reaches sine wave zero crossing, the positive pulsating volage since zero point of the t2 with respect to VR1 It is stepped up peak value VM of the t4 with respect to VR1.In addition, being driven from time t4 to t8 by the HF switch to multi-electrical level inverter It can produce second half cycle curve of output U4 of industrial-frequency alternating current, generate the positively and negatively arteries and veins relative to transmission line LNA potential Dynamic voltage, peak value VM of the U4 from the t4 moment with respect to VD1 are stepped down to the alternating current forward direction pulsation electricity that moment t6 curve U4 is indicated Pressure reaches sine wave zero crossing, and also negative sense pulsating volage is stepped down to t8 since the zero point of zero crossing of the t6 with respect to VD1 Valley-VM of the moment with respect to VD1.The sine wave modulation scheme being discussed in detail by the application content above, it is known that: it is complete The cycle time section of the signal period of SIN function waveform Curve2 is t0-t8.Waveform Curve2 is synthesized by a series of U3 and U4, It is just applied to the standard sine alternating current of load from the perspective of load LD: with negative sense and positive arteries and veins on time shaft T It is to have on positively and negatively the curve U4 or time shaft T of pulsating volage waveform with just after the curve U3 of dynamic voltage waveform It is the curve U3 with negative sense and positive pulsating volage waveform after to the curve U4 with negative sense pulsating volage waveform.Curve U3 from Negative ripple voltage-transition, which is transitioned into negative ripple voltage by positive pulsating volage to positive pulsating volage and curve U4, to be connected into well Sine curve and curve U4 are transitioned into negative ripple voltage and curve U3 by negative ripple voltage-transition to positive arteries and veins by positive pulsating volage Dynamic voltage can also be connected into sine curve well, and wherein curve U3 and curve U4 are alternately present.Load one on load LD The positive pulsating volage and negative sense pulsating volage of series, which alternate interval, to be occurred, to be pulsed by the forward direction applied on load LD It can be equivalent to negative sense pulsating volage: being supplied to first half period of the SIN function Curve2 of the alternating voltage of load LD With second half period.The higher frequency of the control signal of the single-pole switch group of Flying capacitor multilevel inverter is driven to be much higher than Drive the work frequency of the control signal of the control switch Q1-Q2 of output stage.Convenience based on explanation, the application specially will The benchmark of curve U3 is set as the absolute value of VR1, if substantial transmission line LNB is clamped to the negative potential lower than zero potential, Fig. 8 The absolute value of the reference voltage VR1 of middle curve U3 can be substituted for negative value, i.e., negative sign is added before the absolute value of VR1.Default passes Defeated line LNA is above the positive potential of zero potential, and the benchmark of curve U4 is set as the positive electricity place value of VD1.If transmission line LNB and LNA Current potential be positive, then it is positive value VD1 that the reference data of curve U3, which is the reference data of positive value VR1 and curve U4, then first A half period curve U3 has negative sense on the basis of positive VR1 and positive pulsation, second half period curve U4 are with positive VD1 Benchmark has the pulsation of positive and negative sense.If the current potential of transmission line LNB and LNA are negative, curve U3 is using negative value VR1 as ginseng Benchmark and curve U4 are examined also using the VD1 of negative value as benchmark, it is meant that first half period has negative sense on the basis of negative VR1 And positive pulsation, second half period have the pulsation of positive and negative sense on the basis of negative value VD1.

It is explained for being switched referring to shown in Fig. 9 A, Fig. 3 is switched using three, upper arm with lower arm three, Fig. 4 A-4J's is more Level output scheme is substantially also applied in the inverter of more single-pole switch, actual upper and lower arms number of switches Can be higher than three in Fig. 3 or lower than three, the embodiment as shown in 9A, therefore single-pole switch quantity in multi-electrical level inverter The limitation of the present application spirit is not constituted.Electricity output is inputted and exchanged with DC voltage from the timing modulation of each embodiment From the point of view of mode, one of characteristic is: current potential of the DC input voitage equal to transmission line LNA subtracts the current potential of transmission line LNB, output The alternating current that generates or be that voltage reference generates forward direction arteries and veins using transmission line LNB current potential between the output end OUT1-OUT2 of grade 101 Punching --- Q2 connection at this time/Q1 shutdown, the alternating current of generation or be voltage reference generation negative sense arteries and veins using transmission line LNA current potential Punching --- Q1 connection at this time/Q2 shutdown.In addition the characteristic being also equipped with is: exporting among the output end OUT2 or second of alternating current Node NY is switched to the current potential of transmission line LNA at the end of the every half period of alternating current sine wave or is switched to transmission line LNB Current potential export the output end OUT2 or the second intermediate node NY of alternating current at every half week of alternating current sine wave in other words First input end IN1 or the second input terminal IN2 that connection multi-electrical level inverter receives DC input voitage are switched at the end of phase. First input end IN1 is directly coupled to transmission line LNA and the second input terminal IN2 is directly coupled to transmission line LNB.Multi-level inverse conversion The voltage reference of the output voltage of device is jumped once with the timing node that the half period of alternating current sine wave is jump, And hopping amplitude is equal to the voltage value of the input dc power of multi-electrical level inverter.Multi-electrical level inverter is provided in output voltage This current potential of intermediate node frequently jump be it is very significant, those skilled in the art both knows about, semiconductor power switch pipe It is based on the preparation of the dopant of the base and doped three races of semiconductor silicon and five races, many times in switch in current mainstream construction Body diode Body-Diode existing for parasitism is unavoidable between first end and second end namely source electrode and drain electrode.It is mostly electric It, can when the intermediate node that flat inverter provides output voltage tends to switch between transmission line LNA potential and transmission line LNB potential With by the body diode of the body diode of upper arm switch and lower arm switch under reasonable switching cycle Reverse recovery, power switch The storage charge of the body diode of pipe reasonably can be scanned out and be discharged under backward voltage effect.

Referring to shown in Fig. 9 A, in field of photovoltaic power generation, photovoltaic module in parallel again provides after usually first connecting direct current Electricity is conveyed to mostly electric from the first input end IN1 for being coupled to transmission line LNA and the second input terminal IN2 for being coupled to transmission line LNB Flat inverter, the direct current that certain photovoltaic module provides can also be to be conveyed to inverter after boost or depressurization again.Fig. 9 A and above Embodiment use 101 circuit of output stage slightly improve, it is contemplated that multi-electrical level inverter generate output voltage required for The ac output end OUT2/ i.e. intermediate node NY that persistently jumps of source of reference potential self-potential, then node NY and transmission line LNA or Control switch/reversing switch Q1-Q2 between node NY and transmission line LNB subjects the change dramatically of voltage.Substantially, excessively high The differential of current versus time or the change rate of excessively high current versus time will lead to control switch loss it is very high, another Exactly it is easy to cause the electrical failure of power switch tube.In figure 9 a, the intermediate node NY and transmission line LNA of output-stage circuit it Between originally single the first control switch Q1 can be replaced by a series of concatenated switching power tube SW1, the power tube SW1 of concatenation It can synchronize and turn on and off.Similar, script is single between the intermediate node NY and transmission line LNB of output-stage circuit second Control switch Q2 can also also be replaced by a series of concatenated switching power tube SW2, and the power tube SW2 of concatenation can synchronize connection Or shutdown.Certainly many synchronous switch SW2 as many synchronous switch SW1 of upper power tube and as lower power tube are complementary , SW1 connects SW2 shutdown or opposite SW1 shutdown and SW2 is connected, and settable dead time avoids SW1-SW2 straight-through.

Referring to shown in Fig. 9 B, it is assumed that the second input terminal of transmission line LNB/ IN2 is zero potential, and narration explanation will pass for convenience Defeated line LNA/ first input end IN1 is arranged to the DC voltage value VD2 for being input.It realizes in Fig. 9 A multi-level inverse conversion system by arteries and veins Dynamic voltage is connected the scheme at alternating current: the control signal for the first frequency that processor 110 exports drives upper arm switch and lower arm Switch promotes multi-electrical level inverter 100 to generate output voltage, the control for the second frequency that processor 110 exports in intermediate node NX Signal drives the SW2 of output stage to connect and SW1 shutdown, by multi-electrical level inverter 100 relative to taking zero the first current potential VR to generate The first pulsating volage such as curve U5 load load LD on；The control signal driving for the second frequency that processor 110 exports is defeated The SW1 of grade is connected and SW2 shutdown out, and the second pulsating volage that multi-electrical level inverter 100 is generated relative to the second current potential VD2 is such as Curve U6 load is on load LD.The first pulsating volage is the positive half cycle of alternating current in Fig. 9 B and the second pulsating volage is exchange The negative semiaxis of electricity.It is not shown, the first pulsating volage in Fig. 9 B can also be replaced still in other embodiment At first half period curve U3 for having negative sense pulsating volage and positive pulsating volage in Fig. 8, by the second pulsation in Fig. 9 B Voltage is substituted for second half period curve U4 with positive pulsating volage and negative sense pulsating volage in Fig. 8.Fig. 9 B is more straight See, curve U5 be exactly relative to zero potential positive pulsating volage and moment t2 reach peak value be VM, curve U6 is exactly opposite It is-VM in the valley that the opposite VD2 of the negative sense pulsating volage and moment t6 of VD2 reaches, the U5 and U6 of alternate intervals, which are constituted, to be applied In the standard sine alternating current curve Curve3 of load.It realizes and the first and second pulsating volages is connected into alternating current: the first arteries and veins The curve U5 that dynamic voltage indicates is in positive pulsatile change with respect to the first current potential VR, and the curve U6 of the second pulsating volage expression is with respect to the Two current potential VD2 are then negative sense pulsatile changes, and are supplied to the DC input voitage VD2 of multi-electrical level inverter and are equal in fact The absolute value of the difference or difference of two current potentials and the first current potential, so that a series of first and second pulsation of the load on load LD Voltage U5-U6, which alternates interval, to be occurred, to be equivalent to mention by the first and second pulsating volages continuously applied on load LD The positive half cycle and negative half period of the SIN function of the alternating voltage of supply load LD.Fig. 9 A can also be generated based on wave shown in Fig. 8 Shape, others realize the method by the linking of the first and second pulsating volages at alternating current: the curve U3 that the first pulsating volage indicates The curve U4 that opposite first current potential VR1 is indicated in negative sense and positive pulsatile change and the second pulsating volage is with respect to the second current potential VD1 is then to be supplied to the DC input voitage of multi-electrical level inverter in positively and negatively pulsatile change to be equal to the second current potential and the The difference of one current potential or the absolute value of difference make to load a series of first and second pulsating volages U3-U4 phase on load LD Mutual alternate intervals occur, and load the first and second pulsating volages continuously applied on LD and are equivalent to be supplied to the alternating current of load LD First half cycle and second half cycle of the SIN function of pressure.

Shown in Figure 10, in an alternate embodiment of the invention, multi-electrical level inverter 100 includes being connected in transmission line LNA and centre First group of switch or diode group between node NX, multi-electrical level inverter 100 include being connected to transmission line LNB and intermediate node Second group of switch or diode group between NX, upper bridge arm is connected between transmission line LNA and intermediate node NX and lower bridge arm connects Between transmission line LNB and intermediate node NX, it can also directly be expressed as upper and lower arms and be connected on transmission line LNA and transmission line Between LNB.The bridge arm containing upper and lower arms of Figure 1A-B1 and Fig. 3, and others Fig. 6-7 and each embodiment of Fig. 9 A contain There is the bridge arm of upper and lower arms, even without the inverter bridge leg of displaying, is suitable for the multi-electrical level inverter 100 of Figure 10, whereby Constitute the bridge arm of striding capacitance type multi-electrical level inverter.The embodiment of Figure 10 is with difference above: output stage 101 includes The the first control switch Q1 and the second control switch Q2 being connected in series between transmission line LNC and transmission line LND, if the first control Switch Q1 first end is connected to the first end phase of transmission line LNC and the second end of the first control switch Q1 and the second control switch Q2 It is connected in intermediate node NY, and the second end of the second control switch Q2 is then connected to transmission line LND.In order to avoid obscuring, transmission line LNC Transmission line is different with LNA and current potential is also different, and transmission line LND and LNB are different transmission line and current potential is also different.It provides The arm of one flying capacitor type inverter and it also have be connected on receive DC input voitage U first input end IN1 and Upper and lower arms between second input terminal IN2, and the first He being connected between third input terminal and the 4th input terminal is provided Second control switch Q1-Q2 pays attention to third input terminal namely is coupled to transmission line LNC, and the 4th input terminal namely is coupled to biography Defeated line LND, so that the first intermediate node NX between upper and lower arms at interconnection is opened with the first control switch and the second control Alternating current is exported between the second intermediate node NY between the Q1-Q2 of pass at interconnection.Wherein in first half cycle of alternating current sine wave During phase, turns off the first control switch Q1 and connect the second control switch Q2 and the second intermediate node NY is made to switch to tool There is the 4th current potential of LND, the output voltage of bridge arm generates a series of mostly electric using the 4th current potential as voltage reference whereby Flat output voltage, and the of the load by the variation of sine wave rule in load is synthesized by a series of more level output voltages The waveform U1 or U3 of one pulsating volage；Opposite, during second half period of alternating current sine wave, connect the first control Switch Q1 and turning off the second control switch Q2 makes the second intermediate node NY switch to the third current potential with LNC, bridge arm whereby Output voltage generates a series of more level output voltages using third current potential as voltage reference, and by a series of mostly electric Flat output voltage synthesizes the waveform U2 or U4 of second pulsating volage of the load changed by sine wave rule in load.Make : it loads a series of first and second pulsating volages U1-U2 or U3-U4 on load LD and alternates interval appearance, from And the first and second pulsating volages by continuously applying in load are equivalent to be supplied to the alternating voltage of load.Alternating voltage is just The first and second pulsating volages occurred in each complete cycle of string function are respectively seen as first half period and second half The pulsating volage in period.Different from Fig. 3, first input end IN1 has the second current potential and the second input terminal IN2 band in this embodiment There is the first current potential, but the third current potential that third input terminal LNC has is not equal to so-called second current potential, and the 4th input terminal The 4th current potential that LND has is not equal to so-called first current potential, and the second current potential is greater than the first current potential and third current potential is greater than the Four current potentials.

Above by the content of description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, on It states invention and proposes existing preferred embodiment, these contents are not as limitation.For a person skilled in the art, it reads After above description, various changes and modifications undoubtedly be will be evident.Therefore appended claims, which should be regarded as, covers this hair Whole variations and modifications of bright true intention and range.The model of any and all equivalences within the scope of the claim of this application book It encloses and content, is all considered as still belonging to the intent and scope of the invention.

Claims

1. a kind of multi-level converter topology structure characterized by comprising

The upper and lower arms being connected in series between the first and second input terminals for receiving DC input voitage；

The first and second control switches being connected in series between the first and second input terminals；

Wherein:

Between the first intermediate node and the first and second control switches between the upper and lower arms of bridge arm at interconnection at interconnection Alternating current is exported between two intermediate nodes.

2. multi-level converter topology structure according to claim 1, it is characterised in that:

The bridge arm includes being connected in series between the first and second input terminals for receiving DC input voitage to be considered as upper arm First group of switch and second group of switch for being considered as lower arm；And

Interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood are corresponding with second group of switch One or more capacitor is provided between interconnecting nodes between a pair of of adjacent switch.

3. multi-level converter topology structure according to claim 1, it is characterised in that:

The bridge arm includes being connected in series between the first and second input terminals for receiving DC input voitage to be considered as upper arm First group of switch and first group of diode for being considered as lower arm；And

Interconnecting nodes in first group of switch between a pair of switches of arbitrary neighborhood are corresponding with first group of diode A pair of of neighboring diode between interconnecting nodes between be provided with one or more capacitor.

4. multi-level converter topology structure according to claim 1, it is characterised in that:

The bridge arm includes being connected in series between the first and second input terminals for receiving DC input voitage to be considered as upper arm Second group of diode and second group of switch for being considered as lower arm；And

It is opposite in interconnecting nodes and second group of switch in second group of diode between a pair of diodes of arbitrary neighborhood One or more capacitor is provided between interconnecting nodes between a pair of of the adjacent switch answered.

5. multi-level converter topology structure according to claim 1, it is characterised in that:

The bridge arm generates more level output voltages under the driving of the control signal with first frequency；And

First and second control switch switches more level outputs under the driving of the control signal with second frequency The voltage reference of voltage；

Wherein the second frequency is lower than the first frequency.

6. multi-level converter topology structure according to claim 5, it is characterised in that:

In first half period in each period of the alternating current, the bridge arm is produced by first and second control switch Raw more level output voltages are switched to the first current potential using the second input terminal as voltage reference, whereby by a system The waveform for first half period that more level output voltage synthesis of column are changed by sine wave rule；And

In second half period in each period of the alternating current, the bridge arm is produced by first and second control switch Raw more level output voltages are switched to the second current potential using first input end as voltage reference, whereby by a system The waveform for second half period that more level output voltage synthesis of column are changed by sine wave rule；

Any one complete cycle of the alternating current includes first and second half period.

7. multi-level converter topology structure according to claim 6, it is characterised in that:

The waveform of first half period is rendered as positive pulsatile change relative to the first current potential, second half period Waveform is rendered as negative sense pulsatile change relative to the second current potential；And

Any one complete cycle of the alternating current includes being considered as first half period of positive half period and being considered as Second half period of negative half period.

8. multi-level converter topology structure according to claim 6, it is characterised in that:

The waveform of first half period has the part of negative sense pulsatile change relative to the first current potential and pulses with positive The waveform of the part of variation, second half period has the part of positive pulsatile change relative to the second current potential and has negative To the part of pulsatile change；And

Any one complete cycle of the alternating current includes described that positive pulsating volage is transitioned into from negative sense pulsating volage One half period and include second half period that negative sense pulsating volage is transitioned into from positive pulsating volage.

9. multi-level converter topology structure according to claim 6, it is characterised in that:

During first half period of alternating current sine wave, the first control switch is turned off and the second control switch is switched on Then second intermediate node, which switches to, is connected to the second input terminal that the bridge arm receives DC input voitage；And

During second half period of alternating current sine wave, the first control switch is switched on and the second control switch is turned off Then second intermediate node, which switches to, is connected to the first input end that the bridge arm receives DC input voitage.

10. multi-level converter topology structure according to claim 1, it is characterised in that:

The voltage reference for more level output voltages that the bridge arm generates is set as with the half of the sine wave of the alternating current A period is the bound-time node of jump in potential, in first and second half period of the complete cycle of each sine wave Each of finish time the voltage reference jump in potential it is primary；

And the hopping amplitude of voltage reference is equal to the voltage value of the DC input voitage of the bridge arm.

11. a kind of method for generating alternating current based on multi-level converter topology structure described in claim 1, feature exist In, this method comprises:

During first half period of alternating current sine wave, turn off the first control switch and connecting the second control switch makes institute It states the second intermediate node and switches to the second input terminal for being connected to the bridge arm reception DC input voitage, the bridge arm described whereby Output voltage generates a series of more level output voltages using the first current potential of the second input terminal as voltage reference, and The waveform for first half period that synthesis is changed by sine wave rule；And

During second half period of alternating current sine wave, connect the first control switch and turning off the second control switch makes institute It states the second intermediate node and switches to the first input end for being connected to the bridge arm reception DC input voitage, the bridge arm described whereby Output voltage generates a series of more level output voltages using the second current potential of first input end as voltage reference, and The waveform for second half period that synthesis is changed by sine wave rule；

12. according to the method for claim 11, it is characterised in that:

The waveform for modulating first half period makes it be rendered as positive pulsatile change relative to the first current potential, modulates described the The waveform of two half periods makes it be rendered as negative sense pulsatile change relative to the second current potential；And

13. according to the method for claim 11, it is characterised in that:

The part and have that the waveform for modulating first half period makes it relative to the first current potential with negative sense pulsatile change The part of positive pulsatile change, the waveform for modulating second half period become it with positive pulsation relative to the second current potential The part of change and part with negative sense pulsatile change；And

14. a kind of multi-level converter topology structure characterized by comprising

The upper and lower arms being connected in series between the first and second input terminals；

The first and second control switches being connected in series between the third and fourth input terminal；

The third current potential that the third input terminal has is different from the second current potential and the described 4th that the first input end has The 4th current potential that input terminal has is different from the first current potential that second input terminal has；

Wherein:

The first intermediate node and first and second control switch between the upper and lower arms of a bridge arm at interconnection Between export alternating current between the second intermediate node at interconnection.

15. multi-level converter topology structure according to claim 14, it is characterised in that:

16. multi-level converter topology structure according to claim 14, it is characterised in that:

17. multi-level converter topology structure according to claim 14, it is characterised in that:

18. multi-level converter topology structure according to claim 14, it is characterised in that:

Wherein the second frequency is lower than the first frequency.

19. multi-level converter topology structure according to claim 14, it is characterised in that:

In first half period in each period of the alternating current, the bridge arm is produced by first and second control switch Raw more level output voltages are switched to the 4th voltage reference, export electricity by a series of more level whereby It is pressed into the waveform of first half period by the variation of sine wave rule；And

In second half period in each period of the alternating current, the bridge arm is produced by first and second control switch Raw more level output voltages are switched to using third current potential as voltage reference, whereby by a series of described mostly electric The waveform for second half period that flat output voltage synthesis is changed by sine wave rule；

20. multi-level converter topology structure according to claim 19, it is characterised in that:

The waveform of first half period is rendered as positive pulsatile change relative to the 4th current potential, second half period Waveform is rendered as negative sense pulsatile change relative to third current potential；And

21. multi-level converter topology structure according to claim 19, it is characterised in that:

The waveform of first half period has the part of negative sense pulsatile change relative to the 4th current potential and pulses with positive The waveform of the part of variation, second half period has the part of positive pulsatile change relative to third current potential and has negative To the part of pulsatile change；And

22. multi-level converter topology structure according to claim 19, it is characterised in that:

During first half period of alternating current sine wave, the first control switch is turned off and the second control switch is switched on Then second intermediate node, which switches to, is connected to the 4th input terminal；And

During second half period of alternating current sine wave, the first control switch is switched on and the second control switch is turned off Then second intermediate node, which switches to, is connected to the third input terminal.

23. multi-level converter topology structure according to claim 19, it is characterised in that:

And the hopping amplitude of voltage reference is equal to the difference of the 4th current potential and third current potential.