CN109120173B

CN109120173B - Multilevel inverter topology structure

Info

Publication number: CN109120173B
Application number: CN201710482411.2A
Authority: CN
Inventors: 张永; 高波; 胡晓磊
Original assignee: Fonrich Shanghai New Energy Technology Co ltd
Current assignee: Fonrich Shanghai New Energy Technology Co ltd
Priority date: 2017-06-22
Filing date: 2017-06-22
Publication date: 2021-07-02
Anticipated expiration: 2037-06-22
Also published as: CN109120173A

Abstract

The invention mainly relates to a multi-level inverter topology structure, which comprises an upper arm and a lower arm which are connected in series between a first input end and a second input end for receiving direct-current input voltage and form a bridge arm; first and second control switches connected in series between the first and second input terminals; wherein an alternating current is output between a first intermediate node at the interconnection between the upper arm and the lower arm and a second intermediate node at the interconnection between the first and second control switches. An inverter and corresponding inversion scheme capable of achieving multi-level conversion to alternating current are provided in a topology having an inverter circuit.

Description

Multilevel inverter topology structure

Technical Field

The invention mainly relates to the technical field of inverters, in particular to a multi-level inverter topology structure capable of outputting power frequency alternating current and a corresponding inversion scheme.

Background

The power electronic technology has been widely applied to various fields requiring electric energy conversion since the birth of the fifties of the twentieth century through the rapid development of the nearly half century, and the energy conversion in the field of photovoltaic power generation is increasingly adopted to an inverter system along with the exhaustion of chemical energy and the more serious pollution to the environment in recent years. In the field of low-voltage and low-power electricity utilization, the power electronic technology becomes mature gradually, the high power density, the high efficiency and the high performance become mainstream, and the high-voltage and high-power industry and the power transmission and distribution technology become the research focus of the current power electronic technology. There is always a desire in the industry for power electronics to be able to handle higher and higher voltage levels and capacity levels. For example, high-voltage direct-current transmission in an electric power system, flexible alternating-current transmission technology represented by a static synchronous compensator, an active power filter, and the like, and large motor drive and large power supply devices represented by high-voltage frequency conversion, and the like; furthermore, in order to meet the requirement of harmonic content of output voltage, it is desirable that these high power electronic devices can operate at high switching frequency and minimize the electromagnetic interference problem. Power electronics are the core of power electronics devices, and in the past decades, power electronics have gone through several stages, including thyristors, turn-off thyristors, bipolar high power transistors, and field effect control devices. In recent years, various novel power devices, integrated gate commutated thyristors IGCT, injection enhanced gate transistors IEGT, and the like have appeared in a large number.

The various solutions and methods for high-voltage high-power conversion can be roughly classified into the following categories: the first is the series-parallel technology of power devices, which is the simplest and direct scheme, and can realize high-power conversion by using switching devices with smaller power, the devices are connected in series to bear high voltage, and the devices are connected in parallel to bear large current. The voltage-sharing circuit causes complex system control and increased loss; and even current of the device is quite difficult for most power devices with negative temperature coefficients. Meanwhile, for the series-parallel connection of the devices, the requirement of a driving circuit is greatly improved, and the delay time is required to be close to and as short as possible. During the turn-off process, due to the difference of recovery performance, a large number of absorption circuits are also necessary but the reliability of the system is reduced, and the scheme does not contribute to the improvement of the harmonic wave of the output voltage, so the application range is limited. The second inverter parallel technology is to operate a plurality of inverters with small capacity in parallel, and the number of the parallel inverters can be determined according to the capacity required by the system. The main advantages of this method are: the modularization of the inverter is easy to realize, and the capacity of the inverter system can be flexibly enlarged; the N +1 parallel redundant systems are easy to form, and the operation reliability and the system maintainability are improved. The parallel technology of the inverters has the difficulty that three technologies of voltage synchronization, steady-state and dynamic current sharing, N +1 redundancy and hot switching need to be solved from a control circuit. Third, the multiple conversion technique can also be used in order to realize large-capacity power conversion using a small-capacity power device. The multiple technology is that several small power inverters are connected in series or in parallel at their input or/and output ends via transformers, and the inverters work at the same frequency and different phases, so as to achieve the goal of high power operation and improvement of input and output harmonic waves of the system. The multiple techniques can be applied to both single-phase and three-phase circuits. The main disadvantages of the multiplex technology are: a specially designed input-output transformer is required, which not only increases the cost of the system and reduces the efficiency of the system, but also makes the design of the transformer very difficult when the number of inverters increases. Fourth, combine the inverter phase shift SPWM technique, the basic idea is: in a system composed of N-stage modules, all modules use the same modulation wave, but the triangular carrier phase difference of adjacent modules varies. The phase difference enables the SPWM pulse generated by each module to be staggered in phase, the equivalent switching frequency of the SPWM waveform finally output by the modules in a superposition mode is improved by a plurality of times, and output harmonic waves are greatly reduced under the condition that the switching frequency is not improved. In a broad sense, the phase-shifted SPWM combined inverter is also a multiple technology. Unlike the above-mentioned output voltage multiplexing, here, the triangular carrier multiplexing is used, which simplifies the design of the output transformer. The phase-shifted SPWM combined inverter has the advantages that: the high-power switching device with lower switching frequency is adopted to realize equivalent high-switching-frequency output, the switching loss is low, the output harmonic content is low, the size and the capacity of an output filter element are reduced, and the design of a transformer is simplified. The disadvantages are that a line frequency transformer is still needed, the loss and the cost are increased, and the voltage stress of a power device is not reduced. Fifth, the multilevel inverter technology is a novel inverter which realizes high-voltage and high-power output by improving the topology structure of the inverter itself, and does not need a step-up/step-down transformer and a voltage-sharing circuit. Due to the increase of the number of output voltage levels, the output waveform has better harmonic frequency spectrum, and each switching device bears smaller voltage stress.

The multilevel inverter technology has become a new research field for converting high voltage and high power into research objects in power electronics. The multilevel inverter becomes a hot spot of research on high-voltage high-power conversion because it has the following advantages: each power device only bears 1/(N-1) bus voltage, N is the level number, so that high-voltage and high-power output can be realized by using devices with low withstand voltage, and a dynamic voltage-sharing circuit is not needed; the increase of the number of the levels improves the output voltage waveform and reduces the distortion of the output voltage waveform; the lower switching frequency obtains the same output voltage waveform as the two-level inverter under the high switching frequency, so that the switching loss is small and the efficiency is high; an output transformer is not needed, so that the volume and the loss of the system are greatly reduced; the harmonic wave of the input current is reduced, and the pollution to the environment is reduced; when the neutral point voltage level regulator is used for driving a three-phase induction motor, neutral point voltage level fluctuation can be reduced or eliminated to a higher degree; the safety is higher, and the danger of short circuit of the bus is greatly reduced; multilevel inverter technology has received increasing attention and application as a representative and more ideal solution for high voltage high power conversion. The basic principle is to combine several level steps into a step wave to approach a sine wave output voltage, and generally, the higher the level number is, the higher the resolution is, which means that the output voltage waveform is closer to the sine wave. On the topology structure of an inverter circuit, a multi-level inverter has three basic topology structures such as common diode roll-over, flying capacitor, H-bridge cascade and the like.

The present application is primarily aimed at: a control scheme of a multi-level inverter fully considering output alternating current is established, a way for eliminating the defects of the existing inverter circuit is concluded based on a deduced inverter model, the measures are applied to a flying capacitor type inverter structure, feasibility of reducing common-mode current, reducing electromagnetic interference and eliminating harmonic distortion is discussed, and a mechanism for generating the alternating current is clarified through a corresponding disclosed novel inverter topological model. The voltage stress of a change-over switch in the inverter system is guaranteed to be minimized to the maximum extent, a lower total harmonic distortion rate is provided on a power frequency alternating current output waveform, meanwhile, the electromagnetic interference and weakening loss of the system are suppressed to the greatest extent, and reliable guarantee is provided for safe operation of the inverter system.

Disclosure of Invention

In one embodiment, the present invention discloses a multi-level inverter system controlled by a high-frequency switch to generate a power-frequency alternating current, comprising: the bridge arm is driven by a control signal with a first frequency to generate a multi-level output voltage; and an output stage that switches a voltage reference of the multi-level output voltage driven by a control signal having a second frequency; wherein the second frequency is lower than the first frequency; switching, by the output stage, the bridge arm to a voltage reference at a first potential and generating the multilevel output voltage by the bridge arm in a first half cycle of each cycle of the alternating current output by the multilevel inverter system, thereby synthesizing a waveform of the first half cycle varying in a sine wave rule from a series of the multilevel output voltages; and in a second half cycle of each cycle of the alternating current output by the multilevel inverter system, switching the bridge arm by the output stage to a second potential as a voltage reference and generating the multilevel output voltage by the bridge arm, thereby synthesizing a waveform of the second half cycle varying in a sine wave rule from a series of the multilevel output voltages; any one full cycle of the alternating current includes the first and second half cycles.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the waveform of the first half cycle exhibits a positive ripple change with respect to a first potential; the waveform of the second half cycle exhibits a negative going pulsatile change relative to a second potential; and any one full cycle of the alternating current includes the first half cycle considered a positive half cycle and the second half cycle considered a negative half cycle.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the waveform of the first half period has a part with negative pulsating change and a part with positive pulsating change relative to the first potential; the waveform of the second half period has a portion with positive pulsating change and a portion with negative pulsating change relative to the second potential; and any one full cycle of alternating current includes the first half-cycle transitioning from a negative-going pulsating voltage to a positive-going pulsating voltage and includes the second half-cycle transitioning from a positive-going pulsating voltage to a negative-going pulsating voltage.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the bridge arm comprises at least a first and a second group of switches connected in series between a first and a second input terminal receiving a direct current input voltage, the first and second group of switches being driven by a control signal having a first frequency; wherein the first input terminal has a second potential and the second input terminal has a first potential; and one or more capacitors are arranged between the interconnection node between any adjacent pair of the switches in the first group of switches and the interconnection node between a corresponding pair of adjacent switches in the second group of switches.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the bridge arm comprises at least a first group of switches and a first group of diodes which are connected in series between a first input end and a second input end for receiving direct-current input voltage; one or more capacitors are arranged between an interconnection node between any adjacent pair of switches in the first group of switches and an interconnection node between a corresponding pair of adjacent diodes in the first group of diodes; and/or the bridge arm comprises at least a second set of diodes and a second set of switches connected in series between a first and a second input terminal receiving the direct current input voltage; one or more capacitors are arranged between the interconnection node between any adjacent pair of diodes in the second group of diodes and the interconnection node between the corresponding pair of adjacent switches in the second group of switches; wherein a control signal having a first frequency drives the first set of switches and/or the second set of switches and the first input has a second potential and the second input has a first potential.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the output stage comprises first and second control switches connected in series between the first and second input terminals and driven by a control signal having a second frequency; wherein the first input terminal is set to have a second potential and the second input terminal is set to have a first potential; and outputting the alternating current between a first intermediate node of the bridge arm for outputting the multi-level output voltage and a second intermediate node of the output stage at the interconnection position between the first control switch and the second control switch.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: during a first half cycle of the sine wave of the alternating current, the first control switch is in an off state and the second control switch is in an on state, then the second intermediate node of the output stage switches to a second input terminal coupled to the leg that receives the direct current input voltage; and during a second half cycle of the sine wave of the alternating current, the first control switch is in an on state and the second control switch is in an off state, the second intermediate node of the output stage switching to the first input terminal coupled to the leg receiving the direct current input voltage.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the second frequency is the power frequency of the alternating current commercial power.

The above-mentioned many level inverter system who produces power frequency alternating current by high frequency change over switch control, wherein: the voltage reference of the multilevel output voltage generated by the bridge arm is set to be a jump time node which takes a half cycle of an alternating current sine wave as potential jump, the voltage reference jumps once at the end of any one of the first half cycle and the second half cycle of each cycle, and the amplitude of the potential jump of the voltage reference is equal to the value of the direct current input voltage of the bridge arm.

In one embodiment, the present invention discloses a method for controlling the generation of a power frequency alternating current by a high frequency switch in a multi-level inverter system, the multi-level inverter system having a bridge arm and an output stage, the method comprising: driving the bridge arm to generate a multilevel output voltage by using a control signal with a first frequency; driving the output stage with a control signal having a second frequency to effect switching of a voltage reference of the multilevel output voltage between first and second potentials; clamping the second frequency to a power frequency lower than the first frequency; modulating a series of multi-level output voltages generated by the bridge arm into a waveform of a first half period changing according to a sine wave rule, and during the period, forcibly switching the multi-level output voltages generated by the bridge arm to a first potential serving as a voltage reference standard by using the output stage; modulating a series of multi-level output voltages generated by the bridge arm into a waveform of a second half period changing according to a sine wave rule, and forcibly switching the multi-level output voltages generated by the bridge arm to a second potential serving as a voltage reference standard by using the output stage in the period; any one full cycle of alternating current includes the first and second half cycles.

The method described above, wherein: driving the bridge arm by using a control signal with a first frequency, so that the waveform of a sine wave modulated by the multi-level output voltage output by the bridge arm in a first half period presents positive pulse change relative to a first potential; and driving the bridge arm by using a control signal with a first frequency, so that the waveform of the sine wave modulated by the multi-level output voltage output by the bridge arm in the second half period presents negative pulse change relative to a second potential.

The method described above, wherein: driving the bridge arm by using a control signal with a first frequency, so that a sine wave modulated by the multilevel output voltage output by the bridge arm is converted into a positive pulsating voltage after the negative pulsating voltage crosses a zero point in a part with negative pulsating change and a part with positive pulsating change relative to a first potential in the waveform of the first half period; and driving the bridge arm by using a control signal with a first frequency, so that the sine wave modulated by the multilevel output voltage output by the bridge arm is converted into a negative pulsating voltage after the positive pulsating voltage crosses the zero point in a part with positive pulsating change and a part with negative pulsating change relative to a second potential in the waveform of the second half period.

The method described above, wherein: the bridge arm comprises at least a first group of switches and a second group of switches which are connected in series between a first input end and a second input end for receiving direct-current input voltage, wherein the first input end has a second potential and the second input end has a first potential; one or more capacitors are arranged between the interconnection node between any adjacent pair of the switches in the first group of switches and the interconnection node between the corresponding adjacent pair of the switches in the second group of switches, so that the bridge arm forms a bridge arm of the flying capacitor type inverter; the first and second sets of switches are driven with a control signal having a first frequency for generating a multi-level output voltage at a first intermediate node to which the first and second sets of switches are connected.

The method described above, wherein: the bridge arm comprises at least a first group of switches serving as an upper arm and a first group of diodes serving as a lower arm which are connected in series between a first input end and a second input end for receiving direct-current input voltage; one or more capacitors are arranged between an interconnection node between any adjacent pair of switches in the first group of switches and an interconnection node between a corresponding pair of adjacent diodes in the first group of diodes, so that a bridge arm of the flying capacitor type inverter is formed; and/or the bridge leg comprises at least a second set of diodes acting as upper arms and a second set of switches acting as lower arms connected in series between a first and a second input terminal receiving a direct current input voltage; one or more capacitors are arranged between the interconnection node between any adjacent pair of diodes in the second group of diodes and the interconnection node between the corresponding adjacent pair of switches in the second group of switches, so that a bridge arm of the flying capacitor type inverter is formed; wherein the first input terminal has a second potential and the second input terminal has a first potential; the first and/or second set of switches are driven with a control signal having a first frequency for generating a multi-level output voltage at a first intermediate node where the upper and lower arms of the bridge arm are connected.

The method described above, wherein: the output stage comprises first and second control switches connected in series between first and second input terminals, the first input terminal having a second potential and the second input terminal having a first potential; outputting alternating current between a first intermediate node of a bridge arm for outputting a multi-level output voltage and a second intermediate node at an interconnection between a first control switch and a second control switch of the output stage; the first and second control switches are driven with a control signal having a second frequency.

The method described above, wherein: during the first half period of the alternating current sine wave, the first control switch is turned off, the second control switch is turned on, and the second middle node of the output stage is switched to the second input end connected to the bridge arm for receiving the direct current input voltage; during a second half cycle of the ac sine wave, turning on the first control switch and turning off the second control switch switches the second intermediate node of the output stage to the first input terminal connected to the leg receiving the dc input voltage.

The method described above, wherein: the voltage reference of the multilevel output voltage generated by the bridge arm is set as a jump time node which takes a half cycle of an alternating current sine wave as potential jump, the potential of the voltage reference jumps once at each ending moment in the first half cycle and the second half cycle, and the amplitude of the potential jump is equal to the voltage value of the direct current input voltage of the bridge arm.

In one embodiment, the present invention discloses a multi-level inverter topology comprising: an upper arm and a lower arm connected in series between first and second input terminals receiving a direct current input voltage; first and second control switches connected in series between the first and second input terminals; wherein: alternating current is output between a first intermediate node at the interconnection between the upper arm and the lower arm of the bridge arm and a second intermediate node at the interconnection between the first and second control switches.

The multilevel inverter topology described above, wherein: the bridge arm comprises a first group of switches which are regarded as upper arms and a second group of switches which are regarded as lower arms, wherein the first group of switches and the second group of switches are connected in series between a first input end and a second input end which receive direct-current input voltage; and one or more capacitors are arranged between the interconnection node between any adjacent pair of the switches in the first group of switches and the interconnection node between a corresponding pair of adjacent switches in the second group of switches.

The multilevel inverter topology described above, wherein: the bridge arm comprises a first group of switches which are regarded as upper arms and a first group of diodes which are regarded as lower arms, wherein the first group of switches and the first group of diodes are connected in series between a first input end and a second input end which receive direct-current input voltage; and one or more capacitors are arranged between the interconnection node between any adjacent pair of the switches in the first group of switches and the interconnection node between the corresponding pair of adjacent diodes in the first group of diodes.

The multilevel inverter topology described above, wherein: the bridge arm comprises a second group of diodes, which are regarded as upper arms, and a second group of switches, which are regarded as lower arms, which are connected in series between a first input end and a second input end for receiving direct-current input voltage; and one or more capacitors are arranged between the interconnection node between any adjacent pair of diodes in the second group of diodes and the interconnection node between a corresponding pair of adjacent switches in the second group of switches.

The multilevel inverter topology described above, wherein: the bridge arm generates a multilevel output voltage under the driving of a control signal with a first frequency; and the first and second control switches switch the voltage reference of the multilevel output voltage driven by a control signal having a second frequency; wherein the second frequency is lower than the first frequency.

The multilevel inverter topology described above, wherein: switching, by the first and second control switches, the multilevel output voltages generated by the bridge arms to a first potential of a second input terminal as a voltage reference in a first half cycle of each cycle of the alternating current, thereby synthesizing a waveform of the first half cycle varying in a sine wave law from a series of the multilevel output voltages; and in a second half cycle of each cycle of the alternating current, switching the multilevel output voltages generated by the bridge arms to a second potential of the first input end as a voltage reference by the first and second control switches, thereby synthesizing a waveform of the second half cycle changing according to a sine wave rule from a series of the multilevel output voltages; any one full cycle of the alternating current includes the first and second half cycles.

The multilevel inverter topology described above, wherein: the waveform of the first half period presents positive pulse change relative to the first potential, and the waveform of the second half period presents negative pulse change relative to the second potential; and any one full cycle of the alternating current includes the first half cycle considered a positive half cycle and the second half cycle considered a negative half cycle.

The multilevel inverter topology described above, wherein: the waveform of the first half period has a part with negative pulsating change and a part with positive pulsating change relative to the first potential, and the waveform of the second half period has a part with positive pulsating change and a part with negative pulsating change relative to the second potential; and any one full cycle of said alternating current includes said first half cycle of a transition from a negative pulsating voltage to a positive pulsating voltage and includes said second half cycle of a transition from a positive pulsating voltage to a negative pulsating voltage.

The multilevel inverter topology described above, wherein: during a first half cycle of the alternating current sine wave, the first control switch is turned off and the second control switch is turned on such that the second intermediate node switches to a second input terminal connected to the leg receiving the direct current input voltage; and during a second half cycle of the alternating current sine wave, the first control switch is turned on and the second control switch is turned off such that the second intermediate node switches to the first input terminal connected to the leg receiving the direct current input voltage.

The multilevel inverter topology described above, wherein: the voltage reference standard of the multilevel output voltage generated by the bridge arm is set as a jump time node which takes a half cycle of a sine wave of alternating current as potential jump, and the potential of the voltage reference standard jumps once at each ending moment in a first half cycle and a second half cycle of a complete cycle of each sine wave; and the jump amplitude of the voltage reference is equal to the voltage value of the direct current input voltage of the bridge arm.

In one embodiment, the present invention also discloses a method for generating alternating current based on the above multilevel inverter topology, the method comprising: during a first half period of the alternating current sine wave, turning off the first control switch and turning on the second control switch to switch the second intermediate node to a second input end connected to the bridge arm for receiving the direct current input voltage, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking a first potential of the second input end as a voltage reference, and synthesizes a waveform of the first half period changing according to the sine wave rule; during a second half period of the alternating current sine wave, turning on the first control switch and turning off the second control switch to switch the second intermediate node to a first input end connected to the bridge arm for receiving the direct current input voltage, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking a second potential of the first input end as a voltage reference, and synthesizes a waveform of the second half period changing according to the sine wave rule; any one full cycle of alternating current includes the first and second half cycles.

The method described above, wherein: modulating the waveform of the first half cycle to exhibit a positive pulsatile change with respect to a first potential and modulating the waveform of the second half cycle to exhibit a negative pulsatile change with respect to a second potential; and any one full cycle of the alternating current includes the first half cycle considered a positive half cycle and the second half cycle considered a negative half cycle.

The method described above, wherein: modulating the waveform of the first half cycle to have a portion with a negative pulsating change and a portion with a positive pulsating change with respect to a first potential, and modulating the waveform of the second half cycle to have a portion with a positive pulsating change and a portion with a negative pulsating change with respect to a second potential; and any one full cycle of said alternating current includes said first half cycle of a transition from a negative pulsating voltage to a positive pulsating voltage and includes said second half cycle of a transition from a positive pulsating voltage to a negative pulsating voltage.

In one embodiment, the present invention discloses a multi-level inverter topology comprising: an upper arm and a lower arm connected in series between the first and second input terminals; and first and second control switches connected in series between the third and fourth input terminals; a third potential carried by the third input terminal is different from a second potential carried by the first input terminal and a fourth potential carried by the fourth input terminal is different from a first potential carried by the second input terminal; wherein: alternating current is output between a first intermediate node at the interconnection between the upper and lower arms and a second intermediate node at the interconnection between the first and second control switches, which one bridge arm has.

The multilevel inverter topology described above, wherein: switching, by said first and second control switches, said multilevel output voltages produced by said legs to a fourth voltage reference during a first half-cycle of each cycle of said alternating current, whereby a waveform of the first half-cycle varying in a sine wave law is synthesized from a series of said multilevel output voltages; and in a second half cycle of each cycle of said alternating current, switching said multilevel output voltages generated by said bridge arms by said first and second control switches to a third potential as a voltage reference, whereby a waveform of the second half cycle varying in a sine wave law is synthesized from a series of said multilevel output voltages; any one full cycle of the alternating current includes the first and second half cycles.

The multilevel inverter topology described above, wherein: the waveform of the first half period presents positive pulse change relative to a fourth potential, and the waveform of the second half period presents negative pulse change relative to a third potential; and any one full cycle of the alternating current includes the first half cycle considered a positive half cycle and the second half cycle considered a negative half cycle.

The multilevel inverter topology described above, wherein: the waveform of the first half period has a part with negative pulsating change and a part with positive pulsating change relative to a fourth potential, and the waveform of the second half period has a part with positive pulsating change and a part with negative pulsating change relative to a third potential; and any one full cycle of said alternating current includes said first half cycle of a transition from a negative pulsating voltage to a positive pulsating voltage and includes said second half cycle of a transition from a positive pulsating voltage to a negative pulsating voltage.

The multilevel inverter topology described above, wherein: during a first half cycle of the alternating current sine wave, the first control switch is turned off and the second control switch is turned on such that the second intermediate node is switched to connect to the fourth input terminal; and during a second half cycle of the alternating current sine wave, the first control switch is turned on and the second control switch is turned off so that the second intermediate node is switched to be connected to the third input terminal.

The multilevel inverter topology described above, wherein: the voltage reference standard of the multilevel output voltage generated by the bridge arm is set as a jump time node which takes a half cycle of a sine wave of alternating current as potential jump, and the potential of the voltage reference standard jumps once at each ending moment in a first half cycle and a second half cycle of a complete cycle of each sine wave; and the magnitude of the transition of the voltage reference is equal to the difference between the fourth potential and the third potential.

In one embodiment, the present invention discloses a method for connecting pulsating voltage to alternating current in a multi-level inverter system, comprising: loading a first pulsating voltage generated by the multilevel inverter with respect to a first potential on a load; loading a second pulsating voltage generated by the multilevel inverter with respect to a second potential on the load; such that: a series of first and second pulsating voltages applied to the load alternately appear at intervals from each other so that the first and second pulsating voltages successively applied to the load are equivalent to an alternating voltage supplied to the load; and the first and second ripple voltages occurring in each complete cycle of the sinusoidal function of the alternating voltage are treated as ripple voltages for a first half cycle and a second half cycle, respectively.

The method described above, wherein: the first pulsating voltage presents positive pulsating change of alternating current relative to the first potential; the second pulsating voltage presents negative pulsating change of alternating current relative to the second potential; any one full cycle of the alternating voltage comprises a first half cycle, defined as a positive half cycle, and a second half cycle, defined as a negative half cycle.

The method described above, wherein: the waveform of the first half cycle appears as a portion of alternating current with negative going pulsating changes and a portion with positive going pulsating changes relative to a first potential; the waveform of the second half cycle appears as a portion of alternating current with positive going pulsatile changes and a portion with negative going pulsatile changes relative to a second potential; and any one full cycle of said alternating current includes said first half cycle of a negative pulsating voltage to a positive pulsating voltage and includes said second half cycle of a positive pulsating voltage to a negative pulsating voltage.

The method described above, wherein: the DC input voltage supplied to the multilevel inverter is a difference between the second potential and the first potential.

The method described above, wherein: the duration of the high level continuation and the duration of the low level continuation of any one level in the multi-level output voltage generated by the multi-level inverter form a first period value; the sinusoidal function has a second period value that is greater than the first period value.

The method described above, wherein: providing a bridge arm of a flying capacitor inverter having an upper arm and a lower arm connected in series between first and second input terminals receiving a dc input voltage; providing an output stage having first and second control switches connected between first and second input terminals, and said first input terminal carrying a second potential and said second input terminal carrying a first potential; providing an alternating current between a first intermediate node at an interconnection between upper and lower arms of the leg and a second intermediate node at an interconnection between first and second control switches of the output stage: wherein: the switching mode of switching the multi-level output voltage of the bridge arm to generate a first pulsating voltage relative to a first potential and to generate a second pulsating voltage relative to a second potential is as follows: during a first half cycle of the alternating current sine wave, the processor drives the first control switch to be turned off and drives the second control switch to be turned on, and then the second intermediate node is switched to have the first potential; during a second half cycle of the ac sine wave, the processor drives the first control switch on and the second control switch off and the second intermediate node switches to the second potential.

The method described above, wherein: a time node for performing a switching jump between said first potential and said second potential with a half-cycle of a sinusoidal function of said alternating voltage, i.e. a jump of a voltage reference of said multilevel inverter once at each end of the first and second half-cycles of each complete cycle of a sine wave; and the magnitude of the potential jump of the voltage reference is equal to the voltage value of the direct current input voltage of the multi-level inverter.

In one embodiment, the present invention discloses a method for connecting pulsating voltages to alternating current in a multilevel inverter system, providing a bridge leg of a flying capacitor inverter and having an upper arm and a lower arm connected in series between first and second input terminals receiving a direct current input voltage, and providing first and second control switches connected in series between the first and second input terminals, thereby outputting alternating current between a first intermediate node at an interconnection between the upper arm and the lower arm of the bridge leg and a second intermediate node at an interconnection between the first and second control switches; the method comprises the following steps: during a first half period of the alternating current sine wave, turning off the first control switch and turning on the second control switch to switch the second intermediate node to a second input end connected to the bridge arm for receiving the direct current input voltage, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking a first potential of the second input end as a voltage reference, and synthesizes a waveform of a first pulsating voltage loaded on a load, which changes according to a sine wave rule; during the second half period of the alternating current sine wave, turning on the first control switch and turning off the second control switch to switch the second intermediate node to a first input end connected to the bridge arm for receiving the direct current input voltage, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking the second potential of the first input end as a voltage reference, and synthesizes the waveform of a second pulsating voltage loaded on the load, which changes according to the sine wave rule; such that: a series of first and second pulsating voltages applied to the load alternately appear at intervals from each other so that the first and second pulsating voltages successively applied to the load are equivalent to an alternating voltage supplied to the load; and the first and second ripple voltages occurring in each complete cycle of the sinusoidal function of the alternating voltage are treated as ripple voltages for a first half cycle and a second half cycle, respectively.

In one embodiment, the present invention discloses a method for achieving splicing of pulsating voltage into alternating current in a multilevel inverter system, providing a bridge leg of a flying capacitor inverter and having an upper arm and a lower arm connected in series between first and second input terminals receiving direct current input voltage, providing first and second control switches connected in series between third and fourth input terminals, thereby outputting alternating current between a first intermediate node at an interconnection between the upper arm and the lower arm of the bridge leg and a second intermediate node at an interconnection between the first and second control switches; the method comprises the following steps: turning off the first control switch and turning on the second control switch to switch the second intermediate node to have a fourth potential during a first half cycle of the alternating current sine wave, whereby the output voltage of the bridge arm generates a series of multi-level output voltages with the fourth potential as a voltage reference, and the series of multi-level output voltages are synthesized into a waveform of a first pulsating voltage loaded on the load which varies according to a sine wave rule; during the second half period of the alternating current sine wave, turning on the first control switch and turning off the second control switch to enable the second intermediate node to be switched to have a third potential, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking the third potential as a voltage reference standard, and the series of multi-level output voltages are synthesized into a waveform of a second pulsating voltage loaded on the load, wherein the waveform of the second pulsating voltage changes according to a sine wave rule; such that: a series of first and second pulsating voltages applied to the load alternately appear at intervals from each other so that the first and second pulsating voltages successively applied to the load are equivalent to an alternating voltage supplied to the load; and the first and second ripple voltages occurring in each complete cycle of the sinusoidal function of the alternating voltage are treated as ripple voltages for a first half cycle and a second half cycle, respectively.

The method described above, wherein: the first input terminal has a second potential and the second input terminal has a first potential; said third input terminal carries a third potential different from said second potential and said fourth input terminal carries a fourth potential different from said first potential.

The method described above, wherein: the first pulsating voltage presents positive pulsating change of alternating current relative to the fourth potential; the second pulsating voltage presents negative pulsating change of alternating current relative to a third potential; any one full cycle of the alternating voltage comprises a first half cycle, defined as a positive half cycle, and a second half cycle, defined as a negative half cycle.

The method described above, wherein: the waveform of the first half cycle presents a part with negative pulsating change and a part with positive pulsating change of the alternating current relative to a fourth potential; the waveform of the second half cycle appears as a portion of alternating current with positive going pulsatile changes and a portion with negative going pulsatile changes relative to a third potential; and any one full cycle of said alternating current includes said first half cycle of a negative pulsating voltage to a positive pulsating voltage and includes said second half cycle of a positive pulsating voltage to a negative pulsating voltage.

Drawings

The features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following drawings.

Fig. 1A to 1B are architectures of topologies employed by a conventional flying capacitor type multi-level inverter.

Fig. 2 is a multi-level inverter system for generating a commercial frequency ac power by the control of a high frequency switch.

Fig. 3 is an example of an architecture in which a multilevel inverter system is constituted by a multilevel inverter and an output stage.

Fig. 4A to 4J are schematic diagrams of multi-level output voltages generated by a multi-level inverter system.

Fig. 5 is an example of synthesizing an alternating current based on multi-level outputs generated by a multi-level inverter system.

Fig. 6 shows a multilevel inverter system with a lower diode and an output stage.

FIG. 7 is a multi-level inverter system with a multi-level inverter with an upper diode and an output stage.

Fig. 8 is a multi-level composite alternating current output by a diode-equipped multi-level inverter and output stage.

Fig. 9A to 9B illustrate an inversion system constructed by a flying capacitor multi-level inverter and a voltage-dividing output stage.

Fig. 10 shows the difference between the input voltage of the upper and lower arms of the multilevel inverter and the input voltage of the output stage.

Detailed Description

The technical solutions of the present invention will be clearly and completely explained below with reference to various embodiments, and the described embodiments are only used as illustrative embodiments of the present invention and not all embodiments, and the solutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

Referring to fig. 1A, with the rapid development of control theory, power electronics technology and semiconductor technology, a hot spot is found for a lower-cost and higher-efficiency inverter to realize that single-phase or multi-phase ac becomes power electronics, wherein a flying capacitor type multi-level inverter circuit attracts great attention in the industry and in the field of speed regulation of medium and high power ac motors, and the advantages of the inverter system are that the inverter system has small harmonic distortion and low semiconductor device stress and low electromagnetic interference. In the figure, a direct-current voltage source is provided between the transmission line LNA and the transmission line LNB, and assuming that the transmission line LNA has a potential VD and the transmission line LNB has a potential VR, the direct-current voltage output to the multi-level inverter is VD minus VR. The first group of switches SA1-SA6 and the second group of switches SB1-SB6 form one arm of the multilevel inverter, where the number of switches of each group is not limited to six but may be a greater or lesser number, wherein the switches SA1-SA6 of the first group of switches are connected in series between the transmission line LNA and an intermediate node NX, and correspondingly the switches SB1-SB6 of the second group of switches are connected in series between the intermediate node NX and the transmission line LNB. The definition switch is provided with a first end, a second end and a control end for receiving a control signal, wherein the control signal is conducted between the first end and the second end if the control switch is conducted, or the control switch is turned off, and the first end and the second end are disconnected. The positional relationship of the switches in the first group of switches SA1-SA6 is, for example: the first terminal of the first switch SA1 is connected to the transmission line LNA, the first terminal of the following switch SA2 is connected to the second terminal of its neighboring previous switch SA1, and the first terminal of the following switch SA3 is connected to the second terminal of its neighboring previous switch SA2, and so on, according to this rule, the first terminal of the following switch SA5 is connected to the second terminal of its neighboring previous switch SA4, while the first terminal of the last switch SA6 is connected to the second terminal of the switch SA5 and the second terminal of the switch SA6 is connected to the above-mentioned intermediate node NX. The first terminal of the first switch SA1 of the first group of switches SA1-SA6 is connected to the transmission line LNA and the second terminal of the last switch SA6 is connected to the intermediate node NX, the first terminal of any subsequent switch being connected to the second terminal of the adjacent previous switch. Correspondingly, the positional relationship of each switch in the second set of switches SB1-SB6 is, for example: the second end of the first switch SB1 is connected to the transmission line LNB, the second end of the following switch SB2 is connected to the first end of its adjacent previous switch SB1, and the second end of the following switch SB3 is connected to the first end of its adjacent previous switch SB2, and so on, according to this rule, the second end of the following switch SB5 is connected to the first end of its adjacent previous switch SB4, and the second end of the last switch SB6 is connected to the first end of switch SB5 and the first end of the last switch SB6 is connected to the intermediate node NX. The second terminal of the first switch SB1 of the second set of switches SB1-SB6 is connected to the transmission line LNB and the first terminal of the last switch SB6 is connected to the intermediate node NX and the second terminal of any subsequent switch is connected to the first terminal of the adjacent previous switch.

Referring to fig. 1A, the first set of switches SA1-SA6 are ordered sequentially in the topology from the first switch SA1 connected to the transmission line LNA to the switch SA6 connected to the end of the intermediate node NX, while the second set of switches SB1-SB6 are ordered sequentially in the multilevel inversion topology from the first switch SB1 connected to the transmission line LNB to the switch SB6 connected to the end of the intermediate node NX. The first switch SA1 in the first set and the first switch SB1 in the second set are complementary switches to each other, the second switch SA2 in the first set and the second switch SB2 in the second set are complementary switches, the third switch SA3 in the first set and the third switch SB3 in the second set are complementary switches, and also the fourth switch SA4 in the first set and the fourth switch SB4 in the second set are complementary, the fifth switch SA5 in the first set and the fifth switch SB5 in the second set are complementary to each other, and so on until the sixth switch SA6 in the first set and the sixth switch SB6 in the second set are defined as complementary switches, which means that one of the complementary switches is on and the other is off. As a Flying Capacitor type multilevel inverter, one or more capacitors are provided/connected between one interconnection node between any adjacent pair of switches of the first group of switches SA1-SA6 and one interconnection node between a corresponding pair of adjacent switches of the second group of switches SB1-SB6, thereby constituting a Flying Capacitor type multilevel inverter.

Referring to fig. 1A, one or more capacitors C1 are connected between an interconnection node NA1 between an adjacent pair of switches SA1-SA2 in the first set of switches and an interconnection node NB1 between a corresponding adjacent pair of switches SB1-SB2 in the second set of switches, wherein: a second terminal of switch SA1 and a first terminal of switch SA2 are connected to interconnection node NA1 and a first terminal of switch SB1 and a second terminal of switch SB2 are connected to interconnection node NB 1.

Referring to fig. 1A, one or more capacitors C2 are connected between an interconnection node NA2 between an adjacent pair of switches SA2-SA3 in the first set of switches and an interconnection node NB2 between a corresponding adjacent pair of switches SB2-SB3 in the second set of switches, wherein: a second terminal of switch SA2 and a first terminal of switch SA3 are connected to interconnection node NA2 and a first terminal of switch SB2 and a second terminal of switch SB3 are connected to interconnection node NB 2.

Referring to fig. 1A, one or more capacitors C3 are connected between an interconnection node NA3 between an adjacent pair of switches SA3-SA4 in the first set of switches and an interconnection node NB3 between a corresponding adjacent pair of switches SB3-SB4 in the second set of switches, wherein: a second terminal of switch SA3 and a first terminal of switch SA4 are connected to interconnection node NA3 and a first terminal of switch SB3 and a second terminal of switch SB4 are connected to interconnection node NB 3.

Referring to fig. 1A, one or more capacitors C4 are connected between an interconnection node NA4 between an adjacent pair of switches SA4-SA5 in the first set of switches and an interconnection node NB4 between a corresponding adjacent pair of switches SB4-SB5 in the second set of switches, wherein: a second terminal of switch SA4 and a first terminal of switch SA5 are connected to interconnection node NA4 and a first terminal of switch SB4 and a second terminal of switch SB5 are connected to interconnection node NB 4.

Referring to fig. 1A, one or more capacitors C5 are connected between an interconnection node NA5 between an adjacent pair of switches SA5-SA6 in the first set of switches and an interconnection node NB5 between a corresponding adjacent pair of switches SB5-SB6 in the second set of switches, wherein: a second terminal of switch SA5 and a first terminal of switch SA6 are connected to interconnection node NA5 and a first terminal of switch SB5 and a second terminal of switch SB6 are connected to interconnection node NB 5.

Referring to fig. 1B, slightly different from the specific embodiment of the single-arm twelve-switch/seven-level inverter circuit shown in fig. 1A, fig. 1B adopts a single arm with an adjustable switch number, where the switches of the upper arm and the lower arm are both K +1, and the topology is widely representative. The upper bridge arms SA _1 to SA _ K +1 and the lower bridge arms SB _1 to SB _ K +1 respectively form a first group of switches and a second group of switches of the flying capacitor type multi-level inverter. Fig. 1A is an example of a first set of six switches and a second set of six switches, and both the first and second sets of switches are controlled by a high frequency pulse width modulated signal/control signal PWM coupled to control terminals of the switches to switch between off and on. In fact, the number of switches of the first group and the second group is not limited to six, and a greater or lesser number of switches may be selected adaptively as shown in fig. 1B and the switches may be power switches such as IGBTs, MOSFETs or thyristors. In fig. 1B, a flying capacitor C _ K is connected between an interconnection node NA _ K between any adjacent pair of switches SA _ K and SA _ K +1 in the first set of switches and an interconnection node NB _ K between a corresponding pair of adjacent switches SB _ K and SB _ K +1 in the second set of switches, where K is a natural number. Note that of the pair of switches SA _ K and SA _ K +1 and the corresponding pair of switches SB _ K and SB _ K +1, the switch SA _ K in the first set is complementary to the switch SB _ K in the second set, and the switch SA _ K +1 in the first set is complementary to the switch SB _ K +1 in the second set. The upper bridge arms SA _1 to SA _ K +1 and the lower bridge arms SB _1 to SB _ K +1 are connected to the above-described intermediate node NX, i.e., the arm point, and the switches of the number K +1 are applied to the upper and lower bridge arms, respectively. Referring to fig. 1B, the first set of switches is ordered in the topology from the first switch SA _1 connected to the transmission line LNA to the switch SA _ K +1 connected to the end of the intermediate node NX in turn, while the second set of switches is ordered in the topology from the first switch SB _1 connected to the transmission line LNB to the switch SB _ K +1 connected to the end of the intermediate node NX in turn. A dc voltage source is input from between the transmission line LNA and the transmission line LNB, a multi-level ac current is output from the intermediate node NX, and a filter inductor LX as in fig. 1A may be further connected to the intermediate node NX. The first and second sets of switches are generally considered to constitute a single leg of a multilevel inverter, and the combination of the single legs may constitute a multi-phase inverter. Fig. 1B can realize the number of levels of K +2 since the total number of one-arm switches is twice that of K + 1.

Referring to fig. 2, in an alternative embodiment, a multi-level inverter system controlled by a high-frequency switch to generate a power-frequency ac power is disclosed, comprising: a multilevel inverter 100 generating a multilevel output voltage driven by a control signal having a first frequency; an output stage 101 for modulating the multi-level output voltage to an alternating current driven by a control signal having a second frequency. The multi-level inverter 100 may comprise the inverter single arm of fig. 1A-1B, the multi-level inverter may output voltages of multiple levels, and one of the functions of the output stage 101 is to switch the output voltages of multiple levels to proper voltage references, because the output voltages of multiple levels can only reflect the voltage levels or the level levels with relatively definite voltage references; the output stage 101 also functions to directly cross-couple the finally generated ac power with the dc input power of the inverter, so as to properly reduce the potential dc power noise interference and partially suppress the common mode interference problem of the multi-level inverter.

Referring to fig. 3, in an alternative embodiment, multilevel inverter 100 includes a first set of switches SA1-SA3 connected between transmission line LNA and intermediate node NX, and multilevel inverter 100 further includes a second set of switches SB1-SB3 connected between transmission line LNB and intermediate node NX, with upper leg SA1-SA3 connected in series between transmission line LNA and intermediate node NX and lower leg SB1-SB3 connected in series between transmission line LNB and intermediate node NX, also directly expressed as first set of switches and second set of switches connected in series between transmission line LNA and transmission line LNB. Wherein: one or more capacitors C11 are provided between an interconnection node NA1 between any adjacent pair of switches SA1-SA2 in the first set of switches and an interconnection node NB1 between a corresponding adjacent pair of switches SB1-SB2 in the second set of switches, and one or more capacitors C22 are provided between an interconnection node NA2 between any adjacent pair of switches SA2-SA3 in the first set of switches and an interconnection node NB2 between a corresponding adjacent pair of switches SB2-SB3 in the second set of switches. As described above, switches SA1-SB1 are complementary, switches SA2-SB2 are complementary, and switches SA3-SB3 are complementary, thereby constituting a flying capacitor type multilevel inverter. The output stage 101 further includes a first control switch Q1 and a second control switch Q2 connected in series between the transmission line LNA and the transmission line LNB, provided that a first terminal of the first control switch Q1 is connected to the transmission line LNA and a second terminal of the first control switch Q1 and a first terminal of the second control switch Q2 are connected to the intermediate node NY, and a second terminal of the second control switch Q2 is connected to the transmission line LNB. To avoid confusion, the intermediate node NX of the single arm of the inverting part may be set as the first intermediate node, and the intermediate node NY of the output stage may be set as the second intermediate node. It can be said that the first control switch Q1 is connected between the transmission line LNA and the intermediate node NY, and the second control switch Q2 is connected between the intermediate node NY and the transmission line LNB. The control switches Q1-Q2 and the above first and second sets of switches are power semiconductor switches having first and second terminals and a control terminal for receiving a control signal/modulation signal, the control signal corresponding to turning on the first and second terminals of the switch if controlling the switches to turn on or turning off the switches corresponding to turning off the first and second terminals of the switch, for example, the first and second terminals may be drain and source terminals of a field effect transistor or vice versa, for example, the collector and emitter of an insulated gate bipolar transistor or vice versa, of course, the anode and cathode of a thyristor or vice versa, and the control terminal of the switch may be a gate or gate terminal or the like, and the switch may be a thyristor switching device or the like. The inverter single-arm topology of fig. 3 can realize four-level inversion, and although the present application uses four levels as an example to illustrate the inventive spirit in this embodiment, it is not meant that the present application is limited to four levels only. In addition, alternating current is generated between the first output terminal OUT1 and the second output terminal OUT2 as output terminals of the output stage, note that the first output terminal OUT1 is coupled to the intermediate node NX of the single arm, the corresponding second output terminal OUT2 is coupled to the intermediate node NY of the output stage 101, and the load LD is connected between the first output terminal OUT1 and the second output terminal OUT 2. As for the semiconductor power switch, other integrated gate commutated thyristors, gate turn-off thyristors, high power transistors, electron injection enhanced gate transistors, etc. may be applied to the present invention in addition to the conventional field effect transistors.

Referring to fig. 4A, when the transmission line LNA has a potential VD1 and the transmission line LNB has a potential VR1, the dc voltage applied to the multilevel inverter is VD1 minus VR1, and the difference is equal to U. If it is assumed again that capacitors CS1-CS2, etc. are connected in series between the reference ground potential GND and the transmission line LNA, and capacitors CS3-CS4, etc. are connected in series between the reference ground potential GND and the transmission line LNB, it is equivalent to divide the dc input voltage U of the multilevel inverter into two equal parts, for example, a positive U/2 potential of the transmission line LNA with respect to the reference ground potential GND, and a negative U/2 potential of the transmission line LNB with respect to the reference ground potential GND, but still satisfies VD 1-VR 1= U. Assume that the charging of the capacitors C11-C22 establishes a voltage phase, the capacitor C11 is charged to U/2 and the capacitor C22 is charged to U/4.

Referring to fig. 4A, the combined mode of on/off switching of the single arm of the flying capacitor multi-level inverter is: SA1 in the first group of switches SA1-SA3 of the upper arm is turned off and SA2/SA3 is turned on, and SB1 in the second group of switches SB1-SB3 of the lower arm is turned on and SB2/SB3 is turned off in the corresponding complementary relationship of the upper and lower arms. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned off and the second control switch Q2 is turned on, in which mode the output level at the intermediate node NX of the multilevel inverter is about U/2 with respect to NY and the capacitor C11 is discharged. This also means that U/2 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4B, the combined mode of on/off switching of the single arm of the flying capacitor multi-level inverter is: SA1 in the first set of switches SA1-SA3 of the upper arm is turned on and SA2/SA3 is turned off, and the corresponding complementary relationship of the upper and lower arms causes SB1 in the second set of switches SB1-SB3 of the lower arm to be turned off and SB2/SB3 to be turned on. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned off and the second control switch Q2 is turned on, in which mode the output level at the intermediate node NX of the multilevel inverter is about U/2 with respect to NY and the capacitor C11 is charged. This also means that U/2 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4C, a combined switching on/off mode of a single arm of a flying capacitor multi-level inverter: SA1/SA3 in the first set of switches SA1-SA3 of the upper arm is turned on and SA2 is turned off, and the corresponding complementary relationship of the upper and lower arms causes SB1/SB3 in the second set of switches SB1-SB3 of the lower arm to be turned off and SB2 to be turned on. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned off and the second control switch Q2 is turned on, in which the output level at the intermediate node NX of the multilevel inverter is about 3 × U/4 with respect to NY, the capacitor C11 is charged but the capacitor C22 is discharged. This also means that 3 × U/4 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4D, the combined switching on/off mode of the single arm of the flying capacitor multi-level inverter is as follows: SA1/SA2 in the first set of switches SA1-SA3 of the upper arm is turned on and SA3 is turned off, and the corresponding complementary relationship of the upper and lower arms causes SB1/SB3 in the second set of switches SB1-SB3 of the lower arm to be turned off and SB3 to be turned on. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned off and the second control switch Q2 is turned on, in which the output level at the intermediate node NX of the multilevel inverter is about 3 × U/4 with respect to NY and the capacitor C22 is charged. This also means that 3 × U/4 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4E, a combined switching on/off mode of a single arm of a flying capacitor type multilevel inverter: all switches SA1/SA2/SA3 in the first set of switches SA1-SA3 of the upper arm are turned on, and all switches SB1/SB2/SB3 in the second set of switches SB1-SB3 of the lower arm are turned off in the corresponding complementary relationship of the upper and lower arms. The output stage 101 switch on/off combination mode is: the first control switch Q1 is turned off and the second control switch Q2 is turned on, and the output level at the intermediate node NX of the multilevel inverter is about U with respect to NY in this mode, which also means: u is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4F, the combined switching on/off mode of the single arm of the flying capacitor multi-level inverter is: SA1 in the first group of switches SA1-SA3 of the upper arm is turned off and SA2/SA3 is turned on, and SB1 in the second group of switches SB1-SB3 of the lower arm is turned on and SB2/SB3 is turned off in the corresponding complementary relationship of the upper and lower arms. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned on and the second control switch Q2 is turned off, in which mode the output level at the intermediate node NX of the multilevel inverter is about-U/2 with respect to NY and the capacitor C11 is discharged. This also means that a negative U/2 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4G, the combined switching on/off mode of the single arm of the flying capacitor multi-level inverter is as follows: SA1 in the first set of switches SA1-SA3 of the upper arm is turned on and SA2/SA3 is turned off, and the corresponding complementary relationship of the upper and lower arms causes SB1 in the second set of switches SB1-SB3 of the lower arm to be turned off and SB2/SB3 to be turned on. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned on and the second control switch Q2 is turned off, in which mode the output level at the intermediate node NX of the multilevel inverter is about-U/2 with respect to NY and the capacitor C11 is charged. This also means that a negative U/2 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4H, a combined switching on/off mode of a single arm of a flying capacitor type multilevel inverter: SA1/SA3 in the first set of switches SA1-SA3 of the upper arm is turned off and SA2 is turned on, and the corresponding complementary relationship of the upper and lower arms causes SB1/SB3 in the second set of switches SB1-SB3 of the lower arm to be turned on and SB2 to be turned off. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned on and the second control switch Q2 is turned off, in which the output level at the intermediate node NX of the multilevel inverter is about-3 × U/4 with respect to NY, the capacitor C11 is discharged but the capacitor C22 is charged. This also means that negative 3 × U/4 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4I, a combined switching on/off mode of a single arm of a flying capacitor type multilevel inverter: SA1/SA2 in the first set of switches SA1-SA3 of the upper arm is turned off and SA3 is turned on, and the corresponding complementary relationship of the upper and lower arms causes SB1/SB2 in the second set of switches SB1-SB3 of the lower arm to be turned on and SB3 to be turned off. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned on and the second control switch Q2 is turned off, in which the output level at the intermediate node NX of the multilevel inverter is about-3 × U/4 with respect to NY, the capacitor C11 is discharged but the capacitor C22 is charged. This also means that negative 3 × U/4 is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

Referring to fig. 4J, a combined switching on/off mode of a single arm of a flying capacitor type multilevel inverter: all switches SA1/SA2/SA3 in the first set of switches SA1-SA3 of the upper arm are turned off directly, and all switches SB1/SB2/SB3 in the second set of switches SB1-SB3 of the lower arm are turned on directly in the corresponding complementary relationship of the upper and lower arms. The combined on/off switching pattern in the output stage 101 is: the first control switch Q1 is turned on and the second control switch Q2 is turned off, and the output level at the intermediate node NX of the multilevel inverter in this mode is about-U with respect to NY. This also means that a negative U is output between the first output terminal OUT1 and the second output terminal OUT2 of the output stage.

It is noted that the on or off states of the first and second sets of switches and the control switches of the output stage are depicted in fig. 4A-4J as: if any switch is on, the on switch is not covered by the cross symbol, whereas if any switch is off, the off switch is covered by the cross symbol. Based on the timing of fig. 4A-4J, note that the on or off state of the first and second sets of switches of a single arm is essentially controlled by the output control signal or modulation signal of the microprocessor, for example: a logic device, a plurality of processors, a control device, a state machine, a controller, a chip, a software-driven control, a gate array, and/or other equivalent controller. Especially with a pulse width modulated signal PWM.

Referring to FIG. 5, looking at curve U1, the substantial curve U1 is the positive half-cycle of a full AC sine wave. The timing control scheme of fig. 4A-4J may be considered if we attempt to base the topology in fig. 3 on the intention of synthesizing this curve U1 with the output multi-level output voltage at the single-arm intermediate node NX. In a subsequent alternative, but not required, embodiment, it is contemplated that the first control switch Q1 of the output stage 101 is turned off and the second control switch Q2 is turned on, thereby outputting a voltage waveform represented by curve U1 between the first output terminal OUT1 and the second output terminal OUT 2.

Referring to fig. 5, at time points T0 to T4 on the time axis T, in conjunction with fig. 4A-4E, the sinusoidal half-wave or partial segment of the sinusoidal half-wave is replaced by a series of narrow pulses of equal amplitude but unequal width, modulated as the industry SPWM waveform-the pulse width varies sinusoidally and is equivalent to a sinusoidal PWM waveform. The output waveform U1 between the first output terminal OUT1 and the second output terminal OUT2 is to realize a multi-level output based on the potential of the intermediate node NX relative to the potential VR1 of-U/2 of the transmission line LNB as a reference, and in an alternative embodiment, the curve U1 in fig. 5 illustrates a multi-level output mechanism by generating a forward ripple by using the value of VR1 or the absolute value thereof as a reference value.

Referring to FIG. 5, at time t0 to t 1: the output level at intermediate node NX in FIG. 4A is approximately U/2 relative to NY, capacitor C11 discharging; the output level at intermediate node NX in FIG. 4B is approximately U/2 with respect to NY, and capacitor C11 charges; the output level at the intermediate node NX in FIG. 4C is approximately 3 XU/4 with respect to NY, capacitor C11 being charged but capacitor C22 being discharged; the output level at intermediate node NX in FIG. 4D is approximately 3 XU/4 with respect to NY, and capacitor C22 is charged. If intermediate node NX is pulled above potential VR1 of NY, i.e., the base potential of U/2, the additional potential at which intermediate node NX is still above NY in FIG. 4A is about 0, the additional potential at which intermediate node NX is still above NY in FIG. 4B is 0, the additional potential at which intermediate node NX is still above NY in FIG. 4C is about U/4, and the additional potential at which intermediate node NX is still above NY in FIG. 4D is about U/4. The total actual potential at the intermediate node NX above NY should be the base potential plus the extra potential at any time. The curve U1 may therefore be equivalent to: the intermediate node NX is higher than the basic potential NY and is extracted as a reference potential, and then the intermediate node NX is higher than the extra potential NY and is used as the reference potential to synthesize the curve U1. In other words, the curve U1 is a voltage waveform that exhibits a positive pulsation variation with respect to the absolute value of VR1 or VR 1. Specific implementation means, such as the curve part from time t0 to t 1: the additional potentials 0, U/4 generated by the timing sequence of FIGS. 4A-4D above, which are higher than NY at the intermediate node NX, are regarded as multi-levels, and the two values of NX higher than NY 0 and U/4 are used to switch the high frequency to obtain the segment of the curve U1 from time t0 to time t 1; and there are four switching combinations of 0 and U/4, fig. 4A is combined with fig. 4C or fig. 4A is combined with fig. 4D, fig. 4B is combined with fig. 4C or fig. 4B is combined with fig. 4D.

Referring to FIG. 5, at time t1 to t 2: the output level at the intermediate node NX in fig. 4E is about U with respect to NY; knowing that the output level at the intermediate node NX in FIG. 4C is about 3 XU/4 with respect to NY, capacitor C11 charges but capacitor C22 discharges; the output level at intermediate node NX in FIG. 4D is approximately 3 XU/4 with respect to NY, and capacitor C22 is charged. If the intermediate node NX is pulled above the potential VR1 of NY, i.e., the base potential of U/2, the additional potential at which intermediate node NX is still above NY in FIG. 4C is approximately U/4, the additional potential at which intermediate node NX is still above NY in FIG. 4D is approximately U/4, and the additional potential at which intermediate node NX is still above NY in FIG. 4E is approximately U/2. The actual potential at the intermediate node NX above NY should be the base potential plus the extra potential at any time. Thus, the curve U1 may still be equivalent to: the intermediate node NX is higher than the basic potential NY and is extracted as a reference potential, and then the intermediate node NX is higher than the extra potential NY and is used as the reference potential to synthesize the curve U1. In other words, the so-called curve U1 is essentially a voltage waveform that exhibits a positive pulsation change with respect to the absolute value of VR1 or VR 1. Specific implementation means, such as the curve part from time t1 to t 2: the additional levels U/4, U/2 created by the timing sequence corresponding to FIGS. 4C-4E described above, with those additional levels of intermediate node NX above NY being considered multi-levels, are high frequency switched by the two values of U/4 and U/2 with intermediate node NX above NY to obtain a curve segment for curve U1 between times t1 and t 2. And the switching combination of U/4 and U/2 is as follows: fig. 4C-4E or fig. 4D-4E.

Referring to FIG. 5, at time t2 to t 3: it is known that the output level of the intermediate node NX in fig. 4E is about U with respect to NY; the output level at intermediate node NX in FIG. 4C is approximately 3 XU/4 with respect to NY; the output level at the intermediate node NX in fig. 4D is about 3 × U/4 with respect to NY. If the intermediate node NX is pulled above the potential VR1 for NY, i.e., the base potential of U/2 above, the additional potential at which intermediate node NX is also above NY in FIG. 4C is approximately U/4, the additional potential at which intermediate node NX is also above NY in FIG. 4D is approximately U/4, and the additional potential at which intermediate node NX is also above NY in FIG. 4E is approximately U/2. The actual potential at the intermediate node NX above NY should be the base potential plus the extra potential at any time. Thus, the curve U1 may still be equivalent to: the intermediate node NX is higher than the basic potential NY and is extracted as a reference potential, and then the intermediate node NX is higher than the extra potential NY and is used as the reference potential to synthesize the curve U1. Specific implementation means, such as the curve part from time t2 to t 3: the additional levels U/4, U/2 created by the timing sequence of FIGS. 4C-4E described above are considered multi-levels by the additional levels U/4, U/2 of the intermediate node NX above NY, and the two values U/4 and U/2 of the intermediate node NX above NY are high frequency switched to produce the segment of the curve U1 between times t2 and t 3. And the switching combination of U/4 and U/2 is as follows: fig. 4C is combined with fig. 4E or fig. 4D is combined with fig. 4E. We will find that the multilevel levels used for the curve segment from time t2 to t3 and the curve segment from time t1 to t2 are substantially the same, because the curve segment from time t2 to t3 and the curve segment from time t1 to t2 are symmetrical, and the difference is mainly that: the greater the proportion of U/2 in the switching combination of U/4 and U/2 that is present rearwardly over time from time t1 to t2 results in the voltage waveform of curve U1 being progressively larger from time t1 to t2, and conversely, the greater the proportion of U/4 in the switching combination of U/4 and U/2 that is present rearwardly over time from time t2 to t3 results in the voltage waveform of curve U1 being progressively smaller from time t2 to t3, which may be accomplished by modulating the duty cycle.

Referring to FIG. 5, at time t3 to t 4: it is known that the output level of the intermediate node NX in FIG. 4A is about U/2 with respect to NY; the output level of the intermediate node NX of fig. 4B is about U/2 with respect to NY; the output level at intermediate node NX of FIG. 4C is approximately 3 XU/4 with respect to NY; the output level of the intermediate node NX of fig. 4D is about 3 × U/4 with respect to NY. If intermediate node NX is pulled above potential VR1 of NY, i.e., the base potential of U/2, the additional potential above NY for intermediate node NX of FIG. 4A is about 0, the additional potential above NY for intermediate node NX of FIG. 4B is 0, the additional potential above NY for intermediate node NX of FIG. 4C is about U/4, and the additional potential above NY for intermediate node NX of FIG. 4D is about U/4. The actual potential at the intermediate node NX above NY should be the base potential plus the extra potential at any time. Thus, the curve U1 may still be equivalent to: the intermediate node NX is higher than the basic potential NY and is extracted as a reference potential, and then the intermediate node NX is higher than the extra potential NY and is used as the reference potential to synthesize the curve U1. Specific implementation means, such as the curve part from time t3 to t 4: the additional potentials 0, U/4 generated by the timing sequence of FIGS. 4A-4D above, which are considered multi-level, are higher than NY at the intermediate node NX, and can be high-frequency switched from two values of NX higher than NY, 0 and U/4, to obtain a segment of the curve U1 from time t3 to t 4; and there are four switching combinations of 0 and U/4, fig. 4A is combined with fig. 4C or fig. 4A is combined with fig. 4D, fig. 4B is combined with fig. 4C or fig. 4B is combined with fig. 4D. We will find that the multilevel used for the curve segment from time t3 to t4 and the curve segment from time t0 to t1 are substantially the same, because the curve segment from time t3 to t4 and the curve segment from time t0 to t1 are symmetrical, and they are distinguished mainly by: the greater the proportion of U/4 in the 0 and U/4 switching combination as time progresses backward from time t0 to t1, which results in the curve U1 voltage waveform being progressively longer from time t0 to t1, and conversely, the greater the proportion of 0 in the 0 and U/4 switching combination as time progresses backward from time t3 to t4, which results in the curve U1 voltage waveform being progressively smaller from time t3 to t 4.

With reference to fig. 5, by driving the topology of fig. 3 from time t0 to t4, an alternating current voltage waveform curve U1 is generated between the first output terminal OUT1 and the second output terminal OUT2 of the output stage 101, in particular a positive half cycle of alternating current appearing to pulsate in a forward direction with respect to the potential VR1 of the transmission line LNB: the time t0 to t2 are the rising interval of the positive half cycle of the alternating current, and the time t2 to t4 are the falling interval of the positive half cycle of the alternating current. Synthesizing a local curve of t0-t1 of the alternating current curve U1 by high-frequency switching of levels 0, U/4 relative to the absolute value of the high potential VR1 or the high potential VR 1; synthesizing a local curve of t1-t2 of an alternating current curve U1 by high-frequency switching of levels U/4 and U/2 of an absolute value of a high potential VR1 or a high potential VR 1; and synthesizing a local curve of t2-t3 of the alternating current curve U1 by high-frequency switching of levels U/4, U/2 of the absolute value of the high potential VR1 or the high potential VR 1; in addition, a local curve of the alternating current curve U1 over a time period t3 to t4 is synthesized by high-frequency switching of the levels 0, U/4 of the absolute value of the high potential VR1 or the high potential VR 1. Therefore, we consider that: in the positive half cycle of each cycle of the alternating current, the output stage 101 switches the multilevel output voltage generated by the multilevel inverter 100 to the positive half cycle of the output alternating current generated from the output terminal OUT1-OUT synthesized with the potential carried by the power supply line/transmission line LNB as a voltage reference, and the forward pulsating voltage generated by the multilevel inverter with respect to the potential of the power supply line/transmission line LNB is applied to the load LD.

Referring to FIG. 5, looking at curve U2, the substantial curve U2 is the negative half cycle of a full AC sine wave. The timing control schemes of fig. 4F-4J may be considered if we attempt to synthesize the curve U2 with the output multi-level output voltage at the single-arm intermediate node NX based on the topology of fig. 3. In a subsequent alternative, but not required, embodiment, it is contemplated that the first control switch Q1 of the output stage 101 is turned on and the second control switch Q2 is turned off, thereby outputting a voltage waveform represented by curve U2 between the first output terminal OUT1 and the second output terminal OUT 2.

Referring to fig. 5, at time points T4 to T8 on the time axis T, in conjunction with fig. 4F-4J, the sinusoidal half-wave or partial segment of the sinusoidal half-wave is replaced by a series of narrow pulses of equal amplitude but unequal width, modulated as the industry SPWM waveform-the pulse width varies sinusoidally and is equivalent to a sinusoidal PWM waveform. The output waveform U2 between the first output terminal OUT1 and the second output terminal OUT2 is a multi-level output based on the potential of the intermediate node NX relative to the potential VD1 of U/2 of the transmission line LNA as a reference, and in an alternative embodiment, the curve U2 in fig. 5 illustrates a multi-level output mechanism by generating a negative ripple by using the value of VD1 or the absolute value thereof as a reference value.

Referring to FIG. 5, at time t4 to t 5: the output level at intermediate node NX in FIG. 4F is approximately-U/2 with respect to NY, capacitor C11 discharging; FIG. 4G shows the output level at intermediate node NX at approximately-U/2 with respect to NY and the charging of capacitor C11; the output level at intermediate node NX of FIG. 4H is approximately-3 XU/4 with respect to NY, capacitor C11 discharging but capacitor C22 charging; the output level at intermediate node NX in FIG. 4I is approximately-3 XU/4 with respect to NY, and capacitor C22 discharges. If the intermediate node NX is pulled below the potential VD1 for NY, i.e., the base potential of U/2, the additional potential at which intermediate node NX is still below NY in FIG. 4F is about 0, the additional potential at which intermediate node NX is still below NY in FIG. 4G is 0, the additional potential at which intermediate node NX is still below NY in FIG. 4H is about U/4, and the additional potential at which intermediate node NX is still below NY in FIG. 4I is about U/4. The total actual potential at which the intermediate node NX is lower than NY should be the base potential plus the extra potential at any time. Thus, the curve U2 may be equivalent to: the base potential at which the intermediate node NX is lower than NY is extracted as a reference potential, and then the additional potential at which the intermediate node NX is lower than NY is used to synthesize the curve U2. In other words, the curve U2 is a voltage waveform that exhibits negative going pulsatile changes relative to the value of VD1 or the absolute value of VD 1. Specific implementation means, such as the curve part from time t4 to t 5: the additional potential at the intermediate node NX below NY is considered multi-level, and the high frequency switching from two values (0 and-U/4) of NX below NY 0 and U/4 results in the segment of curve U2 from time t4 to t 5. And there are four switching combinations of 0 and-U/4, fig. 4F in combination with this fig. 4H or fig. 4F in combination with fig. 4I, fig. 4G in combination with fig. 4H or fig. 4G in combination with fig. 4I.

Referring to FIG. 5, at time t5 to t 6: the output level at the intermediate node NX in fig. 4J is about-U with respect to NY; knowing that the output level at the intermediate node NX in FIG. 4H is about-3 XU/4 with respect to NY, capacitor C11 is discharged but capacitor C22 is charged; the output level at intermediate node NX in FIG. 4I is approximately-3 XU/4 with respect to NY, and capacitor C22 is discharged. If the intermediate node NX is pulled below the potential VD1 for NY, i.e., the base potential of U/2, the additional potential for intermediate node NX in FIG. 4H is still below NY by about U/4, the additional potential for intermediate node NX in FIG. 4I is still below NY by about U/4, and the additional potential for intermediate node NX in FIG. 4J is still below NY by about U/2. The total actual potential at the intermediate node NX below the NY should be the base potential plus the extra potential at any time. Thus, the curve U2 may still be equivalent to: the base potential at which the intermediate node NX is lower than NY is extracted as a reference potential, and then the additional potential at which the intermediate node NX is lower than NY is used to synthesize the curve U2. In other words, the so-called curve U2 is essentially a voltage waveform that exhibits a negative pulsating change with respect to the absolute value of VD1 or VD 1. Specific implementation means, such as the curve part from time t5 to t 6: the additional potentials at intermediate nodes NX below NY, which are considered multi-level, are generated as multi-levels U/4, U/2 by the above-described timings of FIGS. 4H-4J, and the high-frequency switching from two values (-U/4 and-U/2) at intermediate nodes NX below U/4 and U/2 of NY results in a curve segment of curve U2 lying between time periods t5 and t 6. And the switching combination of-U/4 and-U/2 is as follows: the level values of fig. 4H and 4J are used to combine the switching or the level values of fig. 4I and 4J are used to combine the switching.

Referring to FIG. 5, at time t6 to t 7: it is known that the output level at the intermediate node NX of FIG. 4J is approximately-U with respect to NY; it is known that the output level at the intermediate node NX in FIG. 4H is about-3 XU/4 with respect to NY; the output level at the intermediate node NX in FIG. 4I is approximately-3 XU/4 with respect to NY. If we first deduct that the intermediate node NX is lower than the base potential of the potential VD1 carried by NY, i.e., U/2, the additional potential at which the intermediate node NX is still lower than NY in FIG. 4H is about U/4, the additional potential at which the intermediate node NX is still lower than NY in FIG. 4I is about U/4, and the additional potential at which the intermediate node NX is still lower than NY in FIG. 4J is about U/2. The total actual potential at the intermediate node NX below the NY should be the base potential plus the extra potential at any time. Thus, the curve U2 may still be equivalent to: the base potential of the intermediate node NX lower than the intermediate node NY is extracted as a reference potential, and then the additional potential of the intermediate node NX lower than NY is synthesized into a curve U2 with the reference potential. In other words, the so-called curve U2 is essentially a voltage waveform that exhibits a negative pulsating change with respect to the value of VD1 or with respect to the absolute value of VD 1. Implementation, the curve portion of time t6 to t 7: the time sequences corresponding to FIGS. 4H-4J produce multiple levels U/4, U/2 of additional potentials, with intermediate node NX being lower than NY, these additional potentials being considered as multiple levels, with the segment of curve U2 lying between time periods t6 and t7 being high frequency switched from two values (-U/4 and-U/2) of intermediate node NX being lower than U/4 and U/2 of NY. Based on the above explanation, it can be seen that the switching combinations of-U/4 and-U/2 are: the level values of fig. 4H and 4J are used to combine switching or the level values of fig. 4I and 4J are used to combine switching. The multilevel levels used for the curve segment at time t5 to t6 and the curve segment at time t6 to t7 were found to be substantially the same, because the curve segment at time t5 to t6 and the curve segment at time t6 to t7 are symmetrical, with the difference that: the greater the proportion of-U/2 in the switching combinations of-U/4 and-U/2 as time goes backward from time t5 to t6, the smaller the proportion of-U/2 in the switching combinations of-U/4 and-U/2, the smaller the voltage waveform of curve U2 as time goes backward from time t5 to t6, and conversely, the greater the proportion of-U/4 in the switching combinations of-U/4 and-U/2 as time goes backward from time t6 to t7, the larger the voltage waveform of curve U2 as time t6 to t7, can be achieved by modulating the duty cycle.

Referring to FIG. 5, at time t7 to t 8: it is known that the output level at the intermediate node NX in FIG. 4F is about-U/2 with respect to NY; FIG. 4G shows an output level at intermediate node NX of approximately-U/2 with respect to NY; and the output level at intermediate node NX of FIG. 4H is approximately-3 XU/4 with respect to NY; the output level at intermediate node NX in FIG. 4I is approximately-3 XU/4 with respect to node NY. If the intermediate node NX is pulled below the potential VD1 for NY, i.e., the base potential of U/2, the additional potential at which intermediate node NX is still below NY in FIG. 4F is about 0, the additional potential at which intermediate node NX is still below NY in FIG. 4G is 0, the additional potential at which intermediate node NX is still below NY in FIG. 4H is about U/4, and the additional potential at which intermediate node NX is still below NY in FIG. 4I is about U/4. The total actual potential at which the intermediate node NX is lower than NY should be the base potential plus the extra potential at any time. Thus, the curve U2 may be equivalent to: the base potential at which the intermediate node NX is lower than NY is extracted as a reference potential, and then the additional potential at which the intermediate node NX is lower than NY is used to synthesize the curve U2. In other words, the curve U2 is a voltage waveform that exhibits negative going pulsatile changes with respect to the value of VD1 or with respect to the absolute value of VD 1. Implementation, e.g., the curve portion from time t7 to t 8: the additional potential at the intermediate node NX below NY is considered multi-level corresponding to the additional potential levels 0, U/4 created by the timing of FIGS. 4F-4I. The implementation scheme is as follows: switching at high frequency from two values of 0 and U/4 (0 and-U/4) with NX lower than NY results in a segment of the curve U2 at time t7 to t 8. And there are four switching combinations of 0 and-U/4, fig. 4F is combined with fig. 4H or fig. 4F is combined with fig. 4I, or fig. 4G is combined with fig. 4H or fig. 4G is combined with fig. 4I. It was found that the multilevel levels used for the curve segments from time t4 to t5 and from time t7 to t8 are substantially the same, and the curve segments from time t4 to t5 and from time t7 to t8 are symmetrical, differing mainly in that: moving backwards in time from time t4 to t5, the greater the proportion of-U/4 in the switching combination of-U/4 and 0, so the smaller the curve U2 voltage waveform at time t4 to t5, and conversely moving backwards in time from time t7 to t8, the smaller the proportion of-U/4 in the switching combination of-U/4 and 0, so the larger the curve U2 voltage waveform at time t7 to t8, can be achieved by modulating the duty cycle.

With reference to fig. 5, by driving the topology of fig. 3 from time t4 to t8, an alternating current voltage waveform curve U2 is generated between the first output terminal OUT1 and the second output terminal OUT2 of the output stage 101, in particular an alternating current negative half cycle that appears as a negative ripple with respect to the potential VD1 of the transmission line LNA: the time t4 to t6 is a falling interval of the negative half cycle of the alternating current, and the time t6 to t8 is a rising interval of the negative half cycle of the alternating current. Synthesizing a local curve of t4-t5 of the alternating current curve U2 by high-frequency switching of levels 0 and-U/4 which are relatively lower than the potential VD1 or lower than the absolute value of the potential VD 1; synthesizing a local curve of t5-t6 of the alternating current curve U2 by high-frequency switching of levels-U/4 and-U/2 which are lower than the absolute value of the potential VD1 or the potential VD 1; and synthesizing a local curve of t6-t7 of the alternating current curve U2 by high-frequency switching of levels-U/4 and-U/2 lower than the potential VD1 or lower than the absolute value of the potential VD 1; the local curves of the alternating current curve U2 over the time period t7-t8 are synthesized by high-frequency switching of the levels 0 and-U/4 below the potential VD1 or below the absolute value of the potential VD 1. Therefore, we consider that: in the negative half cycle of each cycle of the alternating current, the output stage 101 switches the multilevel output voltage generated by the multilevel inverter 100 to the negative half cycle of the output alternating current generated from the output terminal OUT1-OUT synthesized with the potential carried by the power supply line/transmission line LNA as a voltage reference, and the load LD is applied with a negative pulsating voltage generated by the multilevel inverter with respect to the potential of the power supply line/transmission line LNA.

Referring to fig. 5, a first group of switches SA1-SA3 and a second group of switches SB1-SB3 of the multilevel inverter are arranged to generate a multilevel output voltage under the driving of a control signal or a modulation signal with a first frequency; and the first and second control switches Q1 and Q2 of the output stage 101 modulate the multi-level output voltage into alternating current driven by a control signal or modulation signal having a second frequency. After the time t0 to t4, the positive half-cycle output curve U1 of the power frequency alternating current can be generated through the high-frequency switch control of the topology shown in the figure 3, namely, the forward pulsating voltage relative to the transmission line LINB potential is generated, the curve U1 is gradually increased from the zero crossing point/zero value of t0 relative to VR1 to the time t2, the forward pulsating voltage of the alternating current represented by the curve U1 reaches the maximum value VM of a sine wave, and is gradually reduced from the peak value of t2 relative to VR1 to the zero crossing point of t 4. In addition, from time t4 to t8, through controlling the high-frequency switch of the topology shown in fig. 3, a negative half-cycle output curve U2 of the power-frequency alternating current can be generated, namely, a negative pulsating voltage relative to the potential of the transmission line LINA is generated, the U2 gradually decreases from a zero-crossing point/zero value of the curve U2 at the time t4 relative to VD1 to a zero-crossing point-VM of the curve U2 at the time t8, and also gradually increases from a valley value of the curve t6 relative to VD1 to a zero-crossing point of the curve t 8. With the sine wave modulation scheme described in detail above in this application, it can be seen that: the cycle time period of a single cycle of the complete sine function waveform Curve1 is t0-t 8. The waveform Curve1 is synthesized by a series of U1 and U2, which is a standard sinusoidal alternating current applied to the load from the point of view of the load LD: a positive ripple voltage, i.e., the curve U1, is followed by a negative ripple voltage, i.e., the curve U2, or, a negative ripple voltage, i.e., the curve U2 is followed by a positive ripple voltage, i.e., the curve U1, and the curve U1 and the curve U2 alternately appear on the time axis T. A series of positive pulsating voltages and negative pulsating voltages applied to the load LD alternately appear, so that the positive pulsating voltages and the negative pulsating voltages applied to the load LD in succession are equivalent to: the positive and negative half cycles of the sine function Curve1 of the ac voltage supplied to the load LD. The high-frequency of the control signals for driving the single-arm switch groups SA1-SA3 and SB1-SB3 of the flying capacitor inverter is far higher than the power frequency of the control signals for driving the control switches Q1-Q2 of the output stage circuit. In addition, for the sake of explanation, the present application intentionally sets the reference of the curve U1 to the absolute value of VR1, and if the transmission line LNB is clamped to a negative potential lower than zero, the absolute value of the reference VR1 of the curve U1 in fig. 5 may be replaced by a negative value, that is, the absolute value of VR1 is preceded by a negative sign. Accordingly, the transmission line LNA defaults to a positive potential higher than zero for ease of explanation, and the reference of the curve U2 is set to a positive value of VD 1. If the transmission lines LNB and LNA are both positive, the reference of the curve U1 is positive VR1 and the reference of the curve U2 is positive VD1, which also means that the positive half cycle is pulsed positive with positive VR1 and the negative half cycle is pulsed negative with positive VD 1. If the potentials of the transmission lines LNB and LNA are both negative potentials, the curve U1 takes the negative value VR1 as a reference and the curve U2 takes the negative value VD1 as a reference, meaning that the positive half cycle is pulsed positively with the negative VR1 as a reference and the negative half cycle is pulsed negatively with the negative VD1 as a reference.

Referring to fig. 6, the flying capacitor multilevel inverter described above in fig. 3 is switched to another topology: specifically in this implementation, the upper arm still includes the first set of switches S11-S13 as in fig. 3, but the lower arm replaces the original second set of switches with a series string of diodes in series. The multilevel inverter 100 comprises a first set of switches S11-S13 connected between the transmission line LNA and the intermediate node NX1, while the multilevel inverter 100 further comprises a first set of diodes D11-D13 connected between the transmission line LNB and the intermediate node NX1, the upper leg S11-S13 being connected in series between the transmission line LNA and the intermediate node NX1 and the lower leg D11-D13 being connected in series between the transmission line LNB and the intermediate node NX1, which can be directly expressed as the first set of switches and the first set of diodes being connected in series between the transmission line LNA and the transmission line LNB. One or more capacitances C11 are provided between the interconnection node NS11 between any adjacent pair of switches S11-S12 in the first set of switches and the interconnection node ND11 between a corresponding adjacent pair of diodes D11-D12 in the first set of diodes, and one or more capacitances C22 are provided between the interconnection node NS12 between any adjacent pair of switches S12-S13 in the first set of switches and the interconnection node ND12 between a corresponding adjacent pair of diodes D12-D13 in the first set of diodes. As described above, the switch S11 is complementary to the diode D11, the switch S12 is complementary to the diode D12, and the switch S13 is complementary to the diode D13, thereby constituting the flying capacitor type multilevel inverter. The output stage 101 may be kept in part consistent with the embodiment of fig. 3. Note that the anode of the first diode D11 of the first group of diodes D11-D13 is connected to the transmission line LNB and the cathode of the last diode D13 is connected to the intermediate node NX1, and the first group of diodes D11-D13 are connected in series with the anode of any subsequent diode connected to the cathode of the adjacent previous diode. In addition, a filter inductance LX may be connected between the one-arm intermediate node NX1 and the first output terminal OUT1, and a filter capacitance CO may be connected between the first and second output terminals OUT1-OUT 2. The control or modulation of the first set of switches S11-S13 of the single arm of fig. 6 and the upper arm switches of fig. 3 is substantially similar, but the lower arm diodes D11-D13 of the single arm of fig. 6 do not need to be controlled to turn off/on.

Referring to fig. 7, the flying capacitor multilevel inverter described above in fig. 3 is switched to another topology: specifically in this implementation, the lower arm still includes the second set of switches S21-S23 as in fig. 3, but the upper arm replaces the original first set of switches with a series string of diodes in series. The multilevel inverter 100 comprises a second set of switches S21-S23 connected between the transmission line LNB and the intermediate node NX2, while the multilevel inverter 100 further comprises a second set of diodes D21-D23 connected between the transmission line LNA and the intermediate node NX2, the upper leg D21-D23 being connected in series between the transmission line LNA and the intermediate node NX2 and the lower leg S21-S23 being connected in series between the transmission line LNB and the intermediate node NX2, which can be directly expressed as the second set of diodes and the second set of switches being connected in series between the transmission line LNA and the transmission line LNB. One or more capacitances C11 are provided between the interconnection node NS21 between any adjacent pair of switches S21-S22 in the second set of switches and the interconnection node ND21 between a corresponding adjacent pair of diodes D21-D22 in the second set of diodes, and one or more capacitances C22 are provided between the interconnection node NS22 between any adjacent pair of switches S22-S23 in the second set of switches and the interconnection node ND22 between a corresponding adjacent pair of diodes D22-D23 in the second set of diodes. As described above, switch S21 is complementary to diode D21, switch S22 is complementary to diode D22, and switch S23 is complementary to diode D23, forming a single arm of the flying capacitor type multilevel inverter. The output stage 101 may remain consistent with the embodiment of fig. 3. Note that the cathode of the first diode D21 of the second group of diodes D21-D23 is connected to the transmission line LNA and the anode of the last diode D23 is connected to the intermediate node NX2, and the second group of diodes D21-D23 are connected in series with the cathode of any subsequent diode connected to the anode of the adjacent previous diode. In addition, a filter inductance LX may be connected between the one-arm intermediate node NX2 and the first output terminal OUT1, and a filter capacitance CO may be connected between the first and second output terminals OUT1-OUT 2. The control or modulation of the second set of switches S21-S23 of the single arm of fig. 7 is substantially similar to the lower arm switches of fig. 3, but the upper arm diodes D21-D23 of the single arm of fig. 7 need not be controlled to turn off/on. In an alternative embodiment the multilevel inverter may comprise both the single-arm of fig. 6 and the single-arm of fig. 7, and then the two single-arms of fig. 6-7 in combination with the output stage circuit comprising the control switches Q1-Q2 form a multilevel inverter system.

Referring to fig. 6-7, the topology of fig. 6 and/or the topology of fig. 7 and the combination of the two topologies may also generate the voltage waveform U1 of the positive half-cycle and the voltage waveform U2 of the negative half-cycle in fig. 5, and further generate the ac sine wave Curve1 composed of the positive pulsation Curve U1 and the negative pulsation Curve U2. It should be noted that the switch control sequences shown in fig. 4A-4J are but one of many alternative control sequences, and that other switch control sequences not listed may be used in the embodiments disclosed in fig. 1A-1B or fig. 2-3 or fig. 6-7 to achieve the same function. In addition, the above embodiments take a flying capacitor multilevel inverter as an example, and the one-arm switch group under high frequency control of the diode-clamped multilevel inverter can also obtain the voltage waveform U1 of the positive half period of the alternating current and the voltage waveform U2 of the negative half period of the alternating current in combination with the output stage circuit under power frequency control. In summary, the following steps: the multi-level inverter system for generating power frequency alternating current by controlling a high-frequency switch comprises: a multilevel inverter 100 generating a multilevel output voltage driven by a control signal having a first frequency; further comprising an output stage 101 circuit for modulating the multi-level output voltage generated by the multi-level inverter 100 into alternating current driven by a control signal having a second frequency; the second frequency is lower than the first frequency. The way in which the output stage 101 modulates the multilevel output voltage into alternating current: in a first half period, such as a positive half period, of each cycle of the alternating current sine wave, the voltage generated by the inverter is switched by the output stage 101 to generate a multilevel output voltage with one of the power supply lines/e.g., the potential of the transmission line LNB as a voltage reference, so that the first half period of the alternating current is output by the multilevel output voltage synthesis; and in a second half period, e.g. a negative half period, of each cycle of the alternating current sine wave, the output stage 101 switches the voltage generated by the inverter to the potential of another one of the power supply lines, e.g. the transmission line LNA, as a voltage reference to generate a multilevel output voltage, whereby the second half period of the alternating current is output from the multilevel output voltage synthesis, the first and second half periods constituting a complete cycle.

Referring to fig. 8, in addition to the ac sine wave Curve1 shown in fig. 5, an ac sine wave Curve2 shown in fig. 8 can be generated by combining a single arm or dual arms of a multi-level inverter with the output stage 101 circuit, as shown in fig. 1A-1B, 2-3 or 6-7, or by using any other type of multi-level inverter, such as a diode-clamped multi-level inverter. In an alternative, but not required, embodiment, the single-arm topology of fig. 6 may be used to obtain the sinusoidal Curve U3 in fig. 8, and the single-arm topology of fig. 7 may be used to obtain the ac sinusoidal Curve U4 in fig. 8, that is, any one complete cycle of the ac Curve2 is formed by combining half cycles (U3-U4) generated by two different single arms (the single arms of fig. 6-7), respectively. From the above explanation, it can be learned that: synthesizing one cycle by the curve U1 producing one-half cycle and the curve U2 remaining one-half cycle as in fig. 5, U1 being the positive half cycle and U2 being the negative half cycle; one cycle can be synthesized by the curve U3 that generates one-half cycle and the curve U4 that generates the remaining one-half cycle as in fig. 8. It is however apparent that in the embodiment of fig. 8, the curve U3 contains the first quarter of the entire cycle (t 0-t 2) and represents the negative waveform of a sine wave, the curve U3 also contains the second quarter of the entire cycle (t 2-t 4) and represents the positive waveform of a sine wave, the curve U4 contains the first quarter of the entire cycle (t 4-t 6) and represents the positive waveform of a sine wave and the curve U4 also contains the second quarter of the entire cycle (t 6-t 8) and represents the negative waveform of a sine wave. In other alternative embodiments, curve U3 still contains a negative ripple voltage and a positive ripple voltage, curve U4 also still contains a positive ripple voltage and a negative ripple voltage, except that the negative ripple voltage of curve U3 may not be limited to one-quarter of a cycle and the positive ripple voltage of curve U3 may not be limited to one-quarter of a cycle, and the positive ripple voltage of curve U4 may not be limited to one-quarter of a cycle and the negative ripple voltage of curve U4 may not be limited to one-quarter of a cycle, as long as the sum of the time that the negative ripple voltage of curve U3 extends and the time that the negative ripple voltage of curve U4 extends equals the half cycle time, as long as the time that the positive ripple voltage of curve U3 extends and the time that the positive ripple voltage of curve U4 extends equals the sum of the half cycle time.

Referring to fig. 8, assuming that the upper arm defined by the first group of switches or cascode diodes and the lower arm defined by the second group of switches or cascode diodes are regarded as a single arm of the multilevel inverter 100, the single arm generates a multilevel output voltage under the driving of the control signal with the first frequency; and the first and second control switches Q1 and Q2 of the output stage 101 modulate the multi-level output voltage into alternating current driven by a control signal or modulation signal having a second frequency. Referring to fig. 8, the multilevel inverter can generate a first half-cycle output Curve U3 of the power frequency alternating current through high-frequency switching control of the inverter topology from time t0 to t4, and can generate a second half-cycle output Curve U4 of the power frequency alternating current through high-frequency switching control of the inverter topology from time t4 to t8, wherein the curves U3-U4 are regarded as a complete cycle of the alternating current sinusoidal waveform Curve 2. Specifically, the method comprises the following steps: by switching the inverter at a high frequency at times t0 to t4 and turning off the first control switch Q1 and on the second control switch Q2 of the output stage 101, the voltage waveform represented by the curve U3 output between the first output terminal OUT1 and the second output terminal OUT2 is the first half cycle pulsating voltage generated with respect to the transmission line LINB potential. In contrast, the time t4 to t8 is controlled by high frequency switching of the inverter and synchronously turns on the first control switch Q1 of the output stage 101 and turns off the second control switch Q2, and the voltage waveform represented by the output curve U4 between the first output terminal OUT1 and the second output terminal OUT2 is the second half cycle pulsating voltage generated with respect to the transmission line LINA potential.

Referring to fig. 8, the first half cycle ripple voltage has both negative and positive pulses with respect to VR 1: setting the time t0 to t1 the inverter produces a first set of multi-levels at the intermediate node NX that is lower than the potential VR1, and the time t1 to t2 produces a second set of multi-levels at the intermediate node NX that is lower than the potential VR 1. The method is characterized in that the width of a first set of multi-level which is negative relative to VR1 is modulated to obtain an equivalent U3 waveform containing amplitude and shape required in a time period from t0 to t1, the width of a pulse is changed according to a sine rule, so that a PWM waveform equivalent to an alternating current sine wave is also called an SPWM waveform, the area of output pulsating voltage is equal to the area of the sine wave expected to be output in a corresponding interval, and the frequency and the amplitude of the output voltage of an inverter circuit can be adjusted by changing the frequency and the amplitude of the modulation wave. The desired equivalent U3 waveform, including amplitude and shape, for the t1 to t2 time period is obtained by modulating the width of the second set of multilevel, which is negative with respect to VR 1. Since the waveform of the curve U3 is generally more negative during the time period t0 to t1 relative to the waveform of the curve U3 during the time period t1 to t2, at least a portion of the levels in the first set of multi-levels must be made more negative than the levels in the second set of multi-levels relative to VR 1.

Referring to fig. 8, the curve U3 of the first half cycle pulsating voltage is negative with respect to VR1 at t0 to t2, and the curve U3 of the first half cycle pulsating voltage is positive with respect to VR1 at t2 to t4, i.e., a positive curve segment, as opposed to a negative curve segment. The above describes the U3 negative curve segment from t0 to t2, and the U3 positive curve segment from t2 to t4 is: the desired equivalent U3 waveform with amplitude and shape for the t2 to t3 time period is obtained by width modulation of the third set of multilevel positive with respect to VR1, and the desired equivalent U3 waveform with amplitude and shape for the t3 to t4 time period is obtained by width modulation of the fourth set of multilevel positive with respect to VR 1. Since the curve U3 is more positive during the segment t3 to t4 relative to the curve U3 during the segment t2 to t3, at least some of the levels in the fourth set of multi-levels are typically made larger than the levels in the third set of multi-levels relative to VR 1. In some alternative embodiments, the output curve U3 of the first half-cycle of the mains-frequency alternating current is generated by switching the control of the high-frequency switches of the single arm of the multilevel inverter, the control of the output stage circuit, from time t0 to time t4, i.e. generating a negative and a positive pulsating voltage with respect to the potential of the transmission line LNB, the negative voltage of the first half-cycle of the alternating current represented by curve U3 at time t0 reaching the lowest sine wave-VM, corresponding to the voltage of curve U3 at time t0 being lower by VM than the absolute value of VR1 or VR 1. The forward voltage of the first half cycle of the alternating current shown by curve U3 at time t4 reaches the peak value VM of the sine wave, i.e. the voltage of curve U3 at time t4 is equal to VM higher than the absolute value of VR1 or VR 1. And as an option: it can be considered that the first set of multi-levels can be obtained by selecting the negative value of each level value in the fourth set of multi-levels relative to VR1, and it can also be considered that the second set of multi-levels can be obtained by selecting the negative value of each level value in the third set of multi-levels relative to VR 1.

Referring to fig. 8, the second half cycle pulsating voltage has both positive and negative pulses with respect to VD 1: setting the time t4 to t5 the inverter generates the fifth set of multi-levels higher than the potential VD1 at the intermediate node NX, and the time t5 to t6 generates the sixth set of multi-levels higher than the potential VD1 at the intermediate node NX. The method is characterized in that the width of a fifth set of multi-level signals which are positive relative to VD1 is modulated to obtain an equivalent U4 waveform containing amplitude and shape required in a time period from t4 to t5, the width of a pulse is changed according to a sine rule, so that a PWM waveform equivalent to an alternating current sine wave is also called an SPWM waveform, the area of an output pulsating voltage is equal to the area of a sine wave expected to be output in a corresponding interval, and the frequency and the amplitude of the output voltage of an inverter circuit can be adjusted by changing the frequency and the amplitude of a modulation wave. The desired equivalent U4 waveform, including amplitude and shape, for the t5 to t6 time period is obtained by modulating the width of the sixth set of multilevel, positive with respect to VD 1. Since the waveform of the curve U4 is generally more positive during the time period t4 to t5 than during the time period t5 to t6 than the waveform of the curve U3, at least a portion of the levels in the fifth set of multilevel levels must be made larger than the levels in the sixth set of multilevel levels relative to VD 1.

Referring to fig. 8, the curve U4 of the second half cycle pulsating voltage is positive with respect to VD1 from t4 to t6, as opposed to a positive curve segment, and the curve U4 of the second half cycle pulsating voltage is negative with respect to VD1 from t6 to t8, i.e., a negative curve segment. The above describes the U4 positive curve segment from t4 to t6, and the U4 negative curve segment from t6 to t8 is: the required equivalent U4 waveform with amplitude and shape for the t6 to t7 time period is obtained by the seventh set of multilevel width modulations that are negative with respect to VD1, and the required equivalent U4 waveform with amplitude and shape for the t7 to t8 time period is obtained by the eighth set of multilevel width modulations that are negative with respect to VD 1. Since the curve U4 is more negative in the segment t7 to t8 relative to the curve U4 in the segment t6 to t7, at least some of the levels in the eighth set of multilevel levels are typically made lower than the seventh set of multilevel levels relative to VD 1. In some alternative embodiments, the output curve U4 of the second half-cycle of the ac power frequency may be generated by controlling the high-frequency switches of the multilevel inverter and the control of the output stage circuit from time t4 to t8, i.e., generating positive and negative pulsating voltages with respect to the transmission line LNA potential, the positive voltage of the second half-cycle of the ac power represented by curve U4 at time t4 reaches the peak VM of a sine wave, corresponding to the voltage of curve U4 at time t4 being higher than the absolute value VM of VD1 or VD 1. In addition, the negative voltage of the second half cycle of the alternating current, which curve U4 represents at time t8, reaches the sine wave trough-VM, i.e. the voltage of curve U4 at time t8 is equal to VM, which is lower than the absolute value of VR1 or VR 1. And as an option: it can be considered that the eighth set of multi-levels can be obtained by selecting each level value of the fifth set of multi-levels to take a negative value relative to VD1, and it can also be considered that the seventh set of multi-levels can be obtained by selecting each level value of the sixth set of multi-levels to take a negative value relative to VD 1.

Referring to fig. 8, an upper arm defined by a first group of switches or diodes and a lower arm defined by a second group of switches or diodes of the multilevel inverter are driven by a control signal or a modulation signal having a first frequency to generate a multilevel output voltage; and the first and second control switches Q1 and Q2 of the output stage 101 modulate the multi-level output voltage into alternating current driven by a control signal or modulation signal having a second frequency. After the output curve U3 of the first half cycle of the power frequency alternating current is generated through high-frequency driving of any type of multi-level inverter from time t0 to t4, negative and positive pulsating voltages relative to the potential of the transmission line LNB are generated, the curve U3 is gradually increased from the valley value-VM of t0 relative to VR1 to the time t2, the curve U3 shows that the negative pulsating voltage of the alternating current reaches the zero crossing point of a sine wave, and the positive pulsating voltage is gradually increased from the zero crossing point of t2 relative to VR1 to the peak value VM of t4 relative to VR 1. In addition, the output curve U4 of the second half cycle capable of generating power frequency alternating current by the high-frequency switch driving of the multilevel inverter from the time t4 to the time t8 generates positive and negative pulsating voltages relative to the potential of the transmission line LNA, the curve U4 gradually decreases from the peak value VM of the curve U4 at the time t4 relative to the VD1 to the time t6, the positive pulsating voltage of the alternating current represented by the curve U4 reaches the zero crossing point of a sine wave, and the negative pulsating voltage gradually decreases from the zero crossing point of the curve T6 relative to the VD1 to the valley value-VM of the curve V at the time t8 relative to the VD 1. With the sine wave modulation scheme detailed above in this application, it can be seen that: the cycle time period of a single cycle of the complete sine function waveform Curve2 is t0-t 8. The waveform Curve2 is synthesized by a series of U3 and U4, which is a standard sinusoidal alternating current applied to the load from the point of view of the load LD: the curve U3 with the negative and positive ripple voltage waveforms on the time axis T is followed by the curve U4 with the positive and negative ripple voltage waveforms, or the curve U4 with the positive and negative ripple voltage waveforms on the time axis T is followed by the curve U3 with the negative and positive ripple voltage waveforms. The curve U3 can be well connected into a sine curve when the curve U3 is changed from a negative pulsating voltage to a positive pulsating voltage and the curve U4 is changed from a positive pulsating voltage to a negative pulsating voltage, and the curve U4 is changed from a positive pulsating voltage to a negative pulsating voltage and the curve U3 is changed from a negative pulsating voltage to a positive pulsating voltage, wherein the curve U3 and the curve U4 appear alternately. A series of positive and negative pulsating voltages applied to the load LD alternately occur, so that the positive and negative pulsating voltages applied to the load LD can be equivalent to: the first half-cycle and the second half-cycle of the sinusoidal function Curve2 of the alternating voltage supplied to the load LD. The high frequency of the control signal driving the single-arm switch group of the flying capacitor multi-level inverter is much higher than the power frequency of the control signal driving the control switches Q1-Q2 of the output stage. For convenience of explanation, the present application intentionally sets the reference of the curve U3 to the absolute value of VR1, and in essence the absolute value of the reference voltage VR1 of the curve U3 in fig. 8 may be replaced by a negative value, i.e., the absolute value of VR1 plus the negative sign, if the transmission line LNB is clamped to a negative potential lower than zero. The default transmission line LNA is at a positive potential above zero, and the reference of the curve U4 is set to the positive potential value of VD 1. If the transmission lines LNB and LNA are both positive in potential, the reference of the curve U3 is positive VR1 and the reference of the curve U4 is positive VD1, then the first half-cycle curve U3 has negative and positive ripples based on positive VR1, and the second half-cycle curve U4 has positive and negative ripples based on positive VD 1. If the transmission lines LNB and LNA are both negative, the curve U3 is referenced to a negative VR1 and the curve U4 is also referenced to a negative VD1, meaning that the first half cycle has negative and positive ripple referenced to a negative VR1 and the second half cycle has positive and negative ripple referenced to a negative VD 1.

Referring to fig. 9A, fig. 3 is explained by taking three switches in the upper arm and three switches in the lower arm as an example, the multi-level output scheme of fig. 4A-4J can also be applied to an inverter with more single-arm switches, and the number of actual upper and lower arm switches can be higher than three or lower than three in fig. 3, as in the embodiment shown in fig. 9A, therefore, the number of single-arm switches in the multi-level inverter does not form a limitation to the spirit of the present invention. From the viewpoint of the timing modulation and the manner of dc voltage input and ac power output of the various embodiments, one of the characteristics is: the direct current input voltage is equal to the potential of the transmission line LNA minus the potential of the transmission line LNB, the alternating current generated between the output ends OUT1-OUT2 of the output stage 101 generates a positive pulse by taking the potential of the transmission line LNB as a voltage reference, at which time Q2 is turned on/Q1 is turned off, and the generated alternating current generates a negative pulse by taking the potential of the transmission line LNA as a voltage reference, at which time Q1 is turned on/Q2 is turned off. Further, the method has the following characteristics: the output OUT2 or the second intermediate node NY from which the alternating current is output is switched to the potential of the transmission line LNA or to the potential of the transmission line LNB at the end of each half cycle of the alternating current sine wave, or IN other words, the output OUT2 or the second intermediate node NY from which the alternating current is output is switched to the first input IN1 or the second input IN2 connected to the multilevel inverter to receive the direct current input voltage at the end of each half cycle of the alternating current sine wave. The first input IN1 is directly coupled to the transmission line LNA and the second input IN2 is directly coupled to the transmission line LNB. The voltage reference of the output voltage of the multi-level inverter jumps once by taking a half cycle of the alternating current sine wave as a jumping time node, and the jumping amplitude is equal to the voltage value of the input direct current of the multi-level inverter. It is significant that such frequent potential jumps of the intermediate node of the multilevel inverter providing the output voltage are significant, and it is known to those skilled in the art that the current mainstream structure of the semiconductor power switch is prepared based on silicon-based doping of iii-group and v-group dopants, and a Body-Diode parasitic between the first end and the second end of the switch, i.e., the source and the drain, is unavoidable in many cases. When the intermediate node of the multi-level inverter for providing the output voltage tends to switch between the transmission line LNA potential and the transmission line LNB potential, the body diode of the upper arm switch and the body diode of the lower arm switch can be reversely recovered under a reasonable switching period, and the stored charges of the body diode of the power switch tube can be reasonably swept out and released under the action of the reverse voltage.

Referring to fig. 9A, IN the field of photovoltaic power generation, the dc power provided by the photovoltaic modules, which are usually connected IN series and then connected IN parallel, is supplied to the multilevel inverter from the first input terminal IN1 coupled to the transmission line LNA and the second input terminal IN2 coupled to the transmission line LNB, although the dc power provided by the photovoltaic modules may be boosted or reduced IN voltage and then supplied to the inverter. The output stage 101 circuit of fig. 9A and the above embodiments is slightly improved, and considering that the reference potential required for the output voltage generated by the multilevel inverter is derived from the ac output terminal OUT 2/i.e. the intermediate node NY, which is continuously jumping from potential, the control switches/commutate switches Q1-Q2 between the node NY and the transmission line LNA or between the node NY and the transmission line LNB are subject to a sharp change in voltage. In essence, too high a voltage-to-time differential or a too high voltage-to-time rate of change can result in very high losses in the control switch, and can also result in electrical damage to the power switching tube. In fig. 9A, the first control switch Q1 between the intermediate node NY of the output stage circuit and the transmission line LNA may be replaced by a series of switching power transistors SW1, and the series of power transistors SW1 may be turned on or off synchronously. Similarly, the second control switch Q2 between the intermediate node NY of the output stage circuit and the transmission line LNB may be replaced by a series of switching power transistors SW2, and the series of power transistors SW2 may be turned on or off synchronously. Of course, the synchronous switches SW1 as the upper power transistor and SW2 as the lower power transistor are complementary, with SW1 being on and SW2 being off or conversely SW1 being off and SW2 being on, and dead time is set to avoid SW1-SW2 going through.

Referring to fig. 9B, assuming that the transmission line LNB/second input terminal IN2 is at zero potential, the transmission line LNA/first input terminal IN1 is set to the dc voltage value VD2 that is an input for convenience of description. Fig. 9A illustrates a scheme for implementing the engagement of pulsating voltages into ac in a multi-level inverter system: the control signal of the first frequency output by the processor 110 drives the upper arm switch and the lower arm switch to cause the multi-level inverter 100 to generate an output voltage at the intermediate node NX, the control signal of the second frequency output by the processor 110 drives the SW2 of the output stage to be turned on and the SW1 to be turned off, and a first pulsating voltage generated by the multi-level inverter 100 relative to the first potential VR which is zero, such as a curve U5, is applied to the load LD; the control signal of the second frequency output by the processor 110 drives the SW1 of the output stage to turn on and the SW2 to turn off, so that the second pulsating voltage generated by the multilevel inverter 100 relative to the second potential VD2, such as the curve U6, is applied to the load LD. In fig. 9B the first ripple voltage is the positive half cycle of the alternating current and the second ripple voltage is the negative half-axis of the alternating current. Although not shown, in an alternative embodiment, the first ripple voltage in fig. 9B may be replaced by the first half-cycle curve U3 with negative ripple voltage and positive ripple voltage in fig. 8, and the second ripple voltage in fig. 9B may be replaced by the second half-cycle curve U4 with positive ripple voltage and negative ripple voltage in fig. 8. As can be seen from the comparison of fig. 9B, Curve U5 is a positive ripple voltage with respect to zero potential and reaches a peak value VM at time t2, Curve U6 is a negative ripple voltage with respect to VD2 and reaches a valley value-VM at time t6 with respect to VD2, and the alternating intervals of U5 and U6 form a standard sinusoidal alternating current Curve3 applied to the load. The first and second ripple voltages are connected to an alternating current: the curve U5 represented by the first pulsating voltage shows a positive pulsating change with respect to the first potential VR, the curve U6 represented by the second pulsating voltage shows a negative pulsating change with respect to the second potential VD2, and the dc input voltage VD2 supplied to the multilevel inverter is substantially equal to the absolute value of the difference or difference between the second potential and the first potential, so that a series of first and second pulsating voltages U5-U6 applied to the load LD alternately appear, whereby the first and second pulsating voltages successively applied to the load LD are equivalent to the positive half cycle and the negative half cycle of the sine function of the ac voltage supplied to the load LD. Fig. 9A may also generate waveforms based on fig. 8, and other methods of implementing the joining of the first and second ripple voltages to ac: the curve U3 represented by the first pulsating voltage is pulsating in negative and positive directions with respect to the first potential VR1, and the curve U4 represented by the second pulsating voltage is pulsating in positive and negative directions with respect to the second potential VD1, the dc input voltage supplied to the multilevel inverter is equal to the absolute value of the difference or difference between the second potential and the first potential, so that a series of the first and second pulsating voltages U3-U4 applied to the load LD alternately appear, and the first and second pulsating voltages continuously applied to the load LD are equivalent to the first half cycle and the second half cycle of the sine function of the ac voltage supplied to the load LD.

Referring to fig. 10, in an alternative embodiment, the multi-level inverter 100 includes a first set of switches or diode sets connected between the transmission line LNA and the intermediate node NX, the multi-level inverter 100 includes a second set of switches or diode sets connected between the transmission line LNB and the intermediate node NX, an upper arm connected between the transmission line LNA and the intermediate node NX and a lower arm connected between the transmission line LNB and the intermediate node NX, which can also be directly expressed as an upper arm and a lower arm connected in series between the transmission line LNA and the transmission line LNB. The bridge arms of fig. 1A-B1 and 3 with upper and lower arms, as well as the other bridge arms of the embodiments of fig. 6-7 and 9A with upper and lower arms, even the inverter bridge arms not shown, are suitable for use in the multilevel inverter 100 of fig. 10, thereby forming the bridge arms of the flying capacitor type multilevel inverter. The embodiment of fig. 10 differs from the above in that: the output stage 101 includes a first control switch Q1 and a second control switch Q2 connected in series between the transmission line LNC and the transmission line LND, a first terminal of the first control switch Q1 is connected to the transmission line LNC and a second terminal of the first control switch Q1 and a first terminal of the second control switch Q2 are connected to the intermediate node NY, and a second terminal of the second control switch Q2 is connected to the transmission line LND. To avoid confusion, the transmission lines LNC and LNA are different transmission lines and different potentials, and the transmission lines LND and LNB are different transmission lines and different potentials. An arm of a flying capacitor inverter is provided and has upper and lower arms connected IN series between a first input terminal IN1 receiving a dc input voltage U and a second input terminal IN2, and first and second control switches Q1-Q2 connected IN series between a third input terminal coupled to transmission line LNC and a fourth input terminal coupled to transmission line LND, whereby alternating current is output between a first intermediate node NX at the interconnection between the upper and lower arms and a second intermediate node NY at the interconnection between the first and second control switches Q1-Q2. Wherein during a first half cycle of the ac sine wave, turning off the first control switch Q1 and turning on the second control switch Q2 causes said second intermediate node NY to switch to a fourth potential having LND, whereby the output voltage of the leg generates a series of multi-level output voltages with the fourth potential as a voltage reference, and the waveform U1 or U3 of the first pulsating voltage applied to the load varying in sine wave law is synthesized from the series of multi-level output voltages; in contrast, during the second half cycle of the ac sine wave, turning on the first control switch Q1 and turning off the second control switch Q2 switches the second intermediate node NY to the third potential having LNC, whereby the output voltage of the bridge arm generates a series of multi-level output voltages with the third potential as a voltage reference, and the waveform U2 or U4 of the second pulsating voltage applied to the load, which varies in accordance with the sine wave law, is synthesized from the series of multi-level output voltages. Such that: a series of first and second pulsating voltages U1-U2 or U3-U4 applied to the load LD alternately occur at intervals from each other so that the first and second pulsating voltages successively applied from the load are equivalent to an alternating voltage supplied to the load. The first and second ripple voltages occurring in each complete cycle of the sinusoidal function of the alternating voltage are considered to be ripple voltages for the first half cycle and the second half cycle, respectively. Unlike fig. 3, IN this embodiment, the first input terminal IN1 carries the second potential and the second input terminal IN2 carries the first potential, but the third input terminal LNC carries the third potential not equal to the so-called second potential and the fourth input terminal LND carries the fourth potential not equal to the so-called first potential, the second potential is greater than the first potential and the third potential is greater than the fourth potential.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. It is therefore intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims of the present application should be considered to be within the intent and scope of the present invention.

Claims

1. A multi-level inverter topology, comprising:

an upper arm and a lower arm connected in series between first and second input terminals receiving a direct current input voltage;

first and second control switches connected in series between the first and second input terminals;

wherein:

outputting alternating current between a first intermediate node at an interconnection between upper and lower arms of a bridge arm and a second intermediate node at an interconnection between first and second control switches;

the bridge arm generates a multilevel output voltage under the driving of a control signal with a first frequency; and

the first and second control switches switch a voltage reference of the multilevel output voltage driven by a control signal having a second frequency;

wherein the second frequency is lower than the first frequency;

switching, by the first and second control switches, the multilevel output voltages generated by the bridge arms to a first potential of a second input terminal as a voltage reference in a first half cycle of each cycle of the alternating current, thereby synthesizing a waveform of the first half cycle varying in a sine wave law from a series of the multilevel output voltages; and

in a second half period of each cycle of the alternating current, switching the multilevel output voltages generated by the bridge arms to a second potential of the first input end as a voltage reference by the first and second control switches, thereby synthesizing a waveform of the second half period changing in a sine wave rule from a series of the multilevel output voltages;

the second potential is greater than the first potential;

any one full cycle of said alternating current comprises said first and second half cycles;

the waveform of the first half period presents positive pulse change relative to the first potential, and the waveform of the second half period presents negative pulse change relative to the second potential; and

any one full cycle of the alternating current includes the first half cycle considered a positive half cycle and the second half cycle considered a negative half cycle.

2. The multilevel inverter topology of claim 1, wherein:

the bridge arm comprises a first group of switches which are regarded as upper arms and a second group of switches which are regarded as lower arms, wherein the first group of switches and the second group of switches are connected in series between a first input end and a second input end which receive direct-current input voltage; and

one or more capacitors are arranged between the interconnection node between any adjacent pair of the switches in the first group of switches and the interconnection node between a corresponding adjacent pair of the switches in the second group of switches.

3. The multilevel inverter topology of claim 1, wherein:

the bridge arm comprises a first group of switches which are regarded as upper arms and a first group of diodes which are regarded as lower arms, wherein the first group of switches and the first group of diodes are connected in series between a first input end and a second input end which receive direct-current input voltage; and

one or more capacitors are arranged between an interconnection node between any adjacent pair of the switches in the first group of switches and an interconnection node between a corresponding pair of adjacent diodes in the first group of diodes.

4. The multilevel inverter topology of claim 1, wherein:

the bridge arm comprises a second group of diodes, which are regarded as upper arms, and a second group of switches, which are regarded as lower arms, which are connected in series between a first input end and a second input end for receiving direct-current input voltage; and

one or more capacitors are arranged between an interconnection node between any adjacent pair of diodes in the second set of diodes and an interconnection node between a corresponding pair of adjacent switches in the second set of switches.

5. The multilevel inverter topology of claim 1, wherein:

during a first half cycle of the alternating current sine wave, the first control switch is turned off and the second control switch is turned on such that the second intermediate node switches to a second input terminal connected to the leg receiving the direct current input voltage; and

during a second half cycle of the ac sine wave, the first control switch is turned on and the second control switch is turned off and the second intermediate node switches to the first input terminal connected to the leg receiving the dc input voltage.

6. The multilevel inverter topology of claim 1, wherein:

the voltage reference of the multilevel output voltage generated by the bridge arm is set as a jump time node which takes a half cycle of the sine wave of the alternating current as potential jump, and the potential of the voltage reference jumps once at each ending moment in the first half cycle and the second half cycle of the complete cycle of each sine wave;

and the jump amplitude of the voltage reference is equal to the voltage value of the direct current input voltage of the bridge arm.

7. A method for generating alternating current based on a multilevel inverter topology, the multilevel inverter topology comprising: an upper arm and a lower arm connected in series between first and second input terminals receiving a direct current input voltage; first and second control switches connected in series between the first and second input terminals; wherein alternating current is output between a first intermediate node at an interconnection between upper and lower arms of the bridge arm and a second intermediate node at an interconnection between the first and second control switches;

the method comprises the following steps:

during a first half period of the alternating current sine wave, turning off the first control switch and turning on the second control switch to switch the second intermediate node to a second input end connected to the bridge arm for receiving the direct current input voltage, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking a first potential of the second input end as a voltage reference, and synthesizes a waveform of the first half period changing according to the sine wave rule; and

during a second half period of the alternating current sine wave, turning on the first control switch and turning off the second control switch to switch the second intermediate node to a first input terminal connected to the bridge arm for receiving the direct current input voltage, so that the output voltage of the bridge arm generates a series of multi-level output voltages by taking a second potential of the first input terminal as a voltage reference, and synthesizes a waveform of the second half period changing according to the sine wave rule;

the second potential is greater than the first potential;

modulating the waveform of the first half cycle to exhibit a positive pulsatile change with respect to a first potential and modulating the waveform of the second half cycle to exhibit a negative pulsatile change with respect to a second potential; and

8. A multi-level inverter topology, comprising:

an upper arm and a lower arm connected in series between the first and second input terminals;

first and second control switches connected in series between the third and fourth input terminals;

a third potential carried by the third input terminal is different from a second potential carried by the first input terminal and a fourth potential carried by the fourth input terminal is different from a first potential carried by the second input terminal;

wherein:

outputting an alternating current between a first intermediate node at an interconnection between the upper and lower arms of one bridge arm and a second intermediate node at an interconnection between the first and second control switches;

switching, by said first and second control switches, said multilevel output voltages produced by said legs to a fourth voltage reference during a first half-cycle of each cycle of said alternating current, whereby a waveform of the first half-cycle varying in a sine wave law is synthesized from a series of said multilevel output voltages; and

switching, by said first and second control switches, said multilevel output voltages generated by said bridge arms to a third potential as a voltage reference during a second half-cycle of each cycle of said alternating current, whereby a waveform of the second half-cycle varying in a sine wave law is synthesized from a series of said multilevel output voltages;

the third potential is greater than the fourth potential;

the waveform of the first half period presents positive pulse change relative to a fourth potential, and the waveform of the second half period presents negative pulse change relative to a third potential; and

9. The multilevel inverter topology of claim 8, wherein:

10. The multilevel inverter topology of claim 8, wherein:

11. The multilevel inverter topology of claim 8, wherein:

12. The multilevel inverter topology of claim 8, wherein:

wherein the second frequency is lower than the first frequency.

13. The multilevel inverter topology of claim 8, wherein:

during a first half cycle of the alternating current sine wave, the first control switch is turned off and the second control switch is turned on such that the second intermediate node is switched to connect to the fourth input terminal; and

during a second half cycle of the ac sine wave, the first control switch is turned on and the second control switch is turned off and the second intermediate node is switched to connect to the third input terminal.

14. The multilevel inverter topology of claim 8, wherein:

and the magnitude of the transition of the voltage reference is equal to the difference between the fourth potential and the third potential.