CN114019272A - Current converter test circuit and test method - Google Patents

Current converter test circuit and test method Download PDF

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Publication number
CN114019272A
CN114019272A CN202111207713.1A CN202111207713A CN114019272A CN 114019272 A CN114019272 A CN 114019272A CN 202111207713 A CN202111207713 A CN 202111207713A CN 114019272 A CN114019272 A CN 114019272A
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time period
load
reactor
converter
time
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CN114019272B (en
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赵彪
白睿航
周天吉
屈鲁
余占清
曾嵘
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Tsinghua University
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Tsinghua University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/003—Environmental or reliability tests
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Inverter Devices (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

The invention discloses a current converter test circuit and a test method, and relates to the technical field of test circuits. The circuit comprises a converter reactor, a plurality of bridge arms and a load reactor; one end of the converter reactor is connected with a power supply, and the other end of the converter reactor is connected with a converter bridge arm; the plurality of bridge arms are divided into a first group and a second group, and the bridge arms in the first group and the second group are connected in parallel; the first group, the load reactor and the second group are sequentially connected in series. The test circuit provided by the invention does not need an alternating current power supply or phase locking on alternating current voltage, and has the advantages of simple control system and high reliability.

Description

Current converter test circuit and test method
Technical Field
The invention belongs to the technical field of test circuits, and particularly relates to a current converter test circuit and a test method.
Background
When the active turn-off converter is applied to a high-voltage high-power occasion, each bridge arm of the active turn-off converter is provided with a plurality of series-connected units, and before the complete machine is manufactured, a small-scale bridge arm power drag test is performed, so that the reasonability of the characteristic design of the bridge arm units such as electrical property, structure and heat dissipation is verified. However, the bridge arm electrical stress is complex in the normal operation process, and various working conditions which can occur in the bridge arm electrical stress are required to be simulated in the drag test so as to be fully verified. At present, the current converter has no large-scale engineering application experience, and a test method of the current converter is lack of research.
Disclosure of Invention
In order to solve the above problems, the present invention provides a test circuit for a current converter.
The circuit comprises a converter reactor, a plurality of bridge arms and a load reactor; one end of the converter reactor is connected with a power supply, and the other end of the converter reactor is connected with a converter bridge arm; the plurality of bridge arms are divided into a first group and a second group, and the bridge arms in the first group and the second group are connected in parallel; the first group, the load reactor and the second group are sequentially connected in series.
The bridge arm comprises a plurality of unit circuits, and the unit circuits are connected in series.
The power supply is a DC power supply with a voltage Udc＝n*UN(ii) a The U isNThe highest working voltage of the bridge arm; and n is the number of unit circuits.
Inductance value L of the converter reactorc＝Udc/(di/dt)N(ii) a The (di/dt)NAnd designing the current change rate for the bridge arm switching-on process.
Inductance value L of the load reactorload>Udc*tonmin/Idelta(ii) a Said t isonminThe minimum turn-on time of the IGCT on the bridge arm of the current converter; said IdeltaAt the desired dc ripple level.
When the current change of the load reactor is larger than the expected change range, setting a load resistor;
the first group, the load resistor, the load reactor and the second group are sequentially connected in series.
The invention also provides a converter testing method.
The method comprises the following steps: determining the voltage of a direct current power supply according to the converter, and supplying power to the converter test circuit through the voltage of the direct current power supply; inverter circuitTest time period T divided into T2Time period and t4Time period, said t2Time period and t4The bridge arms selected to be switched on in time period are not completely the same; according to t2Time period and t4And selecting the switched-on bridge arm in a time period to enable the bridge arm to periodically bear the commutation process so as to test the circuit of the bridge arm unit.
Said t is4Switching bridge arm to t2Setting dead time when the bridge arm is switched on in a time period; the dead time is t2The bridge arm in the time period is turned on and then turned off after dead time4Bridge arms in time periods.
The dead time is less than t2Time period and t4A time period.
The period T also includes T1Time period and t3A time period; said t is1Time period, t2Time period, t3Time period, t4The bridge arms selected to be switched on in time periods are not completely the same.
Said t is2Time period and t4The time periods have different changing directions of current value time curves generated on the load reactor.
Said t is2Time period longer than t4Time period, the difference is delta t; the direct current controlled by delta t is Iload＝Udc*△t/RTa/T; the U isdcIs a direct current power supply voltage; the R isTEquivalent direct current resistance R for load reactorLOr said R isTEquivalent direct current resistance R for load reactorLAnd the sum of the load resistances R.
Passing through t4Duration-controlled direct current ripple Idelta>Udc*t4/Lload(ii) a Said LloadIs the inductance value of the load reactor.
Said t is1Time period, t2Time period, t3Time period, t4The time periods do not produce the same direction of change in the current value time curve on the load reactor.
The slave t1Time period goes tot2Time period, from t2Time period goes to t3Time period, from t3Time period goes to t4The time periods are sequentially set to be dead time; the dead time is less than the associated commutation period.
Compared with the prior art, the technical scheme of the invention does not need an alternating current power supply and does not need to phase-lock the alternating current voltage, and the control system is simple and has high reliability; the direct-current power supply only needs to supplement the loss power of the device, and the power supply capacity is low; and meanwhile, the time difference value of the steady state stage is adopted to control the load current, so that the limiting dependence of the inductance value selection of the load reactance on the shortest switching pulse of the device is weakened, and the volume and the cost of the test device are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an inverter circuit tested according to an embodiment of the present invention.
Fig. 2 is a first schematic diagram of an inverter test circuit according to an embodiment of the invention.
Fig. 3 is a second schematic diagram of an inverter test circuit according to an embodiment of the invention.
Fig. 4 is a first flowchart of a converter testing method according to an embodiment of the present invention.
Fig. 5 is a second flowchart of a converter testing method according to an embodiment of the invention.
FIG. 6 is a diagram showing the bridge arm and load voltage current state.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: the relative arrangement of the components, units, lines and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
For the purpose of describing the embodiments of the present invention in detail, the description will be given mainly of the inverter circuit according to the ac three-phase grid.
A schematic diagram of an inverter circuit tested according to an embodiment of the present invention is shown in fig. 1, where the inverter circuit includes a filter capacitor CACConverter reactor LCAnd a current converter; the filter capacitor CACConnected in parallel with the ac port; the converter reactor LCConnected in series with the ac port; the converter comprises a converter reactor LCThe bridge arms are connected and consist of one or more unit circuits connected in series, and each unit circuit comprises a current on-off control component and an overvoltage suppression component which are connected in parallel.
The filter capacitor CACThe filter is used for filtering and absorbing overvoltage generated on a bridge arm of the converter by the equivalent series inductance of the alternating current power grid in the turn-off moment. The converter reactor LCThe current on-off control component is used for limiting the current change rate when being switched on, thereby protecting the device.
The main topology of the converter is a three-phase fully-controlled bridge, each bridge arm is composed of a plurality of unit circuits, and each unit circuit comprises a current on-off control component, an overvoltage suppression component and a static voltage-sharing resistor Ra which are connected in parallel.
Wherein the current switching control component comprises an asymmetric IGCT device Q2 and a fast recovery diode Q1 connected in series. The IGCT is an integrated gate commutated thyristor. The asymmetric IGCT device Q2 can control whether the current passes through the device in the forward direction.
The overvoltage suppression component comprises an absorption resistor Rb and an absorption capacitor C which are connected in series and used for suppressing overvoltage caused by the converter reactor when the bridge arm is turned off and realizing instantaneous voltage balance of the switch when the bridge arm is provided with a plurality of series-connected units.
And the static equalizing resistor Ra is used for realizing voltage equalization of each unit under the condition that the bridge arm is blocked.
And the other end of the converter is connected with a direct current load or a direct current power grid.
Further, the converter circuit further comprises a smoothing reactor LDCOne end of the smoothing reactor is connected with the bridge arm, and the other end of the smoothing reactor is connected with a direct current load or a direct current power grid.
Fig. 2 is a first schematic diagram of an inverter test circuit according to an embodiment of the present invention. The circuit comprises a converter reactor LCA plurality of bridge arms and a load reactor Lload(ii) a The converter reactor LCOne end of the power supply UdcOne end of the connecting rod is connected with a bridge arm of the current converter; the plurality of bridge arms are divided into a first group and a second group, and the bridge arms in the first group and the second group are connected in parallel; the first group, load reactor LloadAnd the second group are sequentially connected in series; the first set of legs includes Arm1 and Arm3, the second setThe bridge arms include Arm2 and Arm 4.
Each bridge arm comprises a plurality of unit circuits, and the unit circuits are connected in series.
R in said FIG. 2LThe equivalent direct current resistance of the load reactor.
The power supply UdcIs a DC power supply with a voltage Udc＝n*UN(ii) a The U isNThe highest working voltage of the bridge arm; and n is the number of unit circuits.
The bridge legs under test illustrated in fig. 2 are 4, and each bridge leg under test includes 2 unit circuits connected in series with each other. The first set comprises two parallel connected bridge arms Arm1 and Arm3, the second set comprises two parallel connected bridge arms Arm2 and Arm 4; the converter reactor LCOne end of the DC power supply UdcThe other end of the bridge arm is connected with the first group of bridge arms; the first set of bridge arm and load reactor LloadAnd the second group of bridge arms are sequentially connected in series.
Inductance value L of the converter reactorc＝Udc/(di/dt)N(ii) a The (di/dt)NAnd designing the current change rate for the bridge arm switching-on process. Inductance value L of the load reactorload>Udc*tonmin/Idelta(ii) a Said t isonminThe minimum turn-on time of the IGCT on the bridge arm of the current converter; said IdeltaA desired dc ripple level; the direct current ripple level refers to the difference between the maximum value and the minimum value of the current on the load reactor after the system runs stably.
According to the embodiment of the invention, the bridge arm unit circuits respectively and repeatedly bear the current conversion process, so that the thermal characteristics and the reliability are verified. In the test, the temperature of the experimental device is monitored by the infrared thermal imager, so that the judgment device is free from abnormal overheating, and the designed heat dissipation device is reasonable.
Fig. 3 is a second schematic diagram of an inverter test circuit according to an embodiment of the invention. The circuit comprises a converter reactor LCA plurality of bridge arms, a load resistor R and a load reactor Lload(ii) a The converter reactor LCOne end of the power supply UdcOne end of the connecting rod is connected with a bridge arm of the current converter; the plurality of bridge arms are divided into a first group and a second group, and the bridge arms in the first group and the second group are connected in parallel; the first group, the load resistor R and the load reactor LloadAnd the second group are sequentially connected in series; the first set of legs includes Arm1 and Arm3 and the second set of legs includes Arm2 and Arm 4.
Each bridge arm comprises a plurality of unit circuits, and the unit circuits are connected in series.
R in said FIG. 3LThe equivalent direct current resistance of the load reactor.
The power supply UdcIs a DC power supply with a voltage Udc＝n*UN(ii) a The U isNThe highest working voltage of the bridge arm; and n is the number of unit circuits.
The bridge legs under test illustrated in fig. 3 are 4, and each bridge leg under test includes 2 unit circuits connected in series with each other. The first set comprises two parallel connected bridge arms Arm1 and Arm3, the second set comprises two parallel connected bridge arms Arm2 and Arm 4; the converter reactor LCOne end of the DC power supply UdcThe other end of the bridge arm is connected with the first group of bridge arms; the first group of bridge arms, the load resistor R and the load reactor LloadAnd the second group of bridge arms are sequentially connected in series.
Inductance value L of the converter reactorc＝Udc/(di/dt)N(ii) a The (di/dt)NAnd designing the current change rate for the bridge arm switching-on process. Inductance value L of the load reactorload>Udc*tonmin/Idelta(ii) a Said t isonminThe minimum turn-on time of the IGCT on the bridge arm of the current converter; said IdeltaA desired dc ripple level; the direct current ripple level refers to the difference between the maximum value and the minimum value of the current on the load reactor after the system runs stably.
The load resistance R is represented by Iload＝Udc*△t/RLDetermined by the formula/T, said UdcVoltage of the DC power supply, RLIs a loadThe equivalent direct current resistance of the reactor, T is the test time period of the converter circuit, Δ T is the time difference value of different time periods in each time period, and IloadIs the magnitude of the load current. E.g. each time period divided into t2Time period and t4Time period at t2The change direction of the time curve of the load current in the time period is upward, namely the current becomes larger, and at t4The change direction of the load current time curve in the time period is downward, namely the current is reduced, and delta t is the difference value of the two time periods, so that the rise amount of the load reactance current in each period is equal to the equivalent direct current resistance R of the load reactorLThe amount of current drop caused, when dependent on the load reactor equivalent DC resistance RLAnd if the calculated delta t is less than the minimum control precision of the controller, namely the requirement of current change cannot be met, and the current change of the load reactor is greater than the expected change range, the load resistor R needs to be increased to improve the delta t.
According to the embodiment of the invention, the bridge arm unit circuits respectively and repeatedly bear the current conversion process, so that the thermal characteristics and the reliability are verified. In the test, the temperature of the experimental device is monitored by the infrared thermal imager, so that the judgment device is free from abnormal overheating, and the designed heat dissipation device is reasonable.
Fig. 4 shows a first flowchart of a converter testing method according to an embodiment of the present invention. The method comprises the following steps: determining the voltage of a direct current power supply according to the converter, and supplying power to the converter test circuit through the voltage of the direct current power supply; dividing the test time period T of the converter circuit into T2Time period and t4Time period, said t2Time period and t4The bridge arms selected to be switched on in time period are not completely the same; according to t2Time period and t4And selecting the switched-on bridge arm in a time period to enable the bridge arm to periodically bear the commutation process so as to test the circuit of the bridge arm unit.
Said t is4Switching bridge arm to t2Setting dead time when the bridge arm is switched on in a time period; the dead time is t2The bridge arm in the time period is turned on and then turned off after dead time4Bridge arms in time periods. The dead time is smallAt t2Time period and t4A time period. The power verification is carried out on the special working condition that the dead zone cannot complete forced commutation caused by commutation, and the direct-current voltage can be reduced so as to prolong the commutation time to be longer than the dead zone time.
The dead time is set, so that the test circuit can keep normal work all the time, and the problem of disordered switching-on and switching-off of a bridge arm caused by the interruption of the commutation time is prevented. Such as the occurrence of the phenomena of full opening and full closing of the bridge arm, the turning off of the bridge arm which should be turned on, the turning on of the bridge arm which should be turned off, and the like.
In connection with the circuit shown in FIG. 3, t2The bridge Arm1 and the bridge Arm4 are in through-current in the time period t4And the bridge Arm2 and the bridge Arm3 are through-current in the time period. Said t is2Time period and t4Time period at load resistance RLAnd a load reactor LloadThe time curve of the current value generated in the step (a) has different change directions. Said t is2Supply voltage load reactor current rise, t, over a period of time4The supply voltage is applied to the load reactor L in the reverse direction during the time periodloadThus, the current is rapidly decreased.
The bridge Arm2 is turned off after the dead time elapses after the bridge Arm1 is turned on, and is turned on before the bridge Arm1 is turned off. Arm3 is turned off after the dead time elapses after Arm4 is turned on, and is turned on before Arm4 is turned off.
Said t is2Time period longer than t4Time period, the difference is delta t; so that the load reactance current rise amount is equal to the current drop amount per cycle; the direct current I controlled by delta tload＝Udc*△t/RLa/T; the U isdcIs a DC supply voltage, said RLIs a load resistor.
Further, when the equivalent direct current resistance R is based on the load reactorLThe calculated delta t is smaller than the minimum control precision of the controller, namely the requirement of current change cannot be met, and if the current change of the load reactor is larger than the expected change range, the load resistor R needs to be increased to improve the delta t; at this time, Δ t controlled DC current Iload＝Udc*△t/(RL+R)/T。
Passing through said t4Duration-controlled direct current ripple Idelta>Udc*t4/Lload(ii) a Said LloadIs the inductance value of the load reactor. The direct current ripple is the difference between the maximum value and the minimum value of the current on the load reactor after the system runs stably.
The power verification is carried out on the special working condition of forced commutation caused by the fact that the dead zone can not complete commutation, and the direct-current voltage U can be reduceddcTo prolong the commutation time to be greater than the dead time tdeadThe concrete parameters need to satisfy: u shapedc<LC*IDC/tdead(ii) a The U isdcIs a DC supply voltage, said LCFor the inductance value of the converter reactor, IDCFor the load current, tdeadIs the dead time.
By the detection method, the stability and the reliability of the converter circuit can be effectively detected in a simple environment.
Fig. 5 shows a second flowchart of a converter testing method according to an embodiment of the present invention. The method comprises the following steps: determining the voltage of a direct current power supply according to the converter, and supplying power to the converter test circuit through the voltage of the direct current power supply; dividing the test time period T of the converter circuit into T1Time period, t2Time period, t3Time period and t4Time period, said t1Time period, t2Time period, t3Time period, t4The bridge arms selected to be switched on in time period are not completely the same; and selecting the switched-on bridge arm according to each time period to enable the bridge arm to periodically bear the commutation process so as to test the circuit of the bridge arm unit.
Said t is1Time period, t2Time period, t3Time period, t4The time periods do not have exactly the same direction of the current value time curves generated on the load resistance and the load reactor.
The slave t1Time period goes to t2Time period, from t2Time period goes to t3Time period, from t3TimeSegment goes to t4Time period, from t4Time period goes to t1The time periods are sequentially set to be dead time; the dead time is less than the associated commutation period.
The dead time is set, so that the test circuit can keep normal work all the time, and the problem of disordered switching-on and switching-off of a bridge arm caused by the interruption of the commutation time is prevented. Such as the occurrence of the phenomena of full opening and full closing of the bridge arm, the turning off of the bridge arm which should be turned on, the turning on of the bridge arm which should be turned off, and the like.
With the circuit shown in fig. 3, the bridge arms Arm2 and Arm3 are respectively matched with the bridge arms Arm1 and Arm4 to form switches, so that a certain commutation dead time is reserved between each pair of upper and lower bridge arms, and the commutation dead time is set to be consistent with the dead time in the actually designed converter. Such as: arm2 turns off after the dead time elapses after Arm1 turns on, and turns on before Arm1 turns off. Arm3 turns off after the dead time elapses after Arm4 turns on, and turns on before Arm4 turns off.
t1And t3The phases are that bridge arms Arm1 and Arm3 and bridge arms Arm2 and Arm4 are in through-current respectively, and the current is in a load resistor RLSlowly decaying under the action of the magnetic field; t is t2The through current of the stage bridge arms Arm1 and Arm4 is provided, and the power supply voltage U is provideddcRaising the load reactance current; t is t4The through current of the stage bridge arms Arm2 and Arm3 is provided, and the power supply voltage U is provideddcReverse applied to load reactance LloadThus, the current is rapidly decreased.
As shown in FIG. 6, the bridge arm and load voltage and current state diagram is shown, and t is shown1Time period to t4The time period is a complete period T; at t1In the time period, the bridge Arm1 is switched on, and the bridge Arm4 is switched off; at t2In the time period, the bridge Arm1 and the bridge Arm4 are both turned on; at t3In the time period, the bridge Arm1 is turned off, and the bridge Arm4 is turned on; at t4In the time period, the bridge Arm1 and the bridge Arm4 are both turned off; in the process, the bridge arms Arm2 and Arm3 are respectively matched with the bridge arms Arm1 and Arm4 for switching. So as to achieve the purpose of testing the bridge arm unit circuit.
As can be seen in FIG. 6, at t1In the time period, because the bridge Arm1 and the bridge Arm3 are switched on, the bridge Arm2 and the bridge Arm4 are switched off, and the load reactance voltage U isLIs 0, load current IDCThe curve changes in the downward direction, i.e. the load current value IDCThe trend is downward; at t2In the time period, because the bridge Arm1 and the bridge Arm4 are switched on, the bridge Arm2 and the bridge Arm3 are switched off, and the load reactance voltage U isLIs positive, load current IDCThe curve changes in the upward direction, i.e. the load current value IDCThe trend is ascending; at t3In the time period, because the bridge Arm2 and the bridge Arm4 are switched on, the bridge Arm1 and the bridge Arm3 are switched off, and the load reactance voltage U isLIs 0, load current IDCThe curve changes slowly downwards, i.e. the load current value IDCThe trend is downward; at t4In the time period, because the bridge Arm2 and the bridge Arm3 are switched on, the bridge Arm1 and the bridge Arm4 are switched off, and the load reactance voltage U isLIs negative, the load current IDCThe curve changes in the downward direction, i.e. the load current value IDCThe trend of descending at the highest speed is shown; but because of t2The phase time is slightly longer than t4So that each period is loaded with a reactive current IDCThe rise is equal to the DC resistance R of the load reactanceLThe amount of current drop caused thereby ensuring the load current IDCThe aim of testing the bridge arm unit circuit is achieved under the condition of a positive value.
t2The phase time is slightly longer than t4The difference is Deltat, so that the load reactance current rise per cycle is equal to the load reactance DC resistance RLThe amount of current reduction caused by the method controls the direct current through the time length of delta t: the direct current controlled by delta t is Iload＝Udc*△t/RLa/T; the U isdcIs a DC supply voltage, said RLIs a load resistor; t is the modulation period. T ═ T1+t2+t3+t4。
Further, when the equivalent direct current resistance R is based on the load reactorLThe calculated delta t is less than the minimum control precision of the controller, namely the requirement of current change cannot be met, and the load reactorIf the current change is larger than the expected change range, the load resistance R needs to be increased to improve the delta t; at this time, Δ t controlled DC current Iload＝Udc*△t/(RL+R)/T。
Further, by t4Controlling the direct current ripple in time length: i isdelta>Udc*t4/Lload. The direct current ripple refers to the difference between the maximum value and the minimum value of the current on the load reactor after the system runs stably.
Passing through t1And t3And completing the modulation period to realize the required test frequency. Passing through t1And t3The proportion of the current-flowing time of the bridge arms is adjusted, so that the bridge arms Arm1 and Arm3 or Arm2 and Arm4 have higher on-state loss power, and the actual working condition is better simulated.
Based on the above tests, the bridge arms can be made to repeatedly withstand the commutation process, respectively, thereby verifying the thermal characteristics and reliability. In the test, the temperature of the experimental device is monitored by the infrared thermal imager, so that the judgment device is free from abnormal overheating, and the designed heat dissipation device is reasonable.
The power verification is carried out on the special working condition that the dead zone can not finish the forced commutation caused by the commutation, the direct current voltage can be reduced, and the commutation time is prolonged to be larger than the dead zone time tdeadThe concrete parameters need to satisfy: u shapedc<LC*IDC/tdead(ii) a The U isdcIs a DC supply voltage, said LCFor the inductance value of the converter reactor, IDCFor the load current, tdeadIs the dead time.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be understood by those skilled in the art that various changes may be made in the above embodiments and equivalents may be substituted for elements thereof without departing from the scope and spirit of the invention.

Claims (15)

1. A converter test circuit is characterized by comprising a converter reactor, a plurality of bridge arms and a load reactor;
one end of the converter reactor is connected with a power supply, and the other end of the converter reactor is connected with a converter bridge arm;
the plurality of bridge arms are divided into a first group and a second group, and the bridge arms in the first group and the second group are connected in parallel;
the first group, the load reactor and the second group are sequentially connected in series.
2. The circuit of claim 1, wherein the bridge arm comprises a plurality of cell circuits, and the cell circuits are connected in series.
3. The circuit of claim 2, wherein the power supply is a dc power supply, and the dc power supply voltage U isdc＝n*UN；
The U isNThe highest working voltage of the bridge arm;
and n is the number of unit circuits.
4. The circuit of claim 3, wherein the inductance L of the converter reactor is Lc＝Udc/(di/dt)N；
The (di/dt)NAnd designing the current change rate for the bridge arm switching-on process.
5. A circuit as claimed in claim 3, characterized in that the inductance L of the load reactor isload>Udc*tonmin/Idelta；
Said t isonminThe minimum turn-on time of the IGCT on the bridge arm of the current converter;
said IdeltaAt the desired dc ripple level.
6. The circuit of claim 1, wherein:
when the current change of the load reactor is larger than the expected change range, setting a load resistor;
the first group, the load resistor, the load reactor and the second group are sequentially connected in series.
7. A converter testing method, the method comprising:
determining the voltage of a direct current power supply according to the converter, and supplying power to the converter test circuit through the voltage of the direct current power supply;
dividing the test time period T of the converter circuit into T2Time period and t4Time period, said t2Time period and t4The bridge arms selected to be switched on in time period are not completely the same;
according to t2Time period and t4And selecting the switched-on bridge arm in a time period to enable the bridge arm to periodically bear the commutation process so as to test the circuit of the bridge arm unit.
8. The method of claim 7, wherein:
said t is4Switching bridge arm to t2Setting dead time when the bridge arm is switched on in a time period;
the dead time is t2The bridge arm in the time period is turned on and then turned off after dead time4Bridge arms in time periods.
9. The method of claim 8, wherein the dead time is less than t2Time period and t4A time period.
10. The method of claim 7, wherein the period T further comprises T1Time period and t3A time period;
said t is1Time period, t2Time period, t3Time period, t4The bridge arms selected to be switched on in time periods are not completely the same.
11. The method of claim 7, wherein:
said t is2Time period and t4The time periods have different changing directions of current value time curves generated on the load reactor.
12. The method according to any one of claims 7-11, wherein:
said t is2Time period longer than t4Time period, the difference is delta t;
the direct current controlled by delta t is Iload＝Udc*△t/RT/T；
The U isdcIs a direct current power supply voltage;
the R isTEquivalent direct current resistance R for load reactorLOr said R isTEquivalent direct current resistance R for load reactorLAnd the sum of the load resistances R.
13. The method of claim 7, wherein the passing t4Duration-controlled direct current ripple Idelta>Udc*t4/Lload；
Said LloadIs the inductance value of the load reactor.
14. Method according to claim 10 or 11, characterized in that said t is1Time period, t2Time period, t3Time period, t4The time periods do not produce the same direction of change in the current value time curve on the load reactor.
15. Method according to claim 10 or 11, characterized in that said slave t is1Time period goes to t2Time period, from t2Time period goes to t3Time period, from t3Time period goes to t4The time periods are sequentially set to be dead time;
the dead time is less than the associated commutation period.
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