JP5302905B2 - Power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate preventing an inrush current in initial charge of a sub capacitor 9 at a DC side with a simple configuration in a power conversion apparatus, where a single-phase sub converter 4 is connected in series to an AC input line of a main converter 3. <P>SOLUTION: A current command value operation unit 20 for generating an AC current command includes a CPU, the main converter 3 is controlled so that an AC current is suppressed, and an output voltage level at an AC side of the sub converter 4 is controlled to be changed so that the AC current follows the AC current command. In the initial charge, the power conversion apparatus is started after charge of a main capacitor 7 is completed, the main converter 3 is subjected to output control in the same way as normal conditions, and all of switches inside the sub converter 4 are turned off to charge the sub capacitor 7. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a power conversion device having an AC / DC conversion function.

A converter capable of regenerative control as a conventional power converter is shown below.
A power converter is configured by connecting in series the AC side of a single-phase sub-converter having a DC voltage smaller than the DC voltage of the main converter to the AC input line of each phase of the three-phase main converter. Then, the main converter is driven with a single gate pulse in a half cycle, and the generated voltage at the AC terminal of the sub-converter is controlled to be the difference between the AC power supply voltage and the generated voltage at the AC terminal of the main converter. Thereby, a harmonic can be suppressed without enlarging a reactor, and a power loss and electromagnetic noise can also be reduced (for example, refer to patent documents 1).
Moreover, the prior art which carries out the initial charge of the power storage which accumulate | stores each DC power of the main converter of such a power converter device and a subconverter is shown below.
A charging resistor or reactor is provided between the system power supply and the power converter, and the DC power storage of the main converter and the sub-converter is initially charged by a current path from the system power supply through the charging resistor or reactor. Thereby, the rush current to each electric power store at the time of initial charge can be controlled (for example, refer to patent documents 2).

International Publication WO2007 / 129456 International Publication WO2007 / 129469

  In the conventional power conversion device, the power storage device is charged through a current path through a charging resistor or a reactor when the power storage device is initially charged. However, the inrush current to each power storage during initial charging is not sufficient even if it is limited by the charging resistor or the reactor, and there is a problem that voltage distortion occurs on the AC power supply side due to this inrush current. Further, not only charging resistors and reactors but also components for switching such as a relay for bypassing these during normal operation of the power converter are necessary, and the number of components is increased.

  The present invention has been made to solve the above-described problems, and is a power conversion device in which a main converter and a sub-converter each having a power storage on the DC side are connected in series. It is an object of the present invention to initially charge a power storage device with a simple configuration without impairing the reliability on the side.

The power conversion device according to the present invention includes a main converter and a sub-converter that each have a plurality of semiconductor switching elements, perform power conversion between AC and DC, and output to each power storage unit provided on the DC side. The DC voltage of the main converter is greater than the DC voltage of the sub-converter, and the power converter in which the sub-converter is arranged in series between the main converter and an AC power source and the control for controlling the power converter Device. The control device outputs a first control signal to the main converter so as to suppress an AC current instantaneous value based on a phase of the AC power source and the AC current command based on a current command calculation unit that generates an AC current command. And a second control unit that generates a second control signal to the sub-converter so that the instantaneous value of the alternating current follows the alternating current command. Further, the second control unit of the control device includes a hysteresis comparator, and switches the output voltage level on the AC side of the sub-converter so that a deviation between the AC current command and the AC current instantaneous value becomes small. The second control signal is generated, and the control device is configured to charge a power storage unit of the sub-converter in a state where the power storage unit of the main converter is completely charged, the main converter, and the sub-converter. And a normal control mode for controlling the power converter by generating the first and second control signals after completion of charging of each power storage unit, and generating the first signal in the charge control mode. And controlling the main converter and turning off all of the plurality of semiconductor switching elements in the sub-converter. It is intended to charge the power storage device of over data.

  According to this invention, the suppression control of the alternating current instantaneous value is performed in the output control of the main converter in the normal control mode. For this reason, even in the charge control mode for charging the power storage of the sub-converter, by controlling the main converter in the same way, it is possible to easily prevent the inrush current from flowing by suppressing the instantaneous value of the AC current, and the voltage to the AC power supply side. Distortion and the like can be prevented from occurring. In addition, switching between normal control and charge control can be performed only by the control device, and there is no need for parts for current limitation or parts for switching the current path, and without compromising the reliability on the AC power supply side with a simple configuration. The sub-converter power reservoir can be initially charged.

1 is a configuration diagram of a main circuit (power converter) and a main capacitor charging circuit of a power conversion device according to Embodiment 1 of the present invention. It is a wave form chart of each part explaining the normal operation of the power converter device by Embodiment 1 of this invention. It is a figure which shows the hardware constitutions of the control apparatus by Embodiment 1 of this invention. It is a figure which shows the structure of the electric current command value calculating circuit (CPU) of the control apparatus by Embodiment 1 of this invention. It is a figure which shows the structure of the 1st control part which bears the output control of a main converter in the control apparatus by Embodiment 1 of this invention. It is a figure which shows the structure of the 2nd control part which bears the output control of a subconverter in the control apparatus by Embodiment 1 of this invention. It is a figure which shows a part of structure of the 2nd control part which bears the output control of a subconverter in the control apparatus by Embodiment 1 of this invention. It is a figure explaining control of the main converter by the 1st control part by Embodiment 1 of this invention. It is a figure explaining control of the subconverter by the 2nd control part by Embodiment 1 of this invention. It is a figure explaining control of the subconverter by the 2nd control part by Embodiment 1 of this invention. It is a figure which shows the pattern of the gate drive signal of the subconverter by Embodiment 1 of this invention. It is a flowchart explaining the initial stage charging operation of the power converter device by Embodiment 1 of this invention. It is a figure which shows the structure of the charge switching circuit of the sub capacitor | condenser by Embodiment 1 of this invention. It is a block diagram of the main circuit (power converter) of the power converter device by Embodiment 2 of this invention, and a main capacitor charging circuit.

Embodiment 1 FIG.
Hereinafter, a power converter according to Embodiment 1 of the present invention will be described. 1 is a configuration diagram of a main circuit (power converter) and a main capacitor charging circuit of a power conversion device according to Embodiment 1 of the present invention. Specifically, the power converter is a power converter that converts power from a three-phase AC power source (system power source) 1 into DC power and supplies the DC power to the DC load 2.
As shown in FIG. 1, a sub-converter 4 and an AC reactor 5 each consisting of a single-phase full bridge circuit are connected to each phase on the AC line side of the main converter 3 that converts three-phase AC power into DC power. . The main converter 3 is a three-phase two-level converter in which a main capacitor 7 as a power storage is connected on the DC side, and an IGBT or the like in which diodes are connected in antiparallel assuming that DC power is regenerated to the AC side. The self-extinguishing type semiconductor switching element 6 is used.

  The semiconductor switching element 6 used here may be a GCT, GTO, transistor, MOSFET or the like, or a thyristor without a self-extinguishing function, as long as it can perform the forced commutation operation. In addition, when a motor or the like is connected to the DC load 2 via an inverter circuit (not shown), the inverter circuit unit is accompanied by a brake resistor or the like, and it is necessary to regenerate DC power to the AC system. If not, the self-extinguishing semiconductor element (semiconductor switching element 6) may be replaced with a diode. The P-side and N-side semiconductor switching elements 6 constituting the respective phase (R-phase, S-phase, T-phase) arms of the main converter 3 are referred to as RP, RN, SP, SN, TP, and TN.

The sub-converter 4 includes a single-phase full-bridge circuit composed of self-extinguishing semiconductor switching elements 8 such as a plurality of MOSFETs, and sub-capacitors 9 as independent voltage stores. Also in this case, if the semiconductor switching element 8 can be forcibly commutated by a MOSFET, IGBT, GCT, GTO, transistor, etc. with diodes connected in antiparallel, or a thyristor without a self-extinguishing function, etc. Good. The AC power supply side arm of each phase sub-converter 4 is referred to as the X side arm, the load side arm is referred to as the Y side arm, and the P side and N side semiconductor switching elements 8 are referred to as XP, XN, YP, and YN. .
The sub-converter 4 can output a DC voltage charged with the illustrated polarity between the AC terminals (output voltage: Vsub) in an arbitrary period. Specifically, when the DC voltage is V, a three-level voltage value of Vsub = {− V, 0, + V} is applied between the AC terminals of the sub-converter 4 depending on the combination of ON / OFF of the semiconductor switching element 8. be able to.

The voltage sensor 7a for detecting the voltage Vdc of the main capacitor 7 of the main converter 3, the voltage sensor 9a for detecting the voltages Vbr, Vbs and Vbt of the sub capacitor 9 of the sub-converter 4 of each phase, and the three-phase AC power source 1 Are provided with a current sensor 10 for detecting an alternating current i (ir, is, it) of each phase input from the, and a PLL circuit 11 for detecting the phase of the three-phase alternating current power supply 1. The alternating current i has a positive arrow direction.
Further, in order to initially charge the main capacitor 7, the main capacitor 7 has a DC / DC converter 111 for charging from the battery 110, and an AC / DC converter 113 for charging the main capacitor 7 from the AC power supply 1. A main capacitor charging circuit is provided.

The power converter configured in this way is, for example, a three-phase AC power source 1 is a 200V AC system, a DC output voltage Vdc of the main capacitor 7 is 250V, and a voltage of the sub capacitor 9 of each phase is 60V. In this case, the main converter 3 can be composed of an element having a withstand voltage of 600V, and the sub-converter 4 can be composed of an element having a withstand voltage of 100V. When the three-phase AC power supply 1 is a 400V AC system, the voltage Vdc of the main capacitor 7 which is a DC output voltage is 500V, and the voltage of the sub capacitor 9 of each phase is 60V, the main converter 3 has a withstand voltage of 1200V. With the element, the sub-converter 4 can be configured with an element having a withstand voltage of 100V.
The power converter capable of AC / DC conversion may be one in which the DC side is connected to an AC system with an energy source such as sunlight or a fuel cell to exchange power. In that case, the battery 110 and the converters 111 and 113 for initially charging the main capacitor 7 are unnecessary.

The operation of the power converter configured as described above will be described below. 2 shows, for example, an R-phase output voltage Vmain of the main converter 3, gate drive signals of the semiconductor switching elements 6 (RP, RN, SP, SN, TP, TN) constituting the main converter 3, and an R-phase sub-converter. FIG. 6 is a diagram illustrating each waveform of an output voltage Vsub of 4; Here, the voltage per phase will be described.
As shown in the figure, the gate drive signal of each semiconductor switching element 6 of the main converter 3 is a signal of one pulse in one cycle of the power supply phase voltage (hereinafter referred to as one pulse signal). When the R-phase power supply phase voltage is positive, the P-side semiconductor switching element RP is on, the N-side semiconductor switching element RN is off, and when the R-phase power supply phase voltage is negative, semiconductor switching is performed. The element RP is in an off state, and the semiconductor switching element RN is in an on state.

The basic operation of the power converter is to perform power conversion between AC and DC so that the DC voltage Vdc of the main capacitor 7 of the main converter 3 which is a DC output voltage is maintained. It operates to generate a sinusoidal voltage that is a voltage.
The R-phase output voltage Vmain of the main converter 3 viewed from the virtual neutral point of the AC power supply 1 has a stepped waveform as shown in the figure. The R-phase sub-converter 4 finely turns on and off the semiconductor switching element 8 to output a difference voltage between the power supply phase voltage and the R-phase output voltage Vmain of the main converter 3 (output voltage: Vsub). Although details of the switching control of the sub-converter 4 will be described later, the alternating current i is controlled to have a power factor of 1.

FIG. 3 is a diagram illustrating a hardware configuration of the control device 12 that controls such a power converter. The control device 12 generates gate drive signals for the semiconductor switching elements 6 and 8 of the main converter 3 and the sub-converters 4 for each phase, and controls the main converter 3 and the sub-converters 4 for each phase. Note that a gate drive signal for controlling the main converter 3 is a first control signal, and a gate drive signal for controlling the sub-converter 4 of each phase is a second control signal.
As shown in FIG. 3, the control device 12 includes a CPU, and includes a current command value calculation circuit 20 as a current command calculation unit that calculates an alternating current command for each phase, a comparator circuit 30, and a logic circuit 40. It consists of a logic circuit. For the logic circuit 40, an FPGA (Field Programmable Gate Array), a PLD (Programmable Logic Device), or the like is used.

The comparator circuit 30 is obtained from the comparator 31 (hereinafter referred to as the first comparator 31) that detects the imbalance of the voltages Vbr, Vbs, and Vbt of the sub-capacitor 9 of each phase obtained from the voltage sensor 9 a and the current sensor 10. A comparator 32 (hereinafter referred to as a second comparator 32) for detecting the polarity of each phase alternating current ir, is, it, and a current instantaneous value control circuit 33 comprising a plurality of hysteresis comparators. The instantaneous current value control circuit 33 controls the main converter 3 and each phase so that the instantaneous values of the alternating currents ir, is, and it follow the alternating current commands of the phases generated by the current command value calculation circuit 20. The command signal corresponding to the sub-converter 4 is output.
The logic circuit 40 includes a balance correction circuit 41 that corrects the voltage balance of the sub-capacitor 9 of each phase based on the outputs of the first and second comparators 31 and 32, a sub-converter gate pulse generation circuit 42, a main converter And a gate pulse generation circuit 43.

FIG. 4 shows details of control hardware of the current command value calculation circuit 20 composed of the CPU. The current command value calculation circuit 20 can be configured using a microcomputer, a DSP (Digital Signal Processor), or the like.
As shown in the figure, the current command value calculation circuit 20 uses the voltages Vbr, Vbs, Vbt of the sub-capacitor 9 of each phase obtained from the voltage sensor 9a and the voltage Vdc of the main capacitor 7 obtained from the voltage sensor 7a as A The signal is input via the / D converter, and the line voltage phase of the three-phase AC power source 1 is input as a digital signal from the output signal of the IC that can detect the phase, such as the PLL circuit 11. The circuit 21 calculates a sub-capacitor average voltage, which is an average value for three phases, with the sub-capacitor voltages Vbr, Vbs, and Vbt of each phase as inputs. Then, the PI capacitor output is added to the main capacitor voltage command so that the sub capacitor average voltage follows the sub capacitor voltage command, that is, the difference becomes zero, and the main capacitor voltage command is adjusted. Then, the difference between the main capacitor voltage Vdc and the adjusted main capacitor voltage command is input to the current command generation circuit 24.

Further, based on the line voltage phase input from the PLL circuit 11, a reference sine wave of each phase is calculated by the circuit 23, and the reference sine wave is input to the current command generation circuit 24. In the current command generation circuit 24, the difference between the main capacitor voltage Vdc and the adjusted main capacitor voltage command is input to the circuit 25, so that the main capacitor voltage Vdc follows the adjusted main capacitor voltage command. PI control is performed by the circuit 25 so as to be 0, and the amplitude of the alternating current command is calculated. Then, the amplitude of the AC current command is multiplied by each phase reference sine wave from the circuit 23 to calculate a current command value to be an AC current command for each phase.
The calculated alternating current command for each phase is output from the current command value calculation circuit 20 via the D / A converter.

As described above, the current command value calculation circuit 20 adjusts the main capacitor voltage command which is the DC voltage command of the main converter 3 so that the sub capacitor average voltage as the DC voltage of the sub converter 4 follows the sub capacitor voltage command. Then, an alternating current command is generated so that the main capacitor voltage Vdc follows the main capacitor voltage command. In other words, by controlling the alternating current command, the sub capacitor average voltage and the main capacitor voltage Vdc are maintained at desired voltages, respectively. In addition, by adjusting the main capacitor voltage command in order to control the sub-capacitor average voltage to a constant level, the sub-converter 4 does not require a power supply element in the DC section, and the voltage stabilization is realized only by the sub-capacitor 9. it can.
Further, since the AC current command for each phase is generated based on the reference sine wave, each phase AC current ir, is, it is controlled to have a power factor of 1.

Next, the 1st control part which bears output control of the main converter 3 and the 2nd control part which bears output control of the sub-converter 4 of each phase are demonstrated.
The first control unit and the second control unit divide the comparator circuit 30 and the logic circuit 40 into two functions that are responsible for the output control of the main converter 3 and the output control of the sub-converter 4 of each phase. FIG. 5 shows details of the first control unit and FIGS. 6 and 7 show details of the second control unit.
The instantaneous current value control circuit 33 in the comparator circuit 30 includes first to third hysteresis comparators 33a to 33c. The first hysteresis comparator 33a is a part of the first control unit, and the second and third hysteresis comparators 33a to 33c. The hysteresis comparators 33b and 33c are part of the second control unit. The instantaneous current value control circuit 33 compares the alternating current command generated by the current command value calculation circuit 20 with the alternating current of each phase and outputs a command signal. The alternating current handled here is the alternating current. When it is an instantaneous value and will be simply referred to as “AC current” hereinafter, it indicates the AC current instantaneous value.

The first control unit responsible for output control of the main converter 3 includes a first hysteresis comparator 33a and a main converter gate pulse generation circuit 43, and FIG. 5 illustrates the R phase portion of the first control unit. It is. The S phase and the T phase have the same configuration.
As shown in FIG. 5, the R-phase main converter gate pulse generation circuit 43 r includes a one-pulse signal generation circuit 44, a determination circuit 45, and a current suppression circuit 46, and the R-phase semiconductor switching element RP of the main converter 3. , RN gate drive signals (hereinafter referred to as RP gate pulse and RN gate pulse) are generated.
Based on the line voltage phase from the PLL circuit 11, the 1-pulse signal generation circuit 44 generates an RP gate pulse and an RN gate pulse composed of one pulse signal (one pulse signal) in one cycle of the power supply phase voltage ( (See FIG. 2).
Hereinafter, the control of the R phase will be described, but the same applies to the other phases.

  When the current deviation between the alternating current ir and the alternating current command generated by the current command value calculation circuit 20 exceeds a predetermined hysteresis width (± ia), the first hysteresis comparator 33a sends an abnormal signal to the main converter gate pulse. Output to the generation circuit 43r. In the main converter gate pulse generation circuit 43r, the determination circuit 45 receives the abnormal signal from the first hysteresis comparator 33a as an input, and outputs an RP cutoff signal for turning off the semiconductor switching element RP when the current polarity is negative. Is positive, an RN cutoff signal for turning off the semiconductor switching element RN is output. The current suppression circuit 46 receives the outputs of the 1-pulse signal generation circuit 44 and the determination circuit 45, and outputs the RP gate pulse and the RN gate pulse as they are in the normal state, and receives the RP cutoff signal and the RN cutoff signal from the determination circuit 45. When it is done, the RP gate pulse and the RN gate pulse are corrected so as to be turned off during that period, and then output. The RP gate pulse and RN gate pulse output from the current suppression circuit 46 become the first control signal that is the output of the main converter gate pulse generation circuit 43r, and drives and controls the R-phase semiconductor switching elements RP and RN.

  The main converter 3 is controlled by a gate drive signal composed of a single pulse signal when the alternating current ir fluctuates within a normal range, and the control for causing the alternating current ir to follow the alternating current command is controlled by the output control of the sub-converter 4. Is going. The details of the output control of the sub-converter 4 will be described later. However, when the power supply voltage changes suddenly due to an instantaneous drop or a power failure, the current cannot be controlled by the output control of the sub-converter 4 and falls into an overcurrent. There is. In that case, the first hysteresis comparator 33a detects that the current deviation between the alternating current ir and the alternating current command has exceeded the hysteresis width (± ia), that is, an abnormal current is detected, and as described above, according to the current polarity. Thus, the one-pulse signal of any of the semiconductor switching elements RP and RN of the main converter 3 is turned off.

  For example, as shown in FIG. 8, when the alternating current ir is positive, the semiconductor switching element RN is turned on, and a current flows through the illustrated current path. At this time, when the first hysteresis comparator 33a detects a current abnormality, the determination circuit 45 outputs an RN cutoff signal, and the RN gate pulse output from the main converter gate pulse generation circuit 43r is turned off. Thereby, the semiconductor switching element RN is turned off and the alternating current ir is suppressed. When the difference between the alternating current ir and the alternating current command is suppressed within a predetermined hysteresis width (± ia), the semiconductor switching element RN is turned on again according to the original RN gate pulse (one pulse signal). Thus, even when the power supply voltage changes sharply, the current can be suppressed before the overcurrent is reached, and the operation can be continued.

Next, as shown in FIG. 6, the second control unit responsible for the output control of the sub-converter 4 includes second and third hysteresis comparators 33b and 33c and a sub-converter gate pulse generation circuit 42r. Further, as shown in FIG. 7, the first comparator 31 that detects the imbalance of the voltages Vbr, Vbs, and Vbt of the sub-capacitor 9 of each phase and the first that detects the polarities of the AC currents ir, is, and it of each phase. 2 and a balance correction circuit 41 that corrects the voltage balance of the sub-capacitor 9 of each phase based on the outputs of the first and second comparators 31 and 32.
7 shows all the three-phase portions, the configuration shown in FIG. 6 is only the R-phase portion for the sake of convenience, and the S-phase and T-phase are the same configuration. Hereinafter, in the description using FIG. 6, the control of the R phase will be described, but the same applies to the other phases.

As shown in FIG. 6, the current deviation between the alternating current command generated by the current command value calculation circuit 20 and the alternating current ir is input to the second and third hysteresis comparators 33b and 33c.
The hysteresis width (± i2) of the third hysteresis comparator 33c is wider than the hysteresis width (± i1) of the second hysteresis comparator 33b, and the hysteresis width (± ia) of the first hysteresis comparator 33a of the first control unit. Narrower. That is, i1 <i2 <ia when compared in absolute value. When the input current deviation exceeds the hysteresis width, the second and third hysteresis comparators 33b and 33c output an abnormal signal, and the output is input to the sub-converter gate pulse generation circuit 42r. Then, each semiconductor switching element in the R-phase sub-converter 4 is driven and controlled by the sub-converter gate pulse 48r as the second control signal which is the output of the sub-converter gate pulse generation circuit 42r.
The sub-converter gate pulse generation circuit 42r includes a gate pulse switching unit 100r in the output stage, and switches and outputs the sub-converter gate pulse 48r when charging the sub capacitor 9 when the power converter is activated. Details of the gate pulse switching unit 100r will be described later.

A basic configuration of output control of the sub-converter 4 will be described below. The control device 12 has a normal control mode and a charge control mode for charging the sub-capacitor 9 at the start-up, and the following description is output control in the normal control mode.
Since the sub-converter 4 has a full bridge configuration, when the DC voltage is V, three levels of {−V, 0, + V} are selected and output to the AC side. 9A and 9B illustrate switching of the output voltage level, with the horizontal axis representing the current deviation between the alternating current command and the alternating current ir and the vertical axis representing the output voltage level of the sub-converter 4. FIG. FIG. In this case, when the current deviation exceeds the hysteresis width (± i1) using the second hysteresis comparator 33b, the output voltage level is switched so that the alternating current ir is suppressed.
The output voltage level is switched between {−V} and {0} as shown in FIG. 9A and {0} and {+ V} as shown in FIG. 9B. There are several modes. This mode is determined in accordance with the output polarity of the sub-converter 4 determined based on the line voltage phase input from the PLL circuit 11 to the sub-converter gate pulse generation circuit 42r. Then, the output voltage level is switched by switching the switching pattern of the sub-converter gate pulse 48 which is a gate drive signal to the semiconductor switching elements XP, XN, YP and YN.

As described above, the output voltage level is switched so that the alternating current ir follows the alternating current command. However, if there is a fluctuation in the power supply voltage phase or a delay in the phase detection system, the output polarity of the sub-converter 4 is disturbed and the alternating current is changed. The current ir can deviate from the desired range. Correction when the current deviation exceeds the hysteresis width (± i1) of the second hysteresis comparator 33b and does not return even when the output voltage level is switched is shown below based on FIG. 10 (a) and FIG. 10 (b). .
10 (a) and 10 (b) illustrate the switching of the output voltage level with the horizontal axis representing the current deviation between the alternating current command and the alternating current ir and the vertical axis representing the output voltage level of the sub-converter 4. FIG. In this case, the second hysteresis comparator 33b is used to switch the output voltage level so that the alternating current ir is suppressed when the current deviation exceeds the hysteresis width (± i1), and further, the third hysteresis comparator 33c is used. When the current deviation exceeds the hysteresis width (± i2), the output voltage level is further switched so that the alternating current ir is suppressed.

As shown in FIG. 10A, when the current deviation increases in the negative direction and exceeds Δi1, the current deviation (absolute value) decreases even if the output voltage level is switched from {+ V} to {0}. If it continues to increase and exceeds Δi2, the output voltage level is further switched from {0} to {−V} to forcibly change the current polarity and reduce the current deviation (absolute value). Further, as shown in FIG. 10B, when the current deviation increases in the positive direction and exceeds Δi1, even if the output voltage level is switched from {−V} to {0}, the current deviation does not decrease. If it continues to increase and exceeds Δi2, the output voltage level is further switched from {0} to {+ V} to forcibly change the current polarity to reduce the current deviation (absolute value).
As described above, the output control of the sub-converter 4 in the normal control mode is control for switching the output voltage level on the AC side of the sub-converter 4 so that the current deviation between the AC current command and the AC current ir becomes small. A sub-converter gate pulse 48r for switching the output voltage level is generated by the sub-converter gate pulse generation circuit 42r.

As shown in FIG. 6, in the sub-converter gate pulse generation circuit 42r, the outputs of the second and third hysteresis comparators 33b and 33c are input to the flip-flop circuits FF1, FF2, and FF3 and output as pulse signals. The flip-flop FF1 outputs a basic control signal RX for output current control (hereinafter referred to as a current control signal RX) based on the output of the second hysteresis comparator 33b, and the current control signal RX is the X of the sub-converter 4. It becomes a drive signal source for the side arm.
The line voltage phase from the PLL circuit 11 is input to the sub-converter gate pulse generation circuit 42r, and the circuit 47 determines the output polarity of the sub-converter 4 and generates a polarity control signal RY for switching the output polarity. . The polarity control signal RY of the sub-converter 4 is used as a drive signal source for the Y-side arm of the sub-converter 4. The output polarity of the sub-converter 4 is determined from the phase assuming the output voltage Vsub of the sub-capacitor shown in FIG.

  The sub-converter gate pulse 48r, which is a gate drive signal from the current control signal RX and polarity control signal RY to the semiconductor switching elements XP, XN, YP, and YN, is switched in four types as shown in FIG. Can be determined by pattern. Prior to the determination of the sub-converter gate pulse 48r, based on a level shift direction signal DLS as a shift correction signal obtained by balance control of each phase sub-capacitor voltage described later and a correction permission signal PP, a current control signal RX, The polarity control signal RY is changed with a predetermined logic. Then, current control signals based on the outputs of the second and third hysteresis comparators 33b and 33c are output from the flip-flop circuits FF2 and FF3, and the output voltage level of the sub-converter 4 is further switched according to the output. The sub-converter gate pulse 48r is corrected and output so as to forcibly change the current polarity.

  As described above, the control for switching the output voltage level on the AC side of the sub-converter 4 is performed so that the current deviation between the AC current command and the AC current ir becomes small. While this current control is performed for each phase, the alternating current command used uses a sub-capacitor average voltage that is an average value of the sub-capacitor voltages Vbr, Vbs, Vbt of each phase in the current command value calculation circuit 20. Calculated. For this reason, in order to improve the reliability of control, the second control unit responsible for output control of the sub-converter 4 has the circuit configuration shown in FIG. 7 and corrects the voltage balance of the sub-capacitor 9 of each phase. The generated level shift direction signal DLS and the correction permission signal PP are input to the sub-converter gate pulse generation circuit 42 (42r) for each phase, and the sub-converter gate pulse 48 has the voltage of the sub-capacitor 9 for each phase. Output to balance.

  As shown in FIG. 7, the first comparator 31 detects an imbalance of the voltages Vbr, Vbs, Vbt of the sub-capacitors 9 of each phase obtained from the voltage sensor 9a, and the second comparator 32 detects the current sensor 10 The polarity of each phase alternating current ir, is, it obtained from is detected. The outputs of the first and second comparators 31 and 32 and the current control signals RX, SX, TX and the polarity control signal RY of each phase generated in the sub-converter gate pulse generation circuit 42 (42r) of each phase. Based on SY, TY, the balance correction circuit 41 generates a level shift direction signal DLS and a correction permission signal PP. In the balance correction circuit 41, first, based on the outputs of the first and second comparators 31 and 32, it is determined whether or not it is necessary to shift the output voltage level of all phases of the sub-converter 4 in either the positive or negative direction. Based on the current control signals RX, SX, TX and the polarity control signals RY, SY, TY of each phase, the level shift direction signal DLS and the correction permission signal PP that match the actual control are generated.

  Specifically, out of the three phases, the voltage of the sub-capacitor 9 of a certain phase exceeds the upper threshold and the alternating current polarity is negative, or the voltage of the sub-capacitor 9 is equal to or lower than the lower threshold, and the alternating current polarity Is positive, that is, when the current is flowing in the direction from the AC power supply 1 to the load 2, it is determined that correction is required to shift the output voltage level of the sub-converter 4 of each phase simultaneously in the positive direction. However, if any of the phases is output with {+ V}, the level shift direction signal DLS is output by correcting so that the shift operation is not performed. Further, when the voltage of the sub-capacitor 9 of a certain phase exceeds the upper limit threshold and the alternating current is positive, or the voltage of the sub-capacitor 9 is equal to or lower than the lower limit threshold and the alternating current is negative, It is determined that correction is required to shift the output voltage level of the phase sub-converter 4 simultaneously in the negative direction for each phase. However, if any phase is output as {−V}, the level shift direction signal DLS is output by correcting so that the shift operation is not performed.

  The level shift direction signal DLS is used to control the voltage balance of the sub-capacitor 9 that is the DC voltage of the sub-converter 4, but the correction permission signal PP for limiting the level shift operation at a predetermined time interval is provided. Generate. This is because the balance control of the voltage of the sub-capacitor 9 is more effective than the above-described current control that causes the alternating current to follow the alternating current command, and avoids the possibility that the current control diverges. With this, appropriate control becomes possible. Here, the timing at which the level shift operation is permitted / prohibited and the duty ratio thereof can be freely set.

  In this way, when the voltage balance of the sub capacitor 9 is lost, the output voltage level of the sub converter 4 consisting of {−V, 0, + V} is simultaneously shifted in three phases, thereby controlling the energy balance of each phase. Thus, the voltage balance of the sub capacitor 9 can be kept stable. And current control which makes an alternating current follow an alternating current command is performed, performing balance control of the voltage of such a sub capacitor 9.

  This power converter performs a so-called high power factor converter operation that performs input power factor control in a normal control mode in which AC power is converted to constant DC power. In this case, except for a sudden change in the power supply voltage or the like, only the switching control for switching the output voltage level on the AC side of the sub-converter 4 is used to increase or decrease the AC current to obtain the instantaneous value of the AC current as an AC current command. The main converter 3 only needs to switch one pulse in one cycle synchronized with the phase of the AC power source 1. As described above, the main converter 3 switches at a low frequency, and the sub-converter 4 having a small voltage level is switched at a high frequency so as to suppress the alternating current, and the instantaneous value control of the alternating current is performed. High-speed current control can be realized. Further, since the instantaneous value control of the alternating current by the sub-converter 4 uses the two-stage hysteresis comparators 33b and 33c using two types of hysteresis widths, the current control can be stably performed even when the power supply voltage is disturbed. Can be continued and the reliability of the control is improved.

Then, the current control cannot be performed by the output control of the sub-converter 4, and when the current deviation exceeds (± ia), the one-pulse signal of the main converter 3 is turned off to suppress the overcurrent. The operation of the power conversion device can be continued without causing control failure even when it changes suddenly due to low or power failure.
Further, the switching control for switching the output voltage level on the AC side of the sub-converter 4 is performed by performing a correction for shifting the output voltage level so that the voltages of the three-phase sub capacitors 9 are balanced. Are balanced and maintained at a predetermined voltage.

  In addition, as described above, such control is configured by the comparator circuit 30 and the logic circuit 40 as the first and second control units, which are portions other than the current command value calculation circuit 20 that generates the alternating current command. Can be integrated into a hard logic circuit. For this reason, only the current command value arithmetic circuit 20 needs to be constituted by a CPU, so that an expensive and complicated CPU is not required. Further, since the number of information to be taken into the CPU is small, the number of A / D converters can be reduced. The configuration of the peripheral circuit is also simple. Therefore, high-speed and highly reliable current control can be realized with an inexpensive and simple control device 12.

  Since the main converter 3 is switched at a low frequency and the sub-converter 4 having a small voltage level is switched at a high frequency so as to suppress an alternating current, the AC reactor 5 may be small and the semiconductor switching of the sub-converter 4 may be performed. Regarding the element withstand voltage, an element having about one-fifth of the element withstand voltage used in the main converter 3 may be used.

Next, initial charging of the main capacitor 7 and the sub capacitor 9 at the time of starting the power conversion device configured as described above will be described. FIG. 12 is a flowchart showing an initial charging operation of the main capacitor 7 and the sub capacitor 9.
First, when the initial charging of the capacitors 7 and 9 is started at the time of starting the power converter (S0), the main capacitor 7 is charged with the power converter of the main circuit stopped. This is charged from the AC power source 1 via the AC / DC converter 113 or from the battery 110 via the DC / DC converter 111. When charging from a state in which the voltage of the main capacitor 7 is almost zero, charging is performed from the AC power source 1, and when the power converter is stopped due to an abnormality and then restarted, charging is performed from the battery 110. Even when charging is performed from the AC power source 1, the charging operation is performed under the control of the AC / DC converter 113, so that problems such as inrush current do not occur (S 1).

  When charging of the main capacitor 7 is completed (S2), the power converter is activated. At this time, the control device 12 is activated in the charge control mode (S3). Then, the power converter is operated to charge each sub capacitor 9. The sub-converter gate pulse 48 output from the sub-converter gate pulse generation circuit 42 of the control device 12 is switched by the gate pulse switching unit 100 provided in the output stage, and all the semiconductor switching elements in each sub-converter 4 are turned off. To be controlled. The main converter 3 is controlled by a first control signal generated in the same manner as in the normal control mode. That is, the main converter 3 is controlled by a gate drive signal composed of a single pulse signal based on the phase of the AC power supply 1 when the alternating current fluctuates within a normal range, and the gate drive signal is turned off when the alternating current is abnormal. Control is performed to suppress the current. Thereby, each subcapacitor 9 is charged while suppressing the alternating current (S4).

It is determined whether or not charging of all-phase sub-capacitors 9 is completed (S5), and when charging of sub-capacitors 9 of any phase is detected before charging of all phases is completed (S6), sub-charging that has not been fully charged is detected. Only the capacitor 9 continues to be charged. In this case, the sub-converter gate pulse 48 is switched by the gate pulse switching unit 100 so as to be in a through mode (charging stop) in which the charged sub-capacitor 9 is passed, and a predetermined semiconductor in the corresponding sub-converter 4 is switched. The switching element is turned on. The remaining sub-converters 4 continue the state where all the semiconductor switching elements are turned off. Again, the main converter 3 is controlled by the first control signal generated in the same manner as in the normal control mode, and the sub-capacitor 9 that has not been charged is charged while suppressing the alternating current (S7).
When the charging of the sub-capacitors 9 for all phases is completed in step S5, the initial charging of the capacitors 7 and 9 is completed (S8), and the control device 12 controls the power converter in the normal control mode. That is, the main converter 3 is controlled using the first control signal, and each sub-converter 4 is controlled using the second control signal generated so that the instantaneous alternating current value follows the alternating current command. Transition to normal operation of the converter (S9).

FIG. 13 is a diagram showing an example of a charge switching circuit 200 for switching the gate pulse to the sub-converter 4 when charging the sub-capacitor. The charge switching circuit 200 is in the sub-converter gate pulse generation circuit 42 of the control device 12 and includes a gate pulse switching unit 100 (100r, 100s, 100t), and a gate pulse switching unit 100 (100r, 100s, 100t). Is inserted into the output stage of the sub-converter gate pulse 48 (48r, 48s, 48t) in the sub-converter gate pulse generation circuit 42 (42r, 42s, 42t). FIG. 6 shows only the position of the gate pulse switching unit 100r in the sub-converter gate pulse generation circuit 42r for the R phase.
As illustrated in FIG. 13, the charge switching circuit 200 includes a gate pulse switching unit 100, comparators 101 to 103 that determine completion of charging of the sub-capacitors 9 of each phase, and a flip-flop 104 that generates a charging completion flag of each phase. To 106 and an AND circuit 107, and the gate pulse switching unit 100 switches and outputs the gate pulse to the sub-converter 4 by the outputs of the flip-flops 104 to 106.

  When charging of the main capacitor 7 is completed at the start of initial charging, the power converter is started in the charge control mode. At this time, a converter start signal is input to the charge switching circuit 200. The converter activation signal is input to the flip-flops 104 to 106, and the outputs of the flip-flops 104 to 106 are reset. As a result, all the sub-converter gate pulses 48 output from the sub-converter gate pulse generation circuit 42 are turned off. This state is the state of step S4 in the above-described initial charging operation, and the sub capacitors 9 of all phases are charged.

  Next, for example, if only the R-phase sub-capacitor 9 is completely charged, only the outputs of the comparator 101 and the flip-flop 104 change to “H”, and XPOUT (R ) And YPOUT (R) are turned off, and XNOUT (R) and YNOUT (R) are turned on. This state is the state of step S7 in the above-described initial charging operation, and the R-phase sub-converter 4 is in a through mode (charging stop) that passes through the sub-capacitor 9, and the S-phase and T-phase sub-capacitors that are not fully charged. Continue charging 9 only.

  When the charging of all the sub capacitors 9 is completed, the outputs of the flip-flops 104 to 106 all become “H”, and the output of the AND circuit 107 becomes “H”. As a result, the state in which the output of each selector 108 in the gate pulse switching unit 100 is fixed to “L” is switched to the XPIN and YPIN of each phase, which is the previous state before being input to the gate pulse switching unit 100. As shown in step S9, control in the normal control mode is started.

In this embodiment, when starting the power converter, prior to starting the power converter, the main capacitor 7 is connected from the AC power source 1 via the AC / DC converter 113 or from the battery 110 via the DC / DC converter 111. To charge. Thereafter, the power converter is activated, and the output of the main converter 3 and the sub-converter 4 is controlled in the charge control mode to charge each sub capacitor 9. When all the capacitors 7 and 9 are charged, the main converter 3 and the sub-converter 4 are output-controlled in the normal control mode.
The main converter 3 is similarly controlled by the first control signal in both the normal control mode and the charge control mode. That is, when the alternating current fluctuates within the normal range, a one-pulse signal based on the phase of the alternating-current power supply 1 is used. When the AC current is abnormal, the gate drive signal is turned off to control the AC current.
In the normal control mode, the sub-converter 4 is controlled by the second control signal generated so that the alternating current follows the alternating current command. In the charging control mode, the sub-converter 4 includes the sub capacitor 9 to be charged. All the semiconductor switching elements in the sub-converter 4 are turned off to charge the sub-capacitor 9.

  Thus, since the main converter 3 is controlled in the charge control mode for charging the sub-capacitor 9 in the same manner as in the normal control mode, it is possible to easily prevent the inrush current from flowing by suppressing the AC current, Distortion and the like can be prevented from occurring. Further, since the switching between the charging control and the normal control is performed only by the control device 12, there is no need for a current limiting component or a component for switching the current path as in the prior art, and the reliability on the AC power supply side is impaired with a simple configuration. The sub-capacitor 9 can be initially charged without this.

  In addition, the control device 12 includes a charge switching circuit 200. When the power converter is activated, the control device 12 switches to the charge control mode, detects that the sub-capacitors 9 of all phases have been charged, and switches to the normal control mode. The normal control can be easily and surely switched only by the control device 12, and the normal control can be promptly shifted.

  Further, since the main capacitor 7 is charged from the AC power source 1 via the AC / DC converter 113 or from the battery 110 via the DC / DC converter 111, problems such as inrush current do not occur when the main capacitor 7 is charged. . Furthermore, since the power converter is started after the main capacitor 7 is charged to charge the sub-capacitor 9, the sub-capacitor 9 can be reliably charged in the charge control mode, and the above-described effects are ensured. can get.

Embodiment 2. FIG.
In the first embodiment, the AC side is a three-phase AC and the number of sub-converters 4 is one for each phase. However, a plurality of sub-converters 4 may be connected in series for each phase. The AC side may be a single-phase AC.
FIG. 14 is a diagram showing a configuration of a main circuit (power converter) and a main capacitor charging circuit of a power conversion device according to Embodiment 2 of the present invention. As shown in FIG. 14, the power converter is arranged on the AC line side of the main converter 3a composed of a single-phase full-bridge circuit that converts AC power from a single-phase AC power source 1a into DC power. Two similar sub-converters 4 are connected in series, and an AC reactor 5 is further connected. The main converter 3a is a self-extinguishing type semiconductor such as an IGBT in which a diode is connected in anti-parallel, assuming that a main capacitor 7 as a power storage is connected to the DC side and DC power is regenerated to the AC side. A switching element 6 is used. Other configurations are the same as those in the first embodiment.

Also in this case, as in the first embodiment, the control device 12 has a charge control mode and a normal control mode to control the power converter. Further, at the time of starting the power converter, the main capacitor 7 and the sub capacitor 9 are charged in the same manner as the initial charging operation of the first embodiment (see FIG. 12).
That is, when initial charging of the capacitors 7 and 9 is started at the time of starting the power converter (S0), the main capacitor 7 is first switched from the AC power source 1 to the AC / DC converter 113 with the power converter of the main circuit stopped. Or from the battery 110 via the DC / DC converter 111 (S1).
When charging of the main capacitor 7 is completed (S2), the power converter is activated in the charge control mode (S3). Then, the power converter is operated to charge each sub capacitor 9. The main converter 3 is controlled by a first control signal generated in the same way as in the normal control mode, and all the semiconductor switching elements in each sub-converter 4 are controlled to be turned off (S4).
It is determined whether or not charging of all the sub-capacitors 9 has been completed (S5), and all charging has not been completed. If charging of any of the sub-capacitors 9 is detected (S6), the sub-converter 4 that has been charged is through. Switching to the mode (charge stop), all the semiconductor switching elements of the sub-capacitor 9 that has not been fully charged are turned off and charging continues (S7).
When charging of the sub-capacitors 9 for all phases is completed in step S5, the initial charging of the capacitors 7 and 9 is completed (S8), and the control device 12 controls the power converter in the normal control mode. Transition to normal operation (S9).

Also in this embodiment, by controlling the main converter 3 in the charge control mode for charging the sub-capacitor 9 in the same manner as in the normal control mode, it is possible to easily prevent the inrush current from flowing by suppressing the AC current. It is possible to prevent voltage distortion from occurring on the power supply side. Further, since the switching between the charging control and the normal control is performed only by the control device 12, the sub capacitor 9 can be initially charged with a simple configuration without impairing the reliability on the AC power source side, and the same effect as in the first embodiment can be obtained. can get.
In addition, the main converter 3 having a large voltage level is switched at a low frequency, and the sub-converter 4 having a small voltage level is switched at a high frequency so as to suppress an alternating current, as in the first embodiment. In the embodiment, since the generated voltage can be shared by connecting two sub-converters 4 in series, the voltage level of each sub-converter 4 can be further reduced, and the switching loss can be further reduced. Thereby, the efficiency of a power converter device can be improved and also electromagnetic noise can be reduced.

  Note that the voltages of the sub-capacitors 9 of the two sub-converters 4 may be different, and the voltage ratio (ratio of Vsub1 and Vsub2) is set according to the product specifications, such as 2: 1 or 3: 1. Can do. For example, if the voltage ratio between the voltage of the main capacitor 7 and Vsub1 and Vsub2 is 4: 2: 1, the total of these generated voltages is 0-7 depending on the combination of the main converter 3a and the two subconverters 4. Eight gradation voltages can be generated on the AC side. For this reason, a smooth voltage waveform closer to a sine wave is obtained on the AC side of the power converter, and harmonics can be further suppressed.

1 Three-phase AC power source, 1a AC power source, 3, 3a main converter,
4 Sub-converter, 7 Main capacitor as power storage, 7a Voltage sensor,
9 Sub capacitor as power storage, 9a Voltage sensor, 10 Current sensor,
11 PLL circuit, 12 controller,
20 Current command value calculation circuit as a current command calculation unit,
33a first hysteresis comparator, 33b second hysteresis comparator, 33c third hysteresis comparator,
42, 42r sub capacitor gate pulse generation circuit,
43, 43r main converter gate pulse generation circuit,
48 (48r, 48s, 48t) Sub-converter gate pulse as a second control signal,
100 (100r, 100s, 100t) gate pulse switching unit,
111 DC / DC converter, 113 AC / DC converter,
200 Charge switching circuit, i AC current (instantaneous value).

Claims (8)

Each has a plurality of semiconductor switching elements, performs power conversion between AC and DC, and includes a main converter and a sub-converter that outputs to each power storage unit on the DC side, and the DC voltage of the main converter is A power converter that is larger than the DC voltage of the sub-converter and is connected in series by arranging the sub-converter between the main converter and the AC power source;
A current command calculation unit that generates an AC current command, and a first control signal that generates a first control signal to the main converter so as to suppress an AC current instantaneous value based on the phase of the AC power source and the AC current command. Control which has a control part and the 2nd control part which generates the 2nd control signal to the above-mentioned sub-converter so that the above-mentioned alternating current instantaneous value may follow the above-mentioned alternating current command, and controls the above-mentioned power converter With the device,
The second control unit of the control device includes a hysteresis comparator, and switches the output voltage level on the AC side of the sub-converter so as to reduce a deviation between the AC current command and the AC current instantaneous value. 2 control signals,
The control device
A charge control mode for charging the power storage unit of the sub-converter in a state where the power storage unit of the main converter has been charged; and the first and second after the completion of charging of the power storage units of the main converter and the sub-converter. A normal control mode for controlling the power converter by generating a control signal of
In the charge control mode, the first control signal is generated to control the main converter, and the plurality of semiconductor switching elements in the sub-converter are all turned off to charge the power storage of the sub-converter. The power converter characterized by the above-mentioned. The control device includes a switching circuit between the charge control mode and the normal control mode, and the switching circuit is configured to start the power converter when the power converter of the main converter is fully charged. 2. The power conversion device according to claim 1, wherein the power conversion device is switched to the normal control mode by detecting completion of charging of the power storage of the sub-converter in the control mode. Power converter according to claim 1 or claim 2, characterized in that it comprises means for pre-charging the power storage unit of the main converter has a converter. The first control unit suppresses the alternating current instantaneous value when a deviation between the alternating current command and the alternating current instantaneous value exceeds a predetermined value with respect to a pulse signal generated based on the phase of the alternating current power supply. The power converter according to any one of claims 1 to 3, wherein the first control signal is generated by turning it off. The power conversion apparatus according to claim 4, wherein the first control unit includes a hysteresis comparator to generate the first control signal. The power converter includes a plurality of the sub-converters,
In the charging control mode, the control device individually detects completion of charging of each power storage unit of each sub-converter, and turns on a predetermined semiconductor switching element in the sub-converter for the sub-converter that has been charged. The power storage device according to any one of claims 1 to 5 , wherein the power storage device is passed to charge only the power storage devices of the remaining sub-converters. The power converter according to claim 6 , wherein the power converter has the sub-converters connected in series to each phase AC power line of the three-phase main converter. The power converter according to claim 6 , wherein the power converter has the plurality of sub-converters connected in series to an AC power line of the main converter.

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