CN106849719B - Seven electrical level inverters and seven level inverse conversion topological structures - Google Patents
Seven electrical level inverters and seven level inverse conversion topological structures Download PDFInfo
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- CN106849719B CN106849719B CN201710239909.6A CN201710239909A CN106849719B CN 106849719 B CN106849719 B CN 106849719B CN 201710239909 A CN201710239909 A CN 201710239909A CN 106849719 B CN106849719 B CN 106849719B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
Abstract
The present invention provides a kind of seven electrical level inverters and its topological structure, including DC/AC unit and DC/DC unit, DC/AC unit include: it is in parallel with C1 after T1 and T2 series connection, T1 input terminal is the first direct-flow input end P0；In parallel with C2 after T3 and T4 series connection, T4 output end is the second direct-flow input end N0；T5 input terminal is connected with T1 output end and T2 input terminal, and T5 output end is connected in the first end P1 of C3 with T7 input terminal；Second end N1, the T6 output end that T6 input terminal and T8 output end are connected in C3 is connected with T3 output end and T4 input terminal；T7 output end and T8 input terminal are connected with the first output end, and T2 output end and T3 input terminal are connected with second output terminal.DC/DC unit input terminal is P0 and N0, and output end is P1 and N1, maintains C3 voltage stabilization for supplementing C3 power difference.Switching tube quantity of the present invention is few, and capacitor number is few.
Description
Technical field
The present invention relates to converters technical fields, more particularly, to a kind of seven electrical level inverters and seven electricity
Flat inversion topological structure.
Background technique
The fast development of new energy power generation technology proposes requirements at the higher level, high-power inverter conduct to power electronic technique
The quality of the core component of transformation of electrical energy part, performance directly affects the quality of power output.Multi-electrical level inverter is because having
The advantages that output level number is more, harmonic wave of output voltage is small, output power, switching frequency is low, loss is small, high-efficient receive
The favor of persons.The multi-electrical level inverter of existing research specifically includes that diode clamp bit-type multi-electrical level inverter, capacitive mostly electricity
Flat inverter and cascade multilevel inverter.Wherein, diode clamp bit-type multi-electrical level inverter is to obtain higher level number,
A large amount of diode is needed, the complexity of topological structure is increased, a large amount of diode also improves a possibility that breaking down
And overall cost.Capacitive multi-electrical level inverter is also in this way, improving level number to sacrifice capacitor quantity as cost.And it cascades
Type multi-electrical level inverter need of work configures independent DC power supply, or uses Multiple coil phase-shifting transformer, leads to this body of device
Product is big, and the cost of cascade multilevel inverter also allows of no optimist.
Summary of the invention
The present invention provides that a kind of structure is simple, output level number is more, switching device quantity is few, seven level inverse conversions at low cost
Device and seven level inverse conversion topological structures.
According to an aspect of the present invention, a kind of seven level inverse conversion topological structures, including DC/AC unit and DC/DC are provided
Unit, in which: the DC/AC unit include the first DC capacitor C1 and the second DC capacitor C2,8 1~T8 of switch transistor T, with
The 8 diode D1~D8 and intermediate capacitance C3 of switching tube reverse parallel connection, wherein the first DC capacitor C1 and the second direct current
Hold C2 series connection, is respectively provided with initial voltage；Intermediate capacitance C3 has initial voltage；First switch tube T1 and second switch T2 string
In parallel with the first DC capacitor C1 after connection, the input terminal of first switch tube T1 is the first direct-flow input end P0；Third switch transistor T 3
In parallel with the second DC capacitor C2 after connecting with the 4th switch transistor T 4, the output end of the 4th switch transistor T 4 is the second direct-flow input end
N0；The input terminal of 5th switch transistor T 5 is connected with the input terminal of the output end of first switch tube T1 and second switch T2, and the 5th
The output end of switch transistor T 5 and the input terminal of the 7th switch transistor T 7 are connected in the first end P1 of intermediate capacitance C3；6th switch transistor T 6
Input terminal and the output end of the 8th switch transistor T 8 be connected in the second end N1 of intermediate capacitance C3, the output end of the 6th switch transistor T 6
It is connected with the input terminal of the output end of third switch transistor T 3 and the 4th switch transistor T 4；7th switch transistor T 7 and the 8th switch transistor T 8 string
It is in parallel with intermediate capacitance C3 after connection；Wherein, the output end of the 7th switch transistor T 7 and the input terminal of the 8th switch transistor T 8 and first defeated
Outlet O1 is connected, and the output end of the second switch T2 and the input terminal of third switch transistor T 3 are connected with second output terminal O2；
The input terminal of the DC/DC unit is the first direct-flow input end P0 and the second direct-flow input end N0, the output of the DC/DC unit
End is first end P1 and second end N1, for supplementing the power difference of seven level inverse conversion topological structure intermediate capacitance C3, maintains institute
State the voltage stabilization of intermediate capacitance C3.
According to another aspect of the present invention, provide one kind seven electrical level inverters, including at least one above-mentioned seven level is inverse
Variable topological structure.
DC/AC unit in above-mentioned seven level inverse conversions topological structure and seven electrical level inverters, by intermediate capacitance C3 and DC side
The first DC capacitor C1 and the second DC capacitor C2 and 1~T8 of switch transistor T constitute different accesses, and use DC/DC
Unit supplements the power difference of intermediate capacitance C3, and then maintains intermediate capacitance C3 voltage stabilization, thus output seven level voltages,
Compared with seven level topology of diode clamp bit-type, reduce clamp diode quantity；Compared with seven level topology of striding capacitance type,
Reduce striding capacitance quantity；Compared with seven level topology of cascade connection type, reduce independent current source quantity, it is therefore, of the present invention
Seven level inverse conversion topological structures and seven electrical level inverters are few using switching device quantity, and the connection between each switching tube is simple,
It is small in size, at low cost, engineering application value with higher.
Detailed description of the invention
By reference to following specific embodiments content and in conjunction with attached drawing, other objects and results of the present invention will more
Understand and should be readily appreciated that.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of seven level inverse conversions topological structure and seven electrical level inverters of the present invention；
Fig. 2 is the schematic diagram of the first working condition of seven level inverse conversions topological structure of the present invention；
Fig. 3 is the schematic diagram of the second working condition of seven level inverse conversions topological structure of the present invention；
Fig. 4 is the schematic diagram of the third working condition of seven level inverse conversions topological structure of the present invention；
Fig. 5 is the schematic diagram of the 4th working condition of seven level inverse conversions topological structure of the present invention；
Fig. 6 is the schematic diagram of the 5th working condition of seven level inverse conversions topological structure of the present invention；
Fig. 7 is the schematic diagram of the 6th working condition of seven level inverse conversions topological structure of the present invention；
Fig. 8 is the schematic diagram of the 7th working condition of seven level inverse conversions topological structure of the present invention.
Fig. 9 is the schematic diagram of another embodiment of DC/DC unit in seven level inverse conversions topological structure of the present invention；
Figure 10 is the equivalent schematic of seven electrical level inverter of three-phase of the present invention.
In the accompanying drawings, identical appended drawing reference indicates similar or corresponding feature or function.
Specific embodiment
In the following description, for purposes of illustration, it in order to provide the comprehensive understanding to one or more embodiments, explains
Many details are stated.It may be evident, however, that these embodiments can also be realized without these specific details.
Each embodiment according to the present invention is described in detail below with reference to accompanying drawings.
Fig. 1 is the structural schematic diagram of seven level inverse conversions topological structure and seven electrical level inverters of the present invention, such as Fig. 1 institute
Show, the seven level inverse conversions topological structure is made of DC/AC unit 1 and DC/DC unit 2, in which:
DC/AC unit 1 includes the first DC capacitor C1 and the second DC capacitor C2,8 1~T8 of switch transistor T and switching tube
The 8 diode D1~D8 and intermediate capacitance C3 of reverse parallel connection, wherein
First DC capacitor C1 and the second DC capacitor C2 series connection, is respectively provided with initial voltage, can be mentioned by DC power supply
For that can also be provided by the capacitor with initial voltage；
Intermediate capacitance C3 has initial voltage；
In parallel with the first DC capacitor C1 after first switch tube T1 and second switch T2 series connection, first switch tube T1's is defeated
Entering end is the first direct-flow input end P0, and the output end of first switch tube T1 is connected with the input terminal of second switch T2；
Third switch transistor T 3 and the 4th switch transistor T 4 series connection after it is in parallel with the second DC capacitor C2, the 4th switch transistor T 4 it is defeated
Outlet is the second direct-flow input end N0, and the output end of third switch transistor T 3 is connected with the input terminal of the 4th switch transistor T 4；
The input terminal of 5th switch transistor T 5 is connected with the input terminal of the output end of first switch tube T1 and second switch T2,
The output end of 5th switch transistor T 5 and the input terminal of the 7th switch transistor T 7 are connected in the first end P1 of intermediate capacitance C3；
The input terminal of 6th switch transistor T 6 and the output end of the 8th switch transistor T 8 are connected in the second end N1 of intermediate capacitance C3,
The output end of 6th switch transistor T 6 is connected with the input terminal of the output end of third switch transistor T 3 and the 4th switch transistor T 4；
It is in parallel with intermediate capacitance C3 after 7th switch transistor T 7 and the series connection of the 8th switch transistor T 8；
Wherein, the output end of the 7th switch transistor T 7 and the input terminal of the 8th switch transistor T 8 are connected with the first output end O1, institute
The input terminal of the output end and third switch transistor T 3 of stating second switch T2 is connected with second output terminal O2.
The input terminal of the DC/DC unit 2 is the first direct-flow input end P0 and the second direct-flow input end N0, the DC/DC
The output end of unit is the first end P1 and second end N1 of intermediate capacitance C3, for supplementing electricity among seven level inverse conversion topological structures
The power difference for holding C3, maintains the voltage stabilization of the intermediate capacitance C3.
Above-mentioned seven level inverse conversions topological structure switching tube quantity is few, and capacitor number is few, and small in size, at low cost, structure is simple, control
System is simple.
Preferably, each switch tube complementation conducting, that is to say, that the driving of first switch tube T1 and second switch T2
Signal logic on the contrary, the driving signal logic of third switch transistor T 3 and the 4th switch transistor T 4 on the contrary, the 5th switch transistor T 5 and the 6th
The driving signal logic of switch transistor T 6 on the contrary, the driving signal logic of the 7th switch transistor T 7 and the 8th switch transistor T 8 on the contrary, into one
Preferably, first switch tube T1 is identical with 3 driving signal logic of third switch transistor T, and the second switch T2 and the 4th is opened for step
The driving signal logic for closing pipe T4 is identical, and it is first switch respectively that DC/AC unit 1 above-mentioned in this way, which shares 3 groups of independent switching tubes,
Pipe T1, the 5th switch transistor T 5, the 7th switch transistor T 7, so that the control of switching tube is simpler.
The combination of the different conductings and shutdown of each switching tube of above-mentioned seven level inverse conversions topological structure, can make seven level
Inversion topological structure is in different working condition, and Fig. 2~Fig. 8 shows seven kinds of working conditions, in which:
As shown in Fig. 2, the first working condition: the driving of first switch tube T1, the 5th switch transistor T 5 and the 7th switch transistor T 7
Signal is high level, and the driving signal of second switch T2, the 6th switch transistor T 6 and the 8th switch transistor T 8 are low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and P0 → T1 → T5 → T7 →
O1 → O2 → C1 or O2 → O1 → D7 → D5 → D1 → P0 → C1；
As shown in figure 3, the second working condition: the driving of third switch transistor T 3, the 6th switch transistor T 6 and the 7th switch transistor T 7
Signal is high level, and the driving signal of the 4th switch transistor T 4, the 5th switch transistor T 5 and the 8th switch transistor T 8 is low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and O2 → T3 → D6 → C3 →
T7 → O1, or O2 → O1 → D7 → C3 → T6 → D3；
As shown in figure 4, third working condition: the driving of first switch tube T1, the 5th switch transistor T 5 and the 8th switch transistor T 8
Signal is high level, and the driving signal of second switch T2, the 6th switch transistor T 6 and the 7th switch transistor T 7 are low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and P0 → T1 → T5 → C3 →
D8 → O1 → O2 → C1 or O2 → O1 → T8 → C3 → D5 → D1 → P0 → C1；
As shown in figure 5, the 4th working condition: the driving of second switch T2, the 5th switch transistor T 5 and the 7th switch transistor T 7
Signal is high level, and the driving signal of first switch tube T1, the 6th switch transistor T 6 and the 8th switch transistor T 8 are low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and O2 → D2 → T5 → T7 →
O1 or O2 → O1 → D7 → D5 → T2；
As shown in fig. 6, the 5th working condition: the driving of the 4th switch transistor T 4, the 6th switch transistor T 6 and the 7th switch transistor T 7
Signal is high level, and the driving signal of third switch transistor T 3, the 5th switch transistor T 5 and the 8th switch transistor T 8 is low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and N0 → D4 → D6 → C3 →
T7 → O1 → O2 → C2 or O2 → O1 → D7 → C3 → T6 → T4 → N0 → C2；
As shown in fig. 7, the 6th working condition: the driving of second switch T2, the 5th switch transistor T 5 and the 8th switch transistor T 8
Signal is high level, and the driving signal of first switch tube T1, the 6th switch transistor T 6 and the 7th switch transistor T 7 are low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and O2 → D2 → T5 → C3 →
D8 → O1 or O2 → O1 → T8 → C3 → D5 → T2；
As shown in figure 8, the 7th working condition: the driving of the 4th switch transistor T 4, the 6th switch transistor T 6 and the 8th switch transistor T 8
Signal is high level, and the driving signal of third switch transistor T 3, the 5th switch transistor T 5 and the 7th switch transistor T 7 is low level,
The driving signal of remaining complementary switch pipe can may be low level, current direction for high level are as follows: and N0 → D4 → D6 → D8 →
O1 → O2 → C2 or O2 → O1 → T8 → T6 → T4 → N0 → C2.
In seven level inverse conversions topological structure of the present invention, pass through the first DC capacitor C1 of intermediate capacitance C3 and DC side
Plurality of level voltage can be exported with the combinations of voltages of the second DC capacitor C2, for example, the first DC capacitor C1 and the second direct current
Capacitor C2 parameter is identical, and initial voltage is 3E, and the initial voltage of the intermediate capacitance C3 is 2E, the first output end O1 and
Pressure difference of the second output terminal O2 under above-mentioned seven kinds of working conditions is respectively as follows: 3E, 2E, E, 0,-E, -2E, -3E, and for another example, first is straight
Galvanic electricity holds C1 and the second DC capacitor C2 initial voltage is 3E, and the initial voltage of the intermediate capacitance C3 is E, and described first is defeated
Pressure difference of the outlet O1 and second output terminal O2 under above-mentioned seven kinds of working conditions is respectively as follows: 3E, E, 2E, 0, -2E,-E, -3E.Separately
Outside, in each output level value, intermediate capacitance C3 charge/discharge state is only charge/discharge/bypass thrin,
In the case of the initial voltage of C3 is E, at the first working condition, the 4th working condition and the 7th working condition, intermediate capacitance C3
In bypass condition；In the second working condition, by the voltage output+E level of intermediate capacitance C3, intermediate capacitance C3 only charges or only
Electric discharge；In third working condition, output+2E level is subtracted each other by the voltage of the first DC capacitor C1 and the voltage of intermediate capacitance C3,
Intermediate capacitance C3 only charges or only discharges at this time；In the 5th working condition, by the voltage of the second DC capacitor C2 and centre electricity
The voltage for holding C3 is added output -2E level, and intermediate capacitance C3 only charges or only discharges at this time；In the 6th working condition, in
Between capacitor C3 voltage output-E level, intermediate capacitance C3 only charges or only discharges.
The intermediate capacitance C3 of above-mentioned seven level inverse conversions topological structure DC/AC unit 1 is in a modulation wave period, and charge function
Rate and discharge power is unequal leads to be difficult to maintain its voltage stabilization, DC/DC unit 2 is for supplementing seven level inverse conversion topological structures
The power difference of intermediate capacitance C3 maintains the voltage stabilization of the intermediate capacitance C3, in a preferred embodiment, the DC/
DC unit 2 includes 4 9~T12 of switch transistor T, diode D9~D12 and the second inductance L2 group with switching tube reverse parallel connection
At, in which:
The input terminal of 9th switch transistor T 9 is connected with the first direct-flow input end P0, the output end and the tenth of the 9th switch transistor T 9
The input terminal of two switch transistor Ts 12 is connected；
The input terminal of tenth switch transistor T 10 is connected with the output end of the 11st switch transistor T 11, the tenth switch transistor T 10 it is defeated
Outlet is connected with the second direct-flow input end N0；
11st switch transistor T 11, the second inductance L2 and the series connection of the 12nd switch transistor T 12；
The input terminal of 11st switch transistor T 11 is connected with the first end P1 of intermediate capacitance, the output of the 11st switch transistor T 11
End is connected with the second inductance L2；
The input terminal of 12nd switch transistor T 12 is connected with the second inductance L2, the output end of the 12nd switch transistor T 12 and centre
The second end N1 of capacitor is connected.
Preferably, the 9th switch transistor T 9 is simultaneously turned on the tenth switch transistor T 10, and the 11st switch transistor T 11 is opened with the 12nd
It closes pipe T12 to simultaneously turn on, the 9th switch transistor T 9 conducting complementary with the 11st switch transistor T 11, DC/DC unit 2 above-mentioned in this way has 1 group
Independent switching tube, i.e. the 9th switch transistor T 9, so that seven level inverse conversion topological structures can share 4 groups of independent switching tubes, point
It is not first switch tube T1, the 5th switch transistor T 5, the 7th switch transistor T 7 and the 9th switch transistor T 9.
Above-mentioned DC/DC unit can overcome intermediate capacitance C3 to be difficult in a modulation wave period, and maintenance voltage is stable to be lacked
Point, the course of work are as follows:
(1) the 9th switch transistor T 9 and the tenth switch transistor T 10 simultaneously turn on, the 11st switch transistor T 11 and the 12nd switching tube
T12 is simultaneously turned off, and the second inductance L2 stores energy by the 9th switch transistor T 9 and the tenth switch transistor T 10；
(2) the 9th switch transistor T 9 and the tenth switch transistor T 10 simultaneously turn off, the 11st switch transistor T 11 and the 12nd switching tube
T12 is open-minded simultaneously, and the current direction of the second inductance L2 remains unchanged from bottom to top, and the second inductance L2 releases energy to be filled to capacitor C3
Electricity；
(3) the 9th switch transistor T 9 and the tenth switch transistor T 10 simultaneously turn off, the 11st switch transistor T 11 and the 12nd switching tube
T12 is open-minded simultaneously, and capacitor C3 releases energy, and is stored up by the 11st switch transistor T 11 and the 12nd switch transistor T 12 to the second inductance L2
Deposit energy；
(4) the 9th switch transistor T 9 and the tenth switch transistor T 10 while open-minded, the 11st switch transistor T 11 and the 12nd switching tube
T12 is simultaneously turned off, and the second inductance L2 releases energy.
It illustrate only one embodiment of DC/DC unit in Fig. 1, but the present invention is not limited thereto, in actual circuit
Other DC/DC circuit topological structures, such as the double active bridge DC/DC circuit topological structures of bridge-type can also be used, such as Fig. 9 institute
Show, the input and output of this topological structure are formed by connecting by two full bridge units through transformer T, using the control mode of phase shift between bridge
The transmitted in both directions of power flow may be implemented, to maintain the voltage stabilization of capacitor C3.
Above-mentioned seven level inverse conversions topological structure includes DC/AC unit and DC/DC unit, wherein DC/AC unit passes through centre
The combinations of voltages of the first DC capacitor C1 and the second DC capacitor C2 of capacitor C3 and DC side pass through 1~T8 of switch transistor T in turn
Seven level voltages are exported, but since in a modulation wave period, intermediate capacitance C3 charge power and discharge power are difficult to protect
Hold equal, intermediate C3 voltage is difficult to stablize, and in response to this problem, the present invention supplements the power of DC/AC unit using DC/DC unit
Difference, and then intermediate capacitance C3 voltage stabilization is maintained, the power difference that intermediate capacitance C3 is charged and discharged is DC/DC circuit
Transimission power, therefore the circuit capacity of required DC/DC unit is small.
Above-mentioned 1~T12 of switch transistor T can select power switch tube according to virtual voltage and power grade, such as MOSFET or
IGBT is illustrated in attached drawing by taking IGBT as an example, and the anode of diode and the emitter of power switch tube connect, the yin of diode
Pole is connected with the collector of power switch tube, but the present invention is not limited thereto.
In an alternate embodiment of the present invention where, above-mentioned seven level inverse conversions topological structure further includes filter unit, setting
Between the first output end O1 and second output terminal O2, the filter unit can be filter, it is preferable that such as Fig. 1 institute
Show, the filter unit be concatenated filter capacitor C4 and the first inductance L1, filter capacitor C4 and load resistance R it is in parallel after with filter
Wave inductance L series connection, the first inductance L1 are connected to the first output end O1, the filter capacitor C4 and are connected to second output terminal
O2。
Fig. 1 shows seven electrical level inverter of the present invention, as shown in Figure 1, seven electrical level inverter includes at least one
A above-mentioned seven level inverse conversions topological structure, can also include control unit (not shown), and described control unit generates trigger pulse
The on-off for controlling each switching tube in seven electrical level inverter topological structures is connected the combination with shutdown by different switching tubes, realizes
The different working condition of the seven level inverse conversions topological structure.
Seven level inverse conversions topological structure shown in fig. 1 is single-phase seven level inverse conversions topological structure, and shown in fig. 1 includes one
Seven electrical level inverters of single-phase seven level inverse conversions topological structure are single-phase seven electrical level inverter, but the present invention is not limited thereto,
Preferably, seven electrical level inverter includes multiple seven level inverse conversions topological structures, the multiple seven level inverse conversions topology
Structural circuit combination forms polyphase inverter, such as: three-phase inverter, as shown in Figure 10, three single-phase seven level inverse conversions
Three second output terminal O2 of topology, which are connected, is used as neutral point, and three the first output end O1 are connected with three-phase alternating current load, and three
First direct-flow input end P0 is connected after being connected with DC power anode, the connected rear and DC power supply of three the second direct-flow input end N0
Cathode is connected.
In an embodiment of the present invention, anti-parallel diodes D1~D12 can be independent diode, be also possible to
The diode of 1~T12 of switch transistor T integration packaging together.
Above-mentioned seven electrical level inverter is for traditional seven electrical level inverters, diode, switching tube and capacitors count
It is much less, so that inverter losses are small, high-efficient, and the simple topology to simplify seven electrical level inverters of connection structure,
So that control is simple, and reduce costs, while on the basis of guaranteeing intermediate capacitance C3 voltage stabilization, the electricity of DC/DC unit
Appearance of a street amount is small, is suitable for mesohigh, high-power applications occasion, and before new energy grid-connected power field also has wide application
Scape.
Although content disclosed above shows exemplary embodiment of the present invention, it should be noted that without departing substantially from power
Under the premise of benefit requires the range limited, it may be many modifications and modify.In addition, although element of the invention can be with a
The description of body form requires, and is unless explicitly limited individual element it is also contemplated that having multiple elements.
Claims (10)
1. a kind of seven level inverse conversion topological structures, which is characterized in that including DC/AC unit and DC/DC unit, in which:
The DC/AC unit includes the first DC capacitor C1 and the second DC capacitor C2,8 1~T8 of switch transistor T and switching tube
The 8 diode D1~D8 and intermediate capacitance C3 of reverse parallel connection, wherein
First DC capacitor C1 and the second DC capacitor C2 series connection, is respectively provided with initial voltage；
Intermediate capacitance C3 has initial voltage；
, the input terminal of first switch tube T1 in parallel with the first DC capacitor C1 after first switch tube T1 and second switch T2 series connection
For the first direct-flow input end P0；
, the output end of fourth switch transistor T 4 in parallel with the second DC capacitor C2 after third switch transistor T 3 and the series connection of the 4th switch transistor T 4
For the second direct-flow input end N0；
The input terminal of 5th switch transistor T 5 is connected with the input terminal of the output end of first switch tube T1 and second switch T2, and the 5th
The output end of switch transistor T 5 and the input terminal of the 7th switch transistor T 7 are connected in the first end P1 of intermediate capacitance C3；
The input terminal of 6th switch transistor T 6 and the output end of the 8th switch transistor T 8 are connected in the second end N1 of intermediate capacitance C3, and the 6th
The output end of switch transistor T 6 is connected with the input terminal of the output end of third switch transistor T 3 and the 4th switch transistor T 4；
It is in parallel with intermediate capacitance C3 after 7th switch transistor T 7 and the series connection of the 8th switch transistor T 8；
Wherein, the output end of the 7th switch transistor T 7 and the input terminal of the 8th switch transistor T 8 are connected with the first output end O1, and described
The output end of two switch transistor Ts 2 and the input terminal of third switch transistor T 3 are connected with second output terminal O2；
The input terminal of the DC/DC unit is the first direct-flow input end P0 and the second direct-flow input end N0, the DC/DC unit
Output end is the first end P1 and second end N1 of intermediate capacitance C3, for supplementing seven level inverse conversion topological structure intermediate capacitance C3's
Power difference maintains the voltage stabilization of the intermediate capacitance C3.
2. seven level inverse conversions topological structure according to claim 1, which is characterized in that the first switch tube T1 and second
The driving signal logic of switch transistor T 2 on the contrary, the driving signal logic of third switch transistor T 3 and the 4th switch transistor T 4 on the contrary, the 5th
The driving signal logic of switch transistor T 5 and the 6th switch transistor T 6 on the contrary, the 7th switch transistor T 7 and the 8th switch transistor T 8 driving signal
Logic is opposite.
3. seven level inverse conversions topological structure according to claim 2, which is characterized in that the first switch tube T1 and third
3 driving signal logic of switch transistor T is identical, and the driving signal logic of the second switch T2 and the 4th switch transistor T 4 is identical.
4. seven level inverse conversions topological structure according to claim 1, which is characterized in that the work shape of the DC/AC unit
State includes following seven kinds of working conditions, in which:
First working condition: the driving signal of first switch tube T1, the 5th switch transistor T 5 and the 7th switch transistor T 7 are high level,
The driving signal of second switch T2, the 6th switch transistor T 6 and the 8th switch transistor T 8 are low level, current direction are as follows: P0 → T1
→ T5 → T7 → O1 → O2 → C1 or O2 → O1 → D7 → D5 → D1 → P0 → C1；
Second working condition: the driving signal of third switch transistor T 3, the 6th switch transistor T 6 and the 7th switch transistor T 7 is high level,
The driving signal of 4th switch transistor T 4, the 5th switch transistor T 5 and the 8th switch transistor T 8 is low level, current direction are as follows: O2 → T3
→ D6 → C3 → T7 → O1, or O2 → O1 → D7 → C3 → T6 → D3；
Third working condition: the driving signal of first switch tube T1, the 5th switch transistor T 5 and the 8th switch transistor T 8 are high level,
The driving signal of second switch T2, the 6th switch transistor T 6 and the 7th switch transistor T 7 are low level, current direction are as follows: P0 → T1
→ T5 → C3 → D8 → O1 → O2 → C1 or O2 → O1 → T8 → C3 → D5 → D1 → P0 → C1；
4th working condition: the driving signal of second switch T2, the 5th switch transistor T 5 and the 7th switch transistor T 7 are high level,
The driving signal of first switch tube T1, the 6th switch transistor T 6 and the 8th switch transistor T 8 are low level, current direction are as follows: O2 → D2
→ T5 → T7 → O1 or O2 → O1 → D7 → D5 → T2；
5th working condition: the driving signal of the 4th switch transistor T 4, the 6th switch transistor T 6 and the 7th switch transistor T 7 is high level,
The driving signal of third switch transistor T 3, the 5th switch transistor T 5 and the 8th switch transistor T 8 is low level, current direction are as follows: N0 → D4
→ D6 → C3 → T7 → O1 → O2 → C2 or O2 → O1 → D7 → C3 → T6 → T4 → N0 → C2；
6th working condition: the driving signal of second switch T2, the 5th switch transistor T 5 and the 8th switch transistor T 8 are high level,
The driving signal of first switch tube T1, the 6th switch transistor T 6 and the 7th switch transistor T 7 are low level, current direction are as follows: O2 → D2
→ T5 → C3 → D8 → O1 or O2 → O1 → T8 → C3 → D5 → T2；
7th working condition: the driving signal of the 4th switch transistor T 4, the 6th switch transistor T 6 and the 8th switch transistor T 8 is high level,
The driving signal of third switch transistor T 3, the 5th switch transistor T 5 and the 7th switch transistor T 7 is low level, current direction are as follows: N0 → D4
→ D6 → D8 → O1 → O2 → C2 or O2 → O1 → T8 → T6 → T4 → N0 → C2.
5. seven level inverse conversions topological structure according to claim 4, which is characterized in that the first DC capacitor C1 and second is straight
It is 3E that galvanic electricity, which holds C2 initial voltage, and the initial voltage of the intermediate capacitance C3 is 2E, and the first output end O1 and second is defeated
Pressure difference of the outlet O2 under above-mentioned seven kinds of working conditions is respectively as follows: 3E, 2E, E, 0,-E, -2E, -3E.
6. seven level inverse conversions topological structure according to claim 4, which is characterized in that the first DC capacitor C1 and second is straight
It is 3E that galvanic electricity, which holds C2 initial voltage, and the initial voltage of the intermediate capacitance C3 is E, the output of the first output end O1 and second
Pressure difference of the O2 under above-mentioned seven kinds of working conditions is held to be respectively as follows: 3E, E, 2E, 0, -2E,-E, -3E.
7. seven level inverse conversions topological structure according to claim 1, which is characterized in that the DC/DC unit includes 4 and opens
Close pipe T9~T12, diode D9~D12 and the second inductance L2 with switching tube reverse parallel connection, wherein
The input terminal of 9th switch transistor T 9 is connected with the first direct-flow input end P0, and the output end of the 9th switch transistor T 9 is opened with the 12nd
The input terminal for closing pipe T12 is connected；
The input terminal of tenth switch transistor T 10 is connected with the output end of the 11st switch transistor T 11, the output end of the tenth switch transistor T 10
It is connected with the second direct-flow input end N0；
11st switch transistor T 11, the second inductance L2 and the series connection of the 12nd switch transistor T 12；
The input terminal of 11st switch transistor T 11 is connected with the first end P1 of intermediate capacitance, the output end of the 11st switch transistor T 11 with
One end of second inductance L2 is connected；
The input terminal of 12nd switch transistor T 12 is connected with the other end of the second inductance L2, the output end of the 12nd switch transistor T 12 with
The second end N1 of intermediate capacitance is connected.
8. seven level inverse conversions topological structure according to claim 1, which is characterized in that further include concatenated filter capacitor C4
With the first inductance L1, the first inductance L1 is connected to the first output end O1, the filter capacitor C4 and is connected to second output terminal
O2。
9. a kind of seven electrical level inverters, which is characterized in that including described in any claim at least one claim 1~8
Seven level inverse conversion topological structures.
10. seven electrical level inverter according to claim 9, which is characterized in that including multiple seven level inverse conversions topologys
Structure, the multiple seven level inverse conversions topological structure electrical combination form polyphase inverter.
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| CN102710133A (en) * | 2012-06-12 | 2012-10-03 | 阳光电源股份有限公司 | Seven-level circuit, a grid-connected inverter and modulation method and device of seven-level circuit |
| CN104333249A (en) * | 2014-10-28 | 2015-02-04 | 北京合力电气传动控制技术有限责任公司 | Seven-level inverter circuit and control method thereof, multi-phase inverter and frequency converter |
| KR20170037747A (en) * | 2015-09-25 | 2017-04-05 | 전남대학교산학협력단 | Single-phase seven-level grid-connected inverter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102710133A (en) * | 2012-06-12 | 2012-10-03 | 阳光电源股份有限公司 | Seven-level circuit, a grid-connected inverter and modulation method and device of seven-level circuit |
| CN104333249A (en) * | 2014-10-28 | 2015-02-04 | 北京合力电气传动控制技术有限责任公司 | Seven-level inverter circuit and control method thereof, multi-phase inverter and frequency converter |
| KR20170037747A (en) * | 2015-09-25 | 2017-04-05 | 전남대학교산학협력단 | Single-phase seven-level grid-connected inverter |
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