JPWO2012098709A1 - Power converter - Google Patents

Abstract

The AC side of the main inverter (2) and the sub-inverters (3) and (4) having a relatively low DC voltage are connected in series, and the output sum is connected to the power system (8). When the system voltage is normal, the control device (100) outputs a voltage of one pulse from the main inverter (2) in a half cycle in accordance with the system cycle, and performs PWM control on each of the sub inverters (3) and (4). Thus, the output current i is controlled to cause the voltage Vsub of the DC capacitors (3a) and (4a) of the sub inverters (3) and (4) to follow the command value Vsub *. When a voltage drop occurs in the system voltage, the control device (100) switches each sub inverter (3), (4) from PWM control to control bypassing the DC capacitors (3a), (4a), and overcurrent. Is detected and the switching of the main inverter (2) is temporarily switched from on to off to perform overcurrent suppression control.

Description

  The present invention relates to a power conversion device in which an AC side is connected to a power system and performs power conversion between DC and AC.

As a conventional power converter, there is one configured by connecting in series the AC side of a single-phase sub-converter having a DC voltage smaller than the DC voltage of the main converter to the AC line of each phase of the three-phase main converter. . Then, the main converter is driven by a single gate pulse in a half circuit, and the phase voltage of the power converter is generated by the sum of the phase voltages of the converters (see, for example, Patent Document 1).
In addition, a conventional power conversion device according to another example includes a system voltage level drop detection unit that detects that the system voltage is equal to or lower than a predetermined voltage level, and a detection duration measurement unit that measures a detection duration of the detection unit. And detecting the instantaneous voltage drop of the system when the system voltage level drop detecting means detects the level drop and the measurement time by the detection duration measuring means is not less than a predetermined time. The duration measurement means is disabled near the voltage zero cross point. In addition, gate block means for shutting off the gate signal of the inverter is provided, and when an instantaneous voltage drop occurs, the output is stopped by shutting off the gate signal of the inverter to protect the device from overcurrent, and when power is restored A gate signal is sent to the inverter to resume operation (for example, see Patent Document 2).

International Publication WO2007-129456 JP 2003-153433 A

In the power conversion device described in Patent Document 1, a plurality of power converters are combined to output a voltage, thereby reducing the size and increasing the efficiency. However, when the instantaneous voltage drop of the connected power system occurs, an overcurrent is generated, and an overvoltage is generated due to fluctuations in the DC voltage of the sub-converter. Therefore, it is necessary to protect the power converter.
Japanese Patent Application Laid-Open No. 2004-228561 describes a technique for protecting an overcurrent by stopping the operation of the power converter when an instantaneous voltage drop of the power system occurs. However, when the power conversion apparatus that links the distributed power source to the power system stops, there is a problem that the power supply-demand balance in the power system is lost. Further, if the power conversion device converts AC power from the system into DC power and supplies power to the load device, there is a concern that damage due to the stop of the load device occurs. Furthermore, once the power converter is stopped and disconnected from the power system line, it takes time to start the operation of the power converter again.

  The present invention has been made to solve the above-described problems, and is a power conversion device configured by connecting a main power converter and a sub power converter having a relatively low DC voltage in series. The purpose is to continue operation with good reliability by protecting against overcurrent and overvoltage even when the instantaneous voltage drop of the power system.

  The power conversion device according to the present invention has an AC side connected to a power system and performs power conversion between DC and AC, and includes a power converter and a control device. The power converter includes one main power converter and a DC capacitor having a voltage lower than the DC input voltage of the main power converter, and the main power converter and the AC side are connected in series. A power converter, and generates a total voltage of the AC side generated voltages of the main power converter and the sub power converter on the AC side. The control device causes the converter current, which is an output phase current of the power converter, to follow a command value so that the voltage of the DC capacitor of the sub power converter becomes a set voltage. And generating a gate signal to the sub power converter to control the power converter. The control device detects a voltage drop of the system voltage, controls the sub power converter so as to bypass the DC capacitor, and controls the converter current by output control of only the main power converter. To control.

  The power converter according to the present invention suppresses the overvoltage by suppressing the voltage fluctuation of the DC capacitor of the sub power converter when the instantaneous voltage drop of the power system occurs, and suppresses the overcurrent by the operation of the main power converter. Can continue. For this reason, the bad influence which acts on the electric power system which is an electric power supply destination, or load equipment can be reduced, and the reliability of a power converter device improves.

It is a figure which shows the structure of the power converter device by Embodiment 1 of this invention. It is a figure which shows the structure of the main inverter and sub inverter by Embodiment 1 of this invention. It is a wave form diagram of each part for demonstrating operation | movement of the power converter device by Embodiment 1 of this invention. It is a figure explaining the switching operation of the main inverter by Embodiment 1 of this invention. It is a wave form diagram explaining the operation | movement of the main inverter by Embodiment 1 of this invention. It is a figure which shows operation | movement of the sub inverter by Embodiment 1 of this invention. It is a figure which shows switching of the operation mode in the power converter device by Embodiment 1 of this invention. It is a figure which shows the structure of the main inverter by Embodiment 2 of this invention. It is a figure which shows the structure of the main circuit of the power converter device by Embodiment 3 of this invention.

Embodiment 1 FIG.
Hereinafter, a power converter according to Embodiment 1 of the present invention will be described with reference to the drawings.
FIG. 1 shows a power conversion apparatus according to Embodiment 1 of the present invention, more specifically, power that converts DC power from a DC power source 1 such as a solar battery into AC power and transmits power to the power system 8. It is a figure which shows the structure of a converter.
The inverter circuit as a power converter that is a main circuit is connected in series to a main inverter 2 as a main power converter that converts DC power of the DC power source 1 into AC power, and to each phase AC line of the main inverter 2. Sub inverters 3 and 4 as sub power converters, and a smoothing filter connected to the subsequent stage of sub inverter 4 and made up of AC reactors 5 and 6 and a filter capacitor 7 are connected to power system 8 via switch 28. Be lined up. In this case, two sub-inverters 3 and 4 are connected to each other in two phases, but the illustration of each phase is omitted.

  FIG. 2 shows the configuration of the main inverter 2 and the sub-inverters 3 and 4. As shown in FIG. 2 (a), the main inverter 2 is a three-phase three-level inverter having two DC capacitors 2a and 2b connected in series on the DC side, each of which has an IGBT or the like in which diodes are connected in antiparallel. A plurality of self-extinguishing semiconductor switching elements are provided. In the U phase, the high voltage side element MHU and the low voltage side element MLU are connected in series between the DC buses, and are connected with opposite polarities between the connection point and the connection point of the two DC capacitors 2a and 2b. Two elements RF1U and RF2U are connected. Similarly, in the V phase, MHV and MLV are connected in series between the DC buses, and two elements RF1V connected in opposite polarities between the connection point and the connection point of the two DC capacitors 2a and 2b. , RF2V is connected. In the W phase, MHW and MLW are connected in series between DC buses, and two elements RF1W and RF2W connected in opposite polarities are connected between the connection point and the connection point of the two DC capacitors 2a and 2b. Connecting. The semiconductor switching element used here may be GCT, GTO, transistor, MOSFET or the like in addition to IGBT.

As shown in FIG. 2B, each of the sub inverters 3 and 4 is a single-phase full-bridge circuit including four semiconductor switching elements (SHA1, SLA1, SHB1, and SLB1) and (SHA2, SLA2, SHB2, and SLB2). And DC capacitors 3a and 4a for holding a DC voltage. When the voltage of the DC capacitors 3a and 4a is V, three levels of voltage values of {−V, 0, + V} are applied between the AC terminals of the sub-inverters 3 and 4 depending on the on / off combination of the semiconductor switching elements. can do.
Here, the sub-inverters 3 and 4 are connected in series in a two-stage configuration to increase the number of output voltage levels and output a voltage with less harmonics. Three or more multistage configurations may be used.

The output voltage of the sub-inverters 3 and 4 of each phase is superimposed on the output voltage of each phase of the main inverter 2, and the sum of the output voltage of the main inverter 2 and the output voltage of each sub-inverter 3 and 4 is smoothed by the smoothing filter 5. To the power system 8 via .about.7. The switch 28 performs a shut-off operation when there is an abnormality.
The voltage of the DC capacitors 3a and 4a of the sub inverters 3 and 4 is a DC voltage input to the main inverter 2, in this case, 1/2 of the voltage of the DC power supply 1 (or the voltage of the DC capacitors 2a and 2b). It is set smaller than.

  Further, as shown in FIG. 1, the main inverter 2 and the sub-inverters 3 and 4 in the inverter circuit are controlled by gate signals 22a, 23a, and 23b from the control device 100. The power converter detects an AC voltage sensor 10 that detects an AC voltage of the power system 8 and a DC voltage Vsub (hereinafter referred to as a sub DC voltage Vsub) of the DC capacitors 3a and 4a of the sub inverters 3 and 4. Voltage sensors 11 and 12, and a current sensor 13 that detects an output current i (iu, iv, iw) of each phase of the inverter circuit. The control device 100 is based on the detected voltage and current. The main inverter 2 and the sub-inverters 3 and 4 are output-controlled. The current sensor 13 is positive in the direction flowing from the inverter circuit toward the power system 8.

  The control device 100 includes a phase detection unit 14 that detects the phase θ of the power system 8, a current detection unit 15 that detects the effective current (component) ir and reactive current (component) ix of the output current i, and the sub DC voltage Vsub. DC voltage control unit 16 that controls the reactive current control unit 17, active current control unit 18, gate control unit 21 that determines the output signal of the inverter circuit, and main gate that generates the gate signal 22a of the main inverter 2 The circuit unit 22 and the sub-gate circuit unit 23 that generates the gate signals 23a and 23b of the sub-inverters 3 and 4 are provided. Further, the control device 100 detects an overcurrent of the output current i and outputs a signal for switching the switching of the main inverter 2, and monitors the system voltage to instantaneously reduce the voltage (hereinafter referred to as an instantaneous voltage drop). Is provided with a voltage abnormality detection unit 26 for detecting the switching and a switching determination unit 27 for switching control of the inverter circuit at the time of a sag.

Operation | movement of the control apparatus 100 of the power converter device comprised in this way is demonstrated below.
The phase detector 14 detects the phase θ of the power system 8 from the voltage detected by the AC voltage sensor 10, and the current detector 15 is based on the output current (value) i detected by the current sensor 13 and the phase θ. The active current (component) ir and the reactive current (component) ix are detected from the output current i. The reactive current control unit 17 performs control so that the reactive current ix follows the reactive current command ix ^* to which the reactive current ix is applied, and the active current control unit 18 performs control so that the active current ir follows the active current command ir ^*. I do. Further, the DC voltage control unit 16 performs control so that the sub DC voltage Vsub detected by the voltage sensors 11 and 12 follows the given command value Vsub ^* . The gate control unit 21 determines the output signal of the inverter circuit in accordance with the outputs from the DC voltage control unit 16, the reactive current control unit 17, and the active current control unit 18, and the output from the gate control unit 21. The main gate circuit unit 22 generates and outputs a gate signal 22a of the main inverter 2, and the sub-gate circuit unit 23 generates and outputs gate signals 23a and 23b of the sub-inverters 3 and 4. The main inverter 2 is controlled so as to output a voltage of one pulse in a half cycle in accordance with the system cycle, and the sub inverters 3 and 4 are PWM-controlled.

  Further, the output current i detected by the current sensor 13 is also input to the operation determination unit 25, and the operation determination unit 25 causes the main gate when the output current i exceeds a predetermined upper limit value 24 as a predetermined current value. An overcurrent suppression signal is output to the circuit unit 22, and the on signal of the gate signal 22a of the main inverter 2 is temporarily turned off. In addition, the system voltage detected by the AC voltage sensor 10 is also input to the voltage abnormality detection unit 26. The voltage abnormality detection unit 26 detects a voltage drop at the time of the instantaneous drop of the system voltage, and the switching determination unit 27 detects the voltage drop. Then, a switching signal for switching the PWM control of each of the sub-inverters 3 and 4 to the control for bypassing the DC capacitors 3a and 4a, that is, the DC circuit bypass control is output to the gate control unit 21.

In the inverter circuit, the control device 100 controls the output current i as described above, so that the sum of the output voltage of each phase of the main inverter 2 and the output voltage of the sub-inverters 3 and 4 of each phase is substantially equal to the system voltage. It is controlled to be equivalent. Further, since the control device 100 controls the output of the inverter circuit so that the sub DC voltage Vsub of the sub inverters 3 and 4 follows the command value Vsub ^* , the DC capacitors 3a and 4a do not include other power sources outside. Voltage can be stabilized.

  The operation of the inverter circuit controlled in this way will be described below with reference to FIGS. FIG. 3 shows the voltage and current waveforms of each part for one phase of the inverter circuit, and shows the operation when the system voltage is normal from the center to the left side of the waveform diagram and at the right side when the voltage drops instantaneously. 3A is a system voltage, FIG. 3B is an output current i of the inverter circuit, FIG. 3C is an output voltage of the main inverter 2, FIG. 3D is an output voltage of the sub inverters 3 and 4, 3E shows the output voltage of the inverter circuit, which is the sum of the output voltage of the main inverter 2 and the output voltages of the sub inverters 3 and 4, and FIG. 3F shows each waveform of the sub DC voltage Vsub. 4 is a diagram showing a pattern of the switching operation of the main inverter 2, FIG. 5 is a waveform diagram for explaining the operation of the main inverter 2 at the time of a sag, and FIG. 6 is a sub-inverter 3 at the time of a sag. 4 is a diagram illustrating four current paths. FIG.

When the system voltage is normal, in the inverter circuit, the main inverter 2 outputs a voltage of one pulse in a half cycle in accordance with the system cycle, and each of the sub inverters 3 and 4 outputs a voltage by PWM control. The output voltage is controlled to a waveform close to a sine wave similar to the system voltage. Further, the sub DC voltage Vsub is controlled so as to follow a constant command value Vsub ^* .
As shown in FIG. 4, when the main inverter 2 outputs a pulse of positive voltage (P), MH (MHU, MHV, MHW) and RF1 (RF1U, RF1V, RF1W) among the four semiconductor switching elements in each phase. ), And ML (MLU, MLV, MLW) and RF2 (RF2U, RF2V, RF2W) are turned off. When the main inverter 2 outputs a negative voltage (N) pulse, ML and RF2 are turned on, and MH and RF1 are turned off. When the output is 0, RF1 and RF2 are turned on, and MH and ML. And turn off. The gate signal 22a of the main inverter 2 is a combination of four gate signals for turning on and off the four elements in this case.

When an instantaneous drop occurs in the power system 8, an overcurrent is generated in the inverter circuit, and the operation determination unit 25 of the control device 100 outputs an overcurrent suppression signal to the main gate circuit unit 22. In addition, the voltage abnormality detection unit 26 detects an instantaneous drop, the switching determination unit 27 outputs a switching signal, and each of the sub inverters 3 and 4 switches from PWM control to DC circuit bypass control at the time of instantaneous drop.
As described above, when the main inverter 2 outputs a positive voltage pulse, MH and RF1 are turned on, ML and RF2 are turned off, and the output current i flows in the positive direction. When the output current i becomes an overcurrent in this switching state, the output current i is decreased by temporarily turning off MH and RF1. Further, when the main inverter 2 outputs a negative voltage pulse, ML and RF2 are turned on, MH and RF1 are turned off, and the output current i flows in the negative direction. When the output current i becomes an overcurrent in this switching state, the output current i is decreased by temporarily turning off ML and RF2.

As shown in FIG. 5, in the U phase of the main inverter 2, when the overcurrent occurs when the gate signal to the MHU and RF1U is on (H) and the output current i is positive, the overcurrent suppression signal is generated. Then, the gate signal to MHU and RF1U is turned off (L). As a result, the output current i decreases, but the gate signals to the MHU and RF1U are restored to the original state after a predetermined period. Thereafter, the output current i increases again, but when an overcurrent occurs, the current decreases by switching the gate signal. By repeating such a switching operation, the switching operation can be performed without the output current i exceeding the rated current of the apparatus, and the inverter circuit can be continuously operated.
The same control is performed when an overcurrent occurs when the gate signal to the MLU and RF2U is on (H) and the output current i is negative. Further, although the U phase has been described here, the same applies to the V phase and the W phase.

As described above, when an overcurrent is generated in the inverter circuit, the ON signal of the gate signal 22a of the main inverter 2 is temporarily turned OFF to reduce the output current i.
The timing for changing the switching state changed by the overcurrent to the original state is set in consideration of the maximum switching frequency of the semiconductor switching element. For example, after the switching state is changed, it can be changed after a certain time has elapsed, or can be changed in synchronization with the PWM carrier frequency.

On the other hand, in each of the sub-inverters 3 and 4, switching from PWM control to DC circuit bypass control at the time of instantaneous drop occurs, and current flows by bypassing the DC capacitors 3a and 4a through the path shown in FIG. Specifically, SLA1, SLB1, SLA2, and SLB2 are turned on, and SHA1, SHB1, SHA2, and SHB2 are turned off. Thereby, a current flows without passing through the DC capacitors 3a and 4a, and the DC capacitors 3a and 4a can suppress the voltage fluctuation of the sub DC voltage Vsub at the time of an instantaneous drop.
The DC circuit bypass control of each sub-inverter 3 and 4 may be performed by turning on SHA1, SHB1, SHA2, and SHB2 and turning off SLA1, SLB1, SLA2, and SLB2.

  As described above, when an instantaneous drop occurs in the power system 8, the inverter circuit switches to control for suppressing overcurrent and overvoltage and continues to operate, and then the voltage abnormality detection unit 26 confirms that the system voltage has returned to normal. If detected, the original control is restored. That is, each sub-inverter 3 and 4 returns to PWM control, and in the state where no overcurrent is generated in the main inverter 2, a voltage of one pulse is output in the original control, that is, in a half cycle in accordance with the system cycle. It will be a thing.

In the above-described embodiment, it has been described that when an overcurrent occurs in the inverter circuit, the control device 100 performs the overcurrent suppression control for temporarily turning off the ON signal of the gate signal 22a of the main inverter 2. This overcurrent suppression control is PWM control, and an overcurrent is generated when the power system 8 is instantaneously low. Therefore, the control device 100 is similar to switching the main inverter 2 to PWM control when the power supply is instantaneously reduced. explain.
FIG. 7 shows the state of the power system 8 (system voltage) and the control mode of the inverter circuit by the control device 100. When the system voltage is normal (A), the main inverter 2 is output-controlled by 1-pulse control that outputs 1-pulse voltage in accordance with the system cycle, and the sub-inverters 3 and 4 are PWM-controlled. At the time of a sag (B), the main inverter 2 changes the output control method from 1-pulse control to PWM control and outputs a voltage in accordance with the system voltage, and the sub inverters 3 and 4 are controlled by DC circuit bypass control. The output is zero voltage.

In general, in an inverter device connected to the power system, an overcurrent and an overvoltage are detected with respect to an abnormality occurring on the power system side, specifically, an instantaneous drop caused by a lightning strike to a transmission line. Need to be protected from. As described above, the conventional inverter device is disconnected from the power system in order to protect the device.
In this embodiment, when the power system 8 is normal, the output sum of the main inverter 2 and the sub-inverters 3 and 4 is connected to the power system 8 via the smoothing filters 5 to 7, and when the power system 8 is sag, the sub-inverter 3 4 DC capacitors 3 a, 4 a are bypassed, and overcurrent is suppressed by switching control of the main inverter 2.
When a transient power fluctuation occurs due to a voltage drop, there is a concern that the voltage of the sub DC voltage Vsub also fluctuates and becomes an overvoltage. However, when the voltage drops, the voltage of the sub DC voltage Vsub is bypassed to bypass the DC capacitors 3a and 4a. Variation can be suppressed. In addition, since the overcurrent is suppressed and the current is controlled by the switching control of the main inverter 2, the operation of the inverter circuit can be continued and the power system 8 can be stably supplied with power.

Embodiment 2. FIG.
In the power conversion device shown in the first embodiment, the main inverter 200 using a three-phase two-level inverter as shown in FIG. 8 may be used as the main power converter. In this case, for example, when the output current i of the inverter circuit becomes an overcurrent in the positive direction, the high-voltage MHU (MHV, MHW) is turned off from on to decrease the output current i, and again after a lapse of a predetermined period. By turning it on, the output current i flows so as to approach the desired current value. In the case of an overcurrent in the negative direction, the same control is performed to switch the low voltage side element from on to off. Thereby, the overcurrent of the inverter circuit is suppressed, and the same effect as in the first embodiment can be obtained.

  In the first and second embodiments, the main inverters 2 and 200 have a three-phase configuration, but may be a single-phase inverter.

Embodiment 3 FIG.
In the first and second embodiments, a so-called interconnection inverter linked to the power system 8 from the DC power source 1 via the inverter circuit has been described. However, the main circuit of the power conversion device converts AC power into DC power. A converter circuit may be used.
FIG. 9 shows a power converter according to Embodiment 3 of the present invention, more specifically, a power converter that converts AC power from the power system 8 into DC power and supplies the DC load 35 with power. It is a figure which shows a structure.
A converter circuit as a power converter that is a main circuit is connected in series to a main converter 32 as a main power converter that converts DC power of the DC power supply 1 into AC power, and to each phase AC line of the main converter 32. Sub-converters 33 and 34 as sub power converters are arranged on the power system 8 side, and the AC side is connected in series. In addition, a smoothing filter including AC reactors 5 and 6 and a filter capacitor 7 is connected to the front stage of the sub-converters 33 and 34, and the power system 8 is connected via the switch 28. The DC voltage from the main converter 32 is output to the DC load 35 through the smoothing capacitor 36.
Also in this case, by the same control as in the first embodiment, the operation can be continued while suppressing the overvoltage and overcurrent when the power system 8 is instantaneously dropped.

Claims (7)

In the power conversion device in which the AC side is connected to the power system and performs power conversion between DC / AC,
A main power converter and a DC capacitor having a voltage lower than the DC input voltage of the main power converter, and the AC side is connected in series between the AC side of the main power converter and the power system 1 or A power converter comprising a plurality of sub power converters, and generating a total voltage of the AC side generated voltage of the main power converter and the sub power converter on the AC side;
The main power converter and the sub power are adjusted so that the converter current, which is the output phase current of the power converter, follows the command value and the voltage of the DC capacitor of the sub power converter becomes a set voltage. A control device for controlling the power converter by generating a gate signal to the converter,
The control device detects a voltage drop of the system voltage, controls the sub power converter so as to bypass the DC capacitor, and controls the converter current by output control of only the main power converter. Power conversion device.   The control device controls the main power converter so as to output a voltage of one pulse in a half cycle of the system voltage. When the converter current exceeds a predetermined current value, the phase of the main power converter is controlled. The power converter according to claim 1, wherein the gate signal is temporarily turned off from on.   The control device controls the main power converter so as to output a voltage of one pulse in a half cycle of the system voltage, and controls the sub power converter so that the converter current follows the command value. 2. The power converter according to claim 1, wherein when the PWM control is performed and a voltage drop of the system voltage is detected, the sub power converter is controlled to bypass the DC capacitor and the main power converter is PWM controlled. .   The power converter according to any one of claims 1 to 3, wherein the sub power converter is connected between the main power converter and the power system.   The power converter according to claim 4, wherein a DC power source is connected to the DC side of the main power converter, and the DC power of the DC power source is converted into AC power and connected to the power system.   The power converter according to claim 4, wherein a DC load is connected to the DC side of the main power converter, and AC power of the power system is converted to DC power and supplied to the DC load.   The main power converter is a three-phase power converter, and the sub power converter having a single-phase configuration is connected to each phase AC line of the three-phase power converter. The power converter device described in 1.

Images