JP6035845B2 - AC power supply system - Google Patents

AC power supply system Download PDF

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JP6035845B2
JP6035845B2 JP2012101085A JP2012101085A JP6035845B2 JP 6035845 B2 JP6035845 B2 JP 6035845B2 JP 2012101085 A JP2012101085 A JP 2012101085A JP 2012101085 A JP2012101085 A JP 2012101085A JP 6035845 B2 JP6035845 B2 JP 6035845B2
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power supply
voltage
balancer
supply system
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康寛 玉井
康寛 玉井
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Fuji Electric Co Ltd
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本発明は、3レベルの電圧レベルを備えた直流電源を用いる電力変換装置を複数台並列接続する交流電源システムの直流回路に接続されるコンデンサ直列回路の各コンデンサの電圧を均等化するための回路及び制御技術に関する。   The present invention provides a circuit for equalizing the voltages of capacitors in a capacitor series circuit connected to a DC circuit of an AC power supply system in which a plurality of power converters using DC power supplies having three voltage levels are connected in parallel. And control technology.

図6に、特許文献1に記載の3レベル電力変換回路の第1の従来例を示す。直流電源の正極Pと負極Nとの間にはコンデンサC1とC2の直列回路が接続され、直列接続点が零極Mとなる。直流電源と並列に半導体スイッチS1とS2との直列回路が、この直列回路の直列接続点と直流電源の零極との間に半導体スイッチS3とS4を逆並列接続した双方向スイッチが、各々接続され、半導体スイッチS1とS2との直列接続点が交流端子Uに接続され、1相分(U相)の回路となる。V相とW相も同じ構成である。U相を例に説明する。半導体スイッチS1がオンすると交流端子Uには正極Pの電位が、半導体スイッチS3とS4で構成された双方向スイッチがオンすると交流端子Uには零極Mの電位が、半導体スイッチS2がオンすると交流端子Uには負極Nの電位が、各々出力され、3レベルの電位が出力可能である。この時、交流端子UにはコンデンサC1から電力を供給するモード、コンデンサC2から電力を供給するモード、コンデンサC1とC2の直列回路から電力を供給するモードがある。   FIG. 6 shows a first conventional example of the three-level power conversion circuit described in Patent Document 1. A series circuit of capacitors C1 and C2 is connected between the positive electrode P and the negative electrode N of the DC power supply, and the series connection point becomes the zero pole M. A series circuit of semiconductor switches S1 and S2 in parallel with the DC power supply is connected to a bidirectional switch in which semiconductor switches S3 and S4 are connected in reverse parallel between the series connection point of the series circuit and the zero pole of the DC power supply. Then, the series connection point of the semiconductor switches S1 and S2 is connected to the AC terminal U to form a circuit for one phase (U phase). The V phase and the W phase have the same configuration. The U phase will be described as an example. When the semiconductor switch S1 is turned on, the potential of the positive electrode P is applied to the AC terminal U. When the bidirectional switch composed of the semiconductor switches S3 and S4 is turned on, the potential of the zero pole M is applied to the AC terminal U and the semiconductor switch S2 is turned on. The AC terminal U outputs a potential of the negative electrode N, and can output a three-level potential. At this time, the AC terminal U has a mode for supplying power from the capacitor C1, a mode for supplying power from the capacitor C2, and a mode for supplying power from the series circuit of the capacitors C1 and C2.

図7に、特許文献2に記載の3レベル電力変換回路の第2の従来例を示す。直流回路のP端子は直流電源の正極Pに、直流回路のM端子は直流電源の零極Mに、直流回路のN端子は直流電源の負極Nに、各々接続されているが、ここでは直流電源は省略されている。直流電源の正極Pと負極Nとの間にはコンデンサC1とC2の直列回路が接続され、直列接続点が零極Mとなる。
3レベル電力変換回路は、第1の従来例と同様に、交流端子U、V、Wには直流回路の正極Pの電位、零極Mの電位及び負極Nの電位の3つのレベルの電圧を出力可能であるが、詳細は省略する。図6に示した回路と同様に、交流端子にはコンデンサC1から電力を供給するモード、コンデンサC2から電力を供給するモード、コンデンサC1とC2の直列回路から電力を供給するモードがある。コンデンサC1の電圧とC2の電圧は、交流端子に接続される負荷の状態により放電量が違うため、電圧がアンバランスとなり、所望の電圧を交流端子に出力できなくなる課題がある。これを解決するための手段として、図7に示すようなバランサー回路を主回路に設ける方法と、図8に示す特許文献3に記載されているような制御回路を用いる方法が知られている。
FIG. 7 shows a second conventional example of the three-level power conversion circuit described in Patent Document 2. The P terminal of the DC circuit is connected to the positive pole P of the DC power supply, the M terminal of the DC circuit is connected to the zero pole M of the DC power supply, and the N terminal of the DC circuit is connected to the negative electrode N of the DC power supply. The power supply is omitted. A series circuit of capacitors C1 and C2 is connected between the positive electrode P and the negative electrode N of the DC power supply, and the series connection point becomes the zero pole M.
In the three-level power conversion circuit, as in the first conventional example, the AC terminals U, V, and W are supplied with voltages of three levels of the positive electrode P potential, the zero pole M potential, and the negative electrode N potential in the DC circuit. Output is possible, but details are omitted. Similar to the circuit shown in FIG. 6, the AC terminal has a mode in which power is supplied from the capacitor C1, a mode in which power is supplied from the capacitor C2, and a mode in which power is supplied from a series circuit of the capacitors C1 and C2. Since the amount of discharge differs between the voltage of the capacitor C1 and the voltage of the capacitor C2 depending on the state of the load connected to the AC terminal, there is a problem that the voltage becomes unbalanced and a desired voltage cannot be output to the AC terminal. As means for solving this, there are known a method of providing a balancer circuit as shown in FIG. 7 in the main circuit and a method of using a control circuit as described in Patent Document 3 shown in FIG.

図7に示すバランサー回路は、コンデンサC1の電圧とC2の電圧をバランスさせるための回路である。コンデンサC1とC2の直列回路と並列に、IGBTDB1とDB2との直列回路が接続され、コンデンサC1とC2の直列接続点とIGBTDB1とDB2の直列接続点との間にリアクトルL1が接続された構成である。この様な構成における動作を説明する。コンデンサC1の電圧がコンデンサC2の電圧より高い時には、IGBTDB1をオンさせ、リアクトルL1にエネルギーを蓄積して、IGBTDB1をオフさせた時にコンデンサC2を充電する。コンデンサC2の電圧がコンデンサC1の電圧より高い時には、IGBTDB2をオンさせ、リアクトルL1にエネルギーを蓄積して、IGBTDB2をオフさせた時にコンデンサC1を充電する。この様な動作を繰り返すことにより、コンデンサC1とC2の電圧をバランスさせる。   The balancer circuit shown in FIG. 7 is a circuit for balancing the voltage of the capacitor C1 and the voltage of C2. In a configuration in which a series circuit of IGBTDB1 and DB2 is connected in parallel with a series circuit of capacitors C1 and C2, and a reactor L1 is connected between a series connection point of capacitors C1 and C2 and a series connection point of IGBTDB1 and DB2. is there. The operation in such a configuration will be described. When the voltage of the capacitor C1 is higher than the voltage of the capacitor C2, the IGBT DB1 is turned on, energy is accumulated in the reactor L1, and the capacitor C2 is charged when the IGBTDB1 is turned off. When the voltage of the capacitor C2 is higher than the voltage of the capacitor C1, the IGBT DB2 is turned on, energy is accumulated in the reactor L1, and the capacitor C1 is charged when the IGBTDB2 is turned off. By repeating such an operation, the voltages of the capacitors C1 and C2 are balanced.

図8に、特許文献3に記載されたコンデンサ電圧を制御回路でバランスさせる従来例を示す。10がバランス制御回路で、交流出力電圧指令(VR*、VS*、VT*)を、コンデンサC1とC2の電圧差が零になるように補正する制御方式である。コンデンサC1の電圧EDC1とコンデンサC2の電圧EDC2とを加算器11に入力し、この差a1を求め、このa1を零にするための調節器12を通して、補正量a2を求める。この補正量と正弦波テーブルから得られる正弦波信号とを掛算器(14R、14S、14T)で掛算し、補正正弦波を求め、この補正正弦波と電圧指令(VR*、VS*、VT*)とを加算器(21R,21S,21T)で加算して、新たな電圧指令信号(VR**、VS**、VT**)とする構成である。   FIG. 8 shows a conventional example in which the capacitor voltage described in Patent Document 3 is balanced by a control circuit. A balance control circuit 10 is a control system that corrects the AC output voltage command (VR *, VS *, VT *) so that the voltage difference between the capacitors C1 and C2 becomes zero. The voltage EDC1 of the capacitor C1 and the voltage EDC2 of the capacitor C2 are input to the adder 11, the difference a1 is obtained, and the correction amount a2 is obtained through the regulator 12 for making this a1 zero. The correction amount and the sine wave signal obtained from the sine wave table are multiplied by a multiplier (14R, 14S, 14T) to obtain a corrected sine wave, and the corrected sine wave and voltage command (VR *, VS *, VT *). ) Are added by adders (21R, 21S, 21T) to form new voltage command signals (VR **, VS **, VT **).

特開2011−109789号公報JP 2011-109789 A 特開2002−199738号公報JP 2002-199738 A 特開平7−79574号公報Japanese Patent Laid-Open No. 7-79574

上述のように、3レベル電力変換回路で、直列接続された各コンデンサの電圧をバランスさせる方式として、主回路にバランサー回路を設ける方法と制御回路で電圧指令に補正を加える方法(コンバータの場合には電圧指令又は電流指令の何れかに補正を加える方法)があるが、電源装置を並列接続した並列システムにおいては、制御回路で電圧指令に補正を加える方法では下記の問題がある。
並列システムにおいては、図9に示すように、変換器1と変換器2は負荷電流を均等に分担させるために、同一の電圧を出力する。即ち、I1=I2=I/2とする。
ここで、変換器1と変換器2の出力電圧が異なると、2台の変換器間を循環する電流(横流)が流れることになる。この結果、負荷への供給電流以上の電流を変換器が負担することになり、装置容量が大きくなるため、横流は極力抑制する必要がある。しかし、制御回路で電圧指令に補正を加える方法では、電圧指令への補正値は各々のコンデンサ電圧のバランス状態から決まるため、並列接続された各々の変換器の出力電圧が異なった値となり、横流が発生する問題がある。
一方、主回路にバランサー回路を設ける方法では、変換器の並列運転制御と干渉することがなく、並列システムにおいては有用な方式であるが、変換器の主回路に半導体スイッチとリアクトルを追加する必要があり、装置が大型で高価格となる問題がある。
As described above, in the three-level power conversion circuit, as a method of balancing the voltage of each capacitor connected in series, a method of providing a balancer circuit in the main circuit and a method of correcting the voltage command in the control circuit (in the case of a converter) However, in a parallel system in which power supply devices are connected in parallel, the method of correcting the voltage command by the control circuit has the following problems.
In the parallel system, as shown in FIG. 9, the converter 1 and the converter 2 output the same voltage in order to share the load current equally. That is, I1 = I2 = I / 2.
Here, when the output voltages of the converter 1 and the converter 2 are different, a current (cross current) circulating between the two converters flows. As a result, the converter bears more current than the supply current to the load, and the capacity of the apparatus increases, so that it is necessary to suppress cross current as much as possible. However, in the method of correcting the voltage command by the control circuit, the correction value to the voltage command is determined from the balance state of each capacitor voltage, so the output voltage of each converter connected in parallel becomes a different value, There is a problem that occurs.
On the other hand, the method of providing a balancer circuit in the main circuit does not interfere with the parallel operation control of the converter and is a useful method in a parallel system. However, it is necessary to add a semiconductor switch and a reactor to the converter main circuit. There is a problem that the apparatus is large and expensive.

従って、本発明の課題は、3レベルの電力変換装置を並列接続した交流電源システムに適用可能な小型で低価格のコンデンサ電圧バランス手段を提供することである。   Accordingly, an object of the present invention is to provide a compact and low-cost capacitor voltage balancing means applicable to an AC power supply system in which three-level power converters are connected in parallel.

上述の課題を解決するために、第1の発明においては、交流入力電圧を正極、零極及び負極の3つのレベルを持った直流電源に変換する交流−直流変換回路と、前記直流電源の正極と零極との間に接続される第1のコンデンサと、前記直流電源の零極と負極との間に接続される第2のコンデンサと、前記第1及び第2のコンデンサそれぞれの電圧を均等化するバランサー回路と、前記直流電源から3つのレベルを持った交流電圧を作り出す直流−交流変換回路とで構成される交流−交流変換装置の交流入力同士と交流出力同士を複数台並列接続した交流電源システムにおいて、前記バランサー回路の出力電流が所定値未満のときは、前記バランサー回路のみで制御して、前記バランサー回路の出力電流が所定値以上になったことを検出したときは、前記交流−直流変換回路の制御回路又は前記直流−交流変換回路の制御回路の何れか前記第1及び第2のコンデンサそれぞれの電圧を均等化する直流電圧バランス制御を有効にする。 In order to solve the above-described problems, in the first invention, an AC-DC conversion circuit that converts an AC input voltage into a DC power source having three levels of a positive electrode, a zero electrode, and a negative electrode, and a positive electrode of the DC power source The first capacitor connected between the first and second poles, the second capacitor connected between the first and second negative poles of the DC power supply, and the voltages of the first and second capacitors are equalized. AC-AC converter composed of a balancer circuit to be converted and a DC-AC converter circuit that generates an AC voltage having three levels from the DC power supply, and an alternating current in which a plurality of AC inputs and AC outputs are connected in parallel in the power supply system, and the output current of the balancer circuit when less than the predetermined value, by controlling only the balancer circuit, the output current of the balancer circuit detects that equal to or greater than a predetermined value , The AC - Enable DC voltage balance control for equalizing the first and second capacitors each voltage either of the control circuit of the AC conversion circuit - control circuit or the DC-DC converter circuit.

の発明においては、第1の発明における前記バランサー回路は、直流電源の正極と負極との間に接続されたそれぞれのダイオードを逆並列接続した半導体スイッチ直列回路と、前記半導体スイッチ直列回路の直列接続点と前記直流電源の零極との間に接続されたリアクトルと電流検出器との直列回路と、から構成する。 In the second invention, the balancer circuit in the first invention includes a semiconductor switch series circuit in which respective diodes connected between a positive electrode and a negative electrode of a DC power supply are connected in reverse parallel, and the semiconductor switch series circuit. It is comprised from the series circuit of the reactor and current detector which were connected between the series connection point and the zero pole of the said DC power supply.

の発明においては、第1〜第の何れかの発明における前記並列接続された交流−交流変換装置それぞれの直流電源の正極、零極及び負極に双方向性の3レベル昇降圧チョッパ回路を介して蓄電池を接続する。 In a third invention, a bidirectional three-level buck-boost chopper circuit is connected to the positive electrode, the zero electrode, and the negative electrode of each DC power supply of each of the AC-AC converters connected in parallel in any one of the first to second inventions. Connect the storage battery via

の発明においては、第1〜第の何れかの発明における前記複数台並列接続される交流−交流変換装置それぞれの直流電源の正極、零極及び負極同士をそれぞれ接続し、その接続線に双方向性の3レベル昇降圧チョッパ回路を介して蓄電池を接続する。


In the fourth invention, the positive electrode, the zero electrode and the negative electrode of each of the plurality of AC-AC converters connected in parallel in the first to second inventions are connected to each other, and the connection line A storage battery is connected via a bidirectional three-level buck-boost chopper circuit.


本発明では、主回路に接続したバランサー回路の出力電流を検出し、この電流が所定値以下の時にはバランサー回路だけでコンデンサ電圧のバランス制御を行い、所定値(上限値)に達した時には、変換器の制御回路でのバランス制御を有効にするようにした。   In the present invention, the output current of the balancer circuit connected to the main circuit is detected. When this current is less than a predetermined value, the balance control of the capacitor voltage is performed only by the balancer circuit, and when the current reaches the predetermined value (upper limit value), the conversion is performed. The balance control in the control circuit of the vessel was made effective.

この結果、バランサー回路の電流が所定値以下に制限され、バランサー回路が小型、低価格となる。また、負荷に正負の不平衡がない場合はバランサー回路のみが動作するので、制御回路のバランス制御との併用期間は最小限にでき、並列運転時の横流の発生を最小限に抑制できる。   As a result, the current of the balancer circuit is limited to a predetermined value or less, and the balancer circuit becomes small and inexpensive. In addition, when there is no positive / negative imbalance in the load, only the balancer circuit operates, so that the combined use period with the balance control of the control circuit can be minimized, and the occurrence of cross current during parallel operation can be minimized.

本発明を説明するための第1の交流電源並列システム図である。It is a first AC power supply parallel system diagram for explaining the present invention. 本発明を説明するための第2の交流電源並列システム図である。It is a 2nd alternating current power supply parallel system figure for demonstrating this invention. 本発明のバランサー回路の詳細回路図である。It is a detailed circuit diagram of the balancer circuit of the present invention. 本発明のバランサー回路の制御回路ブロック図である。It is a control circuit block diagram of the balancer circuit of the present invention. 本発明のバランス制御回路例である。It is an example of the balance control circuit of this invention. 3レベル電力変換回路の例1である。It is Example 1 of a 3 level power converter circuit. 3レベル電力変換回路の例2とバランサー回路の従来例である。They are Example 2 of a 3 level power converter circuit, and the prior art example of a balancer circuit. 変換器制御回路でのバランス制御回路の例である。It is an example of the balance control circuit in a converter control circuit. 並列システムを説明するための図である。It is a figure for demonstrating a parallel system.

本発明の要点は、3レベル変換回路を用いた交流−交流変換装置を並列接続した交流電源システムの直流回路に接続されたコンデンサ直列回路の各コンデンサ電圧をバランスさせるため、直流回路にはバランサー回路を、変換装置の制御回路にはバランス制御回路を、各々備え、バランサー回路の出力電流が所定値以上になった時には制御回路のバランス制御回路を有効とするようにしている点である。   The main point of the present invention is to balance each capacitor voltage of a capacitor series circuit connected to a DC circuit of an AC power supply system in which AC-AC converters using a three-level conversion circuit are connected in parallel. The control circuit of the converter is provided with a balance control circuit, respectively, and the balance control circuit of the control circuit is made effective when the output current of the balancer circuit exceeds a predetermined value.

図1に、本発明が対象とする第1の交流電源システム図を、図2に第2の交流電源システム図を、各々示す。
図1は、No.1UPS(無停電電源装置)とNo.2UPSを並列接続した交流電源システム図で、交流−交流変換回路の各々の直流回路に双方向性の3レベルチョッパを介して蓄電池を接続して無停電化を図った構成である。両方とも回路構成は同じであるので、No.1UPSについて説明する。交流−交流変換回路の交流入力(Ui、Vi、Wi)は入力フィルタFiとリアクトルLiを介して3レベル回路構成のコンバータ回路CVに接続される。コンバータ回路CVの直流出力にはコンデンサC1とC2の直列回路と、コンデンサ電圧をバランスさせるためのバランサー回路BLと、双方向性の3レベルチョッパCHの出力と、直流を交流に変換する3レベル回路構成のインバータ回路INが、各々接続される。双方向性の3レベルチョッパCHの入力には交流電源が停電した時に無停電化を図るための蓄電池BTが、インバータ回路INの交流出力には波形改善用の出力フィルタFoが、各々接続され、出力フィルタFoの出力が交流電源システムの交流出力(Uo、Vo、Wo)となる。
FIG. 1 shows a first AC power supply system diagram targeted by the present invention, and FIG. 2 shows a second AC power supply system diagram.
Fig. 1 is an AC power supply system diagram in which No.1 UPS (uninterruptible power supply) and No.2 UPS are connected in parallel, and a storage battery is connected to each DC circuit of the AC-AC converter circuit via a bidirectional three-level chopper. It is the structure which aimed at uninterruptible power supply. Since both have the same circuit configuration, No. 1 UPS will be described. An AC input (Ui, Vi, Wi) of the AC-AC conversion circuit is connected to a converter circuit CV having a three-level circuit configuration via an input filter Fi and a reactor Li. The DC output of the converter circuit CV includes a series circuit of capacitors C1 and C2, a balancer circuit BL for balancing the capacitor voltage, an output of a bidirectional three-level chopper CH, and a three-level circuit for converting DC to AC. The inverter circuits IN having the configuration are connected to each other. A storage battery BT is connected to the input of the bi-directional three-level chopper CH when the AC power supply fails, and an output filter Fo for waveform improvement is connected to the AC output of the inverter circuit IN. The output of the output filter Fo becomes the AC output (Uo, Vo, Wo) of the AC power supply system.

図2は、図1で説明した交流−交流変換回路(図2のNo.1電源、No.2電源)の各々の直流回路を並列接続した構成で、この直流回路に双方向性の3レベルチョッパを介して蓄電池を接続して無停電化を図った構成である。図1、図2に示すいずれのシステムにおいても、コンデンサ電圧をバランスさせる本発明の原理は同じである。   FIG. 2 shows a configuration in which the DC circuits of the AC-AC conversion circuits (No. 1 power source and No. 2 power source in FIG. 2) described in FIG. 1 are connected in parallel. It is the structure which aimed at uninterruptible power by connecting a storage battery via a chopper. In both systems shown in FIGS. 1 and 2, the principle of the present invention for balancing capacitor voltages is the same.

図3にバランサー回路BLの詳細を示す。バランサー回路BLは、直流回路の正極Pと負極Nとの間にそれぞれダイオードを逆並列接続したIGBTS5とS6とを直列接続したIGBT直列回路が接続され、IGBT直列回路の直列接続点と直流回路の零極Mとの間にリアクトルL1と電流検出器CTとの直列回路が接続された構成である。また、コンデンサC1には電圧検出器VD1が、コンデンサC2には電圧検出器VD2が、各々接続される。電流検出器CTでの検出値iBAL、電圧検出器VD1での検出値EDC1、及び電圧検出器VD2での検出値EDC2は、それぞれ図4に示すバランサー回路BLの制御回路に入力される。   FIG. 3 shows details of the balancer circuit BL. In the balancer circuit BL, an IGBT series circuit in which IGBTs 5 and S6 in which diodes are connected in reverse parallel are connected in series between the positive electrode P and the negative electrode N of the DC circuit, and the series connection point of the IGBT series circuit and the DC circuit are connected. A series circuit of a reactor L1 and a current detector CT is connected between the zero pole M and the zero pole M. Further, the voltage detector VD1 is connected to the capacitor C1, and the voltage detector VD2 is connected to the capacitor C2. The detection value iBAL at the current detector CT, the detection value EDC1 at the voltage detector VD1, and the detection value EDC2 at the voltage detector VD2 are respectively input to the control circuit of the balancer circuit BL shown in FIG.

図4は、バランサー回路BLの制御回路ブロック図である。コンデンサC1の検出電圧EDC1とコンデンサC2の検出電圧EDC2との差を加算器AD1で求め、移動平均回路AVで平均化された後、電圧調節器AVRに入力され、電圧調節器AVRの出力はバランサー回路BLの出力電流指令値となる。この指令値とバランサー回路BLの出力電流検出値iBALは加算器AD2に入力され、その差が零になるように電流調節器ACRで制御され、変調率λをPWM(パルス幅変調)制御回路の入力量に変換するλ変換回路を通してPWM(パルス幅変調)制御回路へ送出される。PWM制御回路では、バランサー回路BLのIGBTS5とS6用のオンオフ信号を生成する。
電圧調節器AVRの出力であるバランサー回路BLの出力電流指令値はリミッタ回路LMで制限され、IGBT、リアクトルなどの部品に所定値以上の電流が流れないようにしている。ここで、バランサー回路BLへの電流指令値がリミッタ値に達したことを検知して、変換回路の制御回路に対してバランス制御開始指令を出力する。
FIG. 4 is a control circuit block diagram of the balancer circuit BL. The difference between the detection voltage EDC1 of the capacitor C1 and the detection voltage EDC2 of the capacitor C2 is obtained by the adder AD1, averaged by the moving average circuit AV, and then input to the voltage regulator AVR. The output of the voltage regulator AVR is the balancer. It becomes the output current command value of the circuit BL. This command value and the output current detection value iBAL of the balancer circuit BL are input to the adder AD2, and controlled by the current adjuster ACR so that the difference between them becomes zero, and the modulation factor λ is controlled by the PWM (pulse width modulation) control circuit. It is sent to a PWM (pulse width modulation) control circuit through a λ conversion circuit that converts it into an input quantity. The PWM control circuit generates on / off signals for the IGBTs 5 and S6 of the balancer circuit BL.
The output current command value of the balancer circuit BL, which is the output of the voltage regulator AVR, is limited by the limiter circuit LM so that a current exceeding a predetermined value does not flow through components such as the IGBT and the reactor. Here, it is detected that the current command value to the balancer circuit BL has reached the limiter value, and a balance control start command is output to the control circuit of the conversion circuit.

本発明の変換回路でのバランス制御回路例を図5に示す。インバータ回路INの電圧制御回路での実施例である。交流出力電圧指令(VR*、VS*、VT*)を、コンデンサC1とC2の電圧差が零になるように補正する制御方式である。コンデンサC1の電圧EDC1とコンデンサC2の電圧EDC2とを加算器11に入力し、この差a1を求め、a1を零にするための調節器12を通して、補正量a2を求める。調節器12の出力には切替えスイッチSWが接続されており、バランサー制御回路からのバランス制御開始指令が入力されると、この補正量S2と正弦波テーブルから得られる正弦波信号とを掛算器(14R、14S、14T)で掛算し、補正正弦波を求め、この補正正弦波と電圧指令(VR*、VS*、VT*)とを加算器(21R,21S,21T)で加算して、新たな電圧指令信号(VR**、VS**、VT**)とする。   FIG. 5 shows an example of a balance control circuit in the conversion circuit of the present invention. This is an embodiment in the voltage control circuit of the inverter circuit IN. In this control method, the AC output voltage command (VR *, VS *, VT *) is corrected so that the voltage difference between the capacitors C1 and C2 becomes zero. The voltage EDC1 of the capacitor C1 and the voltage EDC2 of the capacitor C2 are input to the adder 11, the difference a1 is obtained, and the correction amount a2 is obtained through the regulator 12 for making a1 zero. A changeover switch SW is connected to the output of the regulator 12, and when a balance control start command is input from the balancer control circuit, the correction amount S2 and a sine wave signal obtained from the sine wave table are multiplied by a multiplier ( 14R, 14S, 14T) to obtain a corrected sine wave, and this corrected sine wave and the voltage command (VR *, VS *, VT *) are added by an adder (21R, 21S, 21T) Voltage command signals (VR **, VS **, VT **).

バランサー制御回路からのバランス制御開始指令が入力されない場合は切替えスイッチSWは0V側にあり、掛算器(14R、14S、14T)の一方の入力を0にして、電圧指令(VR*、VS*、VT*)に対する補正量を零にする。従って、バランサー制御回路からのバランス制御開始指令が入力された時だけ、バランス制御する。   When the balance control start command from the balancer control circuit is not input, the changeover switch SW is on the 0V side, one input of the multiplier (14R, 14S, 14T) is set to 0, and the voltage command (VR *, VS *, The correction amount for (VT *) is set to zero. Accordingly, balance control is performed only when a balance control start command is input from the balancer control circuit.

尚、本実施例では、インバータ制御回路でバランス制御する例を示したが、コンバータ制御回路でも同様に制御可能である。コンバータ回路では電圧指令又は交流入力電流の指令値の何れかに補正を加えることにより実現できる。   In this embodiment, the balance control is performed by the inverter control circuit. However, the converter control circuit can perform the same control. The converter circuit can be realized by correcting either the voltage command or the command value of the AC input current.

本発明は、3レベルの電力変換装置を並列接続して使用する電源システムにおけるコンデンサ電圧のバランス制御に関する発明であり、無停電電源装置(UPS)、系統連系装置などへの適用が可能である。   The present invention relates to a capacitor voltage balance control in a power supply system using three-level power converters connected in parallel, and can be applied to an uninterruptible power supply (UPS), a grid interconnection device, and the like. .

S1〜S6、DB1、DB2・・・IGBT C1、C2・・・コンデンサ
L1、Li・・・リアクトル CT・・・電流検出器
VD1,VD2・・・電圧検出器 Fi、Fo・・・フィルタ
BL・・・バランサー回路 IN・・・インバータ回路
CV・・・コンバータ回路 CH・・・チョッパ BT・・・蓄電池
10・・・バランス制御回路 ACR・・・電流調節器
11、21R,21S,21T、AD1、AD2・・・加算器
12、AVR・・・電圧調節器 13・・・Sinテーブル
14R、14S、14T・・・掛算器 LM・・・リミッタ回路
SW・・・切替えスイッチ
S1 to S6, DB1, DB2 ... IGBT C1, C2 ... Capacitor L1, Li ... Reactor CT ... Current detector VD1, VD2 ... Voltage detector Fi, Fo ... Filter BL .. Balancer circuit IN ... Inverter circuit CV ... Converter circuit CH ... Chopper BT ... Storage battery 10 ... Balance control circuit ACR ... Current regulator 11, 21R, 21S, 21T, AD1, AD2 ... adder 12, AVR ... voltage regulator 13 ... Sin table 14R, 14S, 14T ... multiplier LM ... limiter circuit SW ... changeover switch

Claims (4)

交流入力電圧を正極、零極及び負極の3つのレベルを持った直流電源に変換する交流−直流変換回路と、前記直流電源の正極と零極との間に接続される第1のコンデンサと、前記直流電源の零極と負極との間に接続される第2のコンデンサと、前記第1及び第2のコンデンサそれぞれの電圧を均等化するバランサー回路と、前記直流電源から3つのレベルを持った交流電圧を作り出す直流−交流変換回路とで構成される交流−交流変換装置の交流入力同士と交流出力同士を複数台並列接続した交流電源システムにおいて、
前記バランサー回路の出力電流が所定値未満のときは、前記バランサー回路のみで制御して、前記バランサー回路の出力電流が所定値以上になったことを検出したときは、前記交流−直流変換回路の制御回路又は前記直流−交流変換回路の制御回路の何れかで前記第1及び第2のコンデンサそれぞれの電圧を均等化する直流電圧バランス制御を有効にすることを特徴とする交流電源システム。
An AC-DC conversion circuit for converting an AC input voltage into a DC power supply having three levels of a positive electrode, a zero electrode, and a negative electrode; a first capacitor connected between the positive electrode and the zero electrode of the DC power supply; A second capacitor connected between the zero pole and the negative electrode of the DC power supply, a balancer circuit for equalizing the voltages of the first and second capacitors, and three levels from the DC power supply. In an AC power supply system in which a plurality of AC inputs and AC outputs of an AC-AC converter configured with a DC-AC converter circuit that generates an AC voltage are connected in parallel,
When the output current of the balancer circuit is less than a predetermined value, it is controlled only by the balancer circuit, and when it is detected that the output current of the balancer circuit has exceeded a predetermined value, the AC-DC conversion circuit An AC power supply system, wherein a DC voltage balance control for equalizing the voltages of the first and second capacitors is made effective by either a control circuit or a control circuit of the DC-AC conversion circuit.
前記バランサー回路は、直流電源の正極と負極との間に接続されたそれぞれのダイオードを逆並列接続した半導体スイッチ直列回路と、前記半導体スイッチ直列回路の直列接続点と前記直流電源の零極との間に接続されたリアクトルと電流検出器との直列回路と、から構成されることを特徴とする請求項1に記載の交流電源システム。 The balancer circuit includes a semiconductor switch series circuit in which respective diodes connected between a positive electrode and a negative electrode of a DC power supply are connected in reverse parallel, a series connection point of the semiconductor switch series circuit, and a zero pole of the DC power supply. The AC power supply system according to claim 1, comprising a series circuit of a reactor and a current detector connected between each other . 前記並列接続された交流−交流変換装置それぞれの直流電源の正極、零極及び負極に双方向性の3レベル昇降圧チョッパ回路を介して蓄電池を接続することを特徴とする請求項1〜2のいずれか1項に記載の交流電源システム。 The storage battery is connected to a positive electrode, a zero electrode, and a negative electrode of each DC power source of each of the AC-AC converters connected in parallel via a bidirectional three-level buck-boost chopper circuit . The AC power supply system according to any one of the above. 前記複数台並列接続される交流−交流変換装置それぞれの直流電源の正極、零極及び負極同士をそれぞれ接続し、その接続線に双方向性の3レベル昇降圧チョッパ回路を介して蓄電池を接続することを特徴とする請求項1〜2のいずれか1項に記載の交流電源システム。 The positive, zero, and negative electrodes of each of the plurality of AC-AC converters connected in parallel are connected to each other, and a storage battery is connected to the connection line via a bidirectional three-level buck-boost chopper circuit. The AC power supply system according to claim 1 , wherein the AC power supply system is a power supply system.
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