JPH03118793A - Inverter controller - Google Patents

Abstract

PURPOSE:To enable an inverter circuit to be controlled with a PWM wave and simplify circuit composition by using a command signal generating means and a few digital ICs such as memories. CONSTITUTION:The ratio of pattern between the voltage output vectors V1-V6 and zero voltage vectors V0, V7, written previously in a memory by using frequency command signal and voltage command signal, is controlled, and at the same time, V/F-control for varying frequency and output voltage can be performed. Accordingly, by using the command signal generating means and a few digital ICs such as memories, an inverter circuit can be controlled with a PWM wave.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverter control device for variable speed control of an AC motor.

[Prior Art] Figure 13 shows the basic configuration of a transistor inverter that uses PWM control to control the variable speed of a three-phase induction motor M, in which AC power source AC is rectified by a rectifier BD and smoothed by a capacitor C. The obtained DC is sent to the inverter control device INV.
The PWM waveform output from the switch element Su of each phase consisting of a transistor is passed through the driver circuit DR.
1, S g 2, S v + +Sv2, SwI,
Drive Sw2 on and off to generate U and V.

A W-phase inverter output is obtained, and a three-phase induction motor M is controlled at variable speed by this inverter output.

By the way, inverter control device I that performs conventional PWM control
NV has a frequency equal to the inverter output frequency,
The switching elements StB, Sul, SV, SV of each phase are controlled depending on the magnitude of the sine wave control signal whose amplitude is proportional to the desired output voltage and the carrier wave consisting of a triangular wave with a constant peak value.
, sw, , using an analog circuit to obtain a PWM waveform for controlling sw, or writing the above-mentioned on/off drive pattern in advance into memory over the entire frequency control range. Some used digital circuits that read out this pattern according to the output frequency.

There is also a circuit that calculates the pulse width of a PWM waveform every fixed period of a carrier wave.

[Problems to be Solved by the Invention] However, the analog device has a complicated circuit configuration and requires a time constant capacitor, so even if it is made into a hybrid IC, there is a problem that the cost is high.

Further, in devices in which patterns are written in memory in advance, there is a problem in that when the resolution of the output voltage is increased, the capacity of the memory in which the patterns are written increases.

Furthermore, the method of calculating the pulse width required arithmetic processing.

The present invention has been made in view of the above-mentioned problems, and its purpose is to be able to be constructed using a general-purpose digital IC, and to require less memory capacity for storing data. Without special calculation processing,
An object of the present invention is to provide an inverter control device that can control the output frequency and output voltage of an inverter circuit.

[Means for Solving the Problems] The present invention provides an inverter circuit that connects a pair of series-connected switch elements corresponding to each phase to a DC power supply section and obtains an inverter output of each phase from a connection point of multiple pairs of switch elements. In an inverter control device that is used in the , the trajectory of the magnetic flux vector obtained by integrating the voltage vector was selected so as to draw the largest circle, and the pattern data corresponding to the selected voltage output vector was written, and the pattern data corresponding to the zero voltage vector was written. comprising a memory and a bit counter that counts clocks input during an on period of a frequency command signal with a variable duty ratio, with bits of the voltage command signal formed by the signal having a variable duty ratio as upper bits; Set the address for reading pattern data from the memory to either a voltage output vector pattern data write address or a zero voltage vector pattern data write address using address data whose lower bits are the output bits of the bit counter, The switch elements are controlled based on pattern data sequentially read from the set addresses.

In addition, when switching from a voltage output vector pattern to a voltage output vector pattern or when switching between a voltage output vector pattern and a zero voltage vector pattern, the switching elements of each phase pair whose switching operation is reversed are connected together. The dead pattern data that sets the dead time for turning off may be written in the above memory, and the dead pattern data may be read out from the above memory for a certain period of time when each pattern is switched. The voltage command signal may be created using the signal, and the time point at which the voltage command signal ends on is delayed from the time at which the frequency command signal ends on.

[According to the Invar 714111M device of the present invention,
V that uses a frequency command signal and a voltage command signal to vary the frequency and output voltage while controlling the ratio of the voltage output vector pattern and the zero voltage vector pattern of the voltage vector written in advance in the memory. /F control can be performed, and a means for generating a command signal,
By using a small amount of digital IC such as memory, P
It is possible to realize an inverter control device that is inexpensive and has a simple circuit configuration that can control an inverter circuit using WM waves.

In particular, by pre-writing a dead pattern in a memory and reading this dead pattern for a certain period of time when switching the pattern of voltage output vectors or from a pattern of voltage output vectors to a pattern of zero voltage vectors or vice versa, It is not necessary to provide a dead time circuit, and the circuit configuration can be further simplified.

[Example] First, Fig. 1 shows a three-phase inverter circuit showing the basic principle of the present invention. In this three-phase inverter circuit, switch elements SU, SV, and Sv of each phase of U, V, and W are connected. “
By selecting one of 1n O'', eight voltage vectors V0 to V7 can be selected as shown in FIG.

Therefore, the trajectory of the magnetic flux vector ψ ψ = 5vdt is calculated by integrating the voltage vector ■, as shown in Figure 3, by integrating the pattern of the six voltage output vectors ■1 to V6 excluding the zero voltage vectors Vo and Vy. The pattern data is selected so that it draws the largest circle and written in advance in the memory, and the written pattern data is sequentially read out and the switch element S is selected based on the pattern data.
By driving u, Sv, and Syu, a PWM-controlled inverter circuit can be realized.

Here, the output frequency of the inverter circuit is determined by the cycle of reading pattern data written in the memory. On the other hand, the output voltage of the inverter circuit is adjusted as follows.

In other words, the above zero voltage vector ■. , V7 is written in the memory in the same manner as the voltage output vectors V1 to V, and this zero voltage vector V,. ,
■ The pattern data of above voltage output vector ■1 to V
This can be done by changing the pattern data in the middle of reading from the memory and changing the output ratio of the voltage output vector and the zero voltage vector.

The inverter control device of the present invention is based on such a system, and the present invention will be explained below using examples.

FIG. 4 shows the configuration of an embodiment of the present invention, and the configuration of this embodiment is as shown in the figure.
V6 and zero voltage vectors V,,V.

pattern data and dead pattern data for dead time setting, which will be described later, are inverted so as to correspond to the positive and negative pairs of switch elements of each phase of the inverter circuit as shown in FIG. Both pattern data are written as 6-bit data at a predetermined address, and a pattern switching signal PC, which will be described later, is written as the 7th bit of the data. When reading, positive (non-inverted) and negative ( 8-bit configuration FR that outputs pattern data (inverted) and pattern switching signals as 7-bit parallel signals from data buses D0 to D6.
C20 for independently generating OMI, a frequency command signal FC for setting the frequency of the output of the inverter circuit, and a voltage command signal VC with variable duty ratios;
A signal generating section 2 consisting of a high frequency clock CL, etc.
A clock generating section 3 that generates K, an AND gate 4 that receives the frequency command signal FC and the high frequency clock CLK, a bit counter 5 that uses the output of the AND gate 4 as a clock, and a bit counter 5 that uses the high frequency clock CLK as a clock. A digital play 6 consisting of a shift register that receives the voltage command signal VC as an input signal, and the high frequency clock CL.
It is composed of a digital play 7 consisting of a shift register which uses K as a clock and receives a pattern switching signal PC output from the data bus D6 of FROMI as an input signal, and the read address data of PROMI is A0 to A.
It consists of data input to X * 2 address buses, of which the lower address buses A0 to A Play 7-
The voltage command signal VC is input to the address bus of A□I, which is one bit higher, and the output of the digital play 6 is input to the address bus of Ax, which is one bit higher.

Here, the voltage output vector pattern is U, V.

It consists of a positive (non-inverted) pattern of 3 bits and a negative (inverted) pattern of 3 bits corresponding to a pair of switch elements in each phase of W. For example, a pattern of voltage output vector Vl is "100001". , each. The data of each bit of ~D is the control signal of the switch element u, +v, respectively.
, +w, -u, -v.

-W, for example, if it is “1”, it will turn on signal, “0”
”, it constitutes an off signal.Of course, this on/off signal may be constituted by negative logic.

The pattern data of this voltage output vector is read from FROMI in the selection order shown in FIG. 3, and the write address is set as follows.

In other words, the upper bits of the address bus Ax+1. Ax*2
The address determined by the address buses A0 to A x -1 to which the output bits of the bit counter 5 are input using the upper address set with +Ax of 110'' as an offset value, and the address bus Ax+++Ax, 2.Ax of the upper bits.
Using the upper address set at 111" as an offset value, the addresses determined by the address buses A0 to Ax-□ for the output bits of the bit counter 5 are set according to the selection order of the voltage output vector pattern explained in FIG. Among the write addresses of the voltage output vector pattern written in the selected order, the lower addresses set on address buses A0 to AX-1 are set as consecutive addresses, and when the address bus Ax is set to "1" or 0°
By switching to `` and changing the offset value of the address, pattern data of voltage output vectors can be read out continuously in the selected order. A vacant address between addresses where pattern data of adjacent voltage output vectors are written at addresses with the same offset value is a pair whose switching operation is reversed among the switching elements of each phase pair when switching the pattern of the power output vector. Dead pattern data is written to set a dead time in which both switch elements are turned off.

Here, the dead pattern written in PROM1 is, for example, the pattern of the voltage output vector currently being read.
At 110001°, if the pattern of the voltage output vector that is next switched and read out is “010101”, the U-phase switch element is inverted, so the voltage output vector pattern is “010101”.
001".

Also, the pattern data “00” corresponding to the zero voltage vector
The write address of 0111'' or 111000'' is set at the offset value where address bus Ax+z, AX, I is 00''. This pattern data is written in such a manner that it corresponds to the previous state of the switch element so that only one switching operation is required.

Furthermore, the storage address of the data of the dead pattern for the dead time set when switching from the voltage output vector to the zero voltage vector or from the zero voltage vector to the voltage output vector is the address bus AX6.
21 A X + + is set to "10" or "01".

Then, the offset values determined by the upper address buses A + c + 2 and A x + + are the same so that the dead pattern when switching from the voltage output vector pattern to the zero voltage vector pattern corresponds to the voltage output vector pattern. The lower address is written to the address with the same value as the lower address of the voltage ratio cover turn.

Next, changes in the output of pattern data will be explained based on FIG.

First, in the figure, → represents the pattern of the voltage output vector, ′
indicates a zero voltage vector pattern, ○ indicates a dead pattern for dead time, and the pattern data above the square is U, V.

The data on the positive side of the pair of switch elements of each phase of W is shown, and the pattern data on the negative side shows the data on the other side.

Now, when the voltage command signal VC is “1”, the address bus Ax
+2. Ax++ is '11' and address bus Ax is '0', and the count value of bit counter 5 is X as shown in FIG. 6(a).

X+1. While increasing to X+2, the pattern data of the voltage output vector (A) is read from the FROMI address set by them, and the count value increases to x+3.
Then, the data of the dead pattern (I°) written in the address set by this count value will be read out.

"1" is written as a pattern switching signal PC in the data of the 7th bit D6 read together with this dead pattern (I°), and when the data of the dead pattern corresponding to the count value x+3 is read out, the data of the 7th bit D6 is read. changes to "1" as shown in FIG. 6(c). This 7th bit D6 is input to the digital delay 7, and after a certain period of time, the output to the address bus A8 changes from "0°" to "1" as shown in FIG. 6(d). and the resulting address bus A x + 2 , A x
+ 1, A x changes to '111', and the voltage output vector pattern (
The data in (b) will be read out as shown in FIG. 6(b).

The 7th bit D read out along with this pattern data
6 is written with “1”, and subsequently the address buses A x 42 and A x + + + A x are “1”.
11'', and the voltage output vector pattern (b) is determined from the address set by the count value of bit counter 5.
will be read out.

Next, when switching from the voltage output vector pattern (b) to the voltage output vector pattern (c), when the count value of the bit counter 5 increases to X+9 and shifts to the dead pattern (c'), the dead pattern Since "0" is written in the 7th bit D6 that is read together with the pattern (mouth') data, when data is read from the address set by the count value X+9, the pattern switching signal PC becomes "0". Then, after the delay time due to the digital delay 7 has elapsed, the address bus Ax changes from 1" to 0.0", and the voltage output vector pattern (c) is switched. In this way, the voltage output vector pattern is switched to the voltage output vector pattern, and at the time of switching, a dead time is set due to the delay time of the digital delay 7.

Next, the case of switching between the voltage output vector pattern and the zero voltage vector pattern will be described.

First, in FIG. 5 mentioned above, when reading the data of the voltage output vector pattern (c), the frequency signal FC
When the voltage command signal VC is turned off together with the voltage command signal VC, the count value of the bit counter 5 stops at, for example, X+14 as shown in FIG. changes from "1" to "0", but since the address bus A X l-2 is delayed by the digital delay 6, it does not change to "0" immediately. In other words, address bus A x + 2 r A x * +
is "01°", so the address where the dead pattern (c') used when switching to the zero voltage vector is written is accessed and read out as shown in FIG. 7(b). Since the address bus AX is "O°', the address is a dead pattern (H'
) address is the address bus A x + 21 A x
+ + + A It is set with “010゛′” of A x and the stopped counter value.

The 7th bit read from this address is 0°
Since "" has been written, there is no change in the output of the digital delay 7, and the dead pattern corresponds to the pattern (c) of the voltage output vector that was previously read.

Next, after the delay time due to digital delay 6, Fig. 7 (f
), when the address bus A x + 2 changes from “1” to “0”, the address bus A x or 2 + A
+I +A, changes to 000'', and zero voltage pattern (high degree) data is read out from the address determined by the count value during stop as shown in Fig. 7(d).This zero voltage The data of the pattern (B°) is data obtained by rewriting two bits corresponding to one set of phases in the data of the previous dead pattern (C').

Next, when the frequency command signal FC is turned on and the voltage command signal VC is turned on, the bit counter 5 restarts counting. On the other hand, when address bus A, etc. change to "1", address bus A, X&2. AX*, Ax changes to "010", and from the address set with the counter value of bit counter 5, a dead pattern (bar
The data in ``)'' will be read out as shown in FIG. 7(c). Here, the counter value of bit counter 5 is
If the previously read voltage output vector pattern data does not exceed the stored address, the dead pattern (by°) is a pattern corresponding to the previous voltage output vector pattern.

Now, when the delay time of the digital delay 6 has elapsed and the address bus A x +2 also becomes 01, the process shifts to reading out the pattern data of the voltage output vector.

In this way, a dead time determined by the delay time of the digital delay 6 is also set when switching from a voltage output vector pattern to a zero voltage vector or vice versa.

Figure 8 shows the relationship between the pattern output of the U phase and the voltage command signal VC at the switching part of the pattern of the voltage output vector expressed in negative logic, and Figure 9 shows the switching with the zero voltage vector similarly expressed in negative logic. The relationship between the U-phase pattern output and the voltage command signal VC is shown. In each figure, (a) is the voltage command signal VC1 (b), and (c) is the U-phase positive side and negative side control signal ( pattern output).

In this way, in the example device, an inexpensive shift register is used for digital delays 6 and 7, and the pattern data in PROMI is devised to provide digital delays 6 and 7 on the address input side of PROM1. By providing this, the dead time circuit at the output stage can be omitted.

By the way, if the on-period of the voltage command signal VC is set to be longer than the frequency command signal FC shown in FIG. 10(a) by <(=1) as shown in FIG. 10(b), the operation of the bit counter 5 will be During this period, the voltage output vector pattern is always output, and immediately after the voltage output vector pattern switches, it switches to the zero voltage vector pattern, resulting in a short pulse-like output waveform. It can be prevented. FIG. 11 shows a concrete circuit for interlocking generation of such signals, in which two one-shot multivibrators 8a and 8b are used, and for example, the output of the 1.5 KHz original oscillator 9 is generated by the one-shot multivibrator. 8a, and its output becomes the frequency command signal FC, and is also input to the one-shot multivibrator 8b. Voltage command signal VC
is composed of the logical sum of the outputs of two one-shot multivibrators 8a and 8b, and in this circuit, the pulse width of the one-shot multivibrator 8b is kept constant, and the one-shot multivibrator 8b becomes the frequency command signal FC. If the output pulse width of the shot multivibrator 8a is made variable, the pulse width of the voltage command signal VC will also change according to the change in the pulse width of the frequency command signal FC, and command signals FC and VC with a nearly constant V/F can be obtained. be able to.

The frequency of the high frequency clock CLK (
For example, when V/F constant control is performed using a V/F value determined by 300 KHz), as shown in Fig. 12, V/F constant control is performed in section B, and at point 0, the duty of frequency command signal FC and voltage command signal VC is It becomes 100%, and both the output frequency and output voltage become maximum. If the output frequency is not to be increased any further, as in section D, input high frequency clock C.
All you have to do is raise the LK frequency. In addition, in the low frequency region such as section A, even if the voltage is adjusted, the output distortion is almost the same as under constant V/F control, so voltage boosting is possible, which is effective control for torque boosting when starting an AC motor, etc. I can do it. If it is desired to change the V/F value in section B, this can be easily achieved by changing the frequency of the high frequency clock CLK.

[Effects of the Invention] Since the present invention is configured as described above, the invention according to claim 1 can generate an inverter using PWM waves by using a command signal generating means and a small number of digital ICs such as a memory. It is possible to realize an inverter control device that is inexpensive and has a simple circuit configuration that can control the circuit, and uses a frequency command signal and a voltage command signal to create a voltage output vector pattern of a voltage vector written in advance in a memory. There is an effect that V/F control can be performed to vary the frequency and output voltage while controlling the ratio with the zero voltage vector pattern.

Further, the invention according to claim 2 provides that the switching operation is reversed when switching from a voltage output vector pattern to a voltage output vector pattern or when switching between a voltage output vector pattern and a zero voltage vector pattern. Dead pattern data that sets a dead time for turning off both pairs of switch elements is written in the memory, and when each pattern is switched, the dead pattern data is read from the memory for a certain period of time.
In addition to the effects of the invention as claimed in claim 1, there is an effect that it is not necessary to provide a separate dead time circuit, and the circuit configuration can be further simplified.

Furthermore, the invention according to claim 3 creates a voltage command signal using a signal of the same frequency that is synchronized with the frequency command signal, and delays the time when the voltage command signal ends turning on than the time when the frequency command signal ends turning on. In addition to the effect of the invention described in item 1, the voltage output vector pattern is always output during the operation period of the bit counter 5, and immediately after the voltage output vector pattern is switched, it is switched to the zero voltage vector pattern. This has the effect of preventing the output waveform from ending up in a short pulse shape.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an inverter circuit for explaining the principle of the present invention, Figures 2 and 3 are diagrams explaining the same principle as above, Figure 4 is a circuit configuration diagram of an embodiment of the present invention, and Figure 5 is the same as above. Fig. 6 is a time chart for explaining the operation when outputting the same voltage output vector pattern as above, and Fig. 7 is a time chart for explaining the operation when outputting the zero voltage vector pattern as above. , Fig. 8 is a waveform diagram of each part corresponding to Fig. 6, Fig. 9 is a waveform diagram of each part corresponding to Fig. 7, and Fig. 10 is a waveform diagram of each part corresponding to Fig. 7.
The figure is an explanatory diagram of the waveform of the command signal used in the example, Figure 11 is a specific circuit side diagram of the signal generating section used in the above, Figure 12 is a characteristic diagram of the constant V/F control in the same as the above, and Figure 13 is FIG. 2 is a configuration diagram of an inverter circuit. 1 is a PROM, 2 is a signal generator, 3 is a tarokk generator,
4 is an AND gate, 5 is a bit counter, and 6.7 is a digital delay.

Claims (3)

[Claims] (1) Used in an inverter circuit that connects a series-connected pair of switch elements corresponding to each phase to a DC power supply section and obtains the inverter output of each phase from the connection point of each pair of switch elements. In an inverter control device that controls switching, the voltage output vector excluding the zero voltage vector among the voltage vectors represented by the on/off combination patterns of the switching elements of each phase is integrated. The pattern data corresponding to the selected voltage output vector is written in such a way that the locus of the obtained magnetic flux vector draws a maximum circle, and the pattern data corresponding to the zero voltage vector is written in the memory, and the duty ratio is variable. It is equipped with a bit counter that counts the clock input during the ON period of the freely variable frequency command signal, and the bits of the voltage command signal formed by the signal whose duty ratio can be freely changed are used as the upper bits, and the lower bits are used as the bit counter of the above-mentioned bit counter. Using address data consisting of output bits, the address for reading pattern data from the memory is set to either the voltage output vector pattern data write address or the zero voltage vector pattern data write address, and the data is read sequentially from the set address. An inverter control device characterized in that the switch element is controlled based on read pattern data. (2) The switching elements of each phase pair whose switching operation is reversed when switching from a voltage output vector pattern to a voltage output vector pattern or when switching between a voltage output vector pattern and a zero voltage vector pattern. 2. Dead pattern data for setting a dead time for turning off both of the devices is written in the memory, and the dead pattern data is read from the memory for a certain period of time when each pattern is switched.
The inverter control device described. (3) The voltage command signal is created using a signal of the same frequency that is synchronized with the frequency command signal, and the time when the voltage command signal ends being turned on is delayed from the time when the frequency command signal ends being turned on. The inverter control device described.