JPS61240859A - Pwm control system of single-phase bridge inverter - Google Patents

Abstract

PURPOSE:To improve the safety and the reliability by selecting plural types of PWM signals of the prescribed period stored in a memory, producing them in time series signals, thereby avoiding the unbalance of a duty at the elements of an inverter. CONSTITUTION:The output of a clock oscillator 2 is used as a clock signal of an incremental/decremental counter 4 for addressing to read data of a ROM 5, and applied to a frequency divider 3 to from an up/down command of the counter 4 and a signal for switching to pause the ON/OFF. The ROM 5 stores plural types of PWM signals of 1/4 of the output period of an inverter. The prescribed PWM signal of 1/2 of the period of the inverter output is produced from the ROM 5 through a multiplexer 6, AND gates 7A, 7B as time series signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for controlling a single-phase bridge inverter made of semiconductor switching elements such as transistors, particularly by a pulse width modulation (PWM) method.

[Conventional technology]

FIG. 4 is a configuration diagram showing an example of a general single-phase bridge inverter main circuit. That is, this type of inverter is constructed by combining, for example, a unit inverter made up of transistors U and X and a unit inverter made up of transistors V and Y in a bridge. In addition, DU e DX p
DV and DY are feedback diodes, dc is the direct current input voltage, and v is the inverter output voltage.

By the way, as a method of controlling such an inverter using the PWM method, a method is known in which a driving pulse is generated by comparing a sine wave and a triangular wave or a square wave and a triangular wave, and each switching element constituting the inverter is controlled by this driving pulse. ing.

Note that the former method is exclusively adopted in order to reduce the low-order harmonic components of the inverter output. Figure 5 shows a conventional example of an inverter control device using a drive signal based on a comparison of a sine wave and a triangular wave. The block diagram shown in FIG. 6 is a timing waveform diagram for explaining the operation. In FIG. 5, 11 is a triangular wave generator, 12 is a sine wave generator, 13 is a voltage command unit, 14 is a multiplier, 15 is a phase inverter, and 16A is a
*16B is a comparator, and 17A and 17B are NOT elements.

The amplitude of the sine wave signal from the sine wave signal generator 12 is adjusted by the multiplier 14 in accordance with the command from the voltage command unit 13 . The output from this multiplier 14, that is, the control signal, is compared with the carrier wave signal from the triangular wave generator 11 by a comparator 16A, and the signal obtained by inverting the control signal by a phase inverter 15 is compared with the carrier wave signal by a comparator 16B. As a result, driving pulses to be applied to the transistor switching elements U and V as shown in FIG. 4 are formed. In the inverter shown in Figure 4, transistors U and X, V and Y
Since it is sufficient to create drive pulses so that the on and off states are reversed, the signals obtained from the comparators 16A and 16B are used as the NOT' element 17A.

178 to create reverse on/off signals. The drive pulses thus created are applied to each of the four transistors shown in FIG.

By supplying it between the emitters, inverter operation becomes possible.

Therefore, when the control signal S and carrier wave signal T as shown in FIG. 6(a) are given, the result as shown in FIG. 6(b).

Driving signals such as (c), (=) and (e) are obtained,
The inverter output voltage vI is as shown in FIG. Note that the drive signal is indicated by the voltage between the collector and emitter of the transistor, and therefore, the signal level is high during the period when the transistor is off, and low during the period when the transistor is on. From the above, it can be seen that in the ta5 diagram, if the voltage command is increased and the amplitude of the control signal is increased, the pulse width of the output voltage becomes larger and the fundamental wave amplitude also becomes larger.

[Problem that the invention seeks to solve]

However, the above-mentioned analog methods not only complicate the circuit configuration, but also have problems with accuracy.Recently, the above-mentioned driving signal patterns are predetermined by calculation, and the results are calculated in advance. read-only memory (
A method is used in which the drive signal is obtained by storing the signal in a memory such as a ROM (ROM) and reading it out in chronological order. In this case, Figure 6 (b), (c), (d) and (
Each pattern of drive signals such as (e) is stored in a predetermined memory such as 80M, and its contents are sequentially read out by a counter or the like and distributed to each switching element.

However, each pattern of this drive signal is one of the output fundamental waves.
If you look at 80 degrees as a unit, as shown in Figure 7 (A, A, B,
It can be classified into four patterns: B. Furthermore, Figure 7 shows Figures 6 (b) and (c).

Only the drive signals of (d) and (f) are extracted. However, in Figure 7, the voltage between the base and emitter of a transistor, which is a switching element, is shown, so
The on/off relationship is reversed from that of each waveform in FIG. 6. Here, since patterns A and A and B and B are just reversed on and off, pattern A can be changed by reversing A, and pattern B can be changed by reversing pattern B. However, since it is necessary to store the time series patterns A and B for 360 degrees in the OM, there is a problem that the memory capacity becomes large and the cost increases.

Therefore, in order to reduce the length of the pulse train stored in the ROM, consider a pulse pattern C corresponding to a half cycle of the inverter output voltage vI shown in FIG. For example, two elements such as elements U and
A driving method may also be considered in which the arm is driven and no pulse pattern is applied to the elements v and Y of the remaining two arms.

However, with this method, the switching loss of each element and the responsibility of the pace drive circuit become severe for a specific arm, such as the U and X arms, and problems arise, such as the cooling body and base drive circuit becoming larger in particular. 0 [Means for solving the problem] Pulse width modulation (P
WM) A memory for storing multiple types of signals, and a predetermined P for 1/2 period of the inverter output period from this memory.
A signal extraction means for selecting the WM signal and extracting it as a time series signal is provided.

[Effect]

FIG. 13 is a reference diagram for explaining the invention in detail. In the figure, (a) shows the relationship between the control signal S and the carrier wave signal T, and (b) to (e) show the drive signals (pace, emitter voltage) of each switching element U, X, V, Y. ), and (to) indicates the inverter output voltage vX. 0 In other words, a unit inverter consisting of a U arm and an While driving alternately by applying a predetermined PWM signal every two cycles,
In the section where the PWM signal of each unit inverter is not given, the zero weight is driven so that it remains on or off, and as shown in Fig. If the drive pulse shown in the same figure (b) is applied to the arm, then the drive pulse shown in the same figure (c) is applied to the X arm.
A drive pulse with an on/off relationship opposite to the drive pulse of m<U arm is given, while the ■ arm is shown in the same figure (d).
The Y arm is driven so that it remains off during this period, as shown in FIG. In period ■, this relationship is reversed, and the drive pulse is applied only to the v and Y arms, and not to the U and X arms.
Since the WM pattern is symmetrical at 90 degrees or 270 degrees as shown in FIG.

〔Example〕

#! Figure 1 is a block diagram showing an embodiment of the present invention, and Figure 2 is a timing waveform diagram for explaining the operation of Figure 1. In Figure 1, 1 is a voltage command, 2 is a clock oscillator, and 3 is a frequency divider, 4 is an up/down counter, and 5 is R
OM and 6 are multiplexers, 7A and 7B are AND gates, and s e 9A e 9B is a NOT element.

The operation of the clock oscillator 2 will be explained below with reference to these figures.
It is used as the clock signal (cp) of on.

A signal (fundamental wave signal) for stopping switching off is formed. Since the frequency of this fundamental wave signal is f and the frequency of the up/down command is 2f, the counter 4 repeats up and down at a frequency <2f as shown in FIG. 2(b). As a result, the ROM 5 outputs as many high and low signals as the number of addresses specified by the up/down counter 4.
Since low information can be obtained, a time-series pulse train can be obtained by continuously changing the address from the maximum value to the maximum value. Since the pulse train required here is symmetrical at 90 degrees or 270 degrees, if the counter 4 is made to repeat up and down every 90 degrees, the output voltage will be stored in the ROM 5. A pulse train corresponding to 00 degrees to 90 degrees, for example, the 8th
The first half of the pulse train of pattern C shown in the figure is stored. Therefore, the up-count number corresponding to 90 degrees of the fundamental wave created as described above corresponds to the temporal resolution of the pulse train. Generally, a predetermined number of bits of parallel data can be extracted from the OM5, but in this case, only one type of pulse train needs to be obtained in parallel, so each data output corresponds to a different voltage command. The pulse train to be output is stored in memory, and the multiplexer 6 selects the bit position for outputting an appropriate pulse train in accordance with the command from the voltage command unit 1. Additionally, since the steps (increments) of the output voltage are generally too coarse based on the number of output bits alone, different pulse patterns can also be obtained by using pits that are not connected to the output of the counter 4 among the number of address input bits in the ROM 5. I'll keep it. The thus obtained output of the multiplexer 6 as shown in FIG. 2(d) is input to the AND element 7A together with the previous fundamental wave signal to generate, for example, a drive signal for the U arm. Note that if this signal is inverted by nine NOT elements, a drive signal for the X arm can be obtained. Similarly, NO
The fundamental wave signal inverted by the T element 8 and the output of the multiplexer 6 are combined to create drive signals for the V and Y arms. FIG. 2(e)K shows an example of the arm drive signal.

〔Effect of the invention〕

According to this invention, only 90 degrees of PWM signals need to be stored in the ROM, which provides the advantage of reducing the ROM capacity or increasing the resolution of the pulse train. .

In addition, two unit inverters are connected to 1/2 of the inverter output.
Since the elements are driven alternately every cycle, an imbalance in the responsibilities of each element can be avoided, resulting in an effect of improving safety or reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of this invention, #! Figure 2 is a timing waveform diagram for explaining the operation of Figure 1, Figure 3 is a reference diagram for explaining the invention in detail, and Figure 4 is a configuration showing an example of a general single-phase inverter main circuit. -1
Fig. 5 is a block diagram showing a conventional example of a single-phase inverter control circuit, Fig. 6 is a timing waveform diagram to explain the operation of Fig. #15, and Fig. 7 explains the classification method of drive signals in Fig. 6. FIG. 8 is a reference diagram for explaining a method of sharing drive signals. Symbol explanation 1.13... Voltage command unit, 2... Clock oscillator, 3... Frequency divider, 4... Up/down counter, 5... ...Read only memory (ROM), 6...Multiplexer, 7A,
7B...and gate, 8°9A, 9B, 17
A, 17B...NOT element, 11.
... Triangle wave generator, 12 ... Sine wave generator, 14 ... Multiplier, 15 ... Phase inverter, 16A, 16B ... ·comparator. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Gaa Figure 4 1IIE5 ■ Figure 6 Figure 7 Figure 3 (2) Y

Claims (1)

[Claims] In a single-phase bridge inverter that has a bridge configuration of two unit inverters in which two switching elements are driven with opposite on/off relationships, pulse width modulation (PWM) for 1/4 period of the inverter output period is performed.
A memory for storing a plurality of types of signals and a signal extraction means for extracting a predetermined PWM signal corresponding to 1/2 period of the inverter output period from the memory as a time series signal are provided, and the two unit inverters While driving alternately based on the PWM signal from the signal extraction means every two cycles, one switching element is turned on during a period when the PWM signal of each unit inverter is not applied.
A PWM control method for a single-phase bridge inverter, characterized in that the other is driven so that it remains off.