JPH02216582A - Pipeline arithmetic circuit - Google Patents

Abstract

PURPOSE:To improve the arithmetic processing capacity by preventing a pipeline from being disconnected by an input scaling processing. CONSTITUTION:Variable shifting circuits 10, 20 input samples Xi, Yi from input terminals 1, 2, and perform an operation for shifting input signals 100, 101 to the right by one bit. An arithmetic operation circuit 30 calculates multiplication (1/4)/(Xi*Yi) of two inputs and repeats to transfer it to an accumulating circuit 40. The accumulating circuit 40 repeats addition of a result 104 of multiplication which is transferred and a result of accumulation to the previous step. When the operation to X3 and Y3 is repeated, in the accumulating circuit 40, A = (1/4)(X0*Y0) + (X1*Y1) + (X2*Y2) + (X3*Y3) being the inner product is obtained without generating an overflow.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pipeline arithmetic circuit, and particularly to a pipeline arithmetic circuit for a digital signal processing processor.

[Conventional technology]

To perform a series of arithmetic operations at high speed, such as when performing real-time processing on audio and image signals, dedicated arithmetic units such as multipliers and adders are used, and these arithmetic units are parallelized. Alternatively, they are often connected in series to parallelize arithmetic processing and achieve high processing speed.

In particular, a configuration method in which arithmetic units are connected in series according to the order of arithmetic processing to achieve so-called pipeline processing is often used because it can relatively easily increase the parallelism of arithmetic processing and improve throughput. It is being As an example, Fig. 4 shows the signal processing processor μP of NEC Corporation.
The pipeline arithmetic circuit used in the D7720 is shown. For detailed explanation, refer to μPD7720 issued in January 1986.
15 Fuzz, Signal Processing, Please refer to the User's Manual. In FIG. 4, 21 is a multiplier, 22 is an arithmetic and logic operation circuit, 23 is a register, and 24.2
5 is a space, a muleta, 26.27 is an input terminal, and 28 is a bus.

Using this pipeline arithmetic circuit, two vectors X = (Xo, Xt -----
, Xm-t) and Y= (Yo , Yt , --1,
Let us consider the flow of processing when calculating the inner product A of Y rrl-ri.

Elements Xo of both vectors input to input terminals 26 and 27,
The multiplier 21 multiplies Yo and stores the multiplication result in the register 23. In the next step, this multiplication result is loaded into the accumulator 25 via the P input of the arithmetic logic circuit 22. At this time, Xl input to input terminals 26 and 27
, Yl can be multiplied by the multiplier 21, and the register 23 stores the multiplication result of Xl and Yl. In the next step, the arithmetic and logic operation circuit 22 adds XI)*Yo (input from the Q input) previously loaded into the accumulator 25 and the value X1*Y1 of the register 23, and the accumulator 25 Store the addition result in . Below, similar calculations are repeated for i=2 to m-1,
The inner product value A of the vectors X and Y is found in the accumulator 25.

Also, when performing filter processing as shown in equation (2) using the same pipeline arithmetic circuit, the above-mentioned inner product A
If we replace vector Y with filter coefficient C when calculating , filter processing result B can be found in accumulator 25 in the same way.

As described above, in the product-sum operation in which multiplication and addition are repeatedly performed, multiplication and addition can be performed simultaneously by the multiplier 21 and the arithmetic logic operation circuit 22.

Therefore, it is effective for arithmetic processing centered on product-sum calculations, such as calculations for calculating inner products of vectors and convolution calculations.

[Problem to be solved by the invention]

In the inner product calculation process of equation (1) described above, it is necessary to consider the calculation word length of the pipeline calculation circuit. Equation (1) is m
Since it is an accumulation of times, the inner product result A is multiplied by a maximum of m, which may cause an overflow in the arithmetic circuit. To avoid this overflow, conventionally the multiplication result is (1/m)
The method used was to accumulate the values after the calculation. When this method is implemented using the conventional pipeline arithmetic circuit described above, (1
/m) is required, and the pipeline cannot be used effectively, resulting in a significant deterioration in processing efficiency.

In addition, - In image signal processing for boat fishing, etc., the amplitude of the input signal is O
It is often treated as a signal of 1.0. When the above-mentioned pipeline arithmetic circuit performs filter arithmetic processing on an image signal, the processing result may be negative or 1.0 or more. Therefore, after processing equation (2), the output is further set to 0.
It is necessary to perform calculation processing to limit the value from 1.0 to 1.0. As a method for implementing this process, first, the result of equation (2) is divided into cases as follows, and the result is limited for each case.

When the processing of equation (3) is implemented using the above-mentioned conventional pipeline arithmetic circuit, three conditional jumps and value assignment processing at each branch destination are required. Even when these processes are performed, the pipeline cannot be used effectively, resulting in a reduction in processing efficiency.

An object of the present invention is to provide an arithmetic circuit with high processing efficiency that does not cause such a decrease in processing efficiency and can directly perform calculations with 1 instruction per 1 sample input.

[Means to solve the problem]

The pipeline arithmetic circuit of the first invention includes a variable shift circuit that bit-shifts two inputs supplied from the outside by a preset amount independently, and a predetermined operation using the output of the variable shift circuit as input. The pipeline arithmetic circuit of the invention includes an arithmetic operation circuit to which two inputs are supplied from the outside, an accumulation circuit that receives the output of this arithmetic operation circuit as input, and an upper limit value that is determined in advance for the output of this accumulation circuit. and a comparison circuit that compares in parallel with the lower limit value, and a selection circuit that selects and outputs any one of the output of the accumulation circuit, the upper limit value, or the lower limit value based on the comparison result of the comparison circuit. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a book diagram showing the first embodiment of the present invention, 1 and 2 are input terminals, 10.20 is a variable shift circuit, and 3
0 is an arithmetic operation circuit including multiplication, 40 is an accumulation circuit, and 3 is an output terminal.

Hereinafter, a case will be described in which the vector inner product of equation (1) is calculated using the embodiment shown in FIG. 1, assuming that the dimension of the vector is m=4.

Xo is input from input terminal 1 to variable shift circuit 10, and Yo from input terminal 2 is input to variable shift circuit 2°. The variable shift circuit 10.20 receives input signals loo, xo[-
Performs an operation to shift right by t bits, and input signal 100,1
Multiply 01 by l/2.

In the next step, the output 1 of the variable shift circuits 10 and 2o
02 and 103 are output to the arithmetic operation circuit 30. The arithmetic operation circuit 30 multiplies the two inputs and obtains the multiplication result (1/4
) Calculate (Xo*yo). At the same time, the variable shift circuit 10.20 has an input terminal l.

2, input the next data Xl and Y1, and input the input signal Zoo
, 101 are shifted to the right by 1 bit. Furthermore, in the next step, the output 104 of the arithmetic operation circuit 3o is transferred to the accumulation circuit 40, and at the same time, the variable shift circuit 10.20 receives the next input X,, Y! In the l-bit shift operation, the arithmetic operation circuit 3o calculates (1/4) (X; *Y;).

Hereinafter, in the variable shift circuit 10.20, the input terminal 1.2
Input the input samples Xi and Yi from the input signal 1
Perform an operation to shift 00 and 101 to the right by 1 bit. The arithmetic operation circuit 30 multiplies two inputs (1/4) (
Xi*Yi) and transferring it to the accumulation circuit 40 is repeated. In the accumulation circuit 40, the transferred multiplication result 1
The addition of 04 and the cumulative result up to the previous step is repeated.

As described above, X3. When the calculations up to Y3 are repeated, the accumulation circuit 40 calculates the inner product of vectors X and Y, A=(1/4)((Xo*Y
o)+(Xt*Yt)+(Xt*Yz)+(Xs'kY
s)) is obtained.

FIG. 2 is a block diagram showing a second embodiment of the present invention, in which 4.5 is an input terminal, 6 is an output terminal, 50 is an arithmetic operation circuit including multiplication, 60 is an accumulation circuit, and 70 is a limit circuit. It is a circuit. Note that details of the Ribat circuit 70 will be described later.

Hereinafter, a case in which the above-mentioned equation (2) is calculated using the embodiment shown in FIG. 2 will be described.

An input sample Xo is inputted from the input terminal 4 and a filter coefficient co is inputted from the input terminal 5 at the same time, and the arithmetic operation circuit 50 calculates (X6 * Co ). In the next step, the output 202 of the arithmetic operation circuit 50 is transferred to the accumulation circuit 60. At the same time, the arithmetic operation circuit 5° receives the next data X! from the input terminal 1.2. , C, and calculate (Xs'kY1). Furthermore, in the next step, the output 202 of the arithmetic operation circuit 50 is transferred to the accumulation circuit 60, and is accumulated with the data (Xo*Co) transferred from the arithmetic operation circuit 50 in the previous step.

Thereafter, the arithmetic operation circuit 50 inputs the input sample X1 from the input terminal 4 and the filter coefficient C= from the input terminal 5,
Calculating the multiplication (Xi*Ci) of the two input signals 200 and 201 and transmitting it to the accumulation circuit 6o is repeated. The accumulation circuit 60 repeatedly adds the transferred multiplication result 202 and the accumulation result up to the previous step. If we repeat the calculations up to Xrn-1゜c m-, as above, we get
In the accumulation circuit 6o, the filter processing result B=(Xo*Co)
+(Xl*CI) + ---+ (Cm-1*C
m-1) is obtained.

Next, the limit processing of the above-mentioned equation (3) will be explained. The filter processing result B is transferred to the refit circuit 7°. Although the details will be described later, the limit circuit 70 outputs 0 for input data 203 smaller than 'A□', and
o" for input data 203 larger than V"1.
0" is output, and in other cases, the filter processing result B, which is the input data 203, is output as is. As a result,
A filter processing result in which the amplitude of the signal is limited from '0' to '1.0' is obtained as the output signal 204.

Details of the limit circuit 70 shown in FIG. 2 will be explained using FIG. 3. In Figure 3, 7 is an input terminal, 6 is an output terminal,
71, 72 are comparison circuits, 73 and 74 are registers, and 75 is a selection circuit.

The upper limit value V''1.O'' is stored in the register 73, and the lower limit value V''0'' is stored in the register 74.

The comparison circuit 71 receives data 20 input from the input terminal 7.
3 and the data 205 of the register 73, and the data 2
When 03 is larger than the data 205, the output signal 207 is set to 1", and when it is smaller, the circuit outputs 10".

On the other hand, the comparison circuit 72 compares the data 203 input from the input terminal 7 with the data 206 of the register 74, and if the data 203 is smaller than the data 206, the output signal 2
This is a circuit that converts 08 to 11" and outputs 0" if it is larger. Comparison circuits 71 and 72 perform comparison operations in parallel.

The selection circuit 75 selects one from three data: data 205 from the register 73, data 203 input from the input terminal 7, and data 206 from the register 74,
This circuit outputs the selected data 204 to the output terminal 6. The data to be selected is controlled by the output 20 of the comparator circuit 71.
7 and the output 208 of the comparison circuit 72 as follows. That is, the outputs of the comparison circuits 71 and 72 (207
If ゜208) is (+00), the output signal 205 of the register 73 is selected; if it is (0, 1), the output signal 206 of the register 74 is selected; otherwise, the input signal 203 from the input terminal 7 is selected. Select.

As a result, the selection circuit 75 outputs data limited from 0'' to 11.0'' to the output terminal 6.

〔Effect of the invention〕

As described above, according to the first invention, efficient arithmetic processing can be performed without interrupting the pipeline due to input scaling processing. The variable shift circuit can be realized with small hardware, and the shift amount can be set using software, so even if it is desired to change the number of product-sums, it can be handled flexibly using software.

Further, according to the second invention, efficient arithmetic processing can be performed without interrupting the pipeline by the amplitude +7 (cut processing) performed by the limit circuit having the comparison circuit and the selection circuit.This limit circuit is a simple circuit. The limit values can be configured using software, and if you want to change the limit value, you can do so flexibly using software.

FIG. 2 is a block diagram showing an example of a line calculation circuit.

1.2...Input terminal, 3...Output terminal, 10°2o...Variable shift circuit, 30...
... Arithmetic operation circuit, 4o ... Accumulation circuit, 5,
6...Input terminal, 7...Output terminal, 5
0... Arithmetic operation circuit, 60... Accumulation circuit, 70... Accumulation circuit, 71.72...
・Comparison mouth%, 73, 74...Register, 75・
...Selection circuit.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
FIG. 3 is a block diagram showing the second embodiment of the present invention, FIG. 3 is a block diagram showing details of the limit circuit 70 in FIG. 2, and FIG. 4 is a block diagram showing the limit circuit 70 in FIG.

Claims (2)

[Claims] (1) A variable shift circuit that bit-shifts two inputs supplied from the outside by a preset amount independently, an arithmetic operation circuit that performs a predetermined operation using the output of this variable shift circuit as input, and this arithmetic operation A pipeline arithmetic circuit comprising: an accumulation circuit that receives an output of the circuit as an input. (2) An arithmetic operation circuit to which two inputs are supplied from the outside, an accumulation circuit that receives the output of this arithmetic operation circuit as input, and the output of this accumulation circuit is connected in parallel with predetermined upper and lower limit values. A pipeline comprising: a comparison circuit for comparison; and a selection circuit for selectively outputting any one of the output of the accumulation circuit, the upper limit value, or the lower limit value based on the comparison result of the comparison circuit. Arithmetic circuit.