JP2005353094A - Product-sum computing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a product-sum computing unit for automatically generating an address of a register in which a plurality of calculation data are stored, outputting data in the midst of calculation processes and notifying an overflow, improving processing efficiency of the product-sum computing unit, and simplifying a recursive filter. <P>SOLUTION: The product-sum computing unit is provided with a coefficient register 100, a data register 110, a multiplier 130, an adder 140, and a data bus 120 for performing data transfer to/from an external device. The product-sum computing unit is further provided with a data collectively automatically storing means 180 for automatically generating a data storage address only by inputting an address showing the data register 110 only once at the beginning from an external without individually designating all the addresses of the data register 110 from the external, and storing a series of data. Also, recursive product-sum calculations are performed by automatically storing intermediate result data in the midst of the product-sum calculation processes in the data register 110. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a product-sum calculator, and more specifically, functions as an IIR (Infinite Impulse Response) filter (recursive filter) or FIR (Finite Impulse Response) filter (non-recursive filter), and has a transfer rate. The present invention relates to a fast and high-speed product-sum calculator.

  In recent years, in the fields of automobiles, mechatronics, etc., there has been an increasing demand for filtering data using a digital filter, and a DSP (Digital Signal Processor), which is a product-sum calculator and an LSI (Large Scale Integration Circuit) dedicated to digital signal processing. Etc. are utilized. In these fields, filter calculation with a small number of operation terms is the main, and IIR filters with high processing speed are often used.

FIG. 17 is an explanatory diagram of a conventional product-sum calculator using FIR.
This computing unit multiplies two registers that can be realized by a RAM (Random Accress Memory) or the like, that is, the coefficient register 800 and the data register 810, the output of the coefficient register 800, and the output of the data register 810 as two inputs. A multiplier 830 to be obtained; an adder 840 having the output of the multiplier 830 as one input; an intermediate data register 850 for storing intermediate data in the middle of a product-sum operation by the multiplier 830 and the adder 840; and a product-sum operation result The result register 860 to be stored and the address decoder 870 for designating the address of the data register 810 are constituted. Here, the output of the intermediate data register 850 becomes the other input of the adder 850, thereby enabling a product-sum operation.

  First, coefficient data and input data are previously transferred to the coefficient register 800 and the data register 810 via the data bus 820, respectively. For example, in the case of four-term product-sum operation, four input data and four coefficient data are input to the data register 810 and the coefficient register 800, respectively. Then, the FIR filter operation is executed by sequentially multiplying the data and coefficient one by one and adding them. At this time, the write address of the data register 810 is set by an external CPU (not shown) or the like. That is, an address from an external CPU (not shown) is input to the address decoder 870, and the address decoder 870 decodes this address to obtain the real address of the data register 810, and inputs that address via the data bus 820. The data is written, the written data is read and input to the multiplier 830, and the product-sum operation is started.

  In order to realize an IIR filter with this arithmetic unit, it is necessary to transfer the product-sum operation result stored in the result register 860 to the data register 810 via the data bus 820 and start the product-sum operation again. That is, address designation is performed by an external CPU (not shown), an actual address is obtained from the address data 870, the contents of the result register 860 are written to the address of the data register 810 via the data bus 820, and the data register 810 The read-and-write address is specified, the product-sum operation is restarted, and the next product-sum operation is started.

  However, in the conventional method, there is a problem that an external CPU or the like must execute all addressing and activation of product-sum operations, and software for that is required, and processing speed such as data transfer is slow. It was.

Further, since the CPU designates the write address of the data register, a storage area for storing the designation address is required for each data.
An object of the present invention is to provide a high-speed multiply-accumulate circuit that can perform FIR filter processing, is suitable for realizing an IIR filter, and has a high transfer speed.

  A block diagram of the present invention is shown in FIGS. The present invention relates to a coefficient register 100 that stores a plurality of terms of a product-sum operation coefficient, a data register 110 that stores a plurality of product-sum operation data, a data bus 120, a coefficient in the coefficient register 100, and a data in the data register 110. It is assumed that a multiplier 130 and an adder 140 for performing the product-sum operation, an intermediate data register 150 for storing intermediate data of the product-sum operation, a result register 160 for storing the product-sum operation result, and an address bus 170 are assumed. Here, it is assumed that the data bus 120 and the address bus 170 are connected to a CPU (not shown) and are used for data and address input / output.

  The coefficient register 100 is connected to the data bus 120, the output of the coefficient register 120 is one input of the multiplier 130, and the output of the data register 110 is the other input of the multiplier 130. The output of the multiplier 130 becomes one input of the adder 140, and the output of the intermediate data register 150 becomes the other input. The output of the adder 140 becomes the input of the intermediate data register 150 and the result register 160, and the result register 160 is connected to the data bus 120.

FIG. 1 is a block diagram of a first configuration of the present invention.
Data batch automatic storage means 180 is provided. The data batch automatic storage means 180 automatically and sequentially designates the storage position of the data register 110 by first receiving the address of the data register 110 from an external CPU (not shown) once through the address bus 170. Thus, as long as the address data is input from the external CPU only once at the beginning, the process of sequentially writing the input data sent via the data bus 120 to the data register 110 and the data from the data register 110 are sequentially performed. It is possible to perform a process of reading and performing a product-sum operation.

FIG. 2 is a block diagram of the second configuration of the present invention.
The second configuration has automatic address setting means 200 instead of the data batch automatic storage means 180 of the first configuration.

  The address automatic setting means 200 receives the address of the data register 110 from the external CPU (not shown) via the address bus 170, and thereafter receives the same dummy address as the first address via the address bus 170. Thus, the storage position of the data register 110 is automatically designated, and input data is written and read.

  Conventionally, as shown in FIG. 17, every time one piece of data is stored in the data register 110, an address designated by an external CPU is decoded to obtain an actual address. However, the data batch automatic storage means 180 having this configuration makes it possible to automatically specify the storage position of the data register 110 by inputting the address of the data register 110 as a dummy address each time data is input. This eliminates the need for the CPU to store the address data of each storage location of the data register 110.

FIG. 3 is a block diagram of the third configuration of the present invention.
The third configuration has address setting means 300 in place of the data batch automatic storage means 180 of the first configuration.

  The address setting means 300 receives the address data from the external CPU (not shown) only once for the first time via the address bus 170, and if the pointer value is input for each data input via the data bus 120, the address setting means 300 Specifies the storage location of register 110.

As a result, it is possible to save the trouble of inputting address data through the address bus 170 each time.
FIG. 4 is a block diagram of the fourth configuration of the present invention.

The fourth configuration has intermediate data recursion means 400 in addition to the third configuration.
The intermediate data recursive means 400 returns the intermediate result of the product-sum operation by the multiplier 130 and the adder 140 to the data register 110 without passing through the data bus 120.

  As a result, when configuring a recursive filter such as IIR, it is possible to easily store the result of the operation in the data register 110 and perform the product-sum operation again. At this time, the address of the data register 110 for storing the intermediate result is generated by the address setting means 300 having the third configuration.

The fourth configuration address setting means 300 can be replaced by the first configuration data batch automatic storage means 180 or the second configuration address automatic setting means 200.
FIG. 5 is a block diagram of the fifth configuration of the present invention.

  The fifth configuration includes intermediate data reading means 500 in addition to the fourth configuration. Intermediate data reading means 500 outputs an intermediate result of the product-sum operation by multiplier 130 and adder 140 to data bus 120. As a result, a CPU or the like (not shown) can read intermediate data during the product-sum operation via the data bus 120.

The fifth configuration address setting means 300 can be replaced with the first configuration data batch automatic storage means 180 or the second configuration address automatic setting means 200.
FIG. 6 is a block diagram of the sixth configuration of the present invention.

The sixth configuration has an overflow notification means 600 in addition to the fifth configuration.
When an overflow occurs during the calculation, the overflow notification means 600 stores the product sum term number calculated when the overflow occurs, and notifies an external CPU (not shown).

The address setting means 300 of the sixth configuration can be replaced with the data batch automatic storage means 180 of the first configuration or the address automatic setting means 200 of the second configuration.
Next, the operation of the block diagrams of the first to sixth configurations shown in FIGS. 1 to 6 will be described.

First, the operation of the first configuration (FIG. 1) will be described.
Prior to the multiply-accumulate operation, the coefficient and input data are stored in the coefficient register 100 and the data register 110. When data is stored in the data register 110, first, the data bus 110 and the address bus 170 are connected to each other, and the address of the data register 110 is input to the data batch automatic storage means 180 via the address bus 170 by a CPU or the like (not shown). Further, the stored data is input to the data batch automatic storage means 180 via the data bus 120.

  If the input address is the address of the data register 110, the data batch automatic storage means 180 designates the head real address of the data register 110 and stores the stored data at the head real address. If the address is not the address of the data register 110, it is ignored.

  The start address of the data register 110 is designated by the first address input, and thereafter, the data is sequentially stored at the next address of the data register 110 each time data is input from the data bus 120.

  In the first configuration, address designation from a CPU (not shown) may be performed once. The time required for data transfer and address designation can be shortened compared to the conventional method, and the product-sum operation processing can be executed easily and at high speed.

  Coefficient data is input to the coefficient register 100 from a CPU (not shown) via a data bus. Since coefficient data is not rewritten as often as input data, it is sufficient to specify the address by the CPU and write the coefficient data via the data bus as before. The storage unit 180 may be connected to the coefficient register 100 and addressing similar to that of the data register 110 may be performed.

  When coefficients and input data are stored in the coefficient register 100 and the data register 110, the multiplier 130 and the adder 140 perform a product-sum operation. In this case, the data used first for the product-sum operation is input to the multiplier 130. The coefficient in the coefficient register 100 becomes the other input of the multiplier 130. Multiplier 130 calculates the product and inputs it to adder 140. First, the other input value of the adder 140 is set to 0 to obtain the sum. The output of the adder 140 is stored in the intermediate data register 150, and the output of the intermediate data register 150 becomes the input of the adder 140. As a result, the next product is added to the intermediate result, and the product-sum operation is executed. The result of the product-sum operation is stored in the result register 160 and can be read from a CPU or the like (not shown).

Next, the operation of the second configuration (FIG. 2) will be described.
The difference between the second configuration and the first configuration is the address setting method of the data register 110 by the address automatic setting means 200 of the second configuration. Otherwise, the operation is the same as that of the first configuration.

  In the case of the first configuration, when data is first stored in the data register 110, the address of the data register 110 is inputted to the data batch automatic storage means 180 via the address bus 170 only once. On the other hand, in the second configuration, every time data is input to the data register 110, the address of the data register 110 is input to the address automatic setting means 200 via the address bus 170 from a CPU (not shown). At this time, the address need not be the address of each storage area of the data register 110, and may be the same as the address of the data register 110 inputted first (the same address may be used if it is the address of the data register 110). Therefore, it is called a dummy address).

  If the input address is the address of the data register 110, the automatic address setting means 200 first designates the first real address, and thereafter designates the real address to be stored sequentially, and the input inputted from the data bus 120. Data is stored sequentially. If the address input to the address automatic setting means 200 via the address bus 170 is not the address of the data register 110, the address automatic setting means 200 ignores it.

  As a result, it is not necessary to hold an address used for actual storage in the data register 110 as in the prior art, and the memory area can be reduced. Further, it is not necessary to decode the input addresses one by one as in the prior art except for the first storage address, and the processing speed is increased.

Next, the operation of the third configuration (FIG. 3) will be described.
The difference between the third configuration and the first and second configurations is the address setting method of the data register 110 by the address setting means 300. Other than that, the operation is the same as that of the first and second configurations.

  In the third configuration, a CPU (not shown) first stores, for example, the head address for storing data in the data register 110 via the address bus 170 and the pointer value of the data register 110 via the data bus 120. Input a pair of input data. That is, in the case of the first data, the pointer value 0 and the input data are sequentially input, and then the pointer value 1 and the input data are sequentially input.

  The address setting means 300 designates the head real address stored in the data register 110 from the head address, designates the storage address of the input data by the pointer value, and stores it.

  In the third configuration, the pointer of the data register 110 cannot be automatically generated as in the first and second configurations. However, since it is only necessary to specify the address at the time of the first data transfer, the address transfer processing is less than the conventional method, and the processing speed is improved. Therefore, it can be said that the third configuration is a configuration for a popular version with reduced hardware cost compared to the first and second configurations.

Next, the operation of the fourth configuration (FIG. 4) will be described.
The fourth configuration is a configuration in which intermediate data recursion means 400 is added to the third configuration, and the addressing of the data register 110 is the same as the operation of the third configuration. Data and coefficients are stored in 100, and the product-sum operation is started.

The multiplier 130 calculates the product of the first coefficient and the data in the coefficient register 100 and the data register 110 and inputs them to the adder 140. Initially, the other input value of the adder 140 is set to 0, the sum is calculated,
Is output. The sum is stored in the intermediate data register 150. When the first product sum is calculated and stored in the intermediate data register 150, the product sum of the next coefficient and data is read and the product is calculated by the multiplier 130. The product is input to the adder 140, and the sum stored in the intermediate data register 150 is used as the other input to obtain the sum and stored in the intermediate data register 150 again. The product sum is obtained by repeating this process.

  In the fourth configuration, the intermediate data recursive means 400 performs processing for returning the product-sum intermediate data output from the adder 140 to the data register 110 in response to an instruction from a CPU (not shown). The intermediate data is stored at the address of the data register 110 designated by the CPU (not shown). Thereby, recursive product-sum operation is possible using intermediate data of product-sum. This fourth configuration is suitable for the configuration of the IIR filter.

  The fifth configuration (FIG. 5) is a configuration in which intermediate data reading means 500 is further added to the fourth configuration. Therefore, in addition to the operation of the above-described fourth configuration, the operation of the fifth configuration outputs the product-sum intermediate data output from the adder 140 to the data bus 120 in response to an instruction from the CPU (not shown). The intermediate data is transferred to the CPU.

As a result, intermediate product-sum data can be read at an arbitrary time according to an instruction from a CPU (not shown).
Finally, the sixth configuration (FIG. 6) has an overflow notification means 600 in addition to the fifth configuration. Therefore, data writing to the data register 110 and product-sum operation processing are performed in the same manner as in the fifth configuration.

  In the product-sum operation, the number of bits that can be calculated by the multiplier 130 and the adder 140 is limited, and the number of bits may overflow due to the product-sum operation. Conventionally, even if an overflow occurs, the processing is continued as it is. However, the overflow notification means 600 of the sixth configuration causes an overflow every time intermediate data is obtained by calculating the product sum by the multiplier 130 and the adder 140. In the event of an overflow, the number of overflowed items is sent to the data bus 120 to indicate how many items of product data the overflowed intermediate data is. Output.

  A CPU (not shown) can easily perform a debugging process for correcting coefficients and the like so that overflow does not occur by reading the number of terms.

  According to the present invention, in the first and second configurations, it is possible to generate an address in the product-sum operation circuit without specifying the storage address of the data register for storing the product-sum operation data from the outside. Thus, there is no need to store the address data in an external memory area or the like and transfer it to the product-sum operation circuit, the transfer time and address generation time are shortened, and the processing speed is improved. In the third configuration, the operation data can be stored in the data register at an arbitrary timing. Further, in the fourth configuration, by returning the intermediate data of the product-sum operation to the data register 110, a recursive product-sum operation can be realized without going through the data bus, and the data transfer processing time can be shortened. Further, in the fifth configuration, by outputting the intermediate data of the product-sum operation to the data bus, the intermediate data can be easily processed outside. In the sixth configuration, it is possible to notify an overflow during a product-sum operation, and debugging efficiency such as resetting of coefficients is improved.

  As described above, according to the present invention, it is possible to realize a product-sum operation circuit suitable for not only an FIR filter but also an IIR filter and capable of generating addresses and transferring data at high speed.

FIG. 7 is a system configuration diagram of an embodiment of the present invention. Any of the first to sixth aspects of the present invention described above can be realized with this system configuration.
First, the CPU 700 exists. The CPU 700 corresponds to what is described as a CPU not shown in the explanation of the first to sixth configurations. The CPU 700 has an address bus 710 and a data bus 720. A memory 730 and a product-sum operation circuit 740 are connected to the address bus 710 and the data bus 720.

The memory 730 stores control software for the CPU 700, input data used by the product-sum operation circuit 740, coefficients, address data, pointer values, and the like.
On the other hand, the product-sum operation circuit 740 includes a product-sum operation circuit that realizes the first to sixth configurations.

Note that the present invention is not necessarily limited to the configuration shown in FIG. 7, and can be similarly applied to, for example, a DSP including a sequencer instead of a CPU.
Examples of the first to sixth configurations will be described below.

  In any embodiment, a coefficient register 100 for storing coefficient data for a plurality of terms, a data register 110 for storing input data for a plurality of terms, a multiplier 130 and an adder 140 for performing product-sum operation processing, It is assumed that an intermediate data register 150 for storing intermediate data in the middle of a sum operation and a result register 160 for storing a product-sum operation result are assumed.

  The outputs of the coefficient register 100 and the data register 110 become two inputs of the multiplier 130, respectively. The coefficient register 100 is also connected to the data bus 120, and is shown in FIG. 7 by the CPU 700 not shown in FIG. Coefficient data can be written / read through 120. The output of the multiplier 130 becomes the input of the adder 140, and the output of the intermediate data register 150 is connected to the other input of the adder 140. The output of the adder 140 becomes the input of the intermediate data register 150 and the result register 160. The result register 160 is connected to the data bus 120, and the CPU 700 can perform processing such as reading the product-sum operation result from the result register 160. FIG. 8 is a configuration diagram of an embodiment of the product-sum operation circuit having the first configuration.

  The data batch automatic storage means 180 of the first configuration described in FIG. 1 includes a decoder 800, a counter 810, and a selector 820. Decoder 800 is connected to address bus 170 and counter 810, and counter 810 is connected to decoder 800 and selector 820. The selector 820 is connected to the counter and data bus 120 and the data register 110.

  Address data is input to the decoder 800 via the address bus 170 according to the instruction of the CPU 700. The decoder 800 decodes the input address data. That is, it is determined whether or not the input address is the address of the data register 110, and if it is not the address of the data register 110, it is ignored. On the other hand, a clear signal is input to the counter 810 if it is the address of the data register 110.

  The counter 810 counts the number of terms corresponding to the storage position of the data register 110. For example, in the case of the figure, since the input data for four terms can be stored in the data register 110, the counter 810 counts 0-3. It goes without saying that 0 to 7 is counted for the product-sum operation of 8 terms, and 0 to 31 is counted for the product-sum operation of 32 terms. The counter 810 can be realized by a cyclic counter circuit.

  The counter 810 receives the clear signal from the decoder 800 and clears the count to zero. That is, when the address of the data register 110 is input to the decoder 800 via the address bus 170 by the external CPU 700, the counter 810 is cleared to zero.

  The output of the counter 810 is input to the selector 820 and becomes a selection signal. That is, if the counter output is 0, the input data input to the selector 820 via the data bus 120 is stored in the first address of the data register 110, and if the counter output is 1, the second storage location of the data register 110 is stored. The counter 810 increments when data storage in the data register 110 is completed.

  In this configuration, the CPU 700 transfers the pair of address data and input data to the product-sum operation circuit 740 only when the first data is stored, and thereafter, only the data is transferred to the product-sum operation circuit 740 via the data bus 120. That's fine. The decoder 800 having this configuration is a decoder having a simple configuration that determines whether the input address is the address of the data register 110 and outputs a clear signal to the counter 810 if the address is the data register 110.

  As described above, in this configuration, if the address of the data register 110 is first specified once, then the data can be automatically and sequentially stored in the data register 110. Data can be automatically stored in the data register 110. The configuration is also suitable for reading data for product-sum operation.

  In other words, if the address of the data register 110 is designated once at the start of the multiply-accumulate operation and the read multiplier 130, adder 140, etc. are started, the values of the data register 110 are automatically read sequentially. It is possible to output to 130. At this time, the counter 810 may be incremented every time one product-sum operation is completed.

  In the drawing, the writing / reading of the coefficient register 100 is not performed automatically by the CPU 700, but a circuit similar to the data register 110 may be added to perform batch automatic writing / reading of coefficients.

FIG. 9 is a system configuration diagram of an embodiment of the second configuration (FIG. 2).
Similarly to the first configuration (FIG. 8), the address automatic setting means 200 of the second configuration includes a decoder 900, a counter 910, and a selector 920. The decoder 900 is connected to the address bus 170 and the counter 910, the counter 910 is connected to the decoder 900 and the selector 920, and the selector 920 is connected to the data bus 120, the counter 910 and the data register 110. This connection is also the same as in the first configuration.

  The difference from the first configuration (FIG. 8) is that the CPU 700 always inputs a pair of address and input data. The address is input to the decoder 900 via the address bus 170, and the input data is input to the selector 920 via the data bus 120. However, since the actual address of the data register 110 is not obtained from the address, the address may be any address indicating the data register 110.

  The decoder 900 decodes the address input from the address bus 170 and determines whether the address is an address indicating the data register 110. If the address indicates the data register 110, a signal for incrementing the counter 910 is output to the counter 910. On the other hand, if the address is a different address indicating another register, the address and data pair is ignored.

  The counter 910 receives the increment signal from the decoder 900, increments it, and outputs the counter value to the selector 920. The value of the counter 910 may be cleared to 0 at the time of the first address / data input.

The selector 920 uses the input (counter value) from the counter 910 as a selection signal, and stores the data input from the data bus 120 in the corresponding storage position of the data register 110.
As described above, according to the second configuration, only data for which the address of the data register 110 is designated can be sequentially stored in the data register 110. In the conventional method, the address input from the address bus 170 is decoded to obtain the real address of the data register 110 one by one. In this configuration, the counter 910 is incremented to obtain the storage position of the data register 110. Therefore, the decoder 900 need only have a function of determining whether the address indicates the data register 110 or not. FIG. 10 is a system configuration diagram of an embodiment of the third configuration (FIG. 3).

  The address setting means 300 having the third configuration includes a pointer register 1000, an adder 1010, data 1020, and a selector 1030. The pointer register 1000 is connected to the data bus 120 and one input of the adder 1010, and the other input of the adder 1010 is connected to the address bus 170. The output of the adder 1010 is connected to the decoder 1020, and the output of the decoder 1020 is connected to the selector 1030. The selector 1030 is connected to the data bus 120, the decoder 1020, and the data register 110.

  The third configuration does not automatically generate a selection signal (pointer) for the storage position of the data register 110 internally as in the first and second configurations. That is, the CPU 700 designates the address of the data register 110 and the pointer value indicating the storage position in the data register 110 every time data is stored in the data register 110. As the address, for example, the head address may be designated. Alternatively, a dummy address corresponding to the data address 110 may be designated.

  The address is stored in the adder 1010 via the address bus 170, and the pointer value is stored in the pointer register 1000 via the data bus 120. The pointer value takes a value from 0 to (the number stored in the data register 110 minus 1), and the value is controlled by the CPU 700.

  The address and the pointer value output from the pointer register 1000 are input to the adder 1010 and added. The output of the adder 1010 is input to the decoder 1020 to decode the address. The output of the decoder 1020 is input to the selector 1030 and becomes a selection signal of the selector 1030. The storage position in the data register 110 is determined by the selection signal from the decoder 1020, and the input data input to the selector 1030 via the data bus 120 is stored in the storage position.

  As described above, this configuration requires the CPU 700 to specify the start address and pointer value of the data register 110, and the dependency on the CPU 700 is greater than that in the first and second configurations. However, unlike the conventional method, the CPU 700 does not need to have an address of each storage position of the data register 110. If only the start address and the pointer value are stored in the memory area and specified to the product-sum operation circuit, Good. Further, unlike the first and second configurations, the CPU 700 can specify the storage position in the data register 110 using the start address and the pointer value.

  The third configuration can be realized without the adder 1010. That is, the address input from the address bus 170 is decoded by the decoder 1020 and input to the selector 1030, and the pointer value stored in the pointer register 1000 is also input to the selector 1030 via the data bus 120. Then, the selector 1030 designates the storage position of the data register 110 by using both the decoded address, for example, the head address of the data register 110 and the pointer value as selection signals.

FIG. 11 is a system configuration diagram of an embodiment of the fourth configuration (FIG. 4).
The fourth configuration is obtained by adding the intermediate data recursive means 400 to the third configuration, and is the same as the third configuration except for the intermediate data recursive means 400.

  The intermediate data recursive means 400 is realized by a data line 1100 that returns the output of the adder 140 for the product-sum operation to the data register 110. The storage address in the data register 110 may be directly designated by the CPU 700, or may be designated by the address designation method described in the third configuration example (FIG. 10).

  In this way, by returning the output of the adder 140 to the data register 110, a recursive type process that performs the product-sum operation again using the intermediate data of the product-sum operation can be performed, and an IIR filter can be realized.

FIG. 12 is a system configuration diagram of an embodiment of the fifth configuration (FIG. 5).
The fifth configuration is a configuration obtained by adding intermediate data reading means 500 to the fourth configuration, and is the same as the fourth configuration except for the intermediate data reading means 500.

  The intermediate data reading means 500 can be realized by a data line 1200 that connects the output of the intermediate data register 150 to the data bus 120. Data in the middle of the multiply-accumulate operation stored in the intermediate data register 150 is read via the data bus by the instruction of the CPU 700.

  The read data can be processed by the CPU 700 or stored in the data register 110 again. When data is stored in the data register 110, the address of the data register 110 can be specified and stored by the third addressing method using the pointer register 1000, the adder 1010, the decoder 1020, and the selector 1030. Further, the intermediate data is successively stored in the data register 110 by the method of automatically incrementing the counter and designating the address of the data register 110, which is the address design method of the first configuration, and the product-sum operation is performed again. You can also.

FIG. 13 is a system configuration diagram of an embodiment of the sixth configuration (FIG. 6).
The sixth configuration is a configuration in which an overflow notification unit 600 is added to the fifth configuration, and is the same as the fifth configuration except for the overflow notification unit 600.

  The overflow notification means 600 is realized by an overflow term register 1300 that receives the output of the intermediate data register 150 as an input. The output of the overflow term register 1300 is connected to the data bus 120.

  The overflow term number register 1300 stores the number of terms of the product-sum operation in which an overflow occurs when an overflow occurs during the product-sum operation. By using the data line 1200 to read the number of terms stored in the overflow term register 1300 and the overflowed intermediate data in the intermediate data register 150, debugging processing such as reshaping coefficient data to prevent overflow is easy. You can do it.

FIG. 14 is a more detailed system configuration diagram of the embodiment of the sixth configuration (FIGS. 6 and 13).
In the figure, for example, a product-sum operation of 4 terms is assumed, coefficient data (A0, A1, A2, A3) for 4 terms is stored in the coefficient register 100, and input data for 4 terms is stored in the data register 110 ( X0, X1, X2, X3) can be stored. Any number of terms can be used as long as it is two or more.

  In this embodiment, in addition to the system configuration of FIG. 13, the output of the intermediate data register 150 is used as an input to store the overflowed data, and the output is stored in the overflow data register 1400 connected to the data bus 120 and the data bus 120. Two registers that are connected to store pointer values transferred by the CPU 700, a pointer register 2 1410, a pointer register 3 1420, and a data output from the data register 110 as input data, and a selector that uses the pointer value in the pointer register 3 1420 as a selection signal Realized in 1430. The pointer value of the pointer register 2 1410 becomes the selection signal of the other selector 1030.

  Assume that coefficient data (A0, A1, A2, A3) is stored in the coefficient register 100 and input data (X0, X1, X2, X3) is stored in the data register 110. I will explain later.

  In this product-sum operation unit, the multiplier 130 performs the operation of coefficient data × input data on the data of each term, and the adder 140 sequentially adds the product values. That is, A0 * X0 + A1 * X1 + A2 * X2 + A3 * X3 is calculated.

  If the coefficient data and the input data are 8 bits, if the output line of the adder 140 has a width of 8 + 8 + 2 (which is generated by adding four terms) = 18 bits, the product-sum operation does not cause an overflow. However, if the calculation result is also 8 bits, overflow may occur, and measures against overflow are required for the product-sum operation circuit.

In this embodiment, for example, it is assumed that calculation is performed with Q6 fixed-point data. That is, it is a data format in which an integer part is 1 bit and a decimal part is 6 bits per code bit.
Now, A0 = A1 = A2 = A3 = 1 (decimal number) = 40H (Q6 fixed-point representation is expressed in hexadecimal number, 0100 0000 when expressed in binary number), X0 = X1 = X2 = X3 = 40H . Then, the first product operation A 0 × X 0 = 1000H (0001 0000 0000 0000 in binary number) is obtained. This is 40H in terms of 8-bit Q6 fixed point. Next, when A1 * X1 = 1000H is added to A0 * X0 = 1000H, 2000H is obtained. If this is expressed by 8-bit Q6, it becomes 80H, and the 8-bit Q6 fixed-point data overflows. That is, Q6 fixed-point data can represent only a value between 80H (1000 0000 in binary number and -2 in decimal number) to 7FH (0111 1111 in binary number and 1.984375 in decimal number).

  In this embodiment, in this case, 80H, which is the intermediate data that has overflowed into the overflow data register 1400, has a value of 2 because the overflow term register 1300 has overflowed in the product-sum operation of the second item. Is stored, and the product-sum operation is continued. Then, A0.times.X0 + A1.times.X1 + A2.times.X2 + A3.times.X3 is calculated to the end, 4000H is stored in the result register 160, and further output to the data bus 120 via the data line 1200 to complete the processing. . At this time, if the output is specified as 8-bit Q6 fixed-point data, 00H is stored in the result register 160, and the process is terminated.

  On the other hand, let us consider a case where the next operation is continuously performed. Data register 100 containing X0 when new input data X4 is brought next to previous data X0, X1, X2, X3, and A0.times.X1 + A1.times.X2. + A2.times.X3 + A3.times.X4 is calculated. X4 needs to be stored in the storage location.

  In this case, the CPU 700 sets the value 0 to the pointer register 11000 via the data bus 120, the input data to the selector 1030 via the data bus 120, and the dummy address (data to the adder 1010 via the address bus 170). By designating the address indicating the register 110, etc., X4 is stored at the position of X0 so far.

  Prior to starting the product-sum operation, the CPU 700 changes the value of the pointer register 3 1420 from 0 to 1. As a result, the value of the selection signal of the selector 1430 is increased by 1, and the head read address from the data register 110 is shifted by 1 to become X1.

As described above, the pointer register 3 1420 generates a signal for shifting the head read address from the data register 110.
Further, consider a case where the product-sum operation result or intermediate data is stored in the data register 110 and used for the next product-sum operation.

  In such a case, if the product-sum operation result is obtained, the CPU 700 returns the value of the result register 160 to the selector 1030 via the data bus 120, sets the value in the second pointer register 2 1410, and sets the pointer value to the selector. Enter in 1030. As a result, the storage position of the data register 110 is determined, and the calculation result can be stored. On the other hand, when the intermediate data is returned to the data register 110, the intermediate data may be returned to the selector 1030 by the CPU 700 via the data line 1100. The storage position of the data register 110 is determined by setting a pointer value in the pointer register 2 1410.

By placing the pointer register 2 1410, the IIR filter can be easily configured.
FIG. 15 shows a configuration in which a data length selection selector 1500 is inserted between the output of the adder 140 and the intermediate data register 150 in addition to the configuration of the embodiment of FIG. The data length selection selector 1500 is a selector that selects some bits of the product-sum result data. For example, 8 bits out of 16 bits can be selected, 16 bits out of 32 bits can be selected, or 8 bits can be output as they are.

  Finally, FIG. 16 shows a configuration in which a pointer register 41600 and a controller CTL 1610 are added to the configuration of the embodiment of FIG. The pointer register 4 1600 is connected to the data bus 120 and the controller 1610. The controller 1610 is connected to the data bus 120 and the data register 110, the coefficient register 100, the multiplier 130, and the adder 140.

  When performing sum-of-products operations up to a certain term, and subsequent operations cannot be performed unless sent from another processing device (not shown), etc. use. The pointer register 4 1600 stores a pointer value indicating an address of a term to stop the product-sum operation.

  When the data read address input from the data register 110 to the multiplier 130 matches the address indicated by the pointer register 41600, the controller 1610 stops the product-sum operation. Then, the controller 1610 waits for necessary data to be transferred via the data bus 120. When the data is stored in the data register 110 or the coefficient register 100, the controller 1610 resumes the interrupted product-sum operation. Thus, the multiplier 130, the adder 140, etc. are controlled.

  In the product-sum calculator of the present invention, an FIR filter having various characteristics can be configured by appropriately selecting coefficient data stored in the coefficient register. In addition, by storing the result of the product-sum operation as input data in the data register, various IIR filters can be configured.

  For example, if data corresponding to a signal via a delay element is used as input data, a non-recursive delay filter (transversal filter) or a recursive delay filter can be configured.

It is a block diagram of the 1st composition of the present invention. It is a block diagram of the 2nd composition of the present invention. It is a block diagram of the 3rd composition of the present invention. It is a block diagram of the 4th composition of the present invention. It is a block diagram of the 5th composition of the present invention. It is a block diagram of the 6th composition of the present invention. It is a system configuration diagram of one embodiment. 1 is a system configuration diagram of an embodiment of a first configuration of a product-sum operation circuit. FIG. It is a system block diagram of one Example of the 2nd structure of a product-sum operation circuit. It is a system configuration | structure figure of one Example of the 3rd structure of a product-sum operation circuit. It is a system configuration | structure figure of one Example of the 4th structure of a product-sum operation circuit. It is a system configuration | structure figure of one Example of the 5th structure of a product-sum operation circuit. It is a system block diagram of one Example of the 6th structure of a product-sum operation circuit. It is a more detailed block diagram of the 6th structure of a product-sum operation circuit. It is a system configuration | structure figure of one Example for enabling selection of the data length of the product-sum operation result. 1 is a system configuration diagram of an embodiment that enables a product-sum operation to be temporarily interrupted. FIG. It is a block diagram of the conventional product-sum operation circuit.

Explanation of symbols

100 coefficient register 110 data register 120 data bus 130 multiplier 140 adder 150 intermediate data register 160 result register 170 address bus 180 data batch automatic storage means 300 address setting means 400 intermediate data recursion means 500 intermediate data reading means 600 overflow notification means

Claims (4)

In a product-sum operation unit having a register for product-sum operation, transferring product-sum operation data to the register in advance, and performing product-sum operation using the data of the register,
A product-sum operation unit that outputs intermediate data in the middle of product-sum operation to the register without going through a data bus. A data register for storing data;
A product-sum operation unit for performing a product-sum operation based on data from the data register;
In a product-sum calculator comprising:
The product-sum operation unit, wherein the intermediate result processed by the product-sum operation unit is output to the data register without passing through a data bus.   A data calculation apparatus comprising the product-sum operation unit according to claim 1. Store the sum-of-products data in the register,
Perform product-sum operation using the product-sum operation data stored in the register,
A product-sum operation method, wherein an intermediate result in the middle of a product-sum operation is fed back to the register without going through a bus.

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