JP5953881B2 - 3-level rectifier controller - Google Patents

Description

  The present invention relates to a three-level rectifier, and more particularly to neutral point potential balance control.

In the three-level inverter shown in FIGS. 8 and 9, when the power factor is completely 1 and only the active power is input, the current flowing through the switching elements T1 and T4 becomes zero. Therefore, normal operation is possible even if the switching elements T1 and T4 are omitted.

   Table 1 is a table showing a switching pattern of a normal three-level inverter. If the switching elements T1 and T4 are omitted, the current flows only in one direction in the upper and lower arms, so that the operation with the switching patterns of No. 1 and No. 3 is impossible. However, if the power factor is completely 1 and only active power is input, the switching pattern is limited to the numbers 2 and 4 and can operate without any problem.

   This circuit configuration is generally known as a multilevel rectifier. This is a configuration in which an output terminal and a neutral point are connected to a normal rectifier circuit by bidirectional switches T2 and T3 as shown in FIG. In general, a method of making current distortion smaller than that of a normal rectifier circuit is performed by switching the bidirectional switches T2 and T3 about once every half cycle (see, for example, Patent Documents 1 to 3).

JP 2011-193593 A W02009-028053 A1 JP 2008-022625 A

  However, the method of switching the bidirectional switches T2 and T3 about once in a half cycle can reduce current distortion as compared with a normal rectifier circuit, but increases current distortion as compared with a general inverter. In particular, in applications that are connected to the grid, there is a restriction on harmonic outflow so that harmonic current due to distortion does not adversely affect other devices and equipment, and the current distortion is suppressed to satisfy this restriction. There is a need.

  Furthermore, the unbalance of the neutral point potentials Vdc1 and Vdc2 also becomes a problem. If this unbalance becomes large, an excessive voltage is applied to each switching element (bidirectional switch T2, T3), causing element destruction. It also causes input current distortion. In the case of a normal three-level inverter, a balance control method in which an offset is superimposed on the zero phase of the output voltage command value is generally performed. However, when this method is applied to a multi-level rectifier, an operation with the switching patterns of No. 1 and No. 3 in Table 1 is required. Since the multilevel rectifier cannot operate with the switching patterns of No. 1 and No. 3, the effect of balance control is reduced and current distortion is increased.

  In Patent Document 1, the distortion of the input current is suppressed by switching the bidirectional switches T2 and T3 at a high frequency. However, in Patent Document 1, there is no effect of compensating for the unbalance of the neutral point potentials Vdc1 and Vdc2, and it is necessary to add balance control separately.

Further, claim 11 in Patent Document 1 is a method that takes into account the phase delay due to the filter reactor. However, in this method, it is necessary to detect the phase difference between the rectifier applied voltage and the input current, and as described in Patent Document 1 (FIG. 4), it is necessary to perform an operation with a high load such as tan ⁻¹ , division, and square root. . If the calculation load is too high, the calculation of the output voltage command value will not be in time for the next switching, and the current distortion suppression effect will be reduced.

  Example 2 of Patent Document 2 is a method of compensating for the unbalance of the neutral point potentials Vdc1 and Vdc2 by a method of switching the pulse patterns of the bidirectional switches T2 and T3 or a method of changing the duty ratio. However, changing the pulse pattern or duty ratio is equivalent to changing the rectifier output voltage. Therefore, if the rectifier output voltage is changed, the input current is also affected. As a result, problems such as excess or deficiency in the input active power and increase in current distortion occur.

  Japanese Patent Application Laid-Open No. 2004-228688 is a method of detecting the unbalance of the neutral point potentials Vdc1 and Vdc2, performing compensation by feedback, and changing the pulse pattern to balance the neutral point potentials Vdc1 and Vdc2. Similar to Patent Document 2, when the pulse pattern is changed, the output voltage of the rectifier also changes, which causes problems such as excess or deficiency of input active power and increase in current distortion.

  Further, Patent Documents 1 to 3 do not discuss a method for suppressing current distortion when the unbalance of neutral point potentials Vdc1 and Vdc2 increases. The cause of the occurrence of a large imbalance in the neutral point potentials Vdc1 and Vdc2 is that when a sudden load change occurs when one capacitor is charged, separate loads are connected in parallel to the capacitors C1 and C2. If so, it is possible. In this way, when a large imbalance occurs in the neutral point potentials Vdc1 and Vdc2, the distorted current continues to be input until the imbalance is eliminated by the control.

  As described above, in the AC / DC converter, there is a problem of suppressing neutral point potential imbalance and current distortion.

  The present invention has been devised in view of the conventional problems, and one aspect thereof is a rectifier connected to an AC power supply via a filter, and a plurality of capacitors connected in series between output terminals of the rectifier. The output voltage command value is calculated from the deviation between the rectifier input current and the current command value, the switch having a withstand voltage in both directions inserted between the rectifier and the capacitor, and based on the output voltage command value A control unit that PWM-controls a switch having a withstand voltage in both directions, wherein the control unit outputs an output voltage command value so as to reduce a deviation of the voltage across the capacitor. The correction part which correct | amends is provided.

  Further, the correction unit detects an instantaneous value of the voltage across the capacitor and changes the gain in accordance with the pulsation.

  Further, the correction unit multiplies the output voltage command value by a gain of 1/2 Vdc1 if the output voltage command value is positive and 1/2 Vdc2 if the output voltage command value is negative.

  As another aspect, the correction unit multiplies the output voltage command value by a gain of 2Vdc2 if the output voltage command value is positive and 2vdc1 if the output voltage command value is negative.

  The control unit includes a dq conversion unit that dq-converts the rectifier input current on the rotation coordinates, d-axis and q-axis components of the rectifier input current, a d-axis current command value, a q-axis current command value, A subtractor that calculates a deviation of the dq and a dq inverse conversion unit that inversely converts the d-axis and q-axis output voltage command values calculated based on the deviation onto fixed coordinates. The phase used for conversion is delayed based on the magnitude of the d-axis current command value.

  Furthermore, as another aspect, the control unit includes a dq conversion unit that performs dq conversion of the rectifier input current on the rotation coordinates, d-axis and q-axis components of the rectifier input current, a d-axis current command value, and a q-axis. A subtractor for calculating a deviation between the current command value and a dq reverse conversion unit for performing dq reverse conversion of the d-axis and q-axis output voltage command values calculated based on the deviation onto fixed coordinates, A value obtained by multiplying the d-axis current command value by the gain calculated based on the impedance of the reactor is used as the q-axis current command value.

  According to the present invention, in an AC / DC converter, neutral point potential imbalance and current distortion can be suppressed.

2 is a block diagram illustrating a main circuit and a control unit of the AC / DC converter according to Embodiment 1. FIG. 3 is a block diagram illustrating a correction unit according to Embodiment 1. FIG. 3 is a graph illustrating a waveform of an output voltage command value by a correction unit according to the first embodiment. It is a figure which shows the change of the current pathway at the time of output voltage command value correction | amendment in Embodiment 1. FIG. 6 is a block diagram illustrating a correction unit according to Embodiment 2. FIG. It is a block diagram which shows the control part of the alternating current direct current converter in Embodiment 3. It is a block diagram which shows the control part of the alternating current direct current converter in Embodiment 4. It is a circuit diagram which shows the structure which abbreviate | omitted switching element T1, T4 from the NPC3 level inverter. It is a circuit diagram which shows the structure which abbreviate | omitted switching element T1, T4 from the A-NPC3 level inverter. It is a circuit diagram which shows the structure of the multilevel rectifier which added the bidirectional | two-way switch to the neutral point of the normal rectifier.

  Hereinafter, the AC / DC converters (multilevel rectifiers) in Embodiments 1 to 4 will be described in detail with reference to the drawings.

[Embodiment 1]
FIG. 1 shows the configuration of an AC / DC converter according to Embodiment 1, where (a) shows a main circuit and (b) shows a current control unit. As shown in FIG. 1 (a), the main circuit of the AC / DC converter includes a rectifier 2 that rectifies the AC of the AC power source 1, a reactor L interposed between the AC power source 1 and the rectifier 2, and a rectifier. 2 having a withstand voltage in both directions including capacitors C1 and C2 connected in series between the two output terminals and switching elements T2 and T3 interposed between the rectifier 2 and the neutral point of the capacitors C1 and C2. A switch (hereinafter referred to as a bidirectional switch). The bidirectional switches T2 and T3 are composed of, for example, an IGBT and a diode rectifier. Note that the main circuit of FIG. 1A is simplified to show only one phase.

  Moreover, the AC / DC converter is provided between the reactor L and the rectifier 2, and the voltage detector 3 that detects the phase of the grid connection point voltage Vs provided between the AC power source 1 and the reactor L. A current detector 4 that detects the rectifier input current Iinv and a voltage detector (not shown) that detects neutral point potentials Vdc1 and Vdc2 that are voltages across the capacitors provided in the capacitors C1 and C2. .

As shown in FIG. 1B, the control unit adds a correction unit 12 that corrects the output voltage command values Vu ^* , Vv ^* , and Vw ^* to a general current control unit 5 used in a normal inverter. Is. However, since the switching elements T1 and T4 shown in FIGS. 8 and 9 do not exist in the main circuit, the gate signal Gate is not transmitted to the switching elements T1 and T4.

  First, the current control unit 5 receives the rectifier input current Iinv detected by the current detector 4, removes PWM switching noise and the like in the low-pass filter LPF, and outputs it to the dq conversion unit 6. The dq converter 6 converts the rectifier input current Iinv into a d-axis rectifier input current Iinvd and a q-axis rectifier input current Iinvq, which are values on the rotational coordinates. The phase used for the dq conversion uses the output of the PLL controller 7 that outputs a phase synchronized with the grid connection point voltage Vs.

  Here, the d-axis rectifier input current Iinvd is defined to be positive when active power is output and the R load is driven, and negative when active power is input. On the other hand, the q-axis rectifier input current Iinvq is defined to be positive when driving reactive power is output and driving a C load, and negative when driving reactive load of L and driving L load.

The d-axis rectifier input current Iinvd and the q-axis rectifier input current Iinvq are subtracted by the subtracters 8a and 8b from the d-axis current command value Id ^* and the q-axis current command value Iq ^*, and the deviation is calculated. Here, since the controlled object is a rectifier, the d-axis current command value Id ^* is limited to a negative value, and the q-axis current command value Iq ^* is fixed to zero.

Deviations obtained by comparing the d-axis rectifier input current Iinvd and the q-axis rectifier input current Iinvq with the d-axis current command value Id ^* and the q-axis current command value Iq ^* are applied to the proportional-integral controllers 9a and 9b. Thus, the d-axis and q-axis output voltage command values Vdref and Vqref are obtained.

  A “reference voltage” is added by the adder 10 to the d-axis output voltage command value Vdref. This “reference voltage” means adding the value of the rated amplitude of the grid connection point voltage Vs, and is usually 1. This is equivalent to adding a reference sine wave synchronized with the phase of the grid connection point voltage Vs together with the subsequent dq inverse transformation.

The dq reverse conversion unit 11 performs dq reverse conversion on the d axis output voltage command value Vdref added with the “reference voltage” by the adder 10 and the q axis output voltage command value Vqref output from the q axis proportional integration controller 9b. To obtain output voltage command values Vu ^* , Vv ^* , Vw ^* on fixed coordinates. The phase used for dq inverse conversion is obtained by the PLL controller 7 to which the grid connection point voltage Vs is input.

Using the neutral point potentials Vdc1 and Vdc2, the correction unit 12 corrects the output voltage command values Vu ^* , Vv ^* , and Vw ^* to obtain the corrected output voltage command values Vu ^* ′, Vv ^* ′, and Vw ^* ′. Ask.

Finally, the three-phase corrected output voltage command values Vu ^* ′, Vv ^* ′, and Vw ^* ′, which are the outputs of the correction unit 12, are PWM-modulated by the PWM modulator 13, thereby generating the gate signal Gate. The bidirectional switches T2 and T3 are controlled by the gate signal Gate.

Details of the correction unit 12 in the first embodiment will be described in detail with reference to FIG. In FIG. 2, only one phase (Vu ^* ) is shown for simplification, but actually, three phases of Vu ^* , Vv ^* , and Vw ^* are corrected.

The correction unit 12 first doubles the neutral point potentials Vdc1 and Vdc2 by the gain multiplication units 21a and 21b, calculates the reciprocal number of the gain multiplication units 21a and 21b by the dividers 22a and 22b, and outputs them to the switch SW. To do. The switch SW is input the output voltage command value Vu ^*, outputs a 1 / 2Vdc1 when Vu ^*> 0, when not in Vu ^*> 0 outputs 1 / 2Vdc2.

The product of the output result of the switch SW and the output voltage command value Vu ^* is calculated by the multiplier 23, and the output of the multiplier 23 becomes the corrected output voltage command value Vu ^* ′ which is the output of the correction unit 12. The corrected output voltage command values Vv ^* ′ and Vw ^* ′ are calculated by the same method.

  Next, operation | movement of the correction | amendment part 12 of the AC / DC converter in this Embodiment 1 is demonstrated. Here, it is assumed that the neutral point potential Vdc1 <Vdc2. Further, it is assumed that the neutral point potentials Vdc1 and Vdc2 are normalized to be 0.5 when the DC voltage is rated and balanced.

When output voltage command values Vu ^* , Vv ^* , and Vw ^* that are sine waves are output without correction in the correction unit 12, the positive-side amplitude of the rectifier output voltage is proportional to the neutral point potential Vdc1, and the rectifier output voltage Since the negative-side amplitude is proportional to the neutral point potential Vdc2, the negative-side amplitude becomes a distorted voltage. Thus, the distortion of the output voltage causes current distortion.

As a countermeasure, when the output voltage command values Vu ^* , Vv ^* , and Vw ^* are positive, the correction unit 12 multiplies the output voltage command values Vu ^* , Vv ^* , and Vw ^* by ½ Vdc1 to obtain a negative value. Time is multiplied by 1/2 Vdc2. As a result, as shown in FIG. 3, the corrected output voltage command values Vu ^* ′, Vv ^* ′, and Vw ^* ′ after correction have larger positive amplitudes. By correcting the output voltage command values Vu ^* , Vv ^* , and Vw ^* in this way, it is possible to cancel distortion generated at the output stage and output a voltage having the same positive and negative amplitudes.

  The correction unit 12 detects the instantaneous values of the neutral point potentials Vdc1 and Vdc2, and changes the gain (1 / 2Vdc1, 1 / 2Vdc2) according to the pulsation, thereby pulsating to the neutral point potentials Vdc1 and Vdc2. It is possible to suppress the pulsation even when is superimposed. Therefore, the distortion of the input current can be reduced even when the fluctuation of the DC side load is large or when the capacitances of the capacitors C1 and C2 with respect to the load are small.

The flow of current when correction is performed by the correction unit 12 will be described with reference to FIG. FIG. 4A shows a case where the rectifier output voltage Vu> 0, in which active power is being input. Current passes through either the upper arm or the neutral point. Here, the corrected output voltage command value Vu ^* ′ has a larger positive amplitude because of the correction, and therefore the time during which the upper arm is turned on becomes longer. Therefore, a large amount of current flows through the upper arm, and the discharge of the capacitor C1 is suppressed.

FIG. 10B shows a state where the current passes through either the lower arm or the neutral point because the rectifier output voltage Vu <0. In this case, the corrected output voltage command value Vu ^* 'has a negative amplitude that is reduced by the correction, and therefore, the time during which the bidirectional switches T2 and T3 are turned on becomes longer, and the current has more neutral points. Flowing. As a result, discharge of the capacitor C2 is promoted. As described above, the bidirectional switches T2 and T3 can be operated so that the difference between the neutral point potentials Vdc1 and Vdc2 is reduced by correcting the output voltage command values Vu ^* , Vv ^* , and Vw ^* .

As described above, according to the AC / DC converter according to the first embodiment, the neutral point potentials Vdc1, Vdc2 are detected and the output voltage command values Vu ^* , Vv ^* , Vw ^* are corrected. Even if the point potentials Vdc1 and Vdc2 are unbalanced, the distortion of the rectifier input current Iinv can be reduced, and the neutral point potentials Vdc1 and Vdc2 can be balanced. Further, unlike the conventional method, the operation is such that the rectifier output voltages Vu, Vv, and Vw are brought close to a sine wave, so that the distortion of the input current is not increased in principle.

[Embodiment 2]
FIG. 5 is a block diagram illustrating a configuration of the correction unit 12 according to the second embodiment. In the second embodiment, the dividers 22a and 22b are deleted from the correction unit 12 in the first embodiment, and the switching of the switch SW is reversed from that in the first embodiment. When Vu ^* > 0, the lower state is satisfied, and when Vu ^* > 0 is not satisfied ^. Switches to the top. Specifically, when Vu ^* > 0, 2Vdc2 × Vu ^* is set as the corrected output voltage command value Vu ^* ′, and when Vu ^* > 0 is not set, 2Vdc1 × Vu ^* is set as the corrected voltage command value Vu ^* ′.

  In the second embodiment, the calculation is simplified using approximation under the condition that the neutral point potentials Vdc1 and Vdc2 are close to 0.5. That is, this is a method in which the calculation load is reduced by limiting the effect of suppressing the waveform distortion to a range in which the unbalance of the neutral point potentials Vdc1 and Vdc2 does not become extremely large.

  As described above, according to the AC / DC converter according to the second embodiment, by performing approximation under the condition that the unbalance of the neutral point potentials Vdc1 and Vdc2 does not become extremely large, the calculation load is increased as compared with the first embodiment. It becomes possible to reduce.

[Embodiment 3]
FIG. 6 is a block diagram illustrating a control unit of the AC / DC converter according to the third embodiment. In the third embodiment, the phenomenon that the rectifier input current Iinv is distorted when a filter is connected to the main circuit is suppressed.

The control unit in the third embodiment is different from the control unit in the first embodiment in that the multiplier 14 multiplies the d-axis current command value Id ^* by the gain G, and the output of the multiplier 14 from the output phase of the PLL controller 7. An adder 15 for subtracting the value is added. That is, the difference from Embodiment 1 is that the d-axis current command value Id ^* multiplied by an appropriate gain G is subtracted from the output phase of the PLL controller 7 and used for dq conversion and dq reverse conversion. .

  Since Patent Documents 1 and 3 are based on the premise that a reactor L is connected to the rectifier 2 as a filter, a voltage drop occurs in the reactor L, and a phase delay occurs in the voltage applied to the rectifier 2 with respect to the interconnection point voltage Vs. However, in the control of claim 10 in Patent Document 1, the phases of the interconnection point voltage Vs and the rectifier input current Iinv are tried to be matched, and as a result, the phases of the rectifier input voltage and the rectifier input current Iinv are shifted and cannot be operated originally. The switching patterns of numbers 1 and 3 in Table 1 are required, and the rectifier input current Iinv is distorted.

On the other hand, in the third embodiment, the power factor of the rectifier 2 alone that does not include the filter is set to 1 by delaying the phase used for dq conversion and dq inverse conversion in the control unit in accordance with the delay of the rectifier input voltage. Current distortion can be reduced. Since the voltage drop at the reactor L is proportional to the rectifier input current Iinv, a sufficient effect can be obtained simply by delaying the phase used for control in proportion to the d-axis current command value Id ^* .

  As described above, according to the AC / DC converter according to the third embodiment, the control phase is delayed in accordance with the voltage drop of the filter, so that the power factor of the rectifier 2 alone that does not include the reactor L is set to 1, and the operation is disabled. It is possible to suppress the occurrence of possible switching patterns and reduce the distortion of the input current. In addition, since the configuration added to the control unit of the first embodiment is only one adder and one multiplier, the increase in calculation load is also small.

[Embodiment 4]
FIG. 7 is a block diagram illustrating a control unit of the AC / DC converter according to the fourth embodiment. Although the control unit in the first to third embodiments sets the q-axis current command value Iq ^* to zero, in the fourth embodiment, the multiplier 16 converts the q-axis current command value Iq ^* to the d-axis current command value Id ^* and gain G. The value is multiplied by.

  The fourth embodiment also suppresses the phenomenon that the rectifier input current Iinv is distorted when a filter is connected to the main circuit, as in the third embodiment. As a difference from the third embodiment, the rectifier input current Iinv input by the rectifier 2 is delayed rather than the phase used for control. Since the voltage drop at the reactor L is proportional to the rectifier input current Iinv and the impedance of the reactor L, the gain G specified in the fourth embodiment is the impedance of the reactor L, and an appropriate gain can be easily obtained.

  As described above, according to the AC / DC converter in the fourth embodiment, the same effect as in the third embodiment can be obtained. Furthermore, in addition to the effects of the third embodiment, the gain G can be adjusted to the impedance of the reactor L, so that the gain G can be easily adjusted. Further, since the configuration added to the control unit of the first embodiment is only one multiplier, the increase in calculation load is also small.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  For example, in the first embodiment, the configuration of the AC / DC converter is the A-NPC type, but the NPC type is also applicable.

Further, the d-axis current command value Id ^* may be obtained by detecting a load current connected to the DC side, and is obtained by inputting a deviation between the DC voltage command value and Vdc1 + Vdc2 to an amplifier and configuring DC voltage constant control. As a result.

  Furthermore, in the first embodiment, the reactor L is inserted between the AC power supply 1 and the rectifier 2, but any filter for suppressing harmonics may be used, and an LC filter, an LCL filter, or the like can be applied.

DESCRIPTION OF SYMBOLS 1 ... AC power supply 2 ... Rectifier C1, C2 ... Capacitor T2, T3 ... Switching element (bidirectional switch)
L: Reactor Vdc1, Vdc2: Neutral point potential (voltage across capacitor)
Iinv ... Rectifier input voltage Vs ... Grid connection point voltage Vu ^* , Vv ^* , Vw ^* ... Output voltage command value Vu ^* ', Vv ^* ', Vw ^* '... Corrected output voltage command value

Claims (5)

A rectifier connected to an AC power source through a filter;
A plurality of capacitors connected in series between the output terminals of the rectifier, and
A switch having a withstand voltage in both directions interposed between the rectifier and the capacitor;
A controller that calculates an output voltage command value from a deviation between the rectifier input current and the current command value, and performs PWM control of the switch having a withstand voltage in both directions based on the output voltage command value; A device,
The controller is
A correction unit for correcting the output voltage command value is provided so as to reduce the deviation of the voltage across the capacitor.
The correction unit is
An AC / DC converter characterized by multiplying the output voltage command value by a gain of 1/2 Vdc1 if the output voltage command value is positive and 1/2 Vdc2 if the output voltage command value is negative . A rectifier connected to an AC power source through a filter;
A plurality of capacitors connected in series between the output terminals of the rectifier, and
A switch having a withstand voltage in both directions interposed between the rectifier and the capacitor;
A controller that calculates an output voltage command value from a deviation between the rectifier input current and the current command value, and performs PWM control of the switch having a withstand voltage in both directions based on the output voltage command value; A device,
The controller is
A correction unit for correcting the output voltage command value is provided so as to reduce the deviation of the voltage across the capacitor.
The correction unit is
An AC / DC converter characterized by multiplying the output voltage command value by a gain of 2Vdc2 if the output voltage command value is positive and 2Vdc1 if the output voltage command value is negative . The AC / DC converter according to claim 1 , wherein the correction unit detects an instantaneous value of a voltage between both ends of each capacitor and changes a gain according to pulsation. The controller is
A dq conversion unit that dq-converts the rectifier input current onto the rotation coordinates;
A subtractor for calculating a deviation between the d-axis and q-axis components of the rectifier input current and the d-axis current command value and the q-axis current command value;
A dq reverse conversion unit that dq reversely converts the output voltage command values of the d axis and q axis calculated based on the deviation onto fixed coordinates,
4. The AC / DC converter according to claim 1 , wherein a phase used for dq conversion and dq reverse conversion is delayed based on a magnitude of a d-axis current command value. 5. The controller is
A dq conversion unit that dq-converts the rectifier input current onto the rotation coordinates;
A subtractor for calculating a deviation between the d-axis and q-axis components of the rectifier input current and the d-axis current command value and the q-axis current command value;
A dq reverse conversion unit that dq reversely converts the output voltage command values of the d axis and q axis calculated based on the deviation onto fixed coordinates,
The AC / DC of any one of claims 1 to 3, wherein a value obtained by multiplying the d-axis current command value by a gain calculated based on the impedance of the reactor is a q-axis current command value. Conversion device.

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