JP2019054569A - Three-level power converter - Google Patents

Abstract

To improve the imbalanced state of a neutral point potential while suppressing the scale of a pulse pattern table in a three-level power converter that applies a fixed pulse pattern.SOLUTION: A corrected voltage command value V*' obtained by multiplying a voltage amplitude command value V* by a corrected DC voltage deviation ΔVdc', is inputted into a fixed pulse-pattern selection unit 12. In the fixed pulse-pattern selection unit 12, the corrected voltage command value V*' at a phase deviation θ'=0, π/2, π, or 3π/2 is denoted as a corrected voltage command value Vu*' of U-phase, the corrected voltage command value V*' at a phase deviation θ'=π/6, 2π/3, 7π/6, or 5π/3 is denoted as a corrected voltage command value Vv*' of V-phase, and the corrected voltage command value V*' at a phase deviation θ'=π/3, 5π/6, 4π/3, or 11π/6 is denoted as a corrected voltage command value Vw*' of W-phase. A gate command of the fixed pulse pattern is generated according to the corrected voltage command values Vu*' of U-phase, Vv*' of V-phase, or Vw*' of W-phase.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a three-level power converter, and more particularly to neutral point potential control when a fixed pulse pattern is applied.

  The fixed pulse pattern is one method for generating a gate command in a power converter such as an inverter. The fixed pulse pattern here is defined as outputting a constant pulse pattern with respect to the amplitude of a certain voltage command value.

  This method is a method of outputting a pulse (a gate command for turning on and off a switching device in the power converter) at a specific phase of the output voltage command value, and pulse patterning the phase voltage command of the three-level power converter Thus, harmonics can be reduced.

  The selection of the number of pulses and their phase can be arbitrarily designed by the designer according to the application example of the power converter. In order to further reduce the harmonics, it is necessary to increase the number of switching times of the switching device (that is, the number of times of switching the pulse pattern). In this specification, the three-level power converter shown in FIG. 7 will be described as a representative example. Details of the three-level power converter shown in FIG. 7 are disclosed in Non-Patent Document 1.

  FIG. 6 shows an output voltage waveform when a fixed pulse pattern is applied to the three-level power converter. This is the voltage at the output terminal Uo with respect to the NP terminal in the three-level power converter shown in FIG.

  VP1 and VN1 in FIG. 6 are DC voltage values applied to the first and second DC capacitors Cdc1 and Cdc2 of the three-level power converter, as shown in FIG. In FIG. 6, θ1 and θ2 are control phases of the fixed pulse pattern. These control phases θ1 and θ2 vary according to the amplitude of the voltage command value. Here, the number of pulses is four per cycle of the output frequency. Table 1 shows gate commands of the first to fourth switching devices S1 to S4 for generating the output voltage waveform of FIG.

Japanese Patent Application Laid-Open No. 07-079574 JP 2013-255317 A

Reza Fotohihi, Alexy Sorkin, Ralph Kennel, Hendrik du Toiton Mouton, “An Effective Method to CultivateCertainEverCandErCerCerCentErC, Ecto

  However, in the three-level power converter, the neutral point potential is in an unbalanced state due to disturbances such as the load and other conditions, variations in characteristics of the first to fourth switching devices S1 to S4 and the first and second DC capacitors Cdc1 and Cdc2. (That is, the DC voltage value VP1 and the DC voltage value VN1 in FIG. 7 may become unbalanced). Due to the unbalanced state of the neutral point potential, the voltage applied to the first to fourth switching devices S1 to S4 and the first and second DC capacitors Cdc1 and Cdc2 becomes excessive, and an abnormality occurs in the power converter. There is a fear.

Further, the fixed pulse pattern is vulnerable to disturbance because the control cycle depends on the fundamental wave, and unintended harmonics are superimposed on the output voltage when the neutral point potential is in an unbalanced state. Methods for solving this unbalanced state of neutral point potentials are disclosed in Patent Documents 1 and 2. In Patent Documents 1 and 2, even-order harmonics and DC components are added to the voltage command value. As an example, FIG. 8 shows a waveform in which the second harmonic is superimposed on the voltage command value. Here, each voltage command value is as follows.
Voltage command value 1: Voltage command value output from the current control unit.
Voltage command value 2: Voltage command value obtained by adding second harmonic to voltage command value 1.

  FIG. 9 is a control block described in Patent Document 2. The voltage command value 1 corresponds to the output of the dq inverse transform 36 in FIG. The voltage command value 2 corresponds to the output of the adder 20 in FIG.

  However, in general, the fixed pulse pattern is designed so that harmonics are suppressed as described above, and even-order harmonics and DC components are as zero as possible. If the techniques of Patent Documents 1 and 2 are applied to a three-level power converter having a fixed pulse pattern, a new pulse pattern needs to be redesigned to add even-order harmonics and DC components.

Furthermore, since it is necessary to be able to change the even-order harmonics to be added and the amplitude of the DC component to some extent, it is necessary to design the control phases θ1 and θ2 as follows.
・ Control phases θ1 and θ2 are designed so that the even harmonics become zero when the fundamental amplitude of the output voltage is in the range of zero to the rated value.
• Design θ1 and θ2 so that the even harmonics are within ± 1% of the rated voltage amplitude of the output voltage from zero to the rated range.
• Design θ1 and θ2 so that the even harmonics are within ± 2% of the rating when the fundamental amplitude of the output voltage is from zero to the rated range.
• Design θ1 and θ2 so that the even harmonics are within ± 4% of the rating when the fundamental amplitude of the output voltage is from zero to the rated range.

  As described above, it is necessary to design multiple fixed pulse patterns, which greatly increases the design effort and the size of the pulse pattern table, increasing the size and cost of the power converter control device equipped with the pulse pattern table. To do.

  Therefore, the three-level power converter as shown in FIG. 7 has a problem that it is very difficult to apply the fixed pulse pattern.

  As described above, in the three-level power converter to which the fixed pulse pattern is applied, it becomes an issue to improve the neutral point potential unbalanced state while suppressing the scale of the pulse pattern table.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is a three-phase three-level power converter having first and second DC capacitors common to each phase connected in series. A current control unit that outputs a voltage command value based on the phase and output current of the output voltage; a phase amplitude calculation unit that outputs a voltage amplitude command value and a voltage phase command value based on the voltage command value; A first multiplier for multiplying a DC voltage deviation between the DC voltage value of the two DC capacitors and the DC voltage value of the first DC capacitor by a gain; and a phase deviation θ ′ between the phase of the output voltage and the voltage phase command value Is 1 when π / 6 ≦ θ ′ <π / 2, 5π / 6 ≦ θ ′ <7π / 6, 3π / 2 ≦ θ ′ <11π / 6, and 0 ≦ θ ′ <π / 6, −1 is output when π / 2 ≦ θ ′ <5π / 6, 7π / 6 ≦ θ ′ <3π / 2, and 11π / 6 ≦ θ ′ <2π. A switch, a second multiplier that multiplies the output of the first multiplier and the output of the switch, an adder that adds 1 to the output of the second multiplier and outputs a corrected DC voltage deviation, and the voltage A third multiplier that multiplies the amplitude command value by the correction DC voltage deviation and outputs a correction voltage command value; and the correction voltage command when the phase deviation θ ′ = 0, π / 2, π, 3π / 2. The value is the U-phase correction voltage command value, and the correction voltage command value when the phase deviation θ ′ = π / 6, 2π / 3, 7π / 6, 5π / 3 is the V-phase correction voltage command value, The correction voltage command value when the phase deviation θ ′ = π / 3, 5π / 6, 4π / 3, and 11π / 6 is set as a W-phase correction voltage command value, and correction of the U-phase, V-phase, and W-phase is performed. A fixed pulse pattern selection unit that selects U-phase, V-phase, and W-phase fixed pulse patterns according to the voltage command value. The U-phase, V-phase, based on the fixed pulse pattern of W-phase, and generates a gate command for each switching device.

  Also, as one aspect thereof, the first to fourth switching devices of the respective phases sequentially connected in series between the positive electrode end of the first DC capacitor and the negative electrode end of the second DC capacitor; Two first switching devices and first and second diodes of each phase sequentially connected in series between the common connection point of two switching devices and the common connection point of the third and fourth switching devices. A common connection point of two diodes and a neutral point of the first and second DC capacitors are connected, and a common connection point of the second and third switching devices is used as an output terminal of each phase.

  As another aspect, the first and second switching devices of the respective phases sequentially connected in series between the positive electrode end of the first DC capacitor and the negative electrode end of the second DC capacitor; A third and a fourth switching device of each phase sequentially connected in series between a neutral point of a two DC capacitor and a common connection point of the first and second switching devices, the first and second A common connection point of the switching devices is used as an output terminal of each phase.

  Further, as one aspect thereof, a filter having a reactor is connected to the output terminal.

  In one aspect, the system is connected as a load.

  Moreover, as one aspect, a motor is connected as a load.

  According to the present invention, in a three-level power converter to which a fixed pulse pattern is applied, it is possible to improve the neutral point potential unbalanced state while suppressing the scale of the pulse pattern table.

The control block diagram of the 3 level power converter in embodiment. The block diagram which shows the fixed pulse pattern selection part of each phase in embodiment. The time chart which shows each waveform in embodiment. The time chart which shows the electric current waveform at the time of applying the output voltage and output voltage in an inductive load in embodiment. The circuit diagram which shows the structure of a T type 3 level inverter (for 1 phase). The time chart which shows the output voltage waveform at the time of the fixed pulse pattern application in a 3 level power converter. The circuit diagram which shows an example of the main circuit of a 3 level power converter. The time chart which shows the waveform which superimposed the 2nd harmonic on the voltage command value in the past. The figure which shows the control block of the 3 level power converter in patent document 2. FIG.

  Hereinafter, embodiments of the three-level power converter according to the present invention will be described in detail with reference to FIGS. 1 to 5 and 7.

[Embodiment]
In the present embodiment, neutral point potential control of a three-level power converter having a neutral point as shown in FIG. 7 is performed using a pulse pattern table with a small scale. First, the three-level power converter shown in FIG. 7 will be described.

  A first DC capacitor Cdc1 and a second DC capacitor Cdc2 are connected in series. A common connection point of the first and second DC capacitors Cdc1 and Cdc2 is a neutral point NP, and a current passing through the neutral point NP is a neutral point current INP. The DC voltage value of the first DC capacitor Cdc1 is VP1, and the DC voltage value of the second DC capacitor Cdc2 is VN1.

  The first to fourth switching devices S1 to S4 of each phase (U phase, V phase, W phase) are sequentially connected in series between the positive end of the first DC capacitor Cdc1 and the negative end of the second DC capacitor Cdc2. .

  Between the common connection point of the first and second switching devices S1 and S2 and the common connection point of the third and fourth switching devices S3 and S4, the first and second diodes D1 and D2 of each phase are sequentially connected in series. Connected.

  The common connection point of the first and second diodes D1 and D2 is connected to the neutral point NP of the first and second DC capacitors Cdc1 and Cdc2. Common connection points of the second and third switching devices S2 and S3 are output terminals Uo, Vo, and Wo of the respective phases.

  FIG. 1 shows a control block of the three-level power converter in this embodiment. First, the current control unit 7 calculates the voltage command values Vd * and Vq * based on the three-phase current detection value Iinv and the output voltage phase θ. Based on the phase θ, the dq converter 1 converts the three-phase current detection value Iinv into a d-axis current detection value Id and a q-axis current detection value Iq on the two-phase rotation coordinates. The subtracters 2a and 2b calculate a deviation between the d-axis current command value Id * and the q-axis current command value Iq * and the dq-converted d-axis current detection value Id and q-axis current detection value Iq. The PI controller PI amplifies the deviation by proportional control and integral control, and obtains voltage command values Vd * and Vq * on two-phase rotation coordinates.

  The phase amplitude calculator 3 obtains the voltage amplitude command value V * and the voltage phase command value φ * from the voltage command values Vd * and Vq * on the two-phase rotation coordinates by the following equation (1).

  The subtractor 4 obtains a phase deviation θ ′ = θ−φ * between the phase θ and the voltage phase command value φ *. The subtracter 5 subtracts the DC voltage value VP1 from the DC voltage value VN1 to calculate a DC voltage deviation ΔVdc.

  The corrected DC voltage deviation calculator 6 increases or decreases the DC voltage deviation ΔVdc in accordance with the magnitude of the DC voltage deviation ΔVdc and the phase deviation θ ′. The calculated result is defined as a corrected DC voltage deviation ΔVdc ′.

  In the corrected DC voltage deviation calculation unit 6, the multiplier 8 multiplies the DC voltage deviation ΔVdc by a multiplication gain G (G> 0) that can be arbitrarily set. The switch SW1 outputs 1 when the phase deviation θ ′ is π / 6 ≦ θ ′ <π / 2, 5π / 6 ≦ θ ′ <7π / 6, 3π / 2 ≦ θ ′ <11π / 6, and 0 ≦ When θ ′ <π / 6, π / 2 ≦ θ ′ <5π / 6, 7π / 6 ≦ θ ′ <3π / 2, 11π / 6 ≦ θ ′ <2π, −1 is output.

  Multiplier 9 multiplies the output of switch SW1 by the output GΔVdc of multiplier 8. The adder 10 adds 1 to the output of the multiplier 9. The output of the adder 10 becomes the corrected DC voltage deviation ΔVdc ′.

  The multiplier 11 multiplies the voltage amplitude command value V * output from the phase amplitude calculator 3 by the corrected DC voltage deviation ΔVdc ′ output from the corrected DC voltage deviation calculator 6 to obtain the corrected voltage command value V * ′. Output.

  The fixed pulse pattern selection unit 12 selects a U-phase fixed pulse pattern with phase deviations θ ′ = 0, π / 2, π, 3π / 2, and phase deviations θ ′ = π / 6, 2π / 3, 7π / The V-phase fixed pulse pattern is selected at 6,5π / 3, and the W-phase fixed pulse pattern is selected at phase deviation θ ′ = π / 3, 5π / 6, 4π / 3, 11π / 6.

  The timing of these phase deviations θ ′ latches the correction voltage command value V * ′ = V * × ΔVdc ′ and corrects the U-phase, V-phase, and W-phase correction voltage command values Vu * ′ and Vv * ′ described later. , Vw * ′ is generated.

  FIG. 2A shows the U-phase fixed pulse pattern selection unit 12. The U-phase fixed pulse pattern selection unit 12 inputs the correction voltage command value V * ′ and the phase deviation θ ′. The four comparators 13a to 13d output 1 when the phase deviation θ ′ is equal to 0, π / 2, π, and 3π / 2, respectively. The logical sum unit 14 receives the outputs of the four comparators 13a to 13d, and outputs 1 when any one is 1.

  The hold device hold holds the correction voltage command value V * ′ at the timing when the output of the logical sum unit 14 becomes 1 (the phase deviation θ ′ is equal to 0, π / 2, π, or 3π / 2). And output as a U-phase correction voltage command value Vu * ′.

  The pulse pattern table 15 inputs the U-phase correction voltage command value Vu * ′ and the phase deviation θ ′, and outputs a gate command at the phase deviation θ ′ corresponding to the amplitude (U-phase correction voltage command value) Vu * ′. To do. The output of the pulse pattern table 15 is a gate command for the U-phase switching device.

  FIG. 2B shows the V-phase fixed pulse pattern selection unit 12. The V-phase fixed pulse pattern selection unit 12 is different from the U-phase in that the subtracter 16 subtracts 2π / 3 from the phase deviation θ ′ and inputs it to the comparators 13 a to 13 d and the pulse pattern table 15.

  The timing at which the corrected voltage command value V * ′ is held is the phase deviation θ′−2π / 3 = 0, π / 2, π, 3π / 2. That is, the correction voltage command value V * ′ is held at the phase deviation θ ′ = π / 6, 2π / 3, 7π / 6, 5π / 3, and is output as the V-phase correction voltage command value Vv * ′. The gate command output from the V-phase pulse pattern table 15 is delayed by 2π / 3 in phase as compared to the U-phase.

  FIG. 2C shows the W-phase fixed pulse pattern selection unit 12. The W-phase fixed pulse pattern selection unit 12 is different from the U-phase in that the adder 17 adds 2π / 3 to the phase deviation θ ′ and inputs it to the comparators 13 a to 13 d and the pulse pattern table 15.

  The timing at which the corrected voltage command value V * ′ is held is the phase deviation θ ′ + 2π / 3 = 0, π / 2, π, 3π / 2. That is, the correction voltage command value V * ′ is held at the phase deviation θ ′ = π / 3, 5π / 6, 4π / 3, 11π / 6, and is output as the W-phase correction voltage command value Vw * ′. The gate command output from the W-phase pulse pattern table 15 advances in phase by 2π / 3 as compared with that in the U-phase.

  Neutral point potential control is performed by using only a single fixed pulse pattern that suppresses output voltage distortion as much as possible, superimposing the second harmonic on the output voltage, and flowing a small amount of second harmonic current.

  In the present embodiment, the corrected DC voltage deviation ΔVdc ′ obtained by the corrected DC voltage deviation calculation unit 6 is converted into the voltage amplitude command value V * for each ¼ period of the voltage command value for each of the U phase, the V phase, and the W phase. To generate a corrected voltage command value V * ′ including the second harmonic component.

  For example, consider the voltage amplitude command value V * and the voltage phase command value φ * (plus the delay) as shown in FIG. Further, it is assumed that the DC voltage value VP1> VN1 and the DC voltage deviation ΔVdc is negative.

  As shown in FIG. 3, the corrected DC voltage deviation ΔVdc ′ is generated by the switch SW1 at a timing (phase) of phase deviation θ ′ = π / 6, π / 2, 5π / 6, 7π / 6, 3π / 2, 11π / 6. θ = π / 6 + φ *, π / 2 + φ *, 5π / 6 + φ *, 7π / 6 + φ *, 3π / 2 + φ *, 11π / 6 + φ *.

  For the U phase, in the fixed pulse pattern selection unit 12, the timing of phase deviation θ ′ = 0, π / 2, π, 3π / 2 (phase θ = φ *, π / 2 + φ *, π + φ *, 3π / The correction voltage command value V * ′ = V * × ΔVdc ′ is input at the timing of (2 + φ *), and the value at that time is latched. The latched value is set as a U-phase correction voltage command value Vu * ′. Then, a fixed pulse pattern corresponding to the U-phase correction voltage command value Vu * ′ is selected and output as a gate command for the U-phase switching device.

  The pulse waveform of Vu shown in FIG. 3 shows the waveform of the output voltage of the U phase that is actually output, and the sine waveform of Vu in FIG. 3 switches from the waveform of the output voltage of the U phase that is actually output. It is a waveform from which frequency components have been removed. The amplitude of the sinusoidal waveform of the U-phase output voltage Vu corresponds to the value of the aforementioned U-phase correction voltage command value Vu * ′.

  For the V-phase and W-phase output voltages Vv and Vw, the same waveform as that of the U-phase output voltage Vu is obtained as shown in FIG. 3 just by shifting the timing processed by the fixed pulse pattern selector 12 by 2π / 3. It is done. The V-phase correction voltage command value Vv * ′ latches the correction voltage command value V * ′ = V * × ΔVdc ′ at the timing of phase deviation θ ′ = π / 6, 2π / 3, 7π / 6, 5π / 3. It is obtained by doing.

  W-phase correction voltage command value Vw * ′ latches correction voltage command value V * ′ = V * × ΔVdc ′ at the timing of phase deviation θ ′ = π / 3, 5π / 6, 4π / 3, 11π / 6. It is obtained by doing.

  FIG. 4 shows a current waveform when the U-phase output voltage Vu is applied to the inductive load. In order to simplify the explanation, this waveform is modeled on a main circuit whose output is composed only of the U phase. FIG. 4 shows the U-phase output voltage Vu, the U-phase output current IinvU, the fundamental wave IinvU1 included in the U-phase output current IinvU, the second harmonic IinvU2, and the fourth harmonic IinvU4. Yes.

The reason why the load is inductive is shown below.
・ The output end of the power converter is often connected with a filter reactor to prevent harmonics and noise outflow.
・ In the case of a general grid-connected inverter, since the impedance at the connection destination is small and the parasitic impedance is centered on the inductance component, the load can be regarded as a reactor.
・ In the case of a general motor drive inverter, the load (motor) can be replaced with a reactor and a resistor.

  The U-phase output current IinvU is substantially proportional to the integration result of the U-phase output voltage Vu, and is near zero of the U-phase output voltage Vu (phase deviation θ ′ = π / 2 and θ ′ = 3π / 2). , The positive amplitude (i1) decreases and the negative amplitude (i2) increases. If the U-phase output voltage Vu is close to zero (when θ ′ = π / 2 and θ = 3π / 2), the switching devices (in FIG. The ratio of the period during which the switching devices S2, S3) are ON is the largest, and almost all of the U-phase output current IinvU passes through the neutral point NP.

  At the phase deviation θ ′ = π / 2, since the output current Iinv1 is positive, the current flows out from the neutral point NP (the neutral point current INP flows in the direction of the arrow in FIG. 7), and the first DC capacitor Cdc1 is charged, 2 DC capacitor Cdc2 is discharged.

  When the phase deviation θ ′ = 3π / 2, since the U-phase output current IinvU is negative, the current flows into the neutral point NP (the neutral point current INP flows in the direction opposite to the arrow in FIG. 7), and the first DC capacitor Cdc1 is discharged, and the second DC capacitor Cdc2 is charged. Since the absolute value of the amplitude of the U-phase output current IinvU is larger at the value (i2) at θ ′ = 3π / 2 than at the value (i1) at the phase deviation θ ′ = π / 2, θ ′ = 3π / 2. The DC voltage fluctuation amount due to the first DC capacitor Cdc1 discharge and the second DC capacitor Cdc2 charge at is higher than the DC voltage fluctuation due to the first DC capacitor Cdc1 charge and the second DC capacitor Cdc2 discharge at θ ′ = π / 2.

  Therefore, in one cycle (θ = 0 to 2π) in FIG. 4, the DC voltage value VP1 can be decreased and the DC voltage value VN1 can be increased, and the neutral point potential unbalanced state (VP1> VN1) is improved. be able to. FIG. 4 shows the waveform of the model with only the U phase output, but this effect can be obtained even with the main circuit configuration of the three phase output shown in FIG.

  Hereinafter, the fundamental wave IinvU1 and the harmonic current included in the U-phase output current IinvU shown in FIG. 4 will be described.

  Here, the correction voltage command value V * ′ is expressed by the following equation (2).

  The first term of equation (2) represents the fundamental wave component, and the second term represents the distortion component. As shown in the following equation (3), the distortion component is expanded in the Fourier series.

The positive current peak of the U-phase output current IinvU is i1, and the negative current peak is -i2. The DC component of the U-phase output current IinvU is zero. The sixth and subsequent waveforms are omitted. The following can be seen from FIG.
The fundamental wave IinvU1 is positive when the phase deviation θ ′ = π / 2, and negative when the phase deviation θ ′ = 3π / 2. However, the absolute value of the fundamental wave IinvU1 at the phase deviation θ ′ = π / 2 and the absolute value of the fundamental wave IinvU1 at the phase deviation θ ′ = 3π / 2 are both equal to V1 / ωL.
The second harmonic IinvU2 becomes negative when the phase deviation θ ′ = π / 2 and the phase deviation θ ′ = 3π / 2. However, the value of the second harmonic IinvU2 at the phase deviation θ ′ = π / 2 and the value of the second harmonic IinvU2 at the phase deviation θ ′ = 3π / 2 are both equal to −4d / 3πωL.
The fourth harmonic IinvU4 is positive when the phase deviation θ ′ = π / 2 and the phase deviation θ ′ = 3π / 2. However, the value of the fourth harmonic IinvU4 at the phase deviation θ ′ = π / 2 and the value of the fourth harmonic IiuvU4 at the phase deviation θ ′ = 3π / 2 are both equal to 4d / 15πωL.

  The sixth and subsequent orders also take positive and negative values in the phase deviation θ ′ = π / 2 and the phase deviation θ ′ = 3π / 2, but the distortion component has the largest second-order coefficient (4d / 3πωL). The distortion component (harmonic current) has a great influence on the output current. Therefore, i1−i2≈−2 × 4d / 3πωL, that is, i1 <i2, and the neutral point current INP is negative in one cycle.

  In FIG. 4, the absolute value of the DC voltage deviation ΔVdc = VN1−VP1 increases at the phase θ = π. However, in the phase θ = 2π (the right end in FIG. 4), the absolute value of the DC voltage deviation ΔVdc = VN1−VP1 is reduced as compared to the phase θ = 0 (the left end in FIG. 4).

  By repeating this control for several cycles, the DC voltage value VN1 of the lower arm increases and the DC voltage value VP1 of the upper arm decreases every cycle, so that the DC voltage deviation ΔVdc = VN1−VP1 contracts to zero. As a result, the unbalanced state of the neutral point potential is improved.

  The present embodiment can be applied to configurations other than the configuration of FIG. 7 as long as it is a three-level power converter having a neutral point. As another example, FIG. 5 shows a circuit diagram of a T-type three-level inverter (for one phase). Hereinafter, the T-type three-level inverter shown in FIG. 5 will be described.

  A first DC capacitor Cdc1 and a second DC capacitor Cdc2 are connected in series. A common connection point of the first DC capacitor Cdc1 and the second DC capacitor Cdc2 is defined as a neutral point NP. The first and second switching devices S1, S2 of each phase are sequentially connected in series between the positive terminal of the first DC capacitor Cdc1 and the negative terminal of the second DC capacitor Cdc2.

  The third and fourth switching devices S3 and S4 of each phase are sequentially connected in series between the neutral point NP and the common connection point of the first and second switching devices S1 and S2. A common connection point of the first and second switching devices S1 and S2 is an output terminal.

  As described above, according to the present embodiment, in the three-level power converter to which the fixed pulse pattern method is applied, the neutral point potential is reduced using the second harmonic current while suppressing the scale of the pulse pattern table. Unbalanced state can be improved.

  In addition, since a fixed pulse pattern is used, a three-level power converter with reduced harmonic voltage and current can be realized as compared with a gate command generation method based on a comparison between a voltage command value and a carrier triangular wave.

  Furthermore, since the scale of the pulse pattern table can be suppressed, the cost and size of the control device for the three-level power converter can be reduced.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

DESCRIPTION OF SYMBOLS 1 ... dq conversion part 2a, 2b ... Subtractor 3 ... Phase amplitude calculator 4 ... Subtractor 5 ... Subtractor 6 ... Correction DC voltage deviation calculating part 7 ... Current control part 8 ... 1st multiplier 9 ... 2nd multiplier DESCRIPTION OF SYMBOLS 10 ... Adder 11 ... 3rd multiplier 12 ... Fixed pulse pattern selection part 13a-13d ... Comparator 14 ... Logical sum part 15 ... Pulse pattern table 16 ... Subtractor 17 ... Adder SW ... Switch hold ... Hold device Cdc1, Cdc2: first and second DC capacitors

Claims (6)

A three-phase three-level power converter having first and second DC capacitors common to each phase connected in series,
A current control unit that outputs a voltage command value based on the phase of the output voltage and the output current;
Based on the voltage command value, a phase amplitude calculation unit that outputs a voltage amplitude command value and a voltage phase command value;
A first multiplier for multiplying a DC voltage deviation between a DC voltage value of the second DC capacitor and a DC voltage value of the first DC capacitor by a gain;
The phase deviation θ ′ between the phase of the output voltage and the voltage phase command value is π / 6 ≦ θ ′ <π / 2, 5π / 6 ≦ θ ′ <7π / 6, 3π / 2 ≦ θ ′ <11π / 1 is output when 6 and 0 ≦ θ ′ <π / 6, π / 2 ≦ θ ′ <5π / 6, 7π / 6 ≦ θ ′ <3π / 2, 11π / 6 ≦ θ ′ <2π− A switch that outputs 1,
A second multiplier for multiplying the output of the first multiplier and the output of the switch;
An adder that adds 1 to the output of the second multiplier and outputs a corrected DC voltage deviation;
A third multiplier for multiplying the voltage amplitude command value by the corrected DC voltage deviation and outputting a corrected voltage command value;
The correction voltage command value when the phase deviation θ ′ = 0, π / 2, π, 3π / 2 is set as a U-phase correction voltage command value, and the phase deviation θ ′ = π / 6, 2π / 3, 7π. The correction voltage command value at / 6, 5π / 3 is set as a V-phase correction voltage command value, and the correction at the phase deviation θ ′ = π / 3, 5π / 6, 4π / 3, 11π / 6. A fixed pulse pattern selection unit that uses a voltage command value as a W-phase correction voltage command value and selects U-phase, V-phase, and W-phase fixed pulse patterns according to the U-phase, V-phase, and W-phase correction voltage command values. When,
And a gate command for each switching device is generated based on the selected U-phase, V-phase, and W-phase fixed pulse patterns. First to fourth switching devices of respective phases sequentially connected in series between a positive electrode end of the first DC capacitor and a negative electrode end of the second DC capacitor;
First and second diodes of respective phases sequentially connected in series between the common connection point of the first and second switching devices and the common connection point of the third and fourth switching devices;
A common connection point of the first and second diodes and a neutral point of the first and second DC capacitors, and a common connection point of the second and third switching devices as an output terminal of each phase The three-level power converter according to claim 1, wherein First and second switching devices of respective phases sequentially connected in series between a positive electrode end of the first DC capacitor and a negative electrode end of the second DC capacitor;
Third and fourth switching devices of respective phases sequentially connected in series between a neutral point of the first and second DC capacitors and a common connection point of the first and second switching devices;
The three-level power converter according to claim 1, wherein a common connection point of the first and second switching devices is used as an output terminal of each phase.   The three-level power converter according to any one of claims 1 to 3, wherein a filter having a reactor is connected to the output terminal.   The three-level power converter according to any one of claims 1 to 4, wherein a system is connected as a load.   The three-level power converter according to any one of claims 1 to 4, wherein a motor is connected as a load.

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