JP3989397B2 - Integrated circuit device and data setting device for the device - Google Patents

Description

図３は上記プログラムに対応するデータフローグラフを示す。図中、定数、変数および演算子は丸で囲まれ、ｍｕｌは乗算、ａｄｄは加算を示す。これをそのままリコンフィギュラブル回路１２へマッピングすると、図４の状態になる。以上が実施の形態の基礎である。
【００３２】
以下、ふたつ以上の機能回路をロードする方法を述べる。いま、図５のごとく、２行４列のアレイに含まれるＡＬＵを（ｉ，ｊ）で座標表示する。ただし、ｉ＝１，２、ｊ＝１，２，３，４である。図６、図７はそれぞれ、図４の設定を座標表示したところである。ここでは、例えばふたつのｍｕｌとひとつのａｄｄがそれぞれ（１，１）（１，２）（２，１）に設定され、（１，１）と（１，２）の出力がともに（２，１）の入力へ接続されている。
【００３３】
監視部２３は、すでに命令が設定されている、すなわち使用済みのＡＬＵを調べ、その結果を自己の内部メモリ（図示せず）に記録する。図８はそのための処理を示す。ここで、アレイはＺ行Ｗ列とし、内部変数ｉ，ｊをそれぞれ行、列のカウンタとして使用する。同図のごとく、まずカウンタｉ，ｊに初期値「１」がセットされ（Ｓ１０）、ｉとＺが比較され（Ｓ１２）、ｉがＺ以下なら（Ｓ１２のＹ）調査すべき行がまだ残っているので、Ｓ１４へ進む。Ｓ１４では、ｊとＷが比較され、ｊがＷ以下なら（Ｓ１４のＹ）まだ列が残っているため、Ｓ１６へ進む。
【００３４】
Ｓ１６では、（ｉ，ｊ）のＡＬＵが未設定であるか、すなわち空いているか調べ、空いていれば（Ｓ１６のＹ）「ｉ行の空き数がＷ−ｊ＋１、使用数がｊ−１」を出力し（Ｓ２２）、ｉをインクリメントおよびｊを「１」に戻し（Ｓ２４）、次の行を調査すべくＳ１２へ戻る。Ｓ１６で（ｉ，ｊ）のＡＬＵが使用済みであればＳ１８へ進み、ｊをインクリメントしてＳ１４へ戻る。
【００３５】
Ｓ１４においてｊがすでにＷの値を超えていれば（Ｓ１４のＮ）、その行には空きがなかったため、「ｉ行の空き数がゼロ、使用数がＷ」を出力し（Ｓ２０）、Ｓ２４へ進む。
【００３６】
Ｓ１２においてｉがすでにＺを超えていれば（Ｓ１２のＮ）、すべての行の調査が終わっているので処理を終了する。以上の処理により、監視部２３は各行の空き数を記録できる。空き数がわかるため、監視部２３は結果的にいずれのｉ，ｊについても（ｉ，ｊ）のＡＬＵが空いているか使用済みかを知ることができる。
【００３７】
このアレイに、第２のプログラム、すなわち第２の機能回路を設定する。このプログラムは以下のとおりである。

図９はこのプログラムのデータフローグラフ、図１０は仮にこのプログラムのみをアレイにロードした場合の設定を座標表示で示す。しかし、すでに最初のプログラムがロードされているので、第２のプログラムのロードに当たり、空いているＡＬＵへ命令を設定していく。
【００３８】
図１１は制御部１８が第２のプログラムのロードが可能かどうかを判定する処理を示す。ここでＮは第２のプログラムの設定に必要な行数である。まず、カウンタｉを「１」とし（Ｓ３０）、ｉとＮを比較する（Ｓ３２）。ｉがＮ以下であれば設定は完了していないため、Ｓ３４へ進み、ｉ行目の空いているＡＬＵに第２のプログラムの実現に必要な命令をすべて収容できるか否かを判定する。これは、ＡＬＵの空き数をもとに判断される。収容可能であれば（Ｓ３４のＹ）設定データ１７に反映してｉをインクリメントし（Ｓ３６）、その行で新たに設定したＡＬＵの個数だけ空き数を減らし（Ｓ３８）、Ｓ３２へ戻る。
【００３９】
Ｓ３４において、ｉ行目への命令の収容が不可能だったとき、すなわち、収容すべき命令の数が空き数を上回ったとき（Ｓ３４のＮ）、エラー処理（Ｓ４０）を実行して処理を終える。エラー処理（Ｓ４０）として、このアレイ以外のアレイへの第２のプログラムのロードがある。別の処理として、後述の図１４の処理がある。一方、Ｓ３２において、ｉの値がすでにＮを超えていれば、全命令の設定が完了したことになるので、同じく処理を終える。
【００４０】
図１２、図１３は、第２のプログラムが設定された状態を各命令とＡＬＵの座標表示の関係で示している。ｓｕｂは（１，３）のごとく、空いていたＡＬＵを利用している。図１３は、第１、第２のプログラムを実装した状態のアレイの様子を示す。
【００４１】
図１４は、前述のエラー処理の一例を示す。最初に処理の概要を述べ、後に実例を挙げる。
図１４のごとく、まずカウンタｉ、ｊ、ｋに「１」をセットする（Ｓ５０）。ここでｋは、新たにロードすべきプログラムを構成する第ｋ番目の命令とし、そのプログラムには全部Ｌ個の命令があるとする。
【００４２】
制御部１８は、ｋがＬ以下（Ｓ５２）で、ｉがＺ以下（Ｓ５４）で、ｊがＷ以下（Ｓ５６）のとき、（ｉ，ｊ）のＡＬＵが空いているかどうか調べる（Ｓ５８）。空いていれば第ｋの命令がそのＡＬＵに設定可能かどうか検査する（Ｓ６０）。後述のごとく、ＡＬＵが空いていても、この命令に必要な入力ノード数と出力ノード数によっては、このＡＬＵが使用できないことがある。検査の結果使用できるとわかれば（Ｓ６０のＹ）、設定データ１７に反映し、ｋをインクリメントし（Ｓ６２）、ｊをインクリメントし（Ｓ６４）、Ｓ５２へ戻る。Ｓ６０でＡＬＵが第ｋ命令のために使用できないとわかれば（Ｓ６０のＮ）、Ｓ６２をスキップしてＳ６４へ進む。Ｓ５８で（ｉ，ｊ）が空いていないことがわかれば、Ｓ６０とＳ６２をスキップしてＳ６４へ進む。
【００４３】
Ｓ５６でｊがすでにＷを超えていれば、その行の検査は終わっているため（Ｓ５６のＮ）、次の行を検査すべくｊを「１」に戻し、ｉをインクリメントし（Ｓ６６）、Ｓ５４へ戻る。
【００４４】
Ｓ５４でｉがすでにＺを超えていれば、このプログラムの設定が完了せずに終わったため、エラー処理（Ｓ６８）を実行して処理を終える。一方、Ｓ５２でｋがすでにＬを超えていれば、このプログラムの設定が完了したため、正常に処理を終える。Ｓ６８のエラー処理として、このプログラムを別のアレイへロードする等がある。以上が処理の大筋である。
【００４５】
図１５以下、図１１および図１４の処理を総括して実例で示す。ここでは、複数のプログラムに対応する第１データフローグラフ、第２データフローグラフ、・・・を設定する場合、アレイの空き領域に合わせて適宜データフローグラフを変形することにある。データフローグラフの設定は以下の手順に従う。
【００４６】
（１） 第１データフローグラフを設定する。
（２） 第１データフローグラフの設定情報から未設定のＡＬＵに関する情報を取得し、その未設定のＡＬＵに第２データフローグラフが設定できれば、そのまま設定する（図１１の場合）。
（３） 未設定のＡＬＵに第２データフローグラフが収まらない場合、第２データフローグラフを変形し、設定する（図１４の場合）。
（４） どのように変形しても第２データフローグラフが収まらない場合、残りのデータフローグラフに対して設定処理を行う（図１４のエラー処理）。
（５） 最終的に設定できなかったデータフローグラフは、別のＡＬＵアレイに設定を行う（同エラー処理）。
【００４７】
図１５、図１６、図１７は、設定すべき３つのデータフローグラフを模式的に示す。但し、番号はノードの番号を表し、各ノードには所定の論理演算が割り当てられている。また、アレイは８×８とする。
【００４８】
まず、アレイは初期状態では未設定の状態なので、第１データフローグラフはそのまま設定できる。図１８はその状態を示す。図１９はこの時点でのＡＬＵの空き状態を示す。
【００４９】
つぎに、第２データフローグラフを設定する。図１９の空き状態と図１６の必要なＡＬＵ数から、第２データフローグラフもそのまま設定できることが分かる。図２０は、アレイに第２データフローグラフを設定しおえた状態を示す。また、図２１はこの時点でのＡＬＵの空き状態を示す。
【００５０】
最後に、第３データフローグラフを設定する。図１７から判明する必要なＡＬＵ数と図１９から判明する空き状態を比較すると、第３データフローグラフはそのままの接続状態ではアレイに設定できないことがわかる。第３データフローグラフの接続状態を変更することにより、設定が可能になるか検査する。アレイにノードを設定する規則は以下の通りである。
【００５１】
（１） できるだけ上の行（ｉが小さい行）に設定する。
（２） できるだけ左寄りの列（ｊが小さい列）に設定する。
（３） 空いているＡＬＵが不足するなどの問題があり、データフローグラフを変形するとき、適宜スルーノードを追加する。
【００５２】
図１９に示す未使用のＡＬＵの位置を分かりやすくするため、既述の座標表示を使う。最上行から検査すると、（８，１）に設定できるのは、入力ノード数０で出力ノード数１のノードのみである。図２２は第３データフローグラフを構成する各ノードの入力ノード数と出力ノード数を示す。図２２から、ノード２４を（８，１）に設定する。図２３はこの時点での設定状態を上３行について示す。
【００５３】
次に、設定したノード２４の出力ノードを調べる。ノード２４は出力ノードとしてノード２８を持つが、ノード２８は入力ノード数２であるため、（８，２）には設定できない。従って、更に下行に設定する。ここでは左寄せにするので、ノード２８を仮に（６，３）に設定する。しかし、その場合でもノード２８の２つの入力ノードの設定できないため、更に下行であって左寄せを満たす（４，４）に設定する。ノード２４とノード２８は接続されているので、（６，３）、（８，２）にスルーノード（図中「Ｎ」）を設定することにより接続する。図２４はこの時点での設定状態を示す。
【００５４】
つづいて、ノード２８の入力ノードであるノード２５を設定する。ノード２５はノード２８の上行に設定すればよいので、（７，３）へ設定する。以上でノード２８の入力ノードの設定が終了する。図２５はこの時点での設定状態を示す。
【００５５】
次に、ノード２８の出力ノードはノード３１のみである。既述同様、ノード３１を設定し、ノード３１の入力ノードのうち未設定のノード２９を（５，４）に設定する。更にノード２９の入力ノードのうち未設定のノード２６を（８，４）に設定する。図２６はこの時点での設定状態を示す。
【００５６】
つづいて、ノード３１の出力のノード３３を設定する。ノード３３は入力ノード数が２であるので（１，６）に設定を行い、その入力ノードの設定を前述同様に設定する。しかし、ノード３０の入力ノードのノード２７に対して設定可能なＡＬＵがないため、設定は失敗となる。よって、ノード３３以降の設定をクリアする。図２７はクリア前の設定状態を示す。
【００５７】
ノード２７を設定するために（１，６）にスルーノードを挿入し、ノード３３の設定位置を１行下げてスペースを作る。ノード３３は（１，７）へ設定する。以上の手順で、図２８のごとく、第３データフローグラフの設定が完了する。
【００５８】
以上、本発明を実施の形態をもとに説明した。実施の形態は例示であり、それらの各構成要素や各処理プロセスの組み合わせにいろいろな変形例が可能なこと、またそうした変形例も本発明の範囲にあることは当業者に理解されるところである。以下、そうした例を挙げる。
【００５９】
図１のデータ設定装置２４その他にタイマー（図示せず）を設け、制御部１８がタイマー出力に応じてリコンフィギュラブル回路１２にロードする機能を切り替えてもよい。その場合、複数の機能を順次切り替えて実現することができる。この方法は、集積回路装置１０にいろいろな機能を時分割で行わせる場合、有効である。
【００６０】
実施の形態の集積回路装置１０は、例えばソフトウエア無線機に応用できる。その場合、リコンフィギュラブル回路１２には、適宜ＦＭラジオ、カーナビゲーション機能、テレビジョン受像機能、音声通話機能などをロードすればよい。
【００６１】
【発明の効果】
本発明のデータ設定装置によれば、集積回路装置の利用効率を改善することができる。また、同じ機能を実現する際、回路規模、消費電力を削減することができる。
【図面の簡単な説明】
【図１】 実施の形態に係る集積回路装置およびデータ設定装置の構成図である。
【図２】 図１のリコンフィギュラブル回路の中のＡＬＵアレイ部分の構成図である。
【図３】 あるプログラムの処理を表したデータフローグラフを示す図である。
【図４】 図３のデータフローグラフに対応してマッピングされたＡＬＵアレイの構成図である。
【図５】 ２×４のＡＬＵアレイを座標表示して示す図である。
【図６】 命令セットとＡＬＵの対応関係を示す図である。
【図７】 命令セットとＡＬＵの対応関係を示す図である。
【図８】 監視部がＡＬＵの空き状態を検査する手順を示すフローチャートである。
【図９】 ＡＬＵアレイにロードすべき第２のプログラムのデータフローグラフを示す図である。
【図１０】 第１のプログラムを考慮しない場合、第２のプログラムの命令セットとＡＬＵの対応関係を示す図である。
【図１１】 第２のプログラムが、あるＡＬＵアレイにロード可能かどうかを判定する手順を示すフローチャートである。
【図１２】 第１のプログラムを考慮した場合、第２のプログラムの命令セットとＡＬＵの対応関係を示す図である。
【図１３】 第１および第２のプログラムがＡＬＵアレイにロードされた状態を示す図である。
【図１４】 第２以下のプログラムをＡＬＵアレイにロードする際、ロード可能か否かを判定する手順を示し、とくに図１１のエラー処理の一例を示すフローチャートである。
【図１５】 第１データフローグラフで使用すべきＡＬＵを番号をつけて示す図である。
【図１６】 第２データフローグラフで使用すべきＡＬＵを番号をつけて示す図である。
【図１７】 第３データフローグラフで使用すべきＡＬＵを番号をつけて示す図である。
【図１８】 第１データフローグラフを８×８のＡＬＵアレイにロードした状態を示す図である。
【図１９】 図１８の時点でのＡＬＵの使用状態を示す図である。
【図２０】 第２データフローグラフを８×８のＡＬＵアレイにロードした状態を示す図である。
【図２１】 図２０の時点でのＡＬＵの使用状態を示す図である。
【図２２】 第３データフローグラフに必要なＡＬＵの入力および出力ノード数を示す図である。
【図２３】 第３データフローグラフのノード「２４」を設定した状態を示す図である。
【図２４】 第３データフローグラフのノード「２８」を設定した状態を示す図である。
【図２５】 第３データフローグラフのノード「２５」を設定した状態を示す図である。
【図２６】 第３データフローグラフのノード「２６」「２９」「３１」を設定した状態を示す図である。
【図２７】 第３データフローグラフのノード「２７」が設定できず、設定が一時的に失敗して状態を示す図である。
【図２８】 図２８の失敗を解消して第３データフローグラフの設定が完了した状態を示す図である。
【符号の説明】
１０ 集積回路装置、 １２ リコンフィギュラブル回路、 １２ａ ＡＬＵアレイ、 １４ 設定部、 １８ 制御部、 ２０ コンパイル部、 ２１ データフローグラフ、 ２３ 監視部、 ２４ データ設定装置。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data generation device that generates setting data for loading an intended function to an integrated circuit such as a reconfigurable circuit .
[0002]
[Prior art]
Recently, wireless communications such as mobile phones, GPS, and VICS have become widespread, and the types of wireless devices are increasing. If these radios or their functions are all implemented by hardware, the cost and mounting area increase. Therefore, there is a concept of “software radio” that implements various functions by installing a circuit having general-purpose capability as hardware and switching software loaded thereon.
[0003]
Circuits that implement a software defined radio include an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). Patent Document 1 proposes a method of reusing a circuit configuration by dynamically reconfiguring an FPGA. The type of circuit that can be dynamically changed is hereinafter also referred to as a reconfigurable circuit.
[0004]
[Patent Document 1]
JP-A-10-256383 (full text, Fig. 1-4)
[0005]
[Problems to be solved by the invention]
Based on the FPGA, various logics can be realized by using a look-up table (LUT) for storing the truth table of the logic circuit, but in general, the unit of the logic element is small, and the desired function is realized. In addition, many LUTs and wiring resources are required. As a result, compared with a normal LSI, the mounting area is generally large and the cost is high. In addition, the program time for rewriting a circuit is long to some extent, and is often not suitable for real-time function switching.
[0006]
The present invention has been made in view of such a current situation, and an object of the present invention is to provide a reconfigurable circuit that is advantageous in terms of cost, rewriting speed, circuit utilization efficiency, power consumption, and the like, an integrated circuit device using the same, and data setting To provide an apparatus.
[0007]
[Means for Solving the Problems]
An aspect of the present invention relates to a data generation apparatus that generates setting data for loading an intended function into an array of logic circuits each capable of selectively performing a plurality of arithmetic logic functions, and is used in the array. A monitoring unit that monitors a region that is present, a storage unit that stores setting data based on a data flow graph for setting a function of each logic circuit in the array and a connection relationship between the logic circuits, and the setting from the storage unit A control unit that reads data and generates setting data for loading a function to an unused area in the array based on the information on the used area obtained by monitoring by the monitoring unit, and generated by the control unit A setting unit that loads the set data to the array, and the control unit includes a functional circuit related to the setting data read from the storage unit. Whether the data can be loaded into the array is determined from the use status of the array as the monitoring result. If the functional circuit cannot be loaded, the setting data is changed so that the functional circuit can be loaded into the array. .
[0008]
For example, the setting unit may be constituted by dedicated hardware in addition to a combination of CPU (central processing unit) programs included in the device. The array is configured by arranging 8 × 8 logic circuits, for example. As a result of loading a plurality of functions into an array, ie, the smallest unit of a functional configuration, the effective utilization rate of the array is increased.
[0009]
The control unit receives the result of monitoring by the monitoring unit, and generates setting data for loading another function in an unused area in the array, thereby increasing the utilization efficiency of the array.
[0010]
Note that the control unit and the monitoring unit include, for example, a combination of a compiler, a CPU, and other arbitrary hardware and software.
[0011]
In the above configuration, the control unit may change the setting data by appropriately inserting a through node into the setting data.
[0012]
“ Through node” means NOP (no operation), that is, a node that does nothing. Actually, a wiring simply connecting an input and an output is selected inside the logic circuit, or the logic circuit is an identity mapping operator, ie, multiplication. If a circuit that multiplies 1 as an adder or adds zero as an adder is set, this logic circuit becomes a through node.
[0013]
The data generation device may be an external device that provides setting data to the integrated circuit device including the above-described logic circuit array , for example, and a program written in the C language or other high-level language is used as the setting data. A compiler for conversion may be provided.
[0014]
The monitoring unit may monitor an area used in the logic circuit array at a timing such as when data is sent from the control unit to the setting unit or when data is set by the setting unit. .
[0015]
The integrated circuit device and the data setting device described above may be a single device. In this case, for example, the former setting unit and the latter control unit can be configured by a single CPU and program. Part of the former and part of the latter may be configured as a single device.
[0016]
In any of the above cases, the logic circuit array is an array in which a plurality of rows of logic circuits arranged in the horizontal direction are combined in the vertical direction, and there is no connection for connection between the logic circuits in the horizontal direction. A structure in which a connection for connection is provided between the output of the first logic circuit row and the input of the next-stage logic circuit row may be employed.
[0017]
It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment relates to a reconfigurable circuit having an ALU (Arithmetic Logic Unit) array as a basic element. In this type of circuit, one ALU constitutes one logical unit, and this logical unit can selectively execute a plurality of arithmetic operations. Therefore, the circuit configuration is simple, and a data flow graph described later is directly used. Since mapping is possible, configuration time can be saved. Mapping refers to an instruction set of a program to be executed by the reconfigurable circuit and a connection data set required in the reconfigurable circuit to realize the instruction set loaded into an ALU array (hereinafter also simply referred to as “array”). To set. The configuration is defined below.
[0019]
1. Array: ALU is arranged in a matrix of m × n.
2. Reconfigurable circuit: A plurality of arrays are built in, but in the following description, attention is paid to one array (hereinafter, this array is also referred to as “target array”).
[0020]
An ALU is a “logical unit”, but normally one ALU realizes one function. For this reason, the array becomes a “functional unit”. The setting of the size of the array, that is, the values of m and n described above, is made from an empirical rule based on the assumption of the function to be realized. If the array is too small, one function cannot be realized. On the other hand, if the array is too large, when one function is loaded, unused ALUs increase and use efficiency is poor.
[0021]
From this point of view, the feature of the embodiment is that a plurality of functions are mounted in an array which is a functional unit. That is, first, the first functional circuit is loaded, and if there is an unused area, the second functional circuit is loaded to effectively use the array. Of course, it is effective to load the third and lower functional circuits in the remaining area.
[0022]
FIG. 1 shows a configuration of an integrated circuit device 10 and a data setting device 24 according to the embodiment. The data setting device 24 creates data for setting the circuit configuration of the integrated circuit device 10 and supplies the data to the integrated circuit device 10.
[0023]
The integrated circuit device 10 includes a reconfigurable circuit 12, a setting data storage unit 16 that stores setting data 17 for reconfiguring the reconfigurable circuit 12, and a setting that loads the setting data 17 to the reconfigurable circuit 12. Part 14. “Reconfiguration” refers to creating a circuit for realizing a desired function, and in reality, setting data 17 is loaded.
[0024]
The data setting device 24 includes a control unit 18, a compilation unit 20, a program storage unit 22, and a monitoring unit 23 that monitors the usage status of the ALU in the target array.
The monitoring unit 23 monitors the setting data 17 at any of several possible timings such as when the setting data 17 is sent from the control unit 18 or when the setting data 17 is set by the setting unit 14. As a result, the ALU used in the target array is always grasped, and conversely, an unused ALU is identified and transmitted to the control unit 18. The control unit 18 determines whether or not the second functional circuit can be loaded into the target array from the usage status of the ALU, and generates the setting data 17 to load if possible. If impossible, the setting data 17 is changed so that the second functional circuit is mapped to another array.
[0025]
The program storage unit 22 of the data setting device 24 holds various programs 19 to be executed by the integrated circuit device 10. The compiling unit 20 compiles the program 19 stored in the program storage unit 22, converts it into a data flow graph 21, and stores it in the program storage unit 22. As will be described later, the data flow graph 21 shows the flow of calculation of input variables and constants in a graph structure.
[0026]
The control unit 18 converts the data flow graph 21 into setting data 17 for mapping to the circuit configuration of the reconfigurable circuit 12 and supplies the setting data 17 to the setting unit 14 of the integrated circuit device 10. At this time, information on unused ALUs is acquired from the monitoring unit 23, and setting data 17 is described so that a plurality of functional circuits are loaded into the target array as much as possible. The setting data 17 is stored in the setting data storage unit 16.
[0027]
The setting unit 14 reconfigures the reconfigurable circuit 12 by reading the setting data 17 from the setting data storage unit 16 and loading the setting data 17 into the reconfigurable circuit 12. The reconfigured reconfigurable circuit 12 performs processing based on the loaded setting data 17.
[0028]
FIG. 2 shows the configuration of the target array 12a. The array of interest 12a includes a data input unit 40 for loading the setting data 17 and an area 42 in which rows of ALUs are arranged. The connection switch 44 and the connection connection 30 provided in each row allow the ALU of the previous row to be connected. Output and subsequent ALU input can be arbitrarily connected by setting. The connection connection 30 is selected by the connection switch 44, and is hereinafter also abbreviated as “setting by the connection connection 30”. Each ALU includes, for example, an adder, a subtracter, a multiplier, and the like.
[0029]
As shown in the figure, Y ALUs are arranged in the horizontal direction and X ALUs are arranged in the vertical direction, and input variables and constants are input to ALU11, ALU12,..., ALU1Y in the first row. Depending on the setting, a predetermined calculation is performed. The output of the calculation result is input to the ALU 21, ALU 22,..., ALU 2Y in the second row according to the connection set in the connection connection 30 in the first row. The connection line 30 in the first row is configured so that an arbitrary connection relationship between the output of the ALU group in the first row and the input in the ALU group in the second row can be realized. Becomes effective. Hereinafter, the connection configuration 30 up to the (X-1) th row has the same configuration, and the ALU group in the Xth row, which is the last row, outputs the final result of the operation. Each ALU has a through path (not shown) for outputting the input as it is in order to execute a mov operation described later. By selecting this, the ALU becomes a through node.
[0030]
The setting data 17 for mapping the data flow graph 21 to the target array 12a includes information for selecting the operation of each ALU, information for selecting a connection connection between ALU rows, and variables input to the ALU group in the first row. Contains a constant value.
[0031]
Consider the following execution target program.

FIG. 3 shows a data flow graph corresponding to the above program. In the figure, constants, variables, and operators are circled, mul indicates multiplication, and add indicates addition. If this is mapped to the reconfigurable circuit 12 as it is, the state shown in FIG. 4 is obtained. The above is the basis of the embodiment.
[0032]
Hereinafter, a method for loading two or more functional circuits will be described. Now, as shown in FIG. 5, the coordinates of the ALU included in the 2 × 4 array are represented by (i, j). However, i = 1, 2, j = 1, 2, 3, 4. 6 and 7 show the settings of FIG. 4 in coordinates. Here, for example, two mul and one add are respectively set to (1, 1) (1, 2) (2, 1), and the outputs of (1, 1) and (1, 2) are both (2, 1) connected to the input.
[0033]
The monitoring unit 23 examines an ALU for which an instruction has already been set, that is, a used one, and records the result in its own internal memory (not shown). FIG. 8 shows the processing for that purpose. Here, the array has Z rows and W columns, and the internal variables i and j are used as row and column counters, respectively. As shown in the figure, first, an initial value “1” is set in counters i and j (S10), i and Z are compared (S12), and if i is equal to or less than Z (Y in S12), there are still rows to be investigated. Since it is, it progresses to S14. In S14, j and W are compared, and if j is equal to or less than W (Y in S14), since there are still columns, the process proceeds to S16.
[0034]
In S16, it is checked whether the ALU of (i, j) is not set, that is, it is free. If it is free (Y in S16), “the number of vacant i rows is W−j + 1 and the number of used is j−1”. (S22), i is incremented and j is returned to "1" (S24), and the process returns to S12 to investigate the next line. If the (i, j) ALU has been used in S16, the process proceeds to S18, j is incremented, and the process returns to S14.
[0035]
If j has already exceeded the value of W in S14 (N in S14), since there is no vacancy in the row, “the number of vacant i rows is zero and the number of uses is W” is output (S20), S24 Proceed to
[0036]
If i has already exceeded Z in S12 (N in S12), the process is terminated because all rows have been investigated. Through the above processing, the monitoring unit 23 can record the number of empty spaces in each row. Since the number of vacancies is known, as a result, the monitoring unit 23 can know whether (i, j) ALU is free or used for any i, j.
[0037]
A second program, that is, a second functional circuit is set in this array. The program is as follows.

FIG. 9 is a data flow graph of this program, and FIG. 10 is a coordinate display showing settings when only this program is loaded into the array. However, since the first program has already been loaded, when the second program is loaded, an instruction is set to an empty ALU.
[0038]
FIG. 11 shows a process in which the control unit 18 determines whether or not the second program can be loaded. Here, N is the number of lines necessary for setting the second program. First, the counter i is set to “1” (S30), and i and N are compared (S32). If i is less than or equal to N, the setting is not complete, so the process proceeds to S34, and it is determined whether or not all the instructions necessary for realizing the second program can be accommodated in the vacant ALU in the i-th row. This is determined based on the number of free ALUs. If it can be accommodated (Y in S34), i is reflected in the setting data 17 (S36), the number of empty spaces is reduced by the number of ALUs newly set in the row (S38), and the process returns to S32.
[0039]
In S34, when the instruction cannot be accommodated in the i-th line, that is, when the number of instructions to be accommodated exceeds the number of vacant (N in S34), error processing (S40) is executed to perform the process. Finish. Error processing (S40) includes loading of the second program to an array other than this array. As another process, there is a process shown in FIG. On the other hand, if the value of i has already exceeded N in S32, the setting of all instructions has been completed, and thus the processing is also finished.
[0040]
FIG. 12 and FIG. 13 show the state in which the second program is set in relation to each instruction and ALU coordinate display. Sub uses a free ALU as in (1, 3). FIG. 13 shows a state of the array in which the first and second programs are mounted.
[0041]
FIG. 14 shows an example of the error processing described above. First, an outline of the processing is described, and an example is given later.
As shown in FIG. 14, first, "1" is set in the counters i, j, and k (S50). Here, k is assumed to be the k-th instruction constituting a program to be newly loaded, and all the programs have L instructions.
[0042]
When k is L or less (S52), i is Z or less (S54), and j is W or less (S56), the control unit 18 checks whether the (i, j) ALU is free (S58). If it is free, it is checked whether or not the k-th instruction can be set in the ALU (S60). As will be described later, even if the ALU is free, this ALU may not be used depending on the number of input nodes and the number of output nodes required for this instruction. If it can be used as a result of the inspection (Y in S60), it is reflected in the setting data 17, and k is incremented (S62), j is incremented (S64), and the process returns to S52. If it is found in S60 that the ALU cannot be used for the k-th instruction (N in S60), S62 is skipped and the process proceeds to S64. If it is determined in S58 that (i, j) is not free, S60 and S62 are skipped and the process proceeds to S64.
[0043]
If j has already exceeded W in S56, the inspection of that line has been completed (N in S56), so j is returned to "1" to inspect the next line, i is incremented (S66), Return to S54.
[0044]
If i has already exceeded Z in S54, the setting of this program has been completed without completion, and error processing (S68) is executed to finish the processing. On the other hand, if k has already exceeded L in S52, since the setting of this program is completed, the processing is normally completed. As an error process of S68, there is a load of this program to another array. The above is the outline of the processing.
[0045]
FIG. 15 and subsequent figures collectively show the processes of FIGS. 11 and 14 by way of examples. Here, when setting the first data flow graph, the second data flow graph,... Corresponding to a plurality of programs, the data flow graph is appropriately modified in accordance with the free area of the array. Follow the procedure below to set up the data flow graph.
[0046]
(1) Set the first data flow graph.
(2) Information related to the unset ALU is acquired from the setting information of the first data flow graph, and if the second data flow graph can be set in the unset ALU, it is set as it is (in the case of FIG. 11).
(3) If the second data flow graph does not fit in the unset ALU, the second data flow graph is transformed and set (in the case of FIG. 14).
(4) If the second data flow graph does not fit no matter how it is transformed, setting processing is performed on the remaining data flow graph (error processing in FIG. 14).
(5) The data flow graph that could not be finally set is set in another ALU array (same error processing).
[0047]
FIGS. 15, 16, and 17 schematically show three data flow graphs to be set. However, the number represents a node number, and a predetermined logical operation is assigned to each node. The array is 8 × 8.
[0048]
First, since the array is in an unset state in the initial state, the first data flow graph can be set as it is. FIG. 18 shows this state. FIG. 19 shows the free state of the ALU at this point.
[0049]
Next, a second data flow graph is set. It can be seen that the second data flow graph can be set as it is based on the empty state in FIG. 19 and the necessary number of ALUs in FIG. FIG. 20 shows a state in which the second data flow graph has been set in the array. FIG. 21 shows the free state of the ALU at this time.
[0050]
Finally, a third data flow graph is set. Comparing the necessary number of ALUs found from FIG. 17 and the free state found from FIG. 19, it can be seen that the third data flow graph cannot be set in the array in the same connection state. It is checked whether setting is possible by changing the connection state of the third data flow graph. The rules for setting nodes in the array are as follows.
[0051]
(1) Set the line as high as possible (the line where i is small).
(2) Set the column to the left as much as possible (a column where j is small).
(3) There is a problem such as a shortage of free ALUs, and when transforming the data flow graph, through nodes are added as appropriate.
[0052]
In order to make the positions of unused ALUs shown in FIG. 19 easier to understand, the above-described coordinate display is used. Inspecting from the top row, only nodes with 0 input nodes and 1 output nodes can be set to (8, 1). FIG. 22 shows the number of input nodes and the number of output nodes of each node constituting the third data flow graph. From FIG. 22, the node 24 is set to (8, 1). FIG. 23 shows the setting state at this time point for the top three lines.
[0053]
Next, the output node of the set node 24 is checked. Although the node 24 has the node 28 as an output node, since the node 28 has two input nodes, it cannot be set to (8, 2). Therefore, it is set to the lower line. Here, since it is left-justified, the node 28 is temporarily set to (6, 3). However, even in such a case, since the two input nodes of the node 28 cannot be set, it is further set to (4, 4) which is further down and satisfies the left alignment. Since the node 24 and the node 28 are connected, they are connected by setting a through node (“N” in the figure) to (6, 3) and (8, 2). FIG. 24 shows the setting state at this point.
[0054]
Subsequently, the node 25 that is the input node of the node 28 is set. Since the node 25 may be set in the upper row of the node 28, it is set to (7, 3). Thus, the setting of the input node of the node 28 is completed. FIG. 25 shows the setting state at this point.
[0055]
Next, node 31 is the only output node of node 28. As described above, the node 31 is set, and the unset node 29 among the input nodes of the node 31 is set to (5, 4). Further, among the input nodes of the node 29, the unset node 26 is set to (8, 4). FIG. 26 shows the setting state at this point.
[0056]
Subsequently, an output node 33 of the node 31 is set. Since the number of input nodes is 2, the node 33 is set to (1, 6), and the setting of the input node is set in the same manner as described above. However, the setting fails because there is no ALU that can be set for the node 27 of the input node of the node 30. Therefore, the setting after node 33 is cleared. FIG. 27 shows the setting state before clearing.
[0057]
In order to set the node 27, a through node is inserted at (1, 6), and the setting position of the node 33 is lowered by one line to make a space. The node 33 is set to (1, 7). With the above procedure, the setting of the third data flow graph is completed as shown in FIG.
[0058]
The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. . Here are some examples.
[0059]
A timer (not shown) may be provided in the data setting device 24 of FIG. 1 and the like, and the function that the control unit 18 loads into the reconfigurable circuit 12 may be switched according to the timer output. In that case, a plurality of functions can be switched sequentially. This method is effective when the integrated circuit device 10 performs various functions in a time-sharing manner.
[0060]
The integrated circuit device 10 according to the embodiment can be applied to, for example, a software defined radio. In that case, the reconfigurable circuit 12 may be loaded with an FM radio, a car navigation function, a television reception function, a voice call function, and the like as appropriate.
[0061]
【The invention's effect】
According to the data setting device of the present invention, the utilization efficiency of the integrated circuit device can be improved. Further, when realizing the same function, the circuit scale and power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an integrated circuit device and a data setting device according to an embodiment.
FIG. 2 is a configuration diagram of an ALU array portion in the reconfigurable circuit of FIG. 1;
FIG. 3 is a diagram showing a data flow graph representing processing of a certain program.
4 is a configuration diagram of an ALU array mapped corresponding to the data flow graph of FIG. 3. FIG.
FIG. 5 is a diagram showing coordinates of a 2 × 4 ALU array.
FIG. 6 is a diagram illustrating a correspondence relationship between an instruction set and an ALU.
FIG. 7 is a diagram illustrating a correspondence relationship between an instruction set and an ALU.
FIG. 8 is a flowchart illustrating a procedure for a monitoring unit to check the availability of an ALU.
FIG. 9 is a diagram showing a data flow graph of a second program to be loaded into the ALU array.
FIG. 10 is a diagram illustrating a correspondence relationship between an instruction set of a second program and an ALU when the first program is not considered.
FIG. 11 is a flowchart showing a procedure for determining whether or not a second program can be loaded into a certain ALU array;
FIG. 12 is a diagram illustrating a correspondence relationship between the instruction set of the second program and the ALU when the first program is considered.
FIG. 13 is a diagram showing a state in which the first and second programs are loaded into the ALU array.
FIG. 14 is a flowchart showing a procedure for determining whether or not the second and subsequent programs are loaded into the ALU array, and particularly showing an example of error processing in FIG.
FIG. 15 is a diagram showing ALUs to be used in the first data flow graph with numbers.
FIG. 16 is a diagram showing ALUs to be used in the second data flow graph with numbers.
FIG. 17 is a diagram showing numbers of ALUs to be used in the third data flow graph.
FIG. 18 is a diagram illustrating a state in which a first data flow graph is loaded into an 8 × 8 ALU array.
FIG. 19 is a diagram showing a usage state of the ALU at the time of FIG.
FIG. 20 is a diagram showing a state in which a second data flow graph is loaded into an 8 × 8 ALU array.
FIG. 21 is a diagram showing a usage state of the ALU at the time of FIG.
FIG. 22 is a diagram showing the number of ALU input and output nodes required for the third data flow graph.
FIG. 23 is a diagram showing a state in which a node “24” of the third data flow graph is set.
FIG. 24 is a diagram showing a state where a node “28” of the third data flow graph is set.
FIG. 25 is a diagram showing a state in which a node “25” of the third data flow graph is set.
FIG. 26 is a diagram illustrating a state where nodes “26”, “29”, and “31” of the third data flow graph are set.
FIG. 27 is a diagram illustrating a state in which the node “27” of the third data flow graph cannot be set and the setting temporarily fails.
FIG. 28 is a diagram illustrating a state in which the failure of FIG. 28 is resolved and the setting of the third data flow graph is completed.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Integrated circuit apparatus, 12 Reconfigurable circuit, 12a ALU array, 14 Setting part, 18 Control part, 20 Compile part, 21 Data flow graph, 23 Monitoring part, 24 Data setting apparatus

Claims (3)

A data generation device for generating setting data for loading a functional circuit into an array of logic circuits,
A monitoring unit for monitoring an area used in the array;
A storage unit for storing a data flow graph for configuring the setting data ;
A control unit that reads the data flow graph from the storage unit and generates setting data for loading a function into an unused region in the array based on the information on the used region obtained by monitoring by the monitoring unit When,
A setting unit that loads setting data generated by the control unit into the array;
The controller is
Whether the functional circuit configured based on the data flow graph read from the storage unit can be loaded into the array is determined from the usage status of the array obtained by monitoring in the monitoring unit,
A data generation device that performs transformation of the data flow graph read from the storage unit when the functional circuit cannot be loaded. The data generation apparatus according to claim 1, wherein the control unit transforms the data flow graph by inserting a through node into the data flow graph. The data generation apparatus according to claim 1, wherein the monitoring unit monitors a usage state in the array when data is transmitted from the control unit to the setting unit or when data is set by the setting unit.

Images