JP2018206195A - Calculation system, and control method and program of calculation system - Google Patents

Abstract

To provide a calculation system, and a control method and a program of the calculation system that enable improving accelerator utilization efficiency and maintaining a programming method.SOLUTION: A calculation system 100 comprises; an input device 160 that receives a command; and a support device 170 that maps the input command to a partial reconstruction region of an FPGA accelerator 140 and that controls to connect between the partial reconstruction regions using a data path. When a pipe instruction is issued, the support device 170 maps a previous command to a previous partial reconstruction region, maps a subsequent command to a subsequent partial reconstruction region, and connects the previous and the subsequent partial reconstruction regions to be one dimensional connection by means of data paths one after another, and after the mapping and the connecting are repeated for all pipe instructions, a setting, in which a beginning command input is introduced from a CPU 110 and a terminating command output is returned to the CPU 110, is performed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an arithmetic system, a control method for the arithmetic system, and a program.

First, the outline of the characteristics of the arithmetic unit inside the computer will be described. As the computer, a known general-purpose computer including an arithmetic unit using an electronic integrated circuit, a main storage device (memory), an auxiliary storage device, and the like is assumed.
The computer operates by receiving a group of instructions (programs) defining numerical values and types of operations as inputs, interpreting and executing them by an arithmetic unit, and outputting the results.
A CPU (Central Processing Unit), a representative example of arithmetic devices, has many dedicated processing circuits that support complex arithmetic instructions (for example, division and floating-point arithmetic) in order to demonstrate performance without being limited to specific processing. It has a built-in structure that switches between them depending on the type of instruction. Also, the CPU has a mechanism for predicting the branch destination (branch prediction mechanism) so that performance degradation does not occur before and after execution of a branch instruction (the instruction to be executed next is changed depending on conditions), and when a branch occurs. It may include a mechanism (active execution mechanism) that executes both processes in the case of non-occurrence in advance and selects and uses one of the calculated results after the branch determination result is output Many.

When the CPU performs a certain process, a dedicated processing circuit that is not used for the process enters a standby state. The branch prediction mechanism is a circuit that essentially does not contribute to the operation itself. In addition, in the above-described aggressive execution mechanism, an operation result that has not been used as a result of branching is discarded, so that the circuit that has processed it has not contributed to the operation itself. In other words, when the circuit scale is limited due to the cost applied and the difficulty in manufacturing a large-scale integrated circuit, the processing performance has to be relatively low.
Among computing devices, those that have a structure and instruction set specialized for specific processing, such as those specialized for image processing, are called GPU (Graphics Processing Unit), and are specialized for packet processing in the network. This may be referred to as an NPU (Network Processing Unit).
These include, for example, a large number of specific processing circuits related to the application, and when corresponding processing is performed, they have a function of operating them in parallel and performing high-speed processing. Many.

In addition, the program that performs image processing and packet processing takes advantage of the relatively few conditional branch processing, omitting the branch prediction mechanism and the aggressive execution mechanism, etc., and designed to allocate resources to the main arithmetic processing as much as possible. Sometimes it is done.
In general, an integrated circuit specialized for these specific processes can exhibit very high performance as compared with a CPU having the same circuit scale. On the other hand, if processing that does not correspond is performed, the processing becomes impossible, or even if it can, the performance is very low.
In order to avoid such a situation, a form as shown in FIG. 5 in which a GPU or NPU is connected as an accelerator through a CPU expansion bus or the like is often used for a general-purpose computer equipped with a CPU.

FIG. 5 is a schematic configuration diagram of an arithmetic system in which an arithmetic device specialized for specific processing is added to a general-purpose computer.
As shown in FIG. 5, the arithmetic system 10 includes a CPU 11, a memory 12, an auxiliary storage device 13, an accelerator 14, and an expansion bus 15 that connects them. The accelerator 14 includes an arithmetic unit made up of GPU / (hereinafter referred to as “/” in this specification is “and / or”) NPU / FPGA (Field Programmable Gate Array).
The arithmetic system 10 is instructed by the CPU 11 to use the accelerator 14, and data to be calculated is transmitted to the accelerator 14 through the expansion bus 15. Then, the arithmetic system 10 performs an arithmetic operation on the accelerator 14, and finally the result is sent to the CPU 11. It is configured to return.

The structure of the arithmetic device group realized by the above-described integrated circuit is usually determined at the time of production, and executable instructions, operation speeds, and the like are not changed later.
Therefore, when using an arithmetic device specialized for a specific process, it is normal that an appropriate arithmetic device is selected and installed in accordance with the purpose of use of the computer.

Next, a reconfigurable integrated circuit device will be described.
Reconfigurable integrated circuits such as FPGAs (Field Programmable Gate Arrays) have an LUT (Look Up Table) structure that applies rewritable memory (SRAM, Static Random Access Memory), and the structure of electronic circuits. Is written on a built-in LUT, a device capable of temporarily configuring an arbitrary electronic circuit. In SRAM-based FPGA (SRAM-based FPGA), the LUT and the wiring switch are composed of SRAM, and these are composed of SRAM. Therefore, when power is turned on, an operation (configuration) for writing information to the SRAM is required. .
In this specification, an SRAM FPGA, which is a typical implementation, will be described below. However, the same applies to a case where a device that can form an electronic circuit by another method is used.

Conventionally, in the design stage of an ASIC (Application Specific Integrated Circuit), an FPGA is configured in a circuit designed for the ASIC, thereby verifying the operation before producing a high-cost ASIC, Used as a device to help fix.
In addition, if the production of equipment is limited to a small number, the equipment is configured to introduce a pre-fixed circuit configuration from an external storage element or the like when the equipment is started up, as if the application It is used to realize the same state as that equipped with the ASIC.

Describes Reconfigurable Computing.
In recent years, the use of FPGA for general-purpose computing called “reconfigurable computing” has attracted attention (see, for example, Non-Patent Document 1). Reconfigurable computing combines the flexibility of software with high-performance hardware processing through highly flexible high-speed computing structures such as FPGAs. One form is to actively utilize the reconfigurable structure of the FPGA, and instead of selecting and manufacturing an appropriate arithmetic device for each computer, a computer equipped with the FPGA as an accelerator is prepared, and the arithmetic device The circuit configuration representing the circuit design is introduced into the FPGA, and processing is performed by configuring an ad hoc arithmetic circuit.
At this time, if a circuit configuration specialized for various processes is prepared in advance and the circuit to be introduced is changed in accordance with the process to be performed, the structure and instruction set specialized for the process are always applied to various processes. It is thought that it is possible to continue using an arithmetic device having However, note that the FPGA has an overhead derived from the configuration of emulating the electronic circuit on the electronic circuit, and may be inferior in terms of operation speed, power efficiency, and the like as compared to GPU, NPU, etc. of the same circuit scale. There is a need.

Describe program description and compilation.
A conventional executable program for CPU / GPU / NPU is often a binary machine language defined for each arithmetic device. Instead of describing machine language directly, a method of describing a program in a programming language represented by C language or the like and converting it into binary using a compiler is widely used.
This compile operation can typically be executed in the order of seconds to minutes, so the programmer, for example, compiles the program after describing the function unit, etc., and then performs the actual operation to check whether the processing results are correct. , Move on to the description of the next function, and so on. When the scale of a program becomes very large, the compilation time may be longer than a few minutes, but many compilers compile in units of files describing the program. Also, in many cases, it has a function capable of skipping compilation of a file that has not been changed, and the programmer can divide and describe the file for each function or the like, thereby suppressing an increase in compilation time.

  It is also possible to directly execute a program without compiling it using a special program called an interpreter. In many cases, the execution speed is lower than the binary creation using a compiler, but there is an advantage that the program can be executed immediately after the program is written. Because of this advantage, for example, when it is desired to repeatedly execute a series of operations on a computer, it is also suitable for usage such as describing and calling it as a simple program (also called a script or the like). In this specification, such usage is referred to as ad hoc programming.

On the other hand, when an arithmetic unit is configured with an FPGA, the structure of the arithmetic circuit itself must be designed in addition to the program for instructing the operation for the arithmetic circuit configured thereon.
The structure of the arithmetic circuit is defined by the circuit configuration described above and is typically in binary format. Instead of describing the binary circuit configuration directly, it can be written in a hardware description language (HDL, hardware description language) such as Verilog HDL or VHDL, or C language, and then converted into a circuit configuration using a compiler. It is normal.
However, the operation of the FPGA synthesis tool chain for creating a circuit configuration is much slower than a normal program compiler, and typically requires several tens of minutes to several hours.
This is because, for example, the “place and route” process in the FPGA synthesis tool chain “assigns which circuit function to which position of the LUT group two-dimensionally arranged on the FPGA, and how between them. One of the causes is considered to belong to the NP difficult problem that is not guaranteed to be solved mathematically in polynomial time.

  This length of operation time greatly hinders the description and test cycle in conventional programming. In the development of a large-scale circuit configuration, in order to avoid this, a circuit simulator that simulates the operation when a circuit configuration is introduced on the FPGA is not performed every time an FPGA configuration is actually written on the CPU. Often used. Although the operation speed of the circuit simulator is limited, the time until the operation starts is about the same as the compilation of the program.

On the other hand, in order to perform reconfigurable computing by the above-described ad hoc programming, a circuit configuration creation process is inevitable as long as the purpose is to obtain an actual operation.
It takes a long time to create a script that assists in the operation and operation of a computer, which can be an obstacle to the use of the user. For example, assume that it takes several minutes to create a program that records a series of processes performed by manually issuing a plurality of commands on an OS (Operating System). In this case, rather than waiting for several hours of tool chain operation time until execution, the total processing time is faster when a program that operates on the CPU is allowed even if performance degradation of the program execution is allowed. There may be many cases.

Next, reconfigurable computing using partial dynamic reconfiguration techniques is described.
In some FPGAs that are currently mainstream, a partial dynamic reconfiguration mechanism may be implemented. This is a mechanism that can rewrite the circuit configuration of another part during the operation of a part of the circuit written on the FPGA. In the implementation, one or more partial reconfiguration areas for dynamic reconfiguration are defined in advance on the FPGA, and the introduction of the partial circuit configuration into the partial area is independent of other parts. There is a case where a format that can be used is used (for example, see non-patent documents 2 and 3).
By utilizing the above method, it is considered that the above-mentioned problem of “Reconfigurable computing is not suitable for ad hoc programming because of the long operation time of the tool chain until the circuit configuration is created” is considered. .

For this purpose, first, functions used in the program, OS system calls, OS commands, etc. are created in advance as partial circuit configurations that can be executed by changing only the arguments, and are stored in a storage area. . Next, when the program is directly executed by an interpreter or the like (this is performed on the main CPU) and a function or the like for which a partial circuit configuration is prepared is called in the program, the partial circuit configuration prepared in advance is called. Is written in a partially reconfigured area that is empty on the FPGA.
Data to be processed is written into the FPGA through the CPU expansion bus and the result is similarly retrieved through the expansion bus. The above operation will be specifically described.

FIG. 6 is a diagram showing the above operation added to the calculation system 10 of FIG. FIG. 6 shows an example in which an FPGA accelerator or the like is mounted on a general-purpose computer, and an arithmetic circuit constructed on the FPGA without using a circuit configuration generation time by using a partial circuit configuration group prepared in advance is used.
As shown in FIG. 6, the accelerator 14A of the computing system 10 is an FPGA accelerator equipped with an FPGA, and the FPGA accelerator 14A includes partial reconfiguration areas (1) to (9). The auxiliary storage device 13 of the arithmetic system 10 stores a partial circuit configuration group 13A created in advance. Here, the partial circuit configuration group 13A is the partial circuit configurations A to D. The memory 12 of the calculation system 10 temporarily stores calculation target data 12A.

The CPU 11 of the arithmetic system 10 executes a program, and when a function for which a partial circuit configuration is prepared is called in the program, the prepared partial circuit configuration group 13A is in an empty state on the FPGA accelerator 14A. The partial reconfiguration areas (1) to (9) are written and operated. As shown by symbol a in FIG. 6, the CPU 11 executes the partial circuit configuration A in the partial reconfiguration areas (1) and (2) of the FPGA accelerator 14A and the partial circuit configuration in the partial reconfiguration area (5) during program execution. B is written to the partial reconfiguration area (9), respectively. As shown by the symbol b in FIG. 6, the calculation target data 12 </ b> A temporarily stored in the memory 12 is written to the FPGA accelerator 14 </ b> A through the expansion bus 15, and the result is similarly retrieved through the expansion bus 15.
The arithmetic system 10 transmits the data to be calculated to the FPGA accelerator 14A through the expansion bus 15, performs an arithmetic operation in the arithmetic circuit on the FPGA accelerator 14A, and finally returns the result to the CPU 11.

  By doing so, the arithmetic system 10 can use the FPGA to make the most suitable arithmetic type for the type of operation without generating the circuit configuration by the FPGA synthesis tool chain on the spot even in the application of ad hoc programming. Can be obtained (see Non-Patent Document 4 for such usage).

  However, in the structure of the arithmetic system 10 of FIGS. 5 and 6, data is transferred from the memory 12 to the FPGA accelerator 14A through the expansion bus 15 in units of one function, command, etc. in the program, and the result is transferred to the expansion bus 15 The operation of rewriting data in the memory 12 via the relay is repeated. Therefore, the time required for data exchange through the expansion bus 15 limits the speed of execution.

Next, avoidance of the aforementioned bus bottleneck will be described.
In order to avoid the aforementioned expansion bus bottleneck and maximize the performance of reconfigurable computing, multiple FIFO (First In First Out) data structures are provided between the partially reconfigurable areas in the FPGA. Let us consider a structure (reconstruction area map) that is directly connected to each other.
First, the connection relationship between input data and output data to a function or command for which a partial circuit configuration is prepared is identified from the structure of the program input by the user, and the data connection portion is connected by the FIFO-like data structure described above. Thus, the arrangement position is determined and the partial circuit configuration group is loaded, and all of them are executed in parallel.

By doing so, operations are executed one after another (pipeline processing) without temporarily saving intermediate processing results that do not appear in the final operation results to the memory, so data exchange through the expansion bus Can be minimized, and the benefits of high speed due to the “effect of always using the computing device most suitable for the type of computation” by the FPGA can be obtained.
Non-Patent Document 5 shows a configuration in which a bottleneck of a bus used to access a nearby DRAM (Dynamic Random Access Memory) is avoided by connecting the functional modules in the FPGA using a directly connected FIFO structure. Has been. However, although dynamic reconfiguration of functional modules is not mentioned in Non-Patent Document 5, it can be considered that these can be used in combination if Non-Patent Documents 2 and 3 are referred to.

FIG. 7 is a diagram illustrating an example in which the arithmetic system 10 of FIG. 6 is modified by adding the above operation. FIG. 7 shows an example in which a directly connected FIFO type data structure is provided between the partial circuit configurations in the FPGA to avoid an expansion bus bottleneck.
As shown in FIG. 7, the arithmetic system 10A includes a program 20 that instructs the arrangement position (introduction position) of the partial circuit configuration group 13A and the data path that enables each of the partial circuit configurations A to D. Here, the program 20 sets the arrangement positions of the partial circuit configurations A to D (see the reconfiguration area map in which the partial circuit configurations A to D in FIG. 7 are arranged) and the arrangement positions of the partial circuit configurations A to D in a FIFO form. And a data path 21 (see an arrow in the program 20 in FIG. 7) connected by a route.

  As indicated by reference symbol c in FIG. 7, the arithmetic system 10 </ b> A instructs the arrangement position of the partial circuit configuration group and the data path 21 from the structure of the program 20 input by the user. The CPU 11 reads the partial circuit configuration group 13A from the auxiliary storage device 13 according to the instruction of the program 20, and designates the position of the partial circuit configuration group 13A with respect to the partial reconfiguration areas (1) to (9) of the FPGA accelerator 14A. Writing is performed (see symbol d in FIG. 7). That is, the partial circuit configurations A to D are written in the arrangement positions of the partial circuit configurations A to D, which are the same as the FIFO data structure instructed by the program 20, and the data path 21 is the same as the FIFO data structure instructed by the program 20. Input / output data via the path.

In the case of FIG. 7, when executing the program, the CPU 11 stores the partial circuit configuration A in the partial reconfiguration area (1) of the FPGA accelerator 14A, the partial circuit configuration B in the partial reconfiguration areas (3) (5) (7), The partial circuit configuration C is written in the partial reconstruction area (6) (8), and the partial circuit configuration D is written in the partial reconstruction area (9).
As shown by a symbol e in FIG. 7, the calculation target data 12 </ b> A temporarily stored in the memory 12 is written to the FPGA accelerator 14 </ b> A through the expansion bus 15. In the case of FIG. 7, the FPGA accelerator 14A inputs / outputs data through the path of the data path 21, which is the same as the FIFO-like data structure instructed by the program 20 (see the thick arrow indicated by reference sign f in FIG. 7). As shown by the symbol g in FIG. 7, the calculation result by the calculation device on the FPGA accelerator 14 </ b> A is taken out through the expansion bus 15.

“Reconfigurable Computing-Wikipedia”, [online], [March 24, 2017 search], Internet <URL: https: //en.wikipedia.org/wiki /% E5% 86% 8D% E6% A7% 8B% E6% 88% 90% E5% 8F% AF% E8% 83% BD% E3% 82% B3% E3% 83% B3% E3% 83% 94% E3% 83% A5% E3% 83% BC% E3% 83% 86% E3% 82% A3% E3% 83% B3% E3% 82% B0> Zhenzhong Xiao, et al., “A Partial Reconfiguration Controller for Altera Stratix V FPGAs,” FPL2016.29 Aug.-2 Sept. 2016, Lausanne, Switzerland Xie Di, “A Design Flow for FPGA Partial Dynamic Reconfiguration,” IMCCC2012. 8-10 Dec. 2012, 10.1109 / IMCCC.2012.35 Kazuhiro Yamato, “Acceleration of character string division using FPGA suitable for IoT devices”, Miracle Linux Co., 2016/12/1 Z. Wang, “Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs.”

  However, when programming the reconstruction area map directly connected to the FIFO, the structure of the reconstruction area map is fixed in advance. Therefore, unlike a program that runs on the CPU, a programmer or computer user obtains the map structure in advance, and programming is performed so that the flow of data between functions and commands can be realized on the reconstruction area map. Must. The program for this purpose is assumed to be a unique language with extensions and the like that are not present in the existing program in order to indicate the introduction position of the circuit configuration and the data path to be enabled on the map.

  For example, in FIG. 7, the partial circuit configuration B is introduced to the partial reconfiguration areas (3), (5), and (7) and is used in 3 parallels. Since there is no partial reconfiguration area, operation becomes impossible. As described above, when applying reconfigurable computing, the user needs to newly learn a programming method in consideration of the structure of the map. In addition, there is a problem that must be reprogrammed every time the status of the computer or map used changes.

  Further, depending on the characteristics of the program, there is a problem that a portion that is wasted because the reconstruction area map cannot be used up is generated. For example, a FIFO-like data structure is usually realized as an electronic circuit configured on an FPGA. For this reason, the entire area on the FPGA corresponding to the FIFO structure that has not been used for the convenience of the program remains unused.

  Furthermore, the partial reconfiguration area must be set so that an arbitrary partial circuit configuration can be introduced in an arbitrary area in order to allow free programming, while the scale of the partial circuit configuration depends on the contents of functions and commands. It is envisaged that it will be very different. In order to allow the introduction of any partial circuit configuration for any area, the partial reconfiguration area must be designed to accommodate all candidate partial circuit configurations to be introduced, typically The size is adapted to the partial circuit configuration with the largest circuit scale. When a command having a small circuit scale is introduced into this partial reconstruction area, the surplus part becomes an area that cannot be used.

FIG. 8 is a diagram illustrating a decrease in FPGA utilization efficiency when the circuit scale differs greatly between the partial circuit configurations.
The command 31 having a large circuit scale and the command 32 having a small circuit scale shown in FIG. 8A are introduced into the partial reconfiguration areas (1), (2), and (3) shown in FIG. 8B. As described above, the partial reconfiguration areas (1), (2), and (3) are designed so that all of the partial circuit configurations can be accommodated. As shown in FIG. 8B, when a command 32 having a small circuit scale is introduced into the partial reconstruction area (2) (3), the surplus portion (see the hatched portion in FIG. 8B) It becomes an unusable area.
By combining these, the conventional technique has a problem that the utilization efficiency of the FPGA is low.

  The present invention has been made in view of such a background, and it is an object of the present invention to provide an arithmetic system, an arithmetic system control method, and a program capable of improving accelerator utilization efficiency and maintaining a programming technique. To do.

  In order to solve the above-described problems, the invention described in claim 1 is directed to a CPU as a host, an external storage device that stores a partial circuit configuration group, and an arithmetic circuit dynamically loaded by loading the partial circuit configuration group. An arithmetic system comprising a reconfigurable accelerator device and a bus connecting them, an input device for displaying a command line prompt and receiving a command input on a command line, and an input command, A support device that maps to a partial reconfiguration region that is a partial reconfigurable region of the accelerator device and controls the partial reconfiguration regions to be connected by a data path, the support device comprising: When a pipe instruction is issued that connects the output data of the command as input data of the next command, the previous command is Mapping to the partial reconstruction area, mapping a later command to the subsequent partial reconstruction area, and connecting the preceding and following partial reconstruction areas in a line without branching by a data path, After repeating the mapping and the connection for all pipe instructions, the input of the leading command is introduced from the CPU, the output of the terminating command is set back to the CPU, and the accelerator device In the FIFO type data structure in which the mapping of the partial reconstruction area set by the support apparatus and the preceding and following partial reconstruction areas are connected in a line without branching by a data path, all target commands are processed in parallel. It was set as the arithmetic system characterized by starting and processing.

  According to another aspect of the present invention, there is provided a host CPU, an external storage device for storing a partial circuit configuration group, and an accelerator device capable of dynamically reconfiguring an arithmetic circuit by loading the partial circuit configuration group. And a bus for connecting them, an input device that displays a command line prompt and accepts a command input on a command line, and the input command to the accelerator device A support device that maps to a partial reconfiguration area, which is a partial reconfigurable area, and controls the partial reconfiguration areas so as to be connected by a data path. When a pipe instruction, which is an instruction for connecting the output data of the next command as input data for the next command, is issued, the previous command is And mapping the subsequent command to the subsequent partial reconstruction area, and connecting the preceding and following partial reconstruction areas in a line without branching by the data path, After the connection is repeated for all pipe instructions, the step of setting the input of the leading command from the CPU and setting the output of the terminating command back to the CPU is executed, and the accelerator device In the FIFO type data structure in which the partial reconstruction areas set by the support device and the partial reconstruction areas before and after are connected in a line without branching by a data path, all target commands are An arithmetic system control method is characterized in that the processing is executed by starting in parallel.

  According to a seventh aspect of the present invention, there is provided a CPU as a host, an external storage device for storing a partial circuit configuration group, and an accelerator device capable of dynamically reconfiguring an arithmetic circuit by loading the partial circuit configuration group. And a support device that maps the input command to the partial reconfiguration area of the accelerator device and controls the partial reconfiguration areas to be connected by a data path. When a pipe instruction, which is an instruction for connecting the output data of a command as input data for the next command, is issued, the previous command is mapped to the previous partial reconstruction area, and the subsequent command is mapped to the subsequent partial reconstruction. Map to the configuration area and make the partial reconfiguration areas before and after become a line without branching by the data path A control unit configured to connect, repeat the mapping and the connection for all pipe instructions, and then introduce the input of the leading command from the CPU and return the output of the terminating command to the CPU; As a program to function as

  By doing so, the number of times the input / output data passes through the expansion bus can be suppressed to at most once, and a decrease in execution speed due to data exchange between the CPU and the accelerator can be suppressed. Further, while presenting the same interface as the shell to the user, it is possible to obtain the effect of improving the execution speed by performing high-speed arithmetic using a dedicated arithmetic circuit, parallel execution of arithmetic groups, and reducing the number of memory accesses.

  The invention according to claim 2 is characterized in that the external storage device compiles and stores a command or a program group on the CPU in advance in a format that can be introduced at an arbitrary position in the partial reconfiguration area. And

  By doing in this way, a circuit configuration can be introduced to the position of any designated partial reconfiguration area, and the same interface as the shell can be presented to the user.

  The invention according to claim 3 is characterized in that the support device instructs the accelerator device to perform an operation by calling an external program corresponding to the command name of the input command.

  By doing so, the user can perform programming in the same manner as the one-liner execution on the host without being aware of the connection relation information of the partial reconfiguration area group of the equipment to be used. The same usage method as before can be realized, and the programming method can be maintained.

  According to a fourth aspect of the present invention, the accelerator device includes an FPGA, and the support device inputs a shape of a reconstruction area map configured in advance on the FPGA for each partial reconstruction area. A FIFO-type data structure with one output and one output, and a dynamic reconfiguration area chain in which the output and the input are interconnected so as to be in a line in order.

  By doing so, since the data path of the process is straight, the percentage of actually used hardware pipes included in the dynamic reconfiguration area chain is high, and the utilization efficiency of the FPGA accelerator is improved. When the partial circuit config size difference between commands is small and relatively uniform, the surplus ratio can be kept small when introduced into a partial reconfiguration area in accordance with their maximum size. As a result, there is an increased possibility that a larger number of partial reconfiguration areas can be taken on the same scale FPGA accelerator.

  Further, in the invention according to claim 5, when the support device has the number of commands connected by the pipe instruction smaller than the number of the dynamic reconfiguration chains prepared on the FPGA, 2. The computing system according to claim 1, wherein a bypass command is inserted in a pipe and the number of the dynamic reconfiguration chains is the same as the number of piped commands.

  By doing this, the bypass command is written in the partially reconfigured area that is not being used, so that the data is bypassed to the end and finally returned to the host through the end hardware pipe. is there. FIFO type data structure with one input and one output for each partial reconfiguration area even if the number of commands connected by pipe instructions is smaller than the number of dynamic reconfiguration chains prepared on the FPGA (Dynamic reconfiguration area chain) can be configured. Note that any method such as a shortcut may be used as long as the process after the final command is not performed (bypass).

  According to the present invention, it is possible to provide an arithmetic system, an arithmetic system control method, and a program that can improve accelerator utilization efficiency and maintain a programming technique.

It is a block diagram which shows the arithmetic system which concerns on embodiment of this invention. It is a figure explaining operation | movement of the arithmetic system which concerns on embodiment of this invention, (a) is a command line which shows the input to a shell, (b) is a block of the assistance apparatus which is software which provides a shell, (c) FIG. 4 is a diagram illustrating connection of partial reconfiguration areas on an FPGA accelerator. It is a flowchart which shows operation | movement of the support apparatus (shell software) of the arithmetic system which concerns on embodiment of this invention. It is a figure explaining that an FPGA accelerator can be used without a region surplus when the scale of a partial circuit configuration between commands of an arithmetic system according to an embodiment of the present invention is uniform, and (a) is a command with a uniform circuit scale. FIG. 8 is a diagram showing introduction of a command into a partial reconstruction area. It is a schematic block diagram of the arithmetic system which added the arithmetic device specialized to a specific process to the general purpose computer. FIG. 6 is a diagram in which an operation is added to the calculation system of FIG. 5. It is a figure which shows the example which added and changed the operation | movement to the arithmetic system of FIG. It is a figure which shows the FPGA utilization efficiency fall when a circuit scale differs greatly between partial circuit configurations, (a) is a figure which shows a command with a large circuit scale, and a command with a small circuit scale, The introduction to the partial reconfiguration | reconstruction area | region of a command FIG.

Hereinafter, an arithmetic system and the like in a mode for carrying out the present invention (hereinafter referred to as “the present embodiment”) will be described with reference to the drawings.
(Background explanation)
[Existing configuration 1]
The execution of a command group using a shell on a general-purpose computer will be described.
The shell is a program having a role of interpreting commands entered by the user on the command line and causing the computer to execute them. With the shell running, users can type and execute commands on the command line. In addition, the standard output of a command can be directly connected to the standard input of another command instead of a file, and this operation is called a pipe. A pipe is described on the command line by separating a series of commands with a pipe symbol “|”. A series of commands connected by a pipe is called a pipeline.

For example, in order to obtain a list of files on a general-purpose computer, the user can use a keyboard or the like to
$ ls /
(The $ at the beginning of the line is displayed as a prompt symbol from the beginning, indicating that it is waiting for user input.)
(Ls is a command that displays file and directory information on Unix OS systems)
(/ Indicates the highest level of the character string indicating the position in the file system)
And so on.

As a result
bin etc initrd.img lib64 media proc sbin tmp vmlinuz
boot lib libx32 mnt root srv usr dev home
lib32 lost + found opt run sys var
You can receive a file list display. The display here shows an example in the Linux (registered trademark) OS.

In addition, the user can use a pipe (function to connect the standard output of one command to the standard input of the next command) on the shell in a Unix-like operating system, for example,
$ jot -r 1000000 0 65535 | paste -d ''--\
awk '{print $ 1, "^ 2 +", $ 2, "^ 2 <65535 ^ 2"}' \
| bc | grep 1 | wc -l | awk '{print $ 1, "/ 125000"}' | bc? l

(On the shell, you can instruct the use of the pipe by connecting the commands in order using the symbol "|". The output of the command placed before the pipe is the same as the input of the command after the pipe. Become.)
(The \ symbol at the end of a line indicates that the newline is ignored and the next line is directly followed by one line.)
(Jot outputs a group of numerical values according to a certain rule. When this argument is specified, 1000000 numbers between 0 and 65535 are output continuously with line breaks.)
(Paste concatenates one or more files horizontally in units of lines. In this case, two numbers are taken out for each input of a space-separated numeric string, separated by a space, and a line break is inserted each time it is fetched. Work like.)

(Awk is a command that performs text processing according to the command statement. The first awk is “x ^ 2 + y ^ 2 <65536 ^ 2” based on two numerical values x and y entered in units of lines. Create a string that represents the formula.)
(Bc interprets the input string as a mathematical expression and displays the result. The first bc interprets the inequality “x ^ 2 + y ^ 2 <65536 ^ 2” and the inequality is satisfied. 1 when output, 0 otherwise.)
(Grep checks whether the input string contains the substring specified by the argument, and if it does, it prints the entire line. In this case, it displays only the line that contains 1.)
(Wc counts the number of lines in the input string. In this case, the number of lines input from the previous stage is displayed as a numerical value.)
(The second awk creates a string of “z / 125000” based on the input line value z.)
(The second bc displays the result of calculating “z / 125000” as a mathematical expression.)
(This series of commands is intended to derive an approximate value of the circumference by the Monte Carlo method.)
And so on.

As a result
3.14116000000000000000
Etc. can be received. In this case, an approximate value of the upper 4 digits of the circularity ratio 3.14159 ... was obtained.

  According to the existing configuration 1, operations and operations that cannot be achieved with one existing command can be achieved by describing the connection relation of the commands and adjusting the arguments. In other words, the user can program any operation on the general-purpose computer.

<Performance degradation in existing configuration 1>
When the shell (here called the parent shell, which is input by the user) receives and executes a command sequence connected by pipes as described above, there are usually as many child shells that execute only a single command as the number of commands. It is started as a process in parallel from the parent shell.
Next, these inputs and outputs are connected based on the connection relationship indicated by the pipe symbol “|”, and only the output result of the final command is displayed as the output of the parent shell.
Currently commonly used CPUs have a plurality of execution cores. Each child shell process may be assigned to a different core of the CPU and executed in parallel. When the number of commands exceeding the number of installed CPU cores is connected with a pipe, the time taken to occupy the CPU core is divided into time divisions among multiple child shell processes started as a result. In many cases, it is virtually executed in parallel.
Here, the mutual switching work of the processes that occupy the CPU core is called a context switch or the like, and during this work, the calculation is stopped for both the process before switching and the process after switching. When an environment where a large number of context switches occur, that is, when a command in which a large number of commands are pipe-connected to the number of mounted cores is issued, the execution speed is expected to be very slow.

Typically, pipes are duplicated as many as the number of pipes as a first-in-first-out (FIFO) type data structure and placed on the memory. Each child shell process reads data from the FIFO structure on the memory corresponding to the pipe connected to the input side, and writes the data to the FIFO structure on the memory corresponding to the pipe connected to the output side. The bus connecting the CPU and the memory is shared among the processes, and it appears that the processes are apparently operating in parallel by assigning access permission (time-division access) divided in time to each process. .
When the commands are connected by pipe connection, one set of processing for writing the memory of the preceding command and reading the memory of the succeeding command is generated for each connection, and the capacity of one bus is divided and used.
Therefore, even when a sufficient number of CPU cores are provided for the number of piped commands, the transfer capability of one pipe is limited, and the execution speed is expected to be slow.

[Existing configuration 2]
The existing configuration 2 is a configuration in which an accelerator equipped with a reconfigurable arithmetic circuit is added.
The existing configuration 2 includes the following accelerator and the following accelerator card in addition to the existing configuration 1.
The accelerator is a known device (for example, FPGA) that can virtually configure a plurality of dedicated arithmetic circuits on the accelerator, typified by an FPGA or the like, and can partially reconfigure the arithmetic circuit during operation. It is.
The accelerator card is a known accelerator card on which peripheral circuits for exchanging data through a general-purpose bus equipped in a general-purpose computer are mounted.

  In the existing configuration 2, a single command is realized by an arithmetic circuit temporarily configured on the FPGA. In the file that defines the command, instead of an instruction group that directly executes the processing of the command on the CPU, configuration information (referred to as circuit configuration) of the arithmetic circuit that realizes the processing, installation processing of the arithmetic circuit, and deletion Processing is included.

In the above configuration, when the command is activated, the circuit configuration is written into the empty space of the FPGA through the expansion bus, and the arithmetic circuit is temporarily installed on the FPGA. At the same time, an input to the command is input to the arithmetic circuit through the expansion bus, and an output from the command is set to be taken out through the expansion bus. After the command is completed, the configuration information of the arithmetic circuit is deleted from the FPGA.
The existing configuration 2 maps the pipe on the memory as a FIFO structure. The process for connecting the commands is the same as in the existing configuration 1.

<Effects of existing configuration 2>
The existing configuration 2 can perform an operation using a dedicated operation circuit by pipeline processing optimized for data. For this reason, when an appropriate cost standard such as the same power and the same circuit area is fixed and compared, the calculation speed can often be significantly increased as compared with the processing by the CPU.
In the existing configuration 2, when command groups connected by pipes are executed, all the command groups are executed in parallel as long as there is sufficient free space in the FPGA. For this reason, a decrease in execution speed due to a context switch or the like can be suppressed. That is, the existing configuration 2 can improve the processing performance of a single command and can prevent the performance from being degraded due to parallel execution, compared to the configuration of only the CPU.

On the other hand, since the existing configuration 2 is similar to the existing configuration 1 in terms of pipe implementation, a large amount of memory access and a large number of data exchanges between the CPU and the FPGA via the expansion bus occur each time a command is piped. To do. This causes a decrease in execution speed due to the capacity of the bus between the CPU and the memory, as in the existing configuration 1.
Furthermore, in the existing configuration 2, the transfer capacity of the CPU expansion bus is often smaller than the transfer capacity between the normal CPU and the memory. For this reason, the exchange of data between the CPU and the FPGA becomes a bottleneck, and the execution speed may be further reduced as compared with the existing configuration 1.
(Embodiment)

FIG. 1 is a configuration diagram showing an arithmetic system according to an embodiment of the present invention.
As shown in FIG. 1, the arithmetic system 100 loads a CPU 110 as a host, a memory 120 for storing data, an auxiliary storage device 130 (external storage device) for storing a partial circuit configuration group, and a partial circuit configuration group. Then, an FPGA accelerator 140 (accelerator device) that can dynamically reconfigure the arithmetic circuit, an expansion bus 150 that connects them, an input device 160, and a support device 170 are provided.

<CPU110>
The CPU 110 executes the program, and when a function or the like for which the partial circuit configuration is prepared is called in the program, the support device 170 is activated, and the partial circuit configuration group 130A prepared in advance in the auxiliary storage device 130. Is sent to the support device 170. In addition, the CPU 110 executes shell software that realizes the control method of the support device 170.

<Memory 120>
The memory 120 temporarily stores calculation target data 120A.
The operation target data 120A temporarily stored in the memory 120 is written to the FPGA accelerator 140 through the expansion bus 150, and the result is similarly retrieved through the expansion bus 150. However, as shown in FIG. 1, one input of the operation target data 120 </ b> A is transmitted to the FPGA accelerator 140 through the expansion bus 150 (see the symbol h in FIG. 1), and the operation result on the operation circuit on the FPGA accelerator 140. Is returned to the CPU 110 (see symbol j in FIG. 1).

<Auxiliary storage device 130>
The auxiliary storage device 130 compiles and stores in advance a command or program group on the CPU 110 in a format that can be introduced at an arbitrary position in the partial reconstruction area. As shown in FIG. 1, the auxiliary storage device 130 stores a partial circuit configuration group 130A created in advance. Here, the partial circuit configuration group 130A is the partial circuit configurations A to D.

<FPGA Accelerator 140>
The FPGA accelerator 140 is connected to the CPU 110 via the expansion bus 150.
The FPGA accelerator 140 is an FPGA that can dynamically reconfigure the arithmetic circuit by loading the net 170A connected to the partial circuit configuration group 130A set by the support apparatus 170. In the case of FIG. 1, the FPGA accelerator 140 includes partial reconfiguration areas (1) to (9).

The FPGA accelerator 140 performs one-dimensional mapping of the partial reconstruction areas (1) to (9) set by the support apparatus 170 and the front and rear partial reconstruction areas one by one by the data path 141 (symbol i in FIG. 1). In the FIFO type data structure (hereinafter referred to as a hardware pipe as appropriate) connected to, all target commands are activated in parallel to execute processing.
The FPGA accelerator 140 converts the shape of the reconstruction area map that is configured in advance on the FPGA by the support apparatus 170 into a FIFO-type data structure with one input and one output for each partial reconstruction area. Let it be a “dynamic reconfiguration area chain” interconnected so that the inputs are in one line in order.

  That is, the FPGA accelerator 140 preconfigures the shape of the reconstruction area map on the FPGA by the support device 170. The reconstruction area map configured in advance on the FPGA has a FIFO type data structure of one input and one output for each partial reconstruction area, and they are interconnected so that they are sequentially arranged in one column. Dynamic reconfiguration area chain ”. As indicated by symbol h in FIG. 1, in this dynamic reconfiguration area chain, one input is input to the partial reconfiguration area (1) via the expansion bus 150, and one output is output from the partial reconfiguration area (1). Is input to one partial reconstruction area (2) (see symbol i in FIG. 1), and one output from the partial reconstruction area (2) is input to one input partial reconstruction area (3). The FIFO type data structure is repeated in the following order, and one output of the partial reconfiguration area (9) is output to the CPU 110 via the expansion bus 150 (see symbol j in FIG. 1).

<Extended bus 150>
The expansion bus 150 is a connection bus that interconnects the CPU 110, the memory 120, the auxiliary storage device 130, and the FPGA accelerator 140 (accelerator device).
However, it differs from the arithmetic system 10 of FIG. 6 in the number of data input / output through the expansion bus 150. In other words, the arithmetic system 100 transmits one input of data to be operated to the FPGA accelerator 140 via the expansion bus 150 (see symbol h in FIG. 1), and then the FPGA accelerator connected by the dynamic reconfiguration area chain. The operation is performed by the operation circuit 140, and finally one output of the result is returned to the CPU 110 (see symbol j in FIG. 1).

<Input device 160>
The input device 160 displays a command line prompt on the display unit and accepts a command input on the command line.
The input device 160 provides the user with an interface similar to the original shell. The input device 160 receives a program input from a user in a shell one-liner format. A one-liner is a combination command in which commands are connected by a pipe symbol “|” and expressed in one line.
Here, there are many programming languages and environments that can program operations using a general-purpose computer. In the present embodiment, a one-liner for a shell, which is software that provides an interactive interface to a user in a Unix-based OS, is used.

  In addition to the one-liner to the shell, a language characterized by a description method for connecting the output of a function or the like to the next function in one direction may be used. For example, Elixir, which is one of programming languages, may be used. Elixir can use a pipeline operator for description, and can connect the result of a function call as the first argument of the next function call. Elixir can be used like a one-liner to the shell.

  When programming by a one-liner to the shell, a partial circuit configuration for FPGA is prepared in units of commands that are called and used from the shell or the like by a Unix-based OS. As the command, only a command provided by the OS may be used, or a command designed by the user himself / herself may be registered. The registration method in that case depends on the shell. The command registration is typically performed by an operation of adding a command location to a shell environment variable.

<Support device 170>
The support device 170 maps the input command to a partial reconfiguration area that is a partial reconfigurable area of the FPGA accelerator 140 and controls the partial reconfiguration areas to be connected by a data path. It is. In this embodiment, this shell software is executed by the CPU 110.
The support device 170 replaces the pipe symbol in the one-liner type (one-liner type) with a hardware pipe. Specifically, the support device 170 provides the user with an interface similar to the original shell on the CPU 110, but when a one-liner-type command is input from the input device 160, the commands before and after the pipe are changed to the FPGA. It is controlled so that it is mapped to two areas connected by the hardware pipes inside.

  When a pipe instruction that is an instruction for connecting output data of a command as input data of the next command is issued, the support device 170 maps the previous command to the previous partial reconfiguration area and sends the subsequent command to the subsequent command. Are connected in such a way that they are mapped to a partial reconstruction area and the preceding and following partial reconstruction areas are arranged in a line without branching by a data path (for example, one-dimensional connection by one data path). After the mapping and the connection are repeated for all pipe instructions, the input of the head command is introduced from the CPU 110, and the output of the end command is returned to the CPU 110.

The support apparatus 170 instructs the FPGA accelerator 140 to perform an operation by calling an external program corresponding to the command name of the input command.
When the number of commands connected by the pipe instruction is smaller than the number of dynamic reconfiguration chains prepared on the FPGA, the support device 170 inserts a bypass command after the final stage command and performs a pipe connection to perform dynamic reconfiguration. The number of chains is the same as the number of piped commands.

Hereinafter, the operation of the arithmetic system 100 configured as described above will be described.
<Preparation>
The command used on the Unix-based OS uses a command precompiled into a file including a circuit configuration, a configuration setting process, an erasing process, and the like, as in the existing configuration 2 described above.
However, the input / output to the command is not directly connected to the expansion bus 150 that connects the CPU 110 and the FPGA accelerator 140, but is input from one FIFO type data structure (hardware pipe) and output to one hardware pipe. Set to the form to perform.
In parallel with this, one command is defined which only passes the previous input to the subsequent output and does nothing else. Since this is not explicitly called by the user, a name or the like is not necessary, but it is called a bypass command, for example.

As shown in FIG. 1, the area where the arithmetic circuit on the FPGA accelerator 140 is introduced is divided into partial reconfiguration area groups (partial reconfiguration areas (1) to (9)) that can dynamically reconfigure them. Prepared as a reconstruction chain structure connected by hardware pipes connecting the partial reconstruction regions (1) to (9).
The partial reconfiguration areas (1) to (9) in the dynamic reconfiguration area chain structure can accommodate any one of the precompiled circuit configurations described above with respect to an arbitrary partial reconfiguration area. Set the area.
In order to achieve this condition, for example, each precompiled circuit group is considered to have a unique circuit shape, but a partial reconfiguration region using a shape that takes a common part of all the circuit groups. (1) to (9) may be configured.
Along with this, a circuit configuration is introduced to the position of any designated partial reconfiguration area.

The hardware pipe that inputs to the partial reconfiguration area (1) at the beginning of the dynamic reconfiguration area chain structure connects the input from the CPU 110 to the FPGA accelerator 140 through the expansion bus 150 (reference numeral in FIG. 1). h). Similarly, a hardware pipe that performs output from the terminal partial reconfiguration area (9) is connected as an output from the FPGA accelerator 140 through the expansion bus to the CPU 110 (see symbol j in FIG. 1).
Here, the arrangement of the hardware pipe itself is also realized as a part of the circuit configuration to the FPGA accelerator 140, and is set so that, for example, a program for introducing the circuit configuration is automatically started when the OS is started. Thus, preparation can be completed without waiting for an instruction from the user.

<Description of operation>
2A and 2B are diagrams for explaining the operation of the computing system 100. FIG. 2A is a command line indicating input to the shell, FIG. 2B is a block of the support device 170 that is software that provides the shell, and FIG. The connection of the partial reconfiguration | reconstruction area | region on the FPGA accelerator 140 is shown. In addition, the same code | symbol is attached | subjected to the same component as FIG.
The input device 160 (see FIG. 1) receives a program input from the user in a shell one-liner format.
After the command prompt “>”, the user inputs the command line shown in the frame in FIG. 2A into the shell, and after entering the command, presses enter to execute the command. . In this embodiment, a program input is received from the user in a shell one-liner format. The user describes a series of commands separated by a pipe symbol “|”.

  In the example of FIG. 2, after inputting the command “$ jot -r 1000000 0 65535” (see symbol a1 in FIG. 2), the command “paste -d ''--” (denoted in FIG. 2) is separated by the pipe symbol “|”. a2). Similarly, enter the command "awk '{print $ 1," ^ 2 + ", $ 2," ^ 2 <65535 ^ 2 "}'" (see symbol a3 in FIG. 2) separated by "|" A command “bc” (see symbol a4 in FIG. 2) is input separated by “|”, and a command “grep 1” (see symbol a5 in FIG. 2) is input separated by “|”. Then, enter the command “wc -l” (see symbol a6 in FIG. 2) separated by “|”, and delimit the command “awk '{print $ 1," ^ 2 + ", $ 2," ^ 2 <65535 ^ 2 "} '" (see symbol a7 in Fig. 2), and finally enter the command "bc?" (See symbol a8 in Fig. 2) separated by "|" and press Enter to enter the command Execute. As shown in FIG. 2A, eight commands (see symbols a1-a8 in FIG. 2) are connected in order using the symbol “|”, and the output of the command placed in front of the pipe is directly used as the pipe. It becomes the input of the command after.

  2B, the support apparatus 170 replaces the pipe symbol “|” of the input command shown in FIG. 2A with a hardware pipe, and connects the configuration group to the network 170A (FIG. 1). As a reference), it is written (loaded) into the FPGA accelerator 140. Here, as indicated by reference numeral l in FIG. 2B, the support apparatus 170 maps the input command to the partial reconstruction areas (1) to (9) of the FPGA accelerator 140, and the partial reconstruction area. Control is performed so that the data paths 141 connect the intervals (1) to (9). That is, control is performed so that the commands before and after the pipe of the input command are mapped to the front and rear partial reconfiguration areas connected by the hardware pipe in the FPGA accelerator 140. Specifically, it is as follows.

  The command “$ jot -r 1000000 0 65535” shown in FIG. 2A (see symbol a1 in FIG. 2) is introduced into the partial reconfiguration area (1) of the FPGA accelerator 140 shown in FIG. The command “paste -d '′--” shown in FIG. 2 (a) (see symbol a2 in FIG. 2) is introduced into the partial reconfiguration area (2) of the FPGA accelerator 140 shown in FIG. 2 (c). Next, the command “awk '{print $ 1," ^ 2 + ", $ 2," ^ 2 <65535 ^ 2 "}'" (see reference a3 in FIG. 2) shown in FIG. The command “bc” (see symbol a4 in FIG. 2) shown in FIG. 2A is introduced into the partial reconfiguration area (3) of the FPGA accelerator 140 shown in c), and the FPGA accelerator 140 shown in FIG. It is introduced into the partial reconstruction area (4). Similarly, all of the commands shown in FIG. 2A are introduced into the partial reconfiguration area of the FPGA accelerator 140. As shown in FIG. 2A, since the number of commands is 8, the command “bc?” Shown in FIG. 2A (see symbol a8 in FIG. 2) is the final stage, and FIG. Are introduced into the partial reconfiguration area (8) of the FPGA accelerator 140 shown in FIG.

  In the present embodiment, the FPGA accelerator 140 has nine partial reconstruction areas (1) to (9), so that the number of commands is eight for the nine partial reconstruction areas (1) to (9). Thus, one partial reconstruction area (9) remains. However, since the pipe connection needs to take the dynamic reconfiguration area chain configuration, the bypass command is introduced into the partial reconfiguration area after the final stage command (here, the partial reconfiguration area (9)), and the dynamic reconfiguration is performed. Make the number of configuration area chains the same as the number of commands connected by pipes.

  In addition to mapping to the partial reconstruction areas (1) to (9), the partial reconstruction areas before and after (1) to (9) between the partial reconstruction areas are connected one-dimensionally by one data path 141. The (dynamic reconfiguration area chain) configuration is adopted. 2C, one input is input to the partial reconstruction area (1) on the FPGA accelerator 140, and one output of the partial reconstruction area (1) is the partial reconstruction area ( 2) (see symbol i in FIG. 2), one output of the partial reconstruction area (2) is input to the partial reconstruction area (3), and the FIFO type data structure is repeated in the following order, and the partial reconstruction area One output of (9) is output from the FPGA accelerator 140 (see symbol j in FIG. 2).

A single command is realized by an arithmetic circuit temporarily configured on the FPGA accelerator 140. After the command is completed, the configuration information of the arithmetic circuit is deleted from the FPGA accelerator 140.
In the arithmetic system 100, pipes are implemented by hardware pipes on the FPGA accelerator 140, and all the hardware pipes operate in parallel. By doing so, the number of times the input / output data passes through the expansion bus 150 can be suppressed to at most once. For this reason, it is possible to suppress a decrease in execution speed resulting from data exchange between the CPU 110 and the FPGA accelerator 140.

<Operation flowchart>
FIG. 3 is a flowchart showing the operation of the support device 170 (shell software). The shell software is executed by the CPU 110 in FIG.
Processing starts when a command character string is received.
In step S11, the CPU 110 sets the maximum command reception number N and the current reception number n. For example, the maximum command reception number N = 9 and the current reception number n = 0 are set.
In step S12, it is determined whether or not the command character string has reached the end.
When the command character string has not reached the end (step S12: No), in step S13, the CPU 110 determines whether or not the current reception number n is equal to the maximum command reception number N (n = N).
If the current received number n is not equal to the maximum command received number N (step S13: No), in step S14, the CPU 110 displays a command character until a pipe symbol “|” appears in the input command or the end of the character string appears. Read a column.

In step S15, the current acceptance number n is increased (incremented) by 1, and the command read into the partial configuration area n is introduced, and the process returns to step S12.
The processes in steps S11 to S15 will be described with reference to FIG.
As shown in FIG. 2C, the partial reconstruction areas (1) to (9) are configured on the FPGA accelerator 140. Therefore, the maximum command reception number N = 9 is set. If n = N is not satisfied in step S13, the following processing is repeated until the command character string reaches the end in step S12.

  For example, first, the command “$ jot -r 1000000 0 65535” shown in FIG. 2A (see symbol a1 in FIG. 2) is entered in the partial reconfiguration area (1) of the FPGA accelerator 140 shown in FIG. The command "paste -d ''--" (see symbol a2 in FIG. 2) shown in FIG. 2 (a) is introduced into the partial reconfiguration area (2) of the FPGA accelerator 140 shown in FIG. 2 (c). Is done. 2C, one input is input to the partial reconstruction area (1) on the FPGA accelerator 140, and one output from the partial reconstruction area (1) is partially reconstructed. It is input to the area (2) (see symbol i in FIG. 2). Thereafter, the same processing is repeated, and when the command character string reaches the end in step S12, the process exits from this loop and proceeds to step S17. In the example of FIG. 2, since the number of commands is 8, the command “bc?” Shown in FIG. 2A (see symbol a8 in FIG. 2) is the final stage, and the FPGA accelerator shown in FIG. 140 is introduced into the partial reconstruction area (8), and one output of the partial reconstruction area (8) is input to the partial reconstruction area (9), and the process proceeds to step S17.

  Returning to the flow of FIG. 3, in step S13, the CPU 110 determines that the current command number n is equal to the maximum command command number N (step S13: Yes). In step S16, the CPU 110 exceeds the limit of command connections. Is displayed and the process ends (waits for the next command). The case where the number of commands connected exceeds the limit is when the number of commands connected by pipes is larger than the number of dynamic reconfiguration chains prepared on the FPGA. In this case, the user is notified that the operation is impossible by an error message or the like, and the processing of this flow is terminated.

On the other hand, when the command character string has reached the end in step S12 (step S12: Yes), the process proceeds to step S17. In step S <b> 17, the CPU 110 determines whether or not the current reception number n is equal to the maximum command reception number N (n = N).
If the current acceptance number n is not equal to the maximum command acceptance number N (step S17: No), the CPU 110 increments the current acceptance number n by 1 (increment) in step S18, and then sends a bypass command to the partial configuration area n. After introducing (inserting), the process returns to step S17. For example, in the case of FIG. 2, since the number of commands is 8 for the partial reconstruction areas (1) to (9) on the FPGA accelerator 140, the partial reconstruction area (partial reconstruction area (partial reconstruction area ( In 9)), the bypass command is introduced so that the number of dynamic reconfiguration area chains is the same as the number of commands connected by pipes.

When the current number n of receptions is equal to the maximum number N of command receptions (step S17: Yes), the process proceeds to step S19.
In step S19, the CPU 110 operates in parallel the command group introduced to all the partial reconstruction areas.
In the case of FIG. 2, the command group introduced into the partial reconfiguration areas (1) to (9) in the dynamic reconfiguration area chain is operated in parallel, and the output 1 of the partial reconfiguration area (9) as the operation result The book is output from the FPGA accelerator 140 (see symbol j in FIG. 2).
In step S20, the operation is paused until all the commands are finished. When all the commands have been operated, the process of this flow is terminated (waiting for the next command).

  Thus, in the above flow, when the shell software receives an input command, first, the number of commands connected by pipes is larger or smaller than the number of dynamic reconfiguration area chains prepared on the FPGA accelerator 140. Or the same. If the number of commands is larger than the number of dynamic reconfiguration area chains, the user is notified by an error message or the like that the operation is impossible, and the process ends.

If the number of commands connected by pipes is smaller than the number of reconfiguration chains above, the appropriate number of bypass commands are introduced (inserted) after the last stage command and connected by pipes. Ensure that the number is the same as the number of commands connected by pipes.
The inserted bypass command is used when the partial reconfiguration area where the last command is written in the input command sequence is different from the partial reconfiguration area at the end of the dynamic reconfiguration area chain. By writing to the configuration area, the data is bypassed to the end and finally returned to the CPU through the hardware pipe at the end.

Next, the parent shell starts a child shell that executes only each single command separated by pipes. However, it is instructed to introduce circuit configurations in order from the start point of the dynamic reconfiguration area chain in the order of the connected commands.
Finally, the input from the parent shell is connected to the hardware pipe at the beginning of the dynamic reconfiguration area chain, and the result output from the hardware pipe at the end is presented to the user as a standard output.

  As described above, the computing system 100 (see FIG. 1) according to the present embodiment displays the command line prompt and receives the command input on the command line, and the input command is transmitted to the FPGA. A support device 170 that maps to the partial reconstruction area of the accelerator 140 and controls the partial reconstruction areas to be connected by a data path.

When a pipe instruction that is an instruction for connecting output data of a command as input data of the next command is issued, the support device 170 maps the previous command to the previous partial reconfiguration area and sends the subsequent command to the subsequent command. After mapping to the partial reconfiguration area and connecting the front and rear partial reconfiguration areas in a line without branching by the data path, repeating the mapping and the connection for all pipe instructions, The input of the command at the head is introduced from the CPU 110, and the output of the command at the end is returned to the CPU 110.
The FPGA accelerator 140 has a FIFO type data structure in which the partial reconstruction areas set by the support device 170 and the preceding and following partial reconstruction areas are linked one-dimensionally by one data path 141 (see FIG. 1). , Start all target commands in parallel and execute processing.

  In this embodiment, pipes are implemented by hardware pipes on the FPGA, and all the hardware pipes operate in parallel. In this embodiment, similar to the above-described existing configuration 2, high-speed computation using a dedicated computation circuit and complete parallel execution of command groups can be obtained.

Further, as indicated by reference characters h and j in FIG. 1, the number of times that the input / output data passes through the expansion bus 150 can be limited to at most one time, and therefore, between the CPU and the FPGA, which was the problem of the existing configuration 2 described above. Execution speed reduction due to data exchange can be suppressed.
That is, according to the present embodiment, the problem that the above-described existing configuration 1 has is solved, and a dedicated arithmetic circuit is provided as in the above-described existing configuration 2 while presenting the same interface as the shell to the user. It is possible to obtain the effect of suppressing the execution speed reduction by reducing the number of memory accesses, and the high-speed arithmetic used, the parallel execution of the arithmetic group.

In addition to the above effects, the present embodiment has the following effects.
<Maintaining programming methods>
A user inputs a program as a one-liner type command group to the arithmetic system 100 (see FIG. 1). The one-liner of a shell using a pipe can be said to be an environment where programming is originally performed using only a unidirectional data flow by a pipe, and it is easy to map the result to a reconstruction chain.
At this time, the user can perform programming in the same manner as the one-liner execution on the CPU 110 (see FIG. 1) without being aware of the connection relationship information of the partial reconfiguration area group of the equipment to be used.
Note that since a command exceeding the size of the dynamic reconfiguration area chain configured in the FPGA accelerator 140 in advance cannot be connected, the support apparatus 170 needs to pay attention only to the maximum number of command connections that differ depending on the equipment.

<Improvement of FPGA usage efficiency>
The arithmetic system 100 (see FIG. 1) has a dynamic reconfiguration because the processing data path 141 (see FIG. 1 and FIG. 2) is a straight line as indicated by the symbols h, i, and j in FIGS. Of the hardware pipes included in the area chain, the actual usage ratio is high, and the utilization efficiency of the FPGA accelerator 140 is improved.
In particular, in a UNIX-based OS, “manufacturing with a single function and high efficiency” can be cited as a design concept of a command that is often used. Not all commands are created based on this idea, but the complexity of the internal processing of commands created with this guideline is likely to be the same, and even when they are converted into partial circuit configurations, the circuit scale is too large. It is likely that they tend to approach a certain value.

  When the partial circuit config size difference between commands is small and relatively uniform, the surplus ratio can be kept small when introduced into a partial reconfiguration area in accordance with their maximum size. As a result, there is an increased possibility that a larger number of partial reconfiguration areas can be taken on the FPGA accelerator 140 of the same scale. This means that the condition that “a command exceeding the size of the dynamic reconfiguration area chain previously configured in the FPGA cannot be connected” can be relaxed by increasing the number of dynamic reconfiguration area chains. It is possible to provide the user with a feeling of use close to that at the time of execution.

FIG. 4 is a diagram for explaining that the FPGA accelerator 140 can be used without surplus areas when the partial circuit configuration scale between commands is uniform.
As shown in FIG. 4A, the command group 41 having a uniform circuit scale is introduced into the partial reconfiguration areas (1) to (6) shown in FIG. 4B. The partial reconfiguration areas (1) to (6) are designed so as to accommodate the command group 41 having a uniform circuit scale. As shown in FIG. 4B, the command group 41 having a uniform circuit scale is introduced into the partial reconfiguration areas (1) to (6) without surplus areas. Since there are few surplus parts, the utilization efficiency of the FPGA accelerator 140 can be improved.

Of the processes described in the above embodiment, all or part of the processes described as being performed automatically can be performed manually, or the processes described as being performed manually can be performed. All or a part can be automatically performed by a known method. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.
Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured.

  Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Further, each of the above-described configurations, functions, and the like may be realized by software for interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function is stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), an IC (Integrated Circuit) card, an SD (Secure Digital) card, an optical disk, etc. It can be held on a recording medium.

100 computing system 110 CPU (host)
120 memory 130 auxiliary storage device (external storage device)
130A Partial circuit configuration group 140 FPGA accelerator (accelerator device)
141 Data path 150 Expansion bus 160 Input device 170 Support device

Claims (7)

A CPU serving as a host; an external storage device for storing a partial circuit configuration group; an accelerator device capable of dynamically reconfiguring an arithmetic circuit by loading the partial circuit configuration group; and a bus connecting them An arithmetic system,
An input device that displays a command line prompt and accepts commands entered on the command line;
A support device that maps an input command to a partial reconfiguration area that is a partial reconfigurable area of the accelerator device and controls the partial reconfiguration areas to be connected by a data path. ,
The support device includes:
When a pipe instruction, which is an instruction for connecting the output data of the command as input data of the next command, is issued, the previous command is mapped to the previous partial reconfiguration area, and the subsequent command is mapped to the subsequent partial Map to the reconfiguration area, connect the preceding and subsequent partial reconfiguration areas so that they are aligned in a line without branching by the data path, repeat the mapping and the connection for all pipe instructions, and then start The command input to be introduced from the CPU, the output of the terminal command is set back to the CPU,
The accelerator device includes:
In the FIFO type data structure in which the mapping of the partial reconstruction area set by the support apparatus and the preceding and following partial reconstruction areas are connected in a line without branching by a data path, all target commands are processed in parallel. A computing system characterized by starting up and executing processing. The external storage device is
The computing system according to claim 1, wherein the command or program group on the CPU is compiled and stored in advance in a format that can be introduced at an arbitrary position in the partial reconfiguration area. The support device includes:
The arithmetic system according to claim 1, wherein the arithmetic operation is instructed to the accelerator device by calling an external program corresponding to the command name of the input command. The accelerator device includes an FPGA (Field Programmable Gate Array),
The shape of a reconstruction area map that is configured in advance on the FPGA by the support device is a FIFO type data structure of one input and one output for each partial reconstruction area, and the output and the input The arithmetic system according to claim 1, wherein the dynamic reconfiguration area chains are interconnected so that and are sequentially arranged in one line. The support device includes:
When the number of commands connected by the pipe instruction is smaller than the number of the dynamic reconfiguration chains prepared on the FPGA, a bypass command is inserted after the final stage command to connect the dynamic reconfiguration chain. The arithmetic system according to claim 4, wherein the number of commands is the same as the number of piped commands. A CPU serving as a host; an external storage device for storing a partial circuit configuration group; an accelerator device capable of dynamically reconfiguring an arithmetic circuit by loading the partial circuit configuration group; and a bus connecting them A method for controlling an arithmetic system,
An input device that displays a command line prompt and accepts commands entered on the command line;
A support device that maps an input command to a partial reconfiguration area that is a partial reconfigurable area of the accelerator device and controls the partial reconfiguration areas to be connected by a data path. And
The support device includes:
When a pipe instruction, which is an instruction for connecting the output data of the command as input data of the next command, is issued, the previous command is mapped to the previous partial reconfiguration area, and the subsequent command is mapped to the subsequent partial Map to the reconfiguration area, connect the preceding and subsequent partial reconfiguration areas so that they are aligned in a line without branching by the data path, repeat the mapping and the connection for all pipe instructions, and then start Execute the step of setting the command input to be from the CPU and setting the output of the command to be terminated to the CPU,
The accelerator device includes:
In the FIFO type data structure in which the mapping of the partial reconstruction area set by the support apparatus and the preceding and following partial reconstruction areas are connected in a line without branching by a data path, all target commands are processed in parallel. A control method for an arithmetic system, characterized in that the process is started and executed. CPU as host, external storage device for storing partial circuit configuration group, accelerator device capable of dynamically reconfiguring arithmetic circuit by loading partial circuit configuration group, and input command, accelerator device A computer for a computing system comprising: a support device that maps to the partial reconstruction area and controls the partial reconstruction areas to be connected by a data path,
When a pipe instruction, which is an instruction for connecting the output data of the command as input data of the next command, is issued, the previous command is mapped to the previous partial reconfiguration area, and the subsequent command is mapped to the subsequent partial Map to the reconfiguration area, connect the preceding and subsequent partial reconfiguration areas so that they are aligned in a line without branching by the data path, repeat the mapping and the connection for all pipe instructions, and then start A program for functioning as control means for setting a command to be input from the CPU and setting the output of the terminal command to the CPU.

Images