JP3609958B2 - Power converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power converter that connects two or more outputs of an inverter having a switching element to obtain variable frequency, variable voltage multiphase AC power.
[0002]
[Prior art]
As a conventional control device for an AC motor such as an induction motor that is controlled at a variable speed, a voltage multiplex inverter device of a PWM control system shown in FIG. 11 is known.
The voltage multiplex inverter device shown in FIG. 11 is composed of two single-phase inverters 11 connected in series as one phase, and is composed of an inverter having a configuration in which three sets are star-connected, and drives a motor 12.
[0003]
FIG. 12 shows a single-phase inverter.
As shown in FIG. 12, the single-phase inverter is composed of a DC power supply 15 and a single-phase bridge inverse converter 16, and supplies AC with a desired voltage and frequency by PWM control.
[0004]
Switching of individual elements of each single-phase inverter 11 shown in FIG. 11 is performed, for example, in U1 shown in FIG. The carrier wave b shifted by .degree. Is compared with the voltage reference Vuref and controlled by the resulting gate pulses e and f.
[0005]
In addition, as a method for obtaining a switching signal of each single-phase inverter in a multiplex inverter, pages 125 and 126 of “Semiconductor Power Conversion Circuit” (published by the Institute of Electrical Engineers / Ohm Company) and US Pat. No. 4,674,024 are disclosed. As described in US Pat. No. 5,625,545, a phase shift circuit 14-7 is used to shift the phase of a carrier signal with respect to other single-phase inverters, and each element of each single-phase inverter is A method of using a control circuit 14 that provides a PWM circuit and outputs a gate pulse is generally used.
[0006]
FIG. 13 shows an output voltage waveform.
According to FIG. 13, the output voltages U1 and U2 of the two single-phase inverters are switched alternately, and a waveform closer to a sine wave is obtained overall than the output voltage waveform of one single-phase inverter. It has been.
In FIG. 11, an example in which there are two single-phase inverters corresponding to one has been described, but it is apparent that more improved results can be obtained with three or more inverters.
[0007]
[Problems to be solved by the invention]
However, in the conventional control method of a multiple inverter configured as described above, it is necessary to add a PWM circuit and a phase shift circuit for each switching element. There's a problem.
[0008]
Also, in general, in a multiplex operation with a single-phase inverter, when one single-phase inverter fails, the output of the single-phase inverter is short-circuited, and power is supplied to the load only with the other single-phase inverter in a bypass state. Can do. However, if the phase shift circuit is left as it is in the control circuit and only one single-phase inverter is bypassed, the output voltage harmonics increase because the output of the bypassed single-phase inverter is not reflected in the output voltage. To do.
[0009]
Therefore, in view of the above problems, the present invention aims to simplify and miniaturize the PWM circuit applied to each element of the apparatus, and to obtain an output voltage waveform that does not increase harmonics even when operated in a bypass state.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is a power converter that connects two or more outputs of inverters each having a plurality of switching elements to obtain variable frequency, variable voltage multiphase AC power. the switching of the switching elements of the respective phases of the inverter, is provided for each phase, and one of the pulse width modulation circuit to match the carrier phase at each phase of each inverter, gates output from the pulse width modulation circuit And a control means for controlling by a distribution circuit for determining to which switching element of each inverter the pulse is distributed.
[0011]
Further, the invention according to claim 2 is characterized in that the distribution circuit comprises means for storing the switching generation order of the switching elements of each inverter and the current switching state and sequentially switching the switching elements. .
[0012]
Furthermore, the invention according to claim 3 is a power conversion device that obtains variable frequency, variable voltage multiphase AC power by connecting two or more outputs of a single-phase inverter each having a plurality of switching elements in series. A pulse width modulation circuit that matches a carrier wave phase in each phase of each inverter, a voltage reference conversion circuit that converts a voltage reference so as to be capable of pulse width modulation with a carrier wave having a single phase and amplitude, and The switching sequence of each switching element in each single-phase inverter and the current switching state are stored, and switching is performed for the longest period among the elements that have been switched in the opposite direction to the change in the output voltage due to the change in the output voltage. And a distribution circuit that outputs a gate pulse output from the pulse width modulation circuit to an element that has not been provided.
[0013]
The invention according to claim 4 includes a circuit for distributing gate pulses to other single-phase inverters other than the single-phase inverter in the bypass state, in order to use one of the plurality of single-phase inverters as a bypass state. It is characterized by that.
[0014]
According to a fifth aspect of the present invention, there is provided a power converter for obtaining a multi-phase AC power having a variable frequency and a variable voltage by connecting a plurality of three-phase inverters, and providing a carrier phase for each inverter. One pulse width modulation circuit that matches each phase, a voltage reference conversion circuit that converts a voltage reference so as to perform pulse width modulation with a single phase and amplitude carrier wave, and switching of the switching element of each three-phase inverter The generation order and the current switching state are stored, and the pulse is applied to the element that has not been switched for the longest period among the elements that have been switched in the opposite direction to the change in the output voltage due to the change in the output voltage. And a distribution circuit that outputs a gate pulse output from the width modulation circuit.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the structure elements of the embodiment shown in FIG. 1, the same components as FIG. 11, the description thereof will be given the same numbers will be omitted. The difference from FIG. 11 is that the voltage reference conversion circuit 18-converts the voltage reference so that the pulse width modulation control can be performed by a single carrier wave and a single comparison circuit in the gate pulse control circuit 14 () 1 of each inverter. 1, a PWM circuit 18-2 composed of a single carrier wave and a single comparison circuit, and a control circuit 18 constituted by a distribution circuit 18-3. Hereinafter, the description will be made on behalf of the U phase, but the same applies to the V and W phases.
[0017]
The voltage reference conversion circuit 18-1 converts and outputs the voltage reference for the voltage reference Vuref so that PWM control can be performed by a single carrier wave and a single comparison circuit based on the voltage level to be output by the phase.
[0018]
2 and 3 show the concept of the correspondence between the voltage levels of the outputs of the multiple inverters in which the voltage level of the output of the phase is 5 levels from -2 to +2, and the conversion of the voltage reference. Here, the voltage reference is normalized from -1 to +1.
[0019]
FIG. 2 shows the carriers C1 to C4 with respect to the voltage reference before conversion.
As shown in FIG. 3, in the present embodiment, the voltage reference is converted so that the amplitude of the carrier wave is from −1 to +1 in consideration of the relative relationship between the voltage reference and the carrier wave. For example, as shown in FIG. 2, when the voltage reference is in the range of 0 to +1/2, a phase voltage having a pulse width determined from the relationship between the carrier wave and the voltage reference can be obtained. In order to output the same pulse width using the single carrier wave shown in FIG. 3, the following conversion is performed.
[0020]
Eu = (Vuref-1 / 4) × 4 (1)
Eu: The U-phase voltage reference after conversion and other regions are similarly converted as follows.
[0021]
If the voltage reference is in the range of +1/2 to +1,
Eu = (Vuref−3 / 4) × 4 (2)
If the voltage reference is in the range of -1/2 to 0,
Eu = (Vuref + 1/4) × 4 (3)
If the voltage reference is in the range of -1 to -1/2,
Eu = (Vuref + 3/4) × 4 (4)
The converted voltage reference is PWM-controlled by the PWM circuit 18-2 and outputs a gate pulse.
[0022]
The distribution circuit 18-3 determines the element m to be switched next, outputs a gate pulse p to the determined element, and outputs a gate pulse to the other elements so as to continue the previous switching state. To do.
[0023]
Next, the operation of the distribution circuit 18-3 in the multiple inverter in which at least two single-phase inverters are connected in series will be described in detail.
FIG. 4 shows a detailed view of the distribution circuit 18-3 of the power conversion device.
[0024]
First, the voltage level 1 of the phase voltage to be output from the voltage reference is determined by the output voltage level determination circuit 20 according to the magnitude of the voltage reference, as shown in FIG.
Next, the switching element selection circuit 21 determines the element m to be switched next from the voltage level l. The switching element selection circuit 21 includes a single-phase inverter selection circuit 22 and a single-phase inverter internal element selection circuit 23.
[0025]
As shown in FIG. 5, the single-phase inverter selection circuit 22 prepares first-in first-out queues 24a, 24b, and 24c for voltage levels -1 to +1 that can be output from the single-phase inverter. Each single-phase inverter belongs to one queue from each output state. At this time, the queues 24a, 24b, and 24c also have information on the order in which the voltage levels have changed.
[0026]
The phase output voltage level is the sum of the outputs of these single phase inverters. For example, FIG. 5 shows that U1 and U2 belong to the level 0 queue 24b, and U1 has been level 0 first. The phase output voltage level is 0.
[0027]
The single-phase inverter selection circuit 22 receives the voltage level 1 of the phase voltage to be output from the output voltage level determination circuit 20, and compares it with the current output voltage level before switching, which can be seen from the queue state, and the output voltage level is higher. In this case, the output level of the leading single-phase inverter at the lowest level of the queue is increased by 1, and the output voltage level of the phase is increased. In this way, the single-phase inverter q to be switched is determined.
[0028]
Next, the operation of the single-phase inverter element selection circuit 23 will be described.
The element selection circuit 23 in the single-phase inverter determines an element to be switched with respect to the single-phase inverter q that changes the voltage level determined by the single-phase inverter selection circuit 22.
[0029]
FIG. 6 shows the switching state of each element and its transition with respect to the output voltage level of the single-phase inverter. The numbers indicate the output voltage level of the single-phase inverter. + And-in 0 indicate the states of the two arms in the single-phase inverter, + indicates that the upper element is turned on, and-indicates that the lower element is turned on. Represents that There are four switching states 26a, 26b, 26c, and 26d. There are two types of switching states 26a and 26c in which the output voltage level of the single-phase inverter is 0.
[0030]
In the present embodiment, in order to disperse the switching of the elements, the switching state is stored as a flag when the previous level was 0 level, and the element to be switched next is determined. For example, when FLG = 0 and the output voltage level of the inverter changes from +1 to 0, the switching element is selected so that the next state is 26b. Conversely, when FLG = 1, the switching element is selected so as to be 26c. The same applies when the output voltage level changes from −1 to 0. In this way, the switching element m is determined.
[0031]
For the elements not selected, the previous switching signals e ′, f ′, g ′, and h ′ are continuously output from the states of the queues 24a, 24b, and 24c.
The gate pulse allocation circuit 25 outputs the gate pulse p output from the PWM circuit 18-2 to the element m selected by the switching element selection circuit 21, and the switching element selection circuit 21 to other elements. The previous switching signals e ′, f ′, g ′, and h ′ output from are output.
[0032]
As described above, in the first embodiment, in a multiple inverter in which two single-phase inverters are connected in series for each phase, one PWM circuit 18-2 and a distribution circuit 18-3 for distributing gate pulses are used. It can be controlled and the circuit configuration can be made compact. Further, among the single-phase inverters that can realize the change of the output voltage level using the cue 24a, 24b, 24c , each single-phase is controlled by a control method for switching the single-phase inverter that has not changed the output state for the longest period. Since switching of the inverter can be distributed, switching loss can be balanced.
[0033]
Two single-phase inverters are connected in the same way as described in the above case, but when three or more multiple connections are made, the number of single-phase inverters stored in the queues 24a, 24b, and 24c can be increased. Can be processed.
[0034]
Therefore, one PWM circuit and gate pulse distribution circuit can be used to control each element of a multiple inverter connecting two or more single-phase inverters, reducing the number of parts and balancing the switching loss of each element. Can be taken.
[0035]
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. The main circuit configuration is the same as in FIG. In the constituent elements of the embodiment shown in FIG. 7, the same constituent elements as those in FIG.
[0036]
A difference from FIG. 4 is that an initialization circuit 27 for queues 24 a, 24 b, and 24 c is added to the single-phase inverter selection circuit 22.
Since the single-phase inverter that performs switching is performed by shifting the level of this queue, if the information is not included in the queue, a switching signal is not sent and a bypass state is possible. In the same manner, a plurality of single-phase inverters can be bypassed at the same time.
Therefore, one or more single-phase inverters can be bypassed, and hardware changes such as PWM circuit changes are not required.
[0037]
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS.
In the constituent elements of the embodiment shown in FIG. 8 and FIG. 9, the same constituent elements as those in FIG. 1 and FIG.
[0038]
As shown in FIG. 8, the power converter is a double inverter in which two sets of three-phase inverters are coupled by reactors 28a and 28b.
The difference from FIG. 1 is that the main circuit configuration is changed from a series connection of single-phase inverters to a parallel connection of three-phase inverters, and a gate pulse signal line is different in the control circuit 18.
[0039]
The difference from FIG. 4 is that the configuration of the switching element selection circuit 21 is different. In the switching element selection circuit 21 of FIG. 9, for the three-phase inverter, the switching is controlled by the three-phase inverter switching element selection circuit 29.
[0040]
Similar to the single-phase inverter, in order to store the past switching state, a queue as shown in FIG. 10 is also considered for the three-phase inverter. In the three-phase inverter, each phase arm has only two states, positive and negative, and queues 30a and 30b are prepared in each state. The output state of each phase of the three-phase inverter is placed in one of these queues. The output voltage level of the phase is an average value obtained by adding these.
[0041]
The switching element selection circuit 21 receives the output voltage level l of the phase to be output from the output voltage level determination circuit 20, and compares the output voltage level with the current output voltage level determined from the queue state. When the voltage level to be output is high, switching of the inverter at the head of the negative queue 30b is made positive, and the output voltage level of the phase is raised. Conversely, when the voltage level to be output is low, the switching of the leading inverter of the positive queue 30a is made negative to lower the phase output voltage level. In this way, the element m to be switched is determined.
[0042]
As described above, in the third embodiment, in the multiple inverter in which two three-phase inverters are connected in parallel, the control can be performed by using one PWM circuit 18-2 and the circuit 18-3 for distributing the gate pulse. Can be made compact. In addition, among the three-phase inverters that can realize the change in the output voltage level using the queues 30a and 30b, the switching of the three-phase inverters can be distributed by the control method of switching the three-phase inverters that have been switched in the past. Although the case of duplexing the three-phase inverter has been described above, the same processing can be performed by increasing the number of three-phase inverters stored in the queues 30a and 30b when the multiplexing of triple or more is performed.
[0043]
Therefore, one PWM circuit and gate pulse distribution circuit can be used to control each element of a multiple inverter that connects two or more three-phase inverters, reducing the number of parts and balancing the switching loss of each element. Can be taken.
[0044]
【The invention's effect】
As described above, according to the present invention, the PWM circuit applied to each element of the apparatus can be simplified and miniaturized, and an output voltage waveform that does not increase harmonics even when operated in a bypass state can be obtained.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention.
FIG. 2 is a schematic diagram showing an output voltage level and a voltage reference with respect to a voltage reference before conversion in the first embodiment of the present invention.
FIG. 3 is a schematic diagram showing an output voltage level and a voltage reference with respect to a voltage reference after conversion in the first embodiment of the present invention.
FIG. 4 is a schematic configuration diagram showing a single-phase inverter gate pulse control circuit according to the first embodiment of the present invention.
FIG. 5 is a conceptual diagram showing a queue for determining a single-phase inverter to be switched in the first embodiment of the present invention.
FIG. 6 is a conceptual diagram showing state transition for determining a switching element in the first embodiment of the invention.
FIG. 7 is a schematic configuration diagram showing a second embodiment of the present invention.
FIG. 8 is a schematic configuration diagram showing a third embodiment of the present invention. FIG. 9 is a schematic configuration diagram showing a three-phase inverter gate pulse control circuit in the third embodiment of the present invention.
FIG. 10 is a conceptual diagram showing a queue for determining a three-phase inverter to be switched in a third embodiment of the present invention.
FIG. 11 is a schematic configuration diagram showing a conventional multiple inverter device of a multiple PWM control system.
12 is a schematic configuration diagram showing the single-phase inverter shown in FIG. 11. FIG.
FIG. 13 is a waveform diagram showing output waveforms of the multiple inverter shown in FIG.
DESCRIPTION OF SYMBOLS 11 ... Single phase inverter, 12 ... AC motor, 14, 18 ... Control circuit, 15 ... DC power supply, 16 ... Single phase reverse bridge reverse converter, 18-1 ... Voltage reference conversion circuit, 18-2 ... PWM circuit, 18 -3 ... distribution circuit, 20 ... output voltage level determination circuit, 21 ... switching element selection circuit, 22 ... single-phase inverter selection circuit, 23 ... single-phase inverter internal element selection circuit, 24a, 24b, 24c ... first-in first-out for single-phase inverter Queue of system, 25 ... gate pulse allocation circuit, 26a, 26b, 26c, 26d ... single-phase inverter switching state, 27 ... queue initialization circuit, 28a, 28b ... coupled reactor, 29 ... three-phase inverter switching element selection circuit, 30a , 30 ... First-in first-out queue for three-phase inverter.

Claims (5)

Connect two or more outputs of inverters each having multiple switching elements, variable frequency,
In a power converter that obtains variable-voltage multiphase AC power,
The switching of the switching elements of the respective phases of the inverter, is provided for each phase, the transport
One pulse width modulation circuit for matching the wave phase in each phase of each inverter ;
The gate pulse output from this pulse width modulation circuit is applied to which switch of each inverter .
Control means for controlling by a distribution circuit for determining whether to distribute to the chucking element ;
A power conversion device comprising: 2. The power converter according to claim 1, wherein the distribution circuit includes means for storing the switching generation order of the switching elements of each inverter and the current switching state, and sequentially switching the switching elements. In a power converter that obtains multi-phase AC power of variable frequency and variable voltage by connecting two or more outputs of single-phase inverters each having a plurality of switching elements in series,
One pulse width modulation circuit that is provided for each phase and matches the carrier phase in each phase of each inverter ;
A voltage reference conversion circuit for converting a voltage reference to be capable of pulse width modulation with a single phase and amplitude carrier; and
The switching sequence of each switching element in each single-phase inverter and the current switching state are stored, and switching is performed for the longest period among the elements that have been switched in the opposite direction to the change in the output voltage due to the change in output voltage. A power conversion apparatus comprising: a distribution circuit that outputs a gate pulse output from the pulse width modulation circuit to an element that has not been provided. 6. A circuit for distributing a gate pulse to other single-phase inverters other than the single-phase inverter in the bypass state in order to use one of the plurality of single-phase inverters as a bypass state. 3. The power conversion device according to 3. In a power converter that connects multiple three-phase inverters to obtain variable frequency, variable voltage multiphase AC power,
One pulse width modulation circuit that is provided for each phase and matches the carrier phase in each phase of each inverter ;
A voltage reference conversion circuit for converting a voltage reference to be capable of pulse width modulation with a single phase and amplitude carrier; and
The switching sequence of the switching elements of each of the three-phase inverters and the current switching state are stored, and the longest period among the elements that have been switched in the direction opposite to the change of the output voltage due to the change of the output voltage A power conversion device comprising: a distribution circuit that outputs a gate pulse output from the pulse width modulation circuit to an element that has not been switched.

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