JP3248321B2 - Control circuit of three-level inverter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a three-level inverter in which an output voltage takes three states of positive, negative and zero, and more particularly, to a control circuit at a neutral point (intermediate potential point) of a DC power supply circuit of the inverter. The present invention relates to a control circuit for suppressing potential fluctuation.

[0002]

2. Description of the Related Art In recent years, three-level inverters have attracted attention because they can relatively easily realize high voltage and large capacity and have small output harmonics. FIG. 23 shows a basic circuit of this three-level inverter. In FIG. 23, E _DC is a DC power supply, C ₁ and C ₂ are DC input capacitors, P is a positive potential point, N is a negative potential point, and 0 is neutral. Points, G _U1 , G _U2 , G _X1 , G _X2 ,
G _V1 , G _V2 , G _Y1 , G _Y2 , G _W1 , G _W2 , G _Z1 , G _Z2 are semiconductor switching elements made of GTO, D _U0 , D _X0 , D _V0 , D
_Y0 , _DW0 , and _DZ0 are coupling diodes, and M is an AC motor such as an induction motor.

Here, the switching elements G _U1 , G _U2 ,
A series circuit composed of G _X1 and G _X2 and G _V1 , G _V2 , G _Y1 and G _Y2
A series circuit consisting of the two ends of the series circuit consisting of _{G W1, G W2, G Z1} , G Z2 is connected to a positive potential point P and a negative potential point N of the DC power supply circuit. Further, an interconnection point of the switching elements G _U2 and G _X2, an interconnection point of G _V2 and G _Y2 ,
The interconnection point of G _W2 and G _Z2 is connected to AC motor M as an inverter output terminal. Further, the coupling diodes D _U0 , D _X0 , D _V0 , D _Y0 , D _W0 , D _Z0 are connected to the neutral point 0 and the switching elements G _U1 , G _U2 , G _X1 , G _X2 , G _V1 , G _V2 , G
It is connected between the interconnection points of _Y1 , _GY2 , _GW1 , _GW2 , _GZ1 and _GZ2 , respectively. The flywheel diode is not shown for convenience.

In the three-level inverter having the above configuration, there is a period during which the neutral point 0 is connected to the AC motor M via the switching element and the diode due to the switching pattern. It is known that the neutral point potential may fluctuate at three times the fundamental frequency of the inverter depending on the neutral point current (Tanamachi, et al., "Method of suppressing AC fluctuation of neutral point voltage of three-level inverter") No. 91 of the 1992 IEEJ National Industrial Application Conference
reference). Also, this neutral point current has a DC component under specific conditions, and in that case, the neutral point potential may be greatly biased to positive or negative (see Sawada et al.
WM Inverter "1991 IEEJ National Convention NO. 5
33). Such a change in the neutral point potential may cause excessive voltage application to the switching element.

As one method for preventing the above-mentioned inconvenience, a conventional technique described below (Shimamura et al., "Equilibrium Control of DC Input Capacitor Voltage of NPC Inverter", SPC-91-37, IEEJ Semiconductor Power Conversion Study Group) There is. FIG. 24 shows a capacitor voltage balancing control circuit described in the above document, and FIG. 25 shows a three-level inverter controlled by the control circuit.

The operation is briefly described in FIG.
From the capacitor voltages E _D1 and E _{D2 of} FIG.
Creating a _ED, the signal S _ED retrieve a DC component signal S _EDI through a first-order lag filter. Further, the signals S _ED and S
Create an AC component signal S _EAI from _EDI . Also, based on the inverter output active / reactive power P _M1 , Q _M1 detected by the active / reactive power detection circuit 101 and the inverter output frequency (command) F _I from the current control circuit 103, the polarity determination circuit 102 switches the polarity. _{Produce the} signal P _OL1 .

On the other hand, the DC component signal S _EDI and the AC component signal S _EAI are respectively multiplied by feedback coefficients K _DI and K _AI , and a compensation amount S _BI1 which is the sum thereof is a switch controlled by a polarity switching signal P _OL1. The polarity is converted as needed by 104 to generate a final compensation amount S _BI2 . This compensation amount S _BI2 is added to each phase output voltage command V _UI1 ^* , V _VI1 ^* , V _WI1 ^* of the inverter from the current control circuit 103, and the final output voltage command V _UI2 ^* , V _VI2 ^* , V _WI2 ^*

These output voltage commands V _UI2 ^* , V _VI2 ^* , V
By controlling the inverter based on _WI2 ^*, unbalanced capacitor voltage E _D1, E _D2 can be eliminated, variations in the neutral point potential can be suppressed in other words. In FIG. 25, L _S is a DC reactor, D _U1 , D _U2 , D _X1 , D _X2 , D
_V1 , _DV2 , _DY1 , _DY2 , _DW1 , _DW2 , _DZ1 , and _DZ2 denote flywheel diodes, and IM denotes an induction motor.

In the prior art, as is apparent from FIG. 24, in order to generate the polarity switching signal _POL1 , each phase voltage e _UI , e _VI , e _WI and current i _UI , i _VI , i _VI of the electric motor IM are generated.
_WI is detected. This is for determining whether the operation mode of the motor IM is the drive mode (power factor> 0) or the braking mode (power factor <0). The determination of the operation mode is based on the polarity of the DC component of the neutral point current. Is different in the drive / brake mode, and the polarity must be considered and added to the voltage command value.

[0010]

The above prior art has the following problems. In the state of power factor = 0 (completely no load), no _matter how much the compensation amount S _BI2 is added, no DC component of the neutral point current is generated, and the control itself is invalidated. At the time of light load near power factor = 0, the drive / brake mode is disabled due to errors in the instrument transformer and current transformer that detect the motor voltage and current, and the difficulty of current detection due to current pulsation. It is difficult to make an accurate determination, and there is a high possibility that the polarity switching signal _POL1 is also switched. When the polarity switching signal P _OL1 is switched, the polarity of the compensation amount S _BI2 is changed, so that the compensation polarity is also opposite to the original one, and there is a possibility that the unbalance of the capacitor voltage is promoted.

At the time of a light load near the power factor = 0, the signal S after multiplication by the feedback coefficients K _DI and K _AI in FIG.
The ratio of the magnitude of the DC component of the neutral point current generated by these to the magnitudes of _DI1 and _SAI1 becomes small, and the control effect becomes poor. To improve this, the feedback coefficient K _DI ,
Even if K _AI is increased, there is an upper limit to the voltage that can be output by the inverter, and thus there is a limit to this method. As a result, there is a limit to the control at a light load, for example, the control cannot be effectively performed at a power factor of 0.2 or less.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. It is an object of the present invention to enable control even under no load or light load to balance the voltage of a DC input capacitor, An object of the present invention is to provide a three-level inverter control circuit capable of protecting circuit elements such as switching elements.

[0013]

To achieve the above object, a control circuit according to the first invention is connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. A DC power supply circuit having a DC input capacitor,
Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and an interconnection point of the second and third semiconductor switching elements is connected to an inverter output terminal. Respectively, a first coupling diode is connected between the interconnection point of the first and second semiconductor switching elements and the neutral point, respectively, and the interconnection of the third and fourth semiconductor switching elements is In a three-level inverter in which a second coupling diode is connected between a connection point and the neutral point, an inverter is connected according to an output power factor of the inverter.
Phase order of output voltage command and inverter basic frequency
Means for changing the phase difference from the harmonic, and using the phase difference
Means to generate even harmonics of inverter fundamental frequency
And the even-order harmonics generated by this means to the neutral point
Output voltage of each phase of the inverter with a magnitude corresponding to the potential fluctuation of
Means for adding to the command .

The control circuit according to a second aspect of the present invention includes a first balance control unit that adds an even-order harmonic of an inverter fundamental frequency to each phase output voltage command of the inverter, and the control circuit based on the potential change at the neutral point. Means for determining the magnitude of the even-order harmonic, second balance control means for adding a DC component to the output voltage command for each phase of the inverter, and magnitude of the DC component based on the potential fluctuation at the neutral point. and means for determining, and means Ru is operated by selecting either one of the first or the second balance control unit according to the output power factor of the inverter a.

A control circuit according to a third aspect of the invention is based on a means for adding an even-order harmonic of an inverter fundamental frequency to each phase output voltage command of the inverter, and a polarity of a current flowing through the neutral point. Means for determining the magnitude of the even-order harmonic.

[0016] The control circuit according to a fourth aspect of the present invention is a control circuit , wherein each phase output voltage command of the inverter is controlled in accordance with the output power factor of the inverter.
The phase difference between the inverter and the even harmonic of the inverter fundamental frequency
Means for controlling the inverter fundamental frequency using the phase difference.
Means for generating an even number of harmonics, and
Generated even harmonics to the polarity of the current flowing through the neutral point
Add to the output voltage command for each phase of the inverter according to the size
That and means.

A control circuit according to a fifth aspect of the present invention includes a first balance control means for adding an even-order harmonic of an inverter fundamental frequency to each phase output voltage command of the inverter, and a control circuit based on a polarity of a current flowing through the neutral point. Means for determining the magnitude of the even-order harmonic, a second balance control means for adding a DC component to each phase output voltage command of the inverter, and the DC power supply based on the polarity of the current flowing through the neutral point. Means for determining the magnitude of the component;
Or select one of the second balance control means
And means for Ru is operated.

[0018]

First, the characteristics of the DC component of the neutral point current will be obtained when the output voltage command of the inverter includes a DC component or an AC component (n-th harmonic component of the inverter fundamental frequency). FIG. 19 shows the PW used for this analysis.
The method of M is shown, in which a firing pulse for the switching element is generated by comparing the voltage command signal with the triangular carrier to obtain an inverter output phase voltage as shown.

[0019] Now, "1" in the period of the output phase voltage of the inverter is 0, it defines a switching function S _NX becomes "0" during the period of + E _D1 or -E _D2, carrier frequency than the inverter output frequency Assuming that it is sufficiently high, the carrier frequency component is ignored and S _NX is defined by Equation 1.

[0020]

S _NX = 1− {λ sin θ + d + kλ sin n (θ−α)} (0 ≦ θ ≦ π) = 1 + {λ sin θ + d + kλ sin n (θ−α)} (π ≦ θ ≦ 2π)

Where: λ: modulation rate (peak value of voltage command) d: magnitude of DC component k: constant value α: phase difference between inverter output voltage command and nth harmonic component n: 1 , 2, 3, 4, 5,...

The neutral point current i _N ′ for one phase flows only during the period when the inverter output phase voltage is 0, and can be expressed by Equation 2.

[0023]

[Equation 2] i _N ′ = S _NX・ i _M

In the equation (2), i _M : motor current (= √2I _M sin (θ−φ)) I _M : motor current effective value φ: power factor angle

When the above equation 2 is expanded to a Fourier series,
Equation 3 is obtained. In Expression 3, A _mc and A _ms are coefficients.

[0026]

(Equation 3)

Here, the DC component A ₀ ′ included in the neutral point current i _N ′ for one phase is obtained by classifying as follows. (1) When the voltage command includes a DC component d (k = 0 in Equation 1). In this case, the DC component A ₀ ′ is obtained as in Expression 4.

[0028]

(Equation 4)

(2) A case where the voltage command includes an odd harmonic (d = 0, n = 1, 3, 5,... In Equation 1). In this case, the DC component A ₀ ′ is represented by Equation 5, that is, 0.

[0030]

A ₀ '= 0

(3) When the voltage command includes an even harmonic (d = 0, n = 2, 4, 6,... In Equation 1). In this case, the DC component A ₀ ′ is obtained as in Expression 6.

[0032]

(Equation 6)

Next, the DC component A ₀ ′ will be considered. When the voltage command includes a DC component, | A ₀ '| becomes cosφ when the magnitude d of the DC component is a constant value according to Expression 4.
, And becomes maximum when the power factor (cos φ) = ± 1, and the polarity of the DC component A ₀ ′ changes depending on the driving / braking mode. When the voltage command includes an odd harmonic, the DC component A ₀ ′ is 0 according to Expression 5.

When the voltage command includes an even-order harmonic, the properties differ depending on the phase difference α between the voltage command and the n-th harmonic component. That is, in Equation 6, if k is a constant value, | A ₀ '
Is proportional to sinφ when α = 0 or α = π / n [rad] (A ₀ ′ is proportional to sinφ when α = 0, α = π / n
[Rad], and becomes the maximum when the power factor = 0, and the polarity is the same regardless of the driving / braking mode. Also, if k is a constant value, | A ₀ '|
Is proportional to cos φ when ± π / (2n) [rad] (A ₀ ′ is proportional to −cos φ when α = π / (2n) [rad],
When α = −π / (2n) [rad], it is proportional to cos φ), so that it becomes maximum when the power factor = ± 1, and its polarity changes depending on the driving / braking mode.

Here, the relationship between the phase difference α and the polarity of the even-order harmonic will be described. Assuming that an even-order harmonic having a phase difference α is X and an even-order harmonic having a phase difference α- (π / n) [rad] is Y, the relationship of Expression 7 is established from the definition of the phase angle. That is, the even-order harmonic X of the phase difference α and the phase difference are α− (π / n).
It has a polarity opposite to that of the even-order harmonic Y of [rad].

[0036]

X = −Y

The DC component of the neutral point current (for three phases) is obtained as 3 · A ₀ ′ in any of the above-mentioned cases (1) to (3).

From the above analysis results, if a DC component or an even-order harmonic is added to the output voltage command of the inverter, the polarity of the DC component and the phase angle (polarity) of the even-order harmonic can be changed. It can be seen that a direct current component of the neutral point current can be generated in the direction, thereby suppressing a change in the neutral point current or a change in the neutral point potential. From such a point, in the prior art, the DC component is added to the output voltage command to generate a DC component in the neutral point current, thereby suppressing the fluctuation of the neutral point potential.

On the other hand, in the first and fourth inventions,
By adding an even-order harmonic of the inverter fundamental frequency to the inverter output voltage command, fluctuations in the capacitor voltage are suppressed. Here, the phase difference α is changed according to the output power factor of the inverter. That is, the phase difference α is changed according to Equation 8.

[0040]

Α = (1 / n) · φ−π / (2n)

In Expression 8, φ is the power factor angle as described above. The DC component A ₀ ′ of the neutral point current when the phase difference α is changed according to Equation 8 can be obtained by substituting Equation 8 into Equation 6. This is shown in Equation 9.

[0042]

(Equation 9)

FIG. 21A shows the DC component A ₀ ′ according to Equation 9 when the even order is second order (n = 2). Note that FIG.
In, the value of A ₀ ′ is normalized at φ = π / 4 [rad].

When the polarity of the even-order harmonic is opposite,
By subtracting π / n from the phase difference α, Expression 10 is obtained.
By substituting 0 into Equation 6, the DC component A ₀ ′ of the neutral point current is obtained as shown in Equation 11.

[0045]

Α = (1 / n) · φ-3π / (2n)

[0046]

[Equation 11]

The DC component A ₀ ′ according to Equation 11 is shown in FIG.
It is shown in (b). From FIGS. 21 (a) and (b), the power factor cosφ
Even when = 0 (φ = π / 2 [rad]), since A ₀ ′ ≠ 0, suppression control is possible. The polarity of A ₀ ′ becomes the same in the driving / braking mode, and is even-ordered at the polarity corresponding to the voltage deviation of the two DC input capacitors of the inverter (or the polarity corresponding to the polarity of the neutral point current). Wave (phase difference α
(Variable according to the power factor), it can be seen that A ₀ ′ can flow in the direction of suppressing the fluctuation of the capacitor voltage.

Next, in the second and fifth aspects of the present invention, a method of suppressing the fluctuation of the capacitor voltage by adding an even harmonic of the fundamental frequency of the inverter to the output voltage command of the inverter, And the method of suppressing the fluctuation of the capacitor voltage by using the above-mentioned method according to the output power factor of the inverter. Here, even-order harmonic addition (phase difference α
= 0 or π / n [rad]) will be described in the following operation of the third invention.

When the DC component d is added to the output voltage command of the inverter, the DC component A ₀ ′ of the neutral point current is proportional to −cos φ when the polarity of the DC component d to be added is positive, and Is proportional to cosφ. Therefore, if the DC component d is added with a polarity corresponding to the difference between the driving / braking modes and the voltage deviation of the two DC input capacitors of the inverter (or a polarity corresponding to the polarity of the neutral point current), the capacitor voltage can be reduced. The DC component A ₀ ′ of the neutral point current can be caused to flow in a direction to suppress the fluctuation.

When the DC component d is added, control becomes impossible when the power factor = 0. Therefore, for example, when the power factor angle φ ≦ π / 4 [rad] or φ ≧ (3π) / 4 [rad], the DC component d is added, and π / 4 [ra
d] ≦ φ ≦ (3π) / 4 [rad], even-order harmonics are added. The state of the DC component A ₀ ′ of the neutral point current in this case is shown in FIG. FIG. 22 (a),
From (b), power factor cosφ = 0 (φ = π / 2 [rad])
In this case, since A ₀ ≠ 0, suppression control is possible.
In FIG. 22, A ₀ ′ is φ = 0, π and φ = π / 2.
And has been normalized by

When it is desired to flow the positive polarity A ₀ ′ (FIG. 22)
In (a)), according to the power factor angle φ, if φ ≦ π / 4, a DC component d is added (d <0). If π / 4 ≦ φ ≦ (3π) / 4, even-order harmonics are added. Addition (α = 0) If φ ≧ (3π) / 4, the DC component d may be added (d> 0). When it is desired to flow the negative polarity A ₀ ′ (FIG. 9B), if φ ≦ π / 4, the DC component d is added (d> 0) according to the power factor angle φ. If .ltoreq..phi..ltoreq. (3.pi.) / 4, add even-order harmonics (.alpha. = 0). If .phi..gtoreq. (3.pi.) / 4, add DC component d (d <0).

Further, in the third invention, the output voltage command of the inverter includes an even-order harmonic (phase difference α) of the fundamental frequency of the inverter.
= 0 or π / n [rad]).
Suppress fluctuations in capacitor voltage. That is, according to Equation 6, the DC component A ₀ ′ has an even-order harmonic (second harmonic) in the same phase as the output voltage command (α = α) as shown in FIG.
0) is proportional to + sinφ, and FIG.
As shown in the figure (α = π / n = π / 2 [rad])
Is proportional to -sinφ. Therefore, if even-order harmonics are added at a polarity (in-phase or opposite-phase) corresponding to the polarity of the neutral point current, the DC component A ₀ ′ can flow in a direction to suppress the fluctuation of the capacitor voltage.

In the third aspect, the DC component A ₀ ′ is
Since it is proportional to sinφ or −sinφ, it becomes maximum when the power factor = 0, and its polarity becomes the same in both the driving / braking modes. This makes it possible to perform effective capacitor voltage balancing control regardless of the operation mode even under no load or light load.

[0054]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block diagram showing a first embodiment of the first invention. In the figure, the control circuit 201, the voltage of the DC input capacitor (capacitor C _1, C ₂ in FIG. 23) E _D1, E
An adder 11 to which _D2 is input and a deviation S from the adder 11
Controller 12 such as P controller and PI controller to which ₁ is input
And the phase angles θ _R ^* , θ _S ^* , θ
_The difference between _T ^* and the phase difference α is (θ _R ^* −α), (θ _S ^* −α),
Sin in which the value of sin (6θ) corresponding to (θ _T ^* −α) is stored
(6θ) and table 13, which is an output signal of the table ^{_{13 sin6 (θ R * -α)}} , sin6 (θ S * -α), sin6 (θ T * -
α) and the output signal S ₂ of the controller 12 are respectively multiplied by the multipliers 14 _R , 14 _S , and 14 _T, and the output signals of the multipliers 14 _R , 14 _S , and 14 _T are output to the inverter phase output voltage command v _R ^* , v _S ^* , v _T ^*
Are provided with adders 15 _R , 15 _S , and 15 _T respectively. Then, the outputs of the adders 15 _R , 15 _S , and 15 _T become final phase output voltage commands v _R ^** , v _S ^** , and v _T ^** .

Here, the reason why the sixth harmonic is selected as the even harmonic of the inverter fundamental frequency to be added to the inverter phase output voltage commands v _R ^* , v _S ^* , and v _T ^* will be described below. That is, 2, 4, 8, 10,... The next harmonic appears in the inverter line voltage because it is in reverse phase or positive phase.
6, 12, 24,... Since the next harmonic is in zero phase, it does not affect the inverter line voltage. Among them, the sixth harmonic is A
_{Since 0} 'is the largest, it is selected as an even harmonic to be added.

In the control circuit 201, reference numeral 16 denotes a power factor angle calculating means, which outputs inverter output phase voltages e _RI and e _RI .
_SI , e _TI and output currents i _RI , i _SI , i _TI (e _UI , e _VI , e _WI and output currents i _UI , i _UI in FIGS. 23 to 25)
_VI , _iWI ), the following operation is performed, for example, to obtain the output power factor angle φ of the inverter. That is, the output phase voltages e _RI , e _SI , and e _TI are three-phase to two-phase converted, and e
_α and _eβ are obtained. Here, e _α represents the α-axis component of the output phase voltage, and e _β represents the β-axis component. The α axis and β axis are axes in an arbitrary rectangular coordinate system. Next, the angle θ ₁ formed between the output phase voltage vector and the α-axis is obtained by Expression 12.

[0057]

[Equation 12] θ ₁ = tan ⁻¹ (e _β / e _α )

The output currents i _RI , i _SI ,
i _{TI is} also _subjected to three-phase to two-phase conversion to obtain i _α and i _β . Then i
_The rotation coordinate transformation shown in Expression 13 is performed on _α and i _β , and i
_M, determine the i _T. It should be noted that i _M represents the direction component of the output phase voltage vector of the inverter output current vector, and i _T represents the direction component orthogonal to the output phase voltage vector.

[0059]

I _M = i _α · cos θ ₁ + i _β · sin θ ₁ i _T = −i _α · sin θ ₁ + i _β · cos θ ₁

Finally, the output power factor angle φ of the inverter is obtained by Expression (14).

[0061]

## EQU14 ## φ = −tan ⁻¹ (i _T / i _M )

The power factor angle φ thus obtained is input to the phase angle calculating means 17. The phase angle calculating means 17 calculates the phase difference α by using Expression 15 obtained by setting n in Expression 8 to 6 corresponding to the sixth harmonic.

[0063]

Α = φ / 6−π / 12

The phase difference α is calculated by using the sin (6θ) table 13
Are subtracted from the phase angles θ _R ^* , θ _S ^* , θ _T ^* of the respective inverter output voltage commands by the adders 18 _R , 18 _S , 18 _{T at} the preceding stage, and the difference is input to the sin (6θ) table 13. It has been corresponding value ^{_{sin6 (θ R * -α),}} sin6 (θ S * -α), sin6
(θ _T ^* −α) will be output.

That is, in this embodiment, the phase difference α between the output voltage command and the even harmonic is changed according to the output power factor of the inverter, and the even harmonic is added to the original output voltage command. A final output voltage command for each phase is obtained, and the DC component A ₀ ′ of the neutral point current generated thereby is as shown in Expressions 9 and 11 above.

Next, FIG. 2 shows a second embodiment of the first invention. This embodiment does not use the one capacitor voltage E _D1 in the first embodiment, but has a constant value of E _DC / 2.
(E _DC : DC intermediate voltage of 3 level inverter (power supply voltage))
Is used as one input of the adder 11 instead of E _D1 , and the other is the same as in the first embodiment. According to this embodiment, since only one voltage detector is required, the circuit configuration can be simplified.

FIG. 3 shows a third embodiment of the first invention. In this embodiment, the constant value E _DC / 2 is used as one input of the adder 11 instead of E _D2 without using the other capacitor voltage E _D2 in the first embodiment. This is the same as the first embodiment. In this embodiment, the same effects as in the second embodiment can be obtained.

FIG. 4 shows a fourth embodiment of the first invention. This embodiment is based on the sin (6θ) table 1 of the first embodiment.
Instead of 3, the control circuit 202 is provided with a sin (2θ) table 19, and the rest is the same as the first embodiment. In this embodiment, the phase angle calculating means 17
Is α / 2−π / 4 [rad]
Becomes In this embodiment, ^* the inverter phase output voltage command ^{_{v R, v S *, v}} T * We chose the secondary harmonics as the even harmonics of the inverter fundamental frequency to be added to are as follows.

As described in connection with the first embodiment, the second harmonic appears in the inverter line voltage. However, if the application does not cause a problem even if a second harmonic appears in the line voltage (for example, an application in which a fan simply rotates), there is no problem even if the present invention is applied. It can be said. Moreover, as is apparent from Equation 6, when the second harmonic is used, the magnitude of the DC component A ₀ ′ is the largest among the even harmonics, so that the fluctuation suppression effect of the neutral point potential is also the largest. It is.

FIGS. 5 and 6 show the fifth and sixth embodiments of the first invention, respectively. In the second and third embodiments, FIGS.
sin (2θ) table 1 instead of sin (6θ) table 13
9 is used. In these embodiments, the same effects as in the second, third, and fourth embodiments can be obtained.

Next, FIG. 7 shows a first embodiment of the second invention. In FIG. 7, the adder 1 in the control circuit 203
1, controller 12, changeover switch 26, multiplier 14 _R , 1
The 4 _S , 14 _T and sin (6θ) tables 13 constitute first balance control means, and this balance control means
This substantially corresponds to the case where the phase difference α = 0 in the embodiment of FIG. In the embodiment shown in FIG. 7, the first balance control means and the second balance control means described below are selectively used in accordance with the power factor angle to balance the capacitor voltage.

The structure of the second balance control means is as follows. That is, the balance control means includes an adder 20 to which two DC input capacitor voltages E _D1 and E _D2 are input with the polarity shown in the figure, a P adjuster to which a deviation S _{3 as an} output thereof is input, and a PI adjuster. And the like, a switch 22 on the output side thereof, a polarity inverter 23 for switching the polarity of the output signal S ₄ of the controller 21, and a switch 24 on the output side. The inverter output phase voltages e _RI , e _SI , e _TI and the output currents i _RI , i _SI , i
_The drive / brake signal A and the balance control means switching signal B are generated by the power factor angle calculation means 25 to which _TI is input. 22,2
6 can be switched in conjunction with each other.

In the second balance control means, a deviation S ₃ between the capacitor voltages E _D1 and E _D2 is obtained, and an appropriate adjustment operation is performed by the controller 21 to obtain an output signal S ₄ . On the other hand, by switching the changeover switch 24 with the drive / brake signal A output from the power factor angle calculating means 25, the output signal S ₄
Can switch the polarity of the, here, as it is to thereby output the polarity of the output signal S ₄ in the drive mode (S ₅
= S ₄ ) In the braking mode, the polarity of the output signal S ₄ is inverted via the polarity inverter 23 and output (S ₅ = −S ₄ ).
Switch 24 is controlled as described above. The output signal S
₅ corresponds to the direct-current component d in the above mathematical expression 4.

The output signal S ₅ thus obtained is added to the adder 15 _R ,
15 _S, 15 _T phase output voltage command by v _R ^*, v _S ^*, added to v _T ^*, these new voltage command v _R ^**, v _S ^**, and v _T ^**. Tables 1 and 2 below show the relationship between each signal, the DC component A ₀ ′ of the neutral point current, and the capacitor voltage during driving and braking. In addition, Table 1 is for driving and Table 2 is for braking. From these tables,
Driving time, it can be seen that the flow DC component A ₀ 'so as to suppress the fluctuation in braking both capacitor voltage E _D1, E _D2.

[0075]

[Table 1]

[0076]

[Table 2]

The first and second balance control means include:
The changeover switch 22 by the balance control means changeover signal B,
Either one is selected by switching 26. The switching signal B is, for example, the switch 22 when the calculated power factor angle φ is in the range of φ ≦ π / 4 or φ ≧ (3/4) π.
The output signal S ₄ (S ₅ ) is output from each phase output voltage command v _R ^* , v _S
^* , v _T ^* and the output signal S ₂
Is set to 0. That is, the second balance control means is used.

When the calculated power factor angle φ is π / 4 ≦ φ ≦
(3/4) output signal by the changeover switch 22 when it is in the range of [pi S ₄ a (S ₅₎ is 0, the phase output voltage command output signal S ₂ by the changeover switch ^{_{26 v R *, v S *}} , Add to v _T ^* . That is, the first balance control means is used.
The method of calculating the power factor angle φ by the power factor angle calculating means 25 may be the same as the method of calculating by the calculating means 16 in FIG.

As described above, in this embodiment, a DC component or an even-order harmonic component is added to each phase output voltage command in accordance with the output power factor of the inverter, thereby suppressing the fluctuation of the capacitor voltage. A DC component A ₀ ′ of a neutral point current of an arbitrary polarity can flow.

FIG. 8 shows a second embodiment of the second invention. In this embodiment, one capacitor voltage E _D1 in the first embodiment is not used, and a fixed value E _DC / 2 is used as one input of the adders 11 and 20 instead of E _D1. Is the same as in the first embodiment. According to this embodiment, there is an advantage that one of the voltage detectors can be omitted. FIG. 9 shows a third embodiment of the second invention. This embodiment is different from the first embodiment in that the other capacitor voltage E _D2
Is not used, and a fixed value E _DC / 2 is used as one input of the adders 11 and 20 in place of E _D2 , and the other is the same as the first embodiment.

FIGS. 10, 11 and 12 show the fourth, fifth and sixth embodiments of the second invention, respectively. The sin (6θ) table 13 in the first, second and third embodiments is shown in FIGS. Instead, a sin (2θ) table 19 is provided in the control circuit 204, and the rest is the same as the first, second, and third embodiments.

Next, FIG. 13 shows a first embodiment of the third invention. This embodiment adds the even-order harmonic to the output voltage command with a polarity corresponding to the polarity of the neutral point current i _N of the three-level inverter, thereby suppressing the change in the capacitor voltage in the direction to suppress the fluctuation of the capacitor voltage. The DC component A ₀ ′ flows. In FIG. 13, a neutral point current i _N is input to a polarity inverter 27 in a control circuit 205 and output signal S
₁ is obtained. The controller 12 which receives the signals S ₁ suitable regulatory calculation is performed, it becomes the output signal S _2. This output signal S ₂ is multiplied by the output signal of the sin (6θ) table 13, and the result is multiplied by the original output voltage command v _R ^* ,
v _S ^* , v _T ^* and added to the final output voltage command v _R ^** , v _S
^**, v _T ^** can be obtained. The reason why the sixth harmonic is used as the even harmonic is as described above.

In this embodiment, when the polarity of the neutral point current i _N is positive, the polarities of the signals S ₁ and S ₂ become negative, and the phase difference α between the output voltage command of the inverter and the even harmonic is π. / 6
[Rad]. Therefore, the DC component A ₀ ′ of the neutral point current
Is proportional to −sin φ, and its polarity is negative. When the polarity of the neutral point current i _N is negative, the polarities of the signals S ₁ and S ₂ are positive, and the phase difference α between the output voltage command of the inverter and the even harmonic is zero. Therefore, the DC component A ₀ ′ of the neutral point current
Is proportional to sinφ, and its polarity is positive. This allows
The DC component A ₀ ′ flows in a direction to suppress the voltage fluctuation of the DC input capacitor.

FIG. 14 shows a second embodiment of the third invention, which is the same as the first embodiment except that the sin (6θ) table 13 in the first embodiment is changed to a sin (2θ) table 19.
The reason why the even-order harmonic is the second-order harmonic is as described above. In the figure, reference numeral 206 denotes a control circuit.

Next, FIG. 15 shows a first embodiment of the fourth invention. In the embodiment of FIG. 1, instead of detecting the capacitor voltages E _D1 and E _D2 , a neutral point current i _N is detected and a control circuit 2
The signal S ₁ is obtained by inverting the polarity by the polarity inverter 27 in 07. FIG. 16 shows the second aspect of the fourth invention.
This is an embodiment, and is the same as the first embodiment except that the sin (6θ) table 13 in the first embodiment is changed to a sin (2θ) table 19. In the figure, reference numeral 208 denotes a control circuit. Note that the operation of these embodiments is basically the same as the embodiment of the first invention and the like, and a description thereof will be omitted.

FIG. 17 shows a first embodiment of the fifth invention. In the embodiment of FIG. 7, instead of detecting the capacitor voltages E _D1 and E _D2 , a neutral point current i _N is detected. Signals whose polarities are inverted by the polarity inverters 27 and 28 are used as signals S ₁ and S ₃ . FIG.
This is a second embodiment of the present invention, wherein sin (6) in the first embodiment is used.
θ) table 13 is replaced with a sin (2θ) table 19, except that it is the same as in the first embodiment. In the figure, reference numeral 210 denotes a control circuit. The operation of these embodiments is basically the same as the embodiment of the second invention and the like, and the description thereof will be omitted.

[0087]

As described above, according to the present invention, it is possible to effectively suppress the imbalance of the capacitor voltage even at the time of complete no-load or light load, and to prevent application of an excessive voltage to the circuit element. . In addition, since the control polarity is not switched near the power factor = 0 in the capacitor voltage balancing control, there is no disadvantage that the capacitor voltage is unbalanced and promoted as in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the first invention.

FIG. 2 is a block diagram showing a second embodiment of the first invention.

FIG. 3 is a block diagram showing a third embodiment of the first invention.

FIG. 4 is a block diagram showing a fourth embodiment of the first invention.

FIG. 5 is a block diagram showing a fifth embodiment of the first invention.

FIG. 6 is a block diagram showing a sixth embodiment of the first invention.

FIG. 7 is a block diagram showing a first embodiment of the second invention.

FIG. 8 is a block diagram showing a second embodiment of the second invention.

FIG. 9 is a block diagram showing a third embodiment of the second invention.

FIG. 10 is a block diagram showing a fourth embodiment of the second invention.

FIG. 11 is a block diagram showing a fifth embodiment of the second invention.

FIG. 12 is a block diagram showing a sixth embodiment of the second invention.

FIG. 13 is a block diagram showing a first embodiment of the third invention.

FIG. 14 is a block diagram showing a second embodiment of the third invention.

FIG. 15 is a block diagram showing a first embodiment of the fourth invention.

FIG. 16 is a block diagram showing a second embodiment of the fourth invention.

FIG. 17 is a block diagram showing a first embodiment of the fifth invention.

FIG. 18 is a block diagram showing a second embodiment of the fifth invention.

FIG. 19 is an explanatory diagram of PWM used for analysis of the present invention.

FIG. 20 is a diagram showing a phase difference between a voltage command and an even harmonic in the third invention.

FIG. 21 is a diagram showing a DC component of a neutral point current in the first and fourth inventions.

FIG. 22 is a diagram showing a DC component of a neutral point current in the second and fifth inventions.

FIG. 23 is a basic circuit diagram of a three-level inverter.

FIG. 24 is a diagram showing a capacitor voltage balancing control circuit as a conventional technique.

FIG. 25 is a circuit diagram of a three-level inverter controlled by the control circuit of FIG. 24;

[Explanation of symbols]

_{11,15 R, 15 S, 15 T} , 18 R, 18 S, 18 T, 2
0 Adder 14 _R , 14 _S , 14 _T Multiplier 12, 21 Controller 13 sin (6θ) table 16, 25 Power factor angle calculating means 17 Phase angle calculating means 19 sin (2θ) table 22, 24, 26 Switch 23, 27, 28 Polarity inverters 201, 202, 203, 204, 205, 206, 2
07, 208, 209, 210 Control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 7/515 H02M 7/48 H02M 7/5387

Claims (5)

(57) [Claims] A first semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween; Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection points of the second and third semiconductor switching elements are connected to the inverter output terminals, respectively. First coupling diodes are respectively connected between the interconnection point of the second semiconductor switching element and the neutral point,
And a three-level inverter in which a second coupling diode is connected between the interconnection point of the third and fourth semiconductor switching elements and the neutral point, respectively, wherein the inverter according to the output power factor of the inverter Output of each phase
Phase between voltage command and even harmonics of inverter fundamental frequency
Means for changing the difference, and an even harmonic of an inverter fundamental frequency using the phase difference.
And an even harmonic generated by this means is supplied to the neutral point.
Output voltage command for each phase of inverter with magnitude corresponding to phase fluctuation
Control circuit of three-level inverter, characterized by comprising, a means for adding to. 2. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection points of the second and third semiconductor switching elements are connected to the inverter output terminals, respectively. First coupling diodes are respectively connected between the interconnection point of the second semiconductor switching element and the neutral point,
In addition, in a three-level inverter in which a second coupling diode is connected between the interconnection point of the third and fourth semiconductor switching elements and the neutral point, an inverter basic voltage is applied to each phase output voltage command of the inverter. First balance control means for adding even-order harmonics of frequency; means for determining the magnitude of the even-order harmonics based on the potential change at the neutral point; and DC for each phase output voltage command of the inverter. Second balance control means for adding a component, means for determining the magnitude of the DC component based on the potential change at the neutral point, and first or second balance control according to the output power factor of the inverter. control circuit of three-level inverter, characterized in that it comprises means for Ru is operated by selecting either one, the means. 3. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection points of the second and third semiconductor switching elements are connected to the inverter output terminals, respectively. First coupling diodes are respectively connected between the interconnection point of the second semiconductor switching element and the neutral point,
In addition, in a three-level inverter in which a second coupling diode is connected between the interconnection point of the third and fourth semiconductor switching elements and the neutral point, an inverter basic voltage is applied to each phase output voltage command of the inverter. Means for adding even-order harmonics of frequency, and means for determining the magnitude of the even-order harmonics based on the polarity of the current flowing through the neutral point. Control circuit. 4. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection points of the second and third semiconductor switching elements are connected to the inverter output terminals, respectively. First coupling diodes are respectively connected between the interconnection point of the second semiconductor switching element and the neutral point,
And a three-level inverter in which a second coupling diode is connected between the interconnection point of the third and fourth semiconductor switching elements and the neutral point, respectively, wherein the inverter according to the output power factor of the inverter Output of each phase
Phase between voltage command and even harmonics of inverter fundamental frequency
Means for changing the difference, and an even harmonic of an inverter fundamental frequency using the phase difference.
And an even harmonic generated by this means flows through the neutral point.
Output of each phase of the inverter with the magnitude corresponding to the polarity of the current
Means for adding to a voltage command, a control circuit for a three-level inverter. 5. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection points of the second and third semiconductor switching elements are connected to the inverter output terminals, respectively. First coupling diodes are respectively connected between the interconnection point of the second semiconductor switching element and the neutral point,
In addition, in a three-level inverter in which a second coupling diode is connected between the interconnection point of the third and fourth semiconductor switching elements and the neutral point, an inverter basic voltage is applied to each phase output voltage command of the inverter. First balance control means for adding even-order harmonics of frequency; means for determining the magnitude of the even-order harmonics based on the polarity of the current flowing through the neutral point; and each phase output voltage command of the inverter. A balance control means for adding a DC component to the current , a means for determining the magnitude of the DC component based on the polarity of the current flowing through the neutral point, control circuit of three-level inverter, characterized by comprising, a means for Ru is operated by selecting either one of the two balance control unit.