JP3186369B2 - Control circuit of three-level inverter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a three-level inverter in which an output voltage takes three states of positive, negative and zero, and more particularly, to a control circuit at a neutral point (intermediate potential point) of a DC power supply circuit of the inverter. The present invention relates to a control circuit for suppressing potential fluctuation.

[0002]

2. Description of the Related Art In recent years, three-level inverters have attracted attention because they can relatively easily realize high voltage and large capacity and have small output harmonics. FIG. 9 shows a basic circuit of this three-level inverter. In the figure, E _DC is a DC power supply, C ₁ and C ₂ are DC input capacitors, P is a positive potential point, N is a negative potential point, and 0 is a neutral potential point. Points, G _U1 , G _U2 , G _X1 , G _X2 ,
G _V1 , G _V2 , G _Y1 , G _Y2 , G _W1 , G _W2 , G _Z1 , G _Z2 are semiconductor switching elements made of GTO, D _U0 , D _X0 , D _V0 , D
_Y0 , _DW0 , and _DZ0 are coupling diodes, and M is an AC motor such as an induction motor.

Here, the switching elements G _U1 , G _U2 ,
A series circuit composed of G _X1 and G _X2 and G _V1 , G _V2 , G _Y1 and G _Y2
A series circuit consisting of the two ends of the series circuit consisting of _{G W1, G W2, G Z1} , G Z2 is connected to a positive potential point P and a negative potential point N of the DC power supply circuit. Further, an interconnection point of the switching elements G _U2 and G _X2, an interconnection point of G _V2 and G _Y2 ,
The interconnection point of G _W2 and G _Z2 is connected to AC motor M as an inverter output terminal. Further, the coupling diodes D _U0 , D _X0 , D _V0 , D _Y0 , D _W0 , D _Z0 are connected to the neutral point 0 and the switching elements G _U1 , G _U2 , G _X1 , G _X2 , G _V1 , G _V2 , G
It is connected between the interconnection points of _Y1 , _GY2 , _GW1 , _GW2 , _GZ1 and _GZ2 , respectively. The flywheel diode is not shown for convenience.

In the three-level inverter having the above configuration, there is a period during which the neutral point 0 is connected to the AC motor M via the switching element and the diode due to the switching pattern. It is known that the neutral point potential may fluctuate at three times the fundamental frequency of the inverter depending on the neutral point current (Tanamachi, et al., "Method of suppressing AC fluctuation of neutral point voltage of three-level inverter") No. 91 of the 1992 IEEJ National Industrial Application Conference
reference). Also, this neutral point current has a DC component under specific conditions, and in that case, the neutral point potential may be greatly biased to positive or negative (see Sawada et al.
WM Inverter "1991 IEEJ National Convention NO. 5
33). Such a change in the neutral point potential may cause excessive voltage application to the switching element.

As one method for preventing the above-mentioned inconvenience, a conventional technique described below (Shimamura et al., "Equilibrium Control of DC Input Capacitor Voltage of NPC Inverter", SPC-91-37, IEEJ Semiconductor Power Conversion Study Group) There is. FIG. 10 shows a capacitor voltage balancing control circuit described in the above document, and FIG. 11 shows a three-level inverter controlled by the control circuit.

The operation is briefly described in FIG.
From the capacitor voltages E _D1 and E _{D2 of} FIG.
Creating a _ED, the signal S _ED retrieve a DC component signal S _EDI through a first-order lag filter. Further, the signals S _ED and S
Create an AC component signal S _EAI from _EDI . Also, based on the inverter output active / reactive power P _M1 , Q _M1 detected by the active / reactive power detection circuit 101 and the inverter output frequency (command) F _I from the current control circuit 103, the polarity determination circuit 102 switches the polarity. _{Produce the} signal P _OL1 .

On the other hand, the DC component signal S _EDI and the AC component signal S _EAI are respectively multiplied by feedback coefficients K _DI and K _AI , and a compensation amount S _BI1 which is the sum thereof is a switch controlled by a polarity switching signal P _OL1. The polarity is converted as needed by 104 to generate a final compensation amount S _BI2 . This compensation amount S _BI2 is added to each phase output voltage command V _UI1 ^* , V _VI1 ^* , V _WI1 ^* of the inverter from the current control circuit 103, and the final output voltage command V _UI2 ^* , V _VI2 ^* , V _WI2 ^*

These output voltage commands V _UI2 ^* , V _VI2 ^* , V
By controlling the inverter based on _WI2 ^*, unbalanced capacitor voltage E _D1, E _D2 can be eliminated, variations in the neutral point potential can be suppressed in other words. In FIG. 11, L _S is a DC reactor, D _U1 , D _U2 , D _X1 , D _X2 , D
_V1 , _DV2 , _DY1 , _DY2 , _DW1 , _DW2 , _DZ1 , and _DZ2 denote flywheel diodes, and IM denotes an induction motor.

In the above prior art, as is apparent from FIG. 10, in order to generate the polarity switching signal _POL1 , the phase voltages e _UI , e _VI , e _WI and the currents i _UI , i _VI , i _WI of the motor IM are generated.
_WI is detected. This is for determining whether the operation mode of the motor IM is the drive mode (power factor> 0) or the braking mode (power factor <0). The determination of the operation mode is based on the polarity of the DC component of the neutral point current. Is different in the drive / brake mode, and the polarity must be considered and added to the voltage command value.

[0010]

The above prior art has the following problems. In the state of power factor = 0 (completely no load), no _matter how much the compensation amount S _BI2 is added, no DC component of the neutral point current is generated, and the control itself is invalidated. At the time of light load near power factor = 0, the drive / brake mode is disabled due to errors in the instrument transformer and current transformer that detect the motor voltage and current, and the difficulty of current detection due to current pulsation. It is difficult to make an accurate determination, and there is a high possibility that the polarity switching signal _POL1 is also switched. When the polarity switching signal P _OL1 is switched, the polarity of the compensation amount S _BI2 is changed, so that the compensation polarity is also opposite to the original one, and there is a possibility that the unbalance of the capacitor voltage is promoted.

At the time of light load near the power factor = 0, the signal S after multiplying the feedback coefficients K _DI and K _AI in FIG.
The ratio of the magnitude of the DC component of the neutral point current generated by these to the magnitudes of _DI1 and _SAI1 becomes small, and the control effect becomes poor. To improve this, the feedback coefficient K _DI ,
Even if K _AI is increased, there is an upper limit to the voltage that can be output by the inverter, and thus there is a limit to this method. As a result, there is a limit to the control at a light load, for example, the control cannot be effectively performed at a power factor of 0.2 or less.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. It is an object of the present invention to enable control even under no load or light load to balance the voltage of a DC input capacitor, An object of the present invention is to provide a three-level inverter control circuit capable of protecting circuit elements such as switching elements.

[0013]

In order to achieve the above object, the present invention provides a series circuit of first to fourth semiconductor switching elements having both ends connected to a DC power supply circuit.
For example, in a three-level inverter that has three phases including a second coupling diode and is PWM controlled, an even harmonic (for example, a sixth harmonic or a second harmonic) of the inverter fundamental frequency is added to each phase output voltage command of the inverter. Means for detecting the potential fluctuation at the neutral point of the DC power supply circuit based on the voltage deviation of the DC input capacitor, and determining the magnitude of the even-order harmonic to be added to the output voltage command based on the magnitude thereof. Means for performing the operation.

[0014]

First, the characteristics of the DC component of the neutral point current will be obtained when the output voltage command of the inverter includes a DC component or an AC component (n-th harmonic component of the inverter fundamental frequency). FIG. 7 shows the PWM used in this analysis.
It is assumed that a firing pulse for the switching element is generated by comparing the voltage command signal with the triangular carrier to obtain an inverter output phase voltage as shown in the figure.

[0015] Now, "1" in the period of the output phase voltage of the inverter is 0, it defines a switching function S _NX becomes "0" during the period of + E _D1 or -E _D2, carrier frequency than the inverter output frequency Assuming that it is sufficiently high, the carrier frequency component is ignored and S _NX is defined by Equation 1.

[0016]

S _NX = 1− {λ sin θ + d + kλ sin n (θ−α)} (0 ≦ θ ≦ π) = 1 + {λ sin θ + d + kλ sin n (θ−α)} (π ≦ θ ≦ 2π)

Where: λ: modulation factor (peak value of voltage command) d: magnitude of DC component k: constant value α: phase difference between inverter output voltage command and nth harmonic component n: 1 , 2, 3, 4, 5,...

The neutral point current i _N ′ for one phase flows only during a period when the inverter output phase voltage is 0, and can be expressed by Equation 2.

[0019]

[Equation 2] i _N ′ = S _NX・ i _M

In the equation (2), i _M : motor current (= √2I _M sin (θ−φ)) I _M : motor current effective value φ: power factor angle

When the above equation 2 is expanded to a Fourier series,
Equation 3 is obtained. In Expression 3, A _mc and A _ms are coefficients.

[0022]

(Equation 3)

Here, the DC component A ₀ ′ included in the neutral point current i _N ′ for one phase is obtained by classifying as follows. (1) When the voltage command includes a DC component d (k = 0 in Equation 1). In this case, the DC component A ₀ ′ is obtained as in Expression 4.

[0024]

(Equation 4)

(2) The case where the voltage command includes an odd harmonic (d = 0, n = 1, 3, 5,... In Equation 1). In this case, the DC component A ₀ ′ is represented by Equation 5, that is, 0.

[0026]

A ₀ '= 0

(3) When the voltage command includes an even harmonic (d = 0, n = 2, 4, 6,... In Equation 1). In this case, the DC component A ₀ ′ is obtained as in Expression 6.

[0028]

(Equation 6)

Next, the DC component A ₀ ′ will be discussed. When the voltage command includes a DC component, | A ₀ '| becomes cosφ when the magnitude d of the DC component is a constant value according to Expression 4.
, And becomes maximum when the power factor (cos φ) = ± 1, and the polarity of the DC component A ₀ ′ changes depending on the driving / braking mode. When the voltage command includes an odd harmonic, the DC component A ₀ ′ is 0 according to Expression 5.

When the voltage command includes an even-order harmonic, the characteristics differ depending on the phase angle α between the voltage command and the n-th harmonic component. That is, in Equation 6, if k is a constant value, | A ₀ '
Is proportional to sinφ when α = 0 or α = π / n [rad] (A ₀ ′ is proportional to sinφ when α = 0, α = π / n
[Rad], and becomes the maximum when the power factor = 0, and the polarity is the same regardless of the driving / braking mode. Also, if k is a constant value, | A ₀ '|
Is proportional to cos φ when ± π / (2n) [rad] (A ₀ ′ is proportional to −cos φ when α = π / (2n) [rad],
When α = −π / (2n) [rad], it is proportional to cos φ), so that it becomes maximum when the power factor = ± 1, and its polarity changes depending on the driving / braking mode.

Here, the relationship between the phase angle α and the polarity of the even-order harmonic will be described. Assuming that the even-order harmonic having the phase angle α is X and the even-order harmonic having the phase angle α− (π / n) [rad] is Y, the relationship of Expression 7 is established from the definition of the phase angle. That is, the even harmonic X of the phase angle α and the phase angle are α− (π / n).
It has a polarity opposite to that of the even-order harmonic Y of [rad].

[0032]

X = −Y

The DC component of the neutral point current (for three phases) is obtained as 3 · A ₀ ′ in any of the above-mentioned cases (1) to (3).

From the above analysis results, if a DC component or even-order harmonic is added to the output voltage command, the polarity of the DC component or the phase angle (polarity) of the even-order harmonic is changed, so that the desired direction can be obtained. It can be seen that a direct current component of the neutral point current can be generated, thereby suppressing a change in the neutral point current or a change in the neutral point potential. From these points,
In the above prior art, a DC component is added to the output voltage command. However, since the polarity of the DC component of the neutral point current changes depending on the driving / braking mode, the detection of this operation mode is indispensable.

Therefore, in the present invention, an even harmonic of the inverter fundamental frequency (phase angle α
= 0 or π / n [rad]).
The fluctuation of the capacitor voltage can be suppressed without detecting the operation mode. That is, according to Equation 6, the DC component A ₀ ′ is converted into the even-order harmonic (2) as shown in FIG.
When the second harmonic is in phase with the output voltage command (α = 0), it is proportional to + sin φ, and has an opposite phase (α = π / n = π / 2 [rad]) as shown in FIG. ]) For -sin
It is proportional to φ. Therefore, if even-order harmonics are added with polarities (in-phase or opposite-phase) according to the voltage deviation between the two DC input capacitors provided in the inverter, the DC component A ₀ ′ in the direction of suppressing the capacitor voltage fluctuation. Can flow.

In the present invention, the DC component A ₀ ′ is
Since it is proportional to nφ or −sinφ, it becomes maximum when the power factor = 0, and its polarity becomes the same in both the driving / braking modes. This makes it possible to perform effective capacitor voltage balancing control regardless of the operation mode even under no load or light load.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, a control circuit 10 includes a DC input capacitor.
An adder 11 to which the voltages E _D1 and E _D2 of the capacitors C ₁ and C ₂ in FIG. 9 are inputted, and a regulator such as a P regulator and a PI regulator to which a deviation S ₁ from the adder 11 is inputted. 12 and a sin (6θ) table 13 in which the values of sin (6θ) corresponding to the phase angles θ _R ^* , θ _S ^* , θ _T ^* of the inverter phase voltage commands are stored.
If its an output signal ^{_{sin (6θ R *), sin}} (6θ S *), si
n (6θ _T ^* ) and multipliers 14 _R , 14 _S , 14 _T for multiplying the output signal S ₂ of the controller 12, respectively, and multipliers 14 _R , 14 _S ,
The 14 _T output signal is converted to the inverter phase voltage command v _R ^* ,
adders 21 _R , 21 _S , 21 _{T for} adding to v _S ^* , v _T ^* , respectively
It is composed of Then, the adders 21 _R , 21 _S ,
The output of 21 _T is the final output voltage command for each phase v _R ^** ,
v _S ^** and v _T ^** .

Here, each inverter phase voltage command v _R ^* , v
_S ^*, v _T ^* to why you chose the 6-order harmonics as even-order harmonics of the inverter fundamental frequency to be added will be described below. That is, 2, 4, 8, 10,..., The next harmonic appears in the inverter line voltage because it is in reverse phase or positive phase.
24... Since the next harmonic is a zero phase, it does not affect the inverter line voltage. Among them, the sixth harmonic is selected as an even harmonic to be added, because A ₀ ′ is the largest.

In FIG. 1, when E _D2 is larger than E _D1 , the polarities of S ₁ and S ₂ become positive, and the phase difference α = 0 between the inverter voltage command and the even harmonics. Therefore, as described above, A ₀ ′ is proportional to sin φ, and its polarity becomes positive, and E _D1
To increase and reduce E _D2 . This allows
Acts so that the capacitor voltages E _D1 and E _D2 become equal,
Fluctuation of the neutral point potential is suppressed. When E _D1 is larger than E _D2 , the polarities of S ₁ and S ₂ become negative, and the phase difference α = π / 6 [rad] between the inverter voltage command and the even-order harmonic.
Becomes Therefore, A ₀ 'is proportional to -Sinfai, the polarity reduced E _D1 becomes negative, it serves to increase the E _D2. For this reason, the capacitor voltages E _D1 and E _D2 act so as to be equal to each other as described above, and the fluctuation of the neutral point potential is suppressed.

FIG. 2 shows a second embodiment of the present invention. This embodiment does not use one of the capacitor voltage E _D1 in the first embodiment, E _DC / 2 is a fixed value (E _DC:
The DC intermediate voltage (power supply voltage) of the three-level inverter is E _D1
Is one of the inputs of the adder 11 in place of
Others are the same as the first embodiment. According to this embodiment, since only one voltage detector is required, the circuit configuration can be simplified.

FIG. 3 shows a third embodiment of the present invention.
In this embodiment, the constant value E _DC / 2 is used as one input of the adder 11 instead of E _D2 without using the other capacitor voltage E _D2 in the first embodiment. This is the same as the first embodiment. In this embodiment, the same effects as in the second embodiment can be obtained.

FIG. 4 shows a fourth embodiment of the present invention.
In this embodiment, a sin (2θ) table 15 is provided in the control circuit 10A instead of the sin (6θ) table 13 of the first embodiment.
The rest is the same as the first embodiment. In this embodiment, the inverter phase voltage command v
_{^{R *, v S *, v}} T * Why did you choose the second-order harmonics as even-order harmonics of the inverter fundamental frequency to be added to the is as follows.

As described in connection with the first embodiment, the second harmonic appears in the inverter line voltage. However, if the application does not cause a problem even if a second harmonic appears in the line voltage (for example, an application in which a fan simply rotates), there is no problem even if the present invention is applied. It can be said. Moreover, as is apparent from Equation 6, when the second harmonic is used, the magnitude of the DC component A ₀ ′ is the largest among the even harmonics, so that the fluctuation suppression effect of the neutral point potential is also the largest. It is.

FIGS. 5 and 6 show the fifth and sixth embodiments of the present invention, respectively.
An embodiment is shown, and in the second and third embodiments, si
sin (2θ) table 15 instead of n (6θ) table 13
Is used. In these embodiments, the same effects as in the second, third, and fourth embodiments can be obtained.

[0045]

As described above, according to the present invention, it is possible to effectively suppress the imbalance of the capacitor voltage even at the time of complete no-load or light load, and to prevent application of an excessive voltage to the circuit element. . In addition, in the capacitor voltage balancing control, it is not necessary to determine the driving / braking mode, and switching of the control polarity near the power factor = 0 is eliminated. There is no such inconvenience.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

FIG. 7 is an explanatory diagram of PWM used for analysis of the present invention.

FIG. 8 is a diagram showing a phase difference between a voltage command and an even harmonic in the present invention.

FIG. 9 is a basic circuit diagram of a three-level inverter.

FIG. 10 is a diagram showing a capacitor voltage balancing control circuit as a conventional technique.

11 is a circuit diagram of a three-level inverter controlled by the circuit of FIG.

[Explanation of symbols]

10, 10A control circuit 11, 21 _R , 21 _S , 21 _T adder 14 _R , 14 _S , 14 _T multiplier 12 regulator 13 sin (6θ) table 15 sin (2θ) table

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroshi Osawa 2-2-1 Nagasaka, Yokosuka City, Kanagawa Prefecture Inside Fuji Electric Research Laboratory Co., Ltd. (56) References JP-A-2-261630 (JP, A) Hei 5-227796 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H02M 7/48

Claims (1)

(57) [Claims] A first semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween; Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection points of the second and third semiconductor switching elements are connected to the inverter output terminals, respectively. First coupling diodes are respectively connected between the interconnection point of the second semiconductor switching element and the neutral point,
In addition, in a three-level inverter in which a second coupling diode is connected between the interconnection point of the third and fourth semiconductor switching elements and the neutral point, an inverter basic voltage is applied to each phase output voltage command of the inverter. A control circuit for a three-level inverter, comprising: means for adding an even-order harmonic of a frequency; and means for determining the magnitude of the even-order harmonic based on a potential change at the neutral point.