JP3124044B2 - Control processor with watchdog timer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control processing device with a watchdog timer, in which a reset signal is supplied to a CPU by a watchdog timer (watchdog timer) in a predetermined case.

[0002]

2. Description of the Related Art A control processing device (for example, a microcomputer) for performing various calculations and controls by a CPU is used in various fields. As is well known, CPU
The operation is performed according to a predetermined program, and when a predetermined program cannot be executed due to some trouble, a so-called runaway occurs. That is, proper control and calculation based on the program cannot be performed.

In order to cope with such a situation, a so-called watchdog timer is generally provided in a control processing device having a CPU. This watchdog timer receives a timer clear signal output from a predetermined output port when the operation of the CPU is proper, and performs reset control of the CPU based on this signal. Specifically, this watchdog timer is
When the timer clear signal is interrupted for a predetermined period, a reset pulse is output to the CPU.

However, in such operation management of the CPU, there is a problem that a dedicated output port must be allocated for the watchdog timer. This problem has become a serious problem particularly in a system having a limited number of output ports.

Therefore, Japanese Patent Application Laid-Open No. 63-268043 proposes a microcomputer system which does not require an output port dedicated to a watchdog timer. In this system, data is input to and output from the CPU at regular intervals, and the watchdog timer is connected to the data line. Then, the watchdog timer outputs a reset signal to the CPU when data input / output is interrupted for a certain period.

[0006]

However, in the microcomputer system described in Japanese Patent Application Laid-Open No. 63-268043, it is indispensable that data input and output be performed periodically as described above. For this reason, there has been a problem that it is impossible to input / output certain data irregularly. In other words, in this conventional system, it is impossible to transmit and receive certain data only when the power of the system is turned on. For this reason, the application is greatly restricted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a control process with a watchdog timer capable of utilizing an output port occupied for a watchdog timer for other signals. It is to provide a device.

[0008]

In order to achieve the above-mentioned object, the present invention provides a CPU having a data input / output port for performing an operation, and a predetermined output port which is continuously connected to the CPU when the CPU operates properly. A watchdog timer that receives a timer clear signal having a predetermined pulse waveform to be output, and provides a reset signal to the CPU when the timer clear signal has stopped for a predetermined period of time. Determines that a trigger has occurred.
Means for determining the occurrence of a trigger, and determining whether the trigger has occurred
If it is, anda signal superimposing means for superposition with other pulse code signal by a pulse modulation to the timer clear signal, the watchdog timer reset control of the CPU the timer clear signal component as decisions When the CPU is not operating properly, the timer
Output of any of the rear signal and the other pulse code signal
Is also stopped and output continuously during proper operation of the CPU.
Before the timer clear signal
It is characterized in that other pulse code signals can be superimposed .

[0009]

According to the above construction, another pulse code signal can be superimposed on the timer clear signal by pulse modulation independently of the timer clear signal on a regular and irregular basis by the signal superimposing means. It becomes possible to increase by one. That is, the output port that has been occupied conventionally can be used for the other signals. In this case, since the watchdog timer uses the timer clear signal component as a judgment material in accordance with the pulse modulation, malfunction is eliminated, and accurate CPU reset control is realized. When the CPU is not operating properly, the timer clear signal
The output of both the signal and other code signals is stopped. Since another pulse code signal is superimposed on the timer clear signal, if the base timer clear signal is interrupted, the pulse code signal superimposed on it is also interrupted.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a control processing device according to the present invention. In FIG. 1, a CPU 12 which performs various calculations and controls is disposed on a CPU board 10 which is the core of the control processing device. An input buffer 14 that supplies an input signal to the CPU 12 is connected to a plurality of input ports of the CPU 12, while an output buffer 16 is connected to an output port of the CPU 12. The input buffer 14 and the output buffer 16 aim to stabilize input / output data.

The CPU board 10 includes a CPU 12
A power supply IC 18 for supplying power to the power supply is provided. A current is supplied to the power supply IC 18 from a predetermined battery 20 via an ignition key 22.

Therefore, according to such a configuration, the CPU 12 accepts input data through the input buffer 14, processes the contents, and outputs the result to the outside via the output buffer 16, as in the prior art. Will be. In the figure, a system ROM and the like are not shown.

In FIG. 1, reference numeral 24 denotes a watchdog timer (WDT) 24, which receives a clear pulse 100 from a predetermined output port of the CPU 12 and outputs a predetermined reset pulse 102 to the CPU 12. Specifically, when the clear pulse 100 is interrupted for a predetermined period, a reset pulse 102 is set to be output. That is, the CPU 12 is determined to be out of control.

In this embodiment, the clear pulse 1
00 is characterized in that another signal other than this is superimposed. Therefore, in order to output the clear pulse 100 on which other signals are superimposed, an output buffer 26 is additionally provided in the present embodiment. Also, C
A terminal 104 is additionally formed on the PU board 10 to output an output signal from the output buffer 26 to the outside. Here, other signals superimposed on the clear pulse 100 may be output irregularly without any problem. Therefore, for example, when the other signals are required only at the time of system inspection, the probe is directly applied to the line on which the clear pulse 100 is applied without providing the output buffer 26 or the like, and the operation of the CPU 12 is checked. May be.

The control processing device according to the present invention has the above-described configuration. Next, referring to FIG.
The superimposition of another signal on 0 will be described.

FIG. 2 shows a clear pulse transmitted at a period Tx. The first half T ₁ of the cycle Tx is H
has become a i, the second half of T ₂ has a Lo.
Normally, such a clear pulse is continuously output every cycle Tx.

When a predetermined trigger 200 described later occurs, a predetermined output code determined in accordance with the trigger is superimposed on the clear pulse. In the example shown in FIG. 2, "5A" is set as the output code.
That is, in the present embodiment, the Tx period is divided into a plurality of bits (8 bits), and the output code is represented by using each bit. In this embodiment, the code is determined such that the first bit is always 1 and the last bit is 0. That is, in the present embodiment, the watchdog timer 24 determines the clear pulse when the first signal of the period Tx rises. Therefore, even if such an output code is superimposed on the clear pulse 100, no malfunction occurs.

Next, various pulse modulation methods will be described with reference to FIG.
A method of superimposing a signal on a clear pulse using the equation will be described. FIG. 3A shows only a clear pulse on which no other signal is superimposed. Here, the watchdog timer is cleared at the rise of the period T.

FIG. 2B shows an example in which another signal is superimposed on a clear pulse by PWM (duty modulation). That is, the output code is determined by T ₂ / T _1. (C) shows an example in which an output code is superimposed on a clear pulse by PNM (pulse number modulation). That is, the output code is represented by the number of pulses. Further, (D) shows an example in which an output code is superimposed by PCM (pulse code modulation) in the same manner as shown in FIG.

In the control processing device with a watchdog timer according to the present embodiment, any of the methods shown in each example of FIG. 3 can be applied. However, in order for the watchdog timer to correctly determine the clear pulse, it is necessary that a rising or falling edge of the signal indicating the clear pulse is inserted at a specific position in the period T. Of course, the example shown in FIG. 3 is merely an example, and another overlapping method may be used as a matter of course.

Next, signal processing for superimposing another signal on the clear pulse 100 will be described with reference to FIG.

In FIG. 4, this routine starts when the ignition key 22 shown in FIG. 1 is turned on. In step 201, it is determined whether or not a predetermined time has elapsed. That is, this step 201 is provided to execute the following steps at predetermined time intervals. Therefore, according to the use of the control processing device, if it is unnecessary, this step 2
01 does not need to be provided. In step 202, it is determined whether or not a code output flag described later is set. If it is determined that the flag has not been set, the process proceeds to step 203.

In step 203, the clear pulse shown in FIG. 3A is output as it is. Then, in step 204, normal input / output processing is performed.

When a predetermined trigger is generated in such a series of processing, the occurrence of the trigger is determined in the next step 205. Here, in the present embodiment, three triggers are defined as the triggers. The trigger 1 is generated when a condition of input data matches a predetermined condition. Trigger 2 is
This is a trigger that occurs when the ignition key is turned on. The trigger 3 is generated when a certain flag in the program becomes a predetermined state. Each trigger has an attribute of a timing related to output code transmission. For example, when a condition defined for trigger 1 is satisfied, a predetermined time (t1) defined by the attribute elapses. , Trigger 1 will occur.

Such a trigger is determined in step 205. When it is determined that there is no trigger, the process returns to step 201 again. On the other hand, if it is determined that a trigger is present, the process proceeds to the next step 206.

In step 206, a predetermined output code is set in a register according to the type of the determined trigger. At the same time, in step 207, a code output flag is set, and a standby state for outputting a code is set.

When the code output flag is set as described above, the setting of the code output flag is determined in step 202 described above, and step 208 is executed.

In step 208, a clear pulse on which an output code is superimposed is output. In particular,
The clear pulse on which the output code shown in FIG. 2 is superimposed is output to the watchdog timer 24 and the output buffer 26.

As described above, according to the control processing device of this embodiment, the output port for the clear pulse which has been occupied in the past can be used as the output port for another signal. Has the advantage that the output of the CPU can be increased by one. Therefore, for example, a control signal or a status signal that could not be output in the related art can be output to the outside world, and the control processing device can be constructed with multiple functions.

[0031]

As described above, according to the control processing device with a watchdog timer according to the present invention, another signal is superimposed on the clear signal by using the output port occupied for the clear pulse. Since it is possible to output to the outside, it is possible to improve the function of the system which has been conventionally restricted by the number of output ports. In particular, according to the present invention, there is an effect that another signal can be arbitrarily superimposed on the timer clear signal when necessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a control processing device with a watchdog timer according to the present invention.

FIG. 2 is a waveform diagram showing a clear pulse on which a code as another signal is superimposed.

FIG. 3 is an explanatory diagram showing a method of superimposing a code on a clear pulse.

FIG. 4 is a flowchart illustrating a process of superimposing a code on a clear pulse.

[Explanation of symbols]

 12 CPU 24 Watchdog timer 100 Clear pulse 102 Reset pulse

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/00

Claims (1)

(57) [Claims] A CPU having a data input / output port for performing calculations; and a timer clear signal having a predetermined pulse waveform continuously output from a predetermined output port when the CPU operates properly. in the control processor with the watch dog timer comprising a watchdog timer, the providing a reset signal to the CPU when the timer clear signal is interrupted a certain period, a trigger occurrence determination means for determining the occurrence of a trigger, the trigger If the occurrence is determined, the by pulse modulation to the timer clear signal includes a signal superimposing means for heavy <br/> tatami other pulse code signal, and determines the watchdog timer the timer clear signal component material Reset control of the CPU, and when the CPU is not properly operated, the timer clear signal and
And output of any of the other pulse code signals is stopped.
And the timer which is continuously output during proper operation of the CPU.
The other pulse at a desired timing with respect to the mask clear signal
A control processing device with a watchdog timer , wherein a code signal can be superimposed .