JP2009025953A - Arithmetic processing unit and arithmetic processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic processing unit for shortening a whole processing time required for a plurality of processings. <P>SOLUTION: A plurality of floor plan layouts in which areas to be used by a reconfigurable circuit are different are stored for every process belonging to each task. Then, the process is set until the number of use areas exceeds the number of all division areas in the order of the performance object process of a high priority task (S54 to S66). Then, the floor plan layout in which the use areas are not overlapped is selected with respect to the set process (S68 to S74), and the reconfigurable circuit is reconfigured with corresponding configuration data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device or an arithmetic processing program.

  Arithmetic processing devices capable of performing software-like control and reconfiguring hardware-like logic specifications are becoming widespread.

  The following Patent Document 1 discloses a technique for sequentially configuring a plurality of divided circuits formed by dividing one circuit to be generated into a reconfigurable circuit, and an arithmetic unit in the reconfigurable circuit. A technique for inputting a constant in (ALU) is also described.

  Patent Document 2 below discloses a technique for reconfiguring a circuit based on a dependency relationship between operations to be executed.

  Patent Document 3 listed below discloses a technique for reconfiguring a circuit using an external interrupt signal as a trigger to first execute a process with high priority and then resume the interrupted process. .

  In the following Patent Document 4, by switching the configuration in one clock for a plurality of reconfigurable processor elements having a pipeline structure, and executing the arithmetic processing corresponding to the data that flows to the pipeline structure, A technique for realizing time division processing is disclosed.

  Patent Document 5 below discloses a technique for improving the operating frequency of a circuit by holding data being processed near each arithmetic unit in the reconfigurable circuit.

JP 2005-277673 A JP 2004-334429 A Japanese Patent Laid-Open No. 2005-165961 JP 2006-018539 A JP 2005-044329 A

  In the case of sequentially executing each arithmetic processing as in the technique of the above-mentioned Patent Document 1, simply the arithmetic time required for adding the time required for each arithmetic processing is required. This situation is the same when the calculation order is changed as in the technique of Patent Document 2 described above. Further, as in the technique of Patent Document 3 described above, when interrupt processing is performed based on the priority order, the processing with high priority order ends early, but each arithmetic processing is performed before the entire processing ends. It takes about the same time as the sequential execution. In addition, the time division processing adopted in Patent Document 4 does not shorten the entire calculation time, and the number of reconfigurations increases, so there is a possibility that the overhead problem cannot be ignored. The technique of Patent Document 5 also does not solve such a problem related to time reduction.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an arithmetic processing apparatus or an arithmetic processing program capable of reducing the overall processing time required for a plurality of processes.

  In one aspect of the arithmetic processing apparatus of the present invention, a reconfigurable circuit having a plurality of small circuits and capable of reconfiguring logic specifications in a part or all of the small circuits, and one or two or more operations are combined. Storage means for storing the partial logic specifications processed by the small circuit of each unit for each of the one or more operations, an acquisition means for acquiring processing requests for a plurality of operations that can be processed independently of each other, and processing requests A determination unit that determines a logical specification for parallel processing of the two or more operations performed based on a combination of the partial logical specifications that do not overlap the small circuit, and the determination unit determines the logical specification for the reconfigurable circuit Reconfiguring means for dynamically reconfiguring the logical specification.

  In one aspect of the arithmetic processing apparatus of the present invention, the storage means stores a plurality of partial logic specifications for which at least a part of the one or more operations are different in a small circuit for processing the operation, and the determination means Selects a partial logical specification that can be combined without overlapping small circuits from a plurality of partial logical specifications with different small circuits for processing operations, and determines the logical specifications.

  In one aspect of the arithmetic processing device of the present invention, a plurality of subdivisions that divide the reconfigurable circuit so as to include at least one of the subcircuits are set, and the determining means is a subsection used for arithmetic processing. Based on the overlap information of the sections, a combination of the partial logic specifications that do not overlap the small circuits is determined.

  In one aspect of the arithmetic processing unit of the present invention, a part of the small circuit has a physical structure different from other small circuits, and the determining means is based on a difference in physical structure of the small circuit. The combination of the partial logic specifications is determined.

  In one aspect of the arithmetic processing apparatus of the present invention, the acquisition means also acquires processing priority information for the requested processing, and the determination means determines the logical specification based on the priority information. To decide.

  In one aspect of the arithmetic processing apparatus of the present invention, the plurality of determining means determines the logical specification based also on the total processing time for the plurality of operations requested to be processed.

  In one aspect of the arithmetic processing program of the present invention, one or two or more computers having a plurality of small circuits and including a reconfigurable circuit capable of reconfiguring logic specifications in a part or all of the small circuits are provided. Storage means for storing partial logic specifications for processing operations in some of the small circuits for each of the one or more operations, and acquisition means for acquiring processing requests for a plurality of operations that can be processed independently of each other A determination means for determining a logical specification for parallel processing of two or more requested processing operations based on a combination of the partial logic specifications in which the small circuits do not overlap; and for the reconfigurable circuit, the determination means It functions as a reconfiguration means for dynamically reconfiguring the determined logical specification.

  According to the first aspect of the present invention, there is provided an arithmetic processing device that improves the use efficiency of the reconfigurable circuit and speeds up a series of arithmetic processing as a whole.

  According to the present invention of claim 2, the number of combinations of partial logic specifications that can be processed in parallel is increased, and the use efficiency of the reconfigurable circuit is improved.

  According to the third aspect of the present invention, it is possible to quickly determine whether a small circuit is duplicated.

  According to the present invention of claim 4, performance based on the physical structure of the reconfigurable circuit is extracted, and at least one of speeding up of processing, capacity increase, or downsizing (a circuit portion to be used) is possible. Become.

  According to the present invention of claim 5, a combination of parallel processing can be dynamically determined based on the priority order information.

  According to the sixth aspect of the present invention, a combination of parallel processing that shortens the overall processing time is selected.

  According to the present invention of claim 7, there is provided an arithmetic processing program that improves the use efficiency of the reconfigurable circuit and speeds up a series of arithmetic processing as a whole.

[Explanation of terms, etc.]
Here, terms and concepts used in the claims or the specification will be briefly described.

  The reconfigurable circuit is also referred to as a reconfigurable circuit, and refers to a circuit that can change a logical specification that defines a hardware-like operation into software (programmatically). The reconfigurable circuit includes a plurality of small circuits. Examples of each small circuit include an arithmetic logic unit (ALU), a random access memory (RAM), or a combination thereof. The plurality of small circuits may have the same physical structure or different physical structures. For example, an input / output terminal, a memory, an arithmetic circuit, or the like suitable (or unsuitable) for certain types of operations may be provided (or not provided) only for some of the small circuits. In the reconfigurable circuit, the hardware structure is changed (reconfigured) in software by switching the internal logic of the small circuit or the connection logic between each small circuit and the outside. In general, the reconfiguration of the reconfigurable circuit is performed for all the small circuits, but may be performed for some of the small circuits. Such a circuit may be partially reconfigured. Sometimes called a configurable circuit.

  The storage means stores the partial logic specification for each of one or more operations. The partial logical specification refers to a logical specification that performs one or two or more arithmetic processes by using a part of small circuits instead of all the small circuits of the reconfigurable circuit. The storage means may store only one partial logical specification for each one or two or more operations, or may store a plurality of partial logical specifications in which at least some of the small circuits to be used are different.

  The acquisition unit acquires processing requests for a plurality of operations from the outside or from a reconfigurable circuit. Here, the calculation refers to a unit process managed on the arithmetic processing unit, for example, a task, a job, a process, etc., and may be a series of processes linked to another process. In this case, a plurality of small processing units managed on the arithmetic processing unit may be included. The plurality of computations required for processing include those that can be processed independently of each other, that is, those that are not dependent on each other and are not limited in processing order, such that one processing result is used for the other processing. Note that operations that can be processed independently of each other typically have different processing types (for example, image data, color conversion processing, and image data compression processing), but the processing types are the same. It may be. For example, the aspect which performs the same kind of calculation (for example, color conversion process) with respect to each of two or more independent data is mentioned.

  The decision means combines the partial logic specifications that do not overlap the small circuits to be specified, thereby processing the operations corresponding to each partial logic specification in parallel (if each operation is called a task, substantial multitasking is realized. To determine the logical specifications for When only one partial logical specification is stored for each operation, the determining means determines the logical specification based on a combination that does not overlap them. In addition, when two or more partial logical specifications are stored for at least some of the operations, the logical specification may be determined after selecting which partial logical specification is to be adopted. For example, the determination unit may calculate and store in advance whether or not the combination of the partial logical specifications is possible, and may determine the logical specification based on the calculation result, or may determine the logical specification by calculating the combination each time. May be. In addition, when processing for multiple requested operations cannot be performed with a single reconfiguration, the logical specification to be used in the next reconfiguration is determined, the timing of the reconfiguration is determined, etc. Scheduling may be performed. The determining means may determine the logical specification based on the processing priority information of the requested processing, that is, based on information representing the priority of the arithmetic processing in two or more categories.

  The reconfiguring means dynamically reconfigures the reconfigurable circuit according to the logical specification determined by the determining means. Reconfiguration is performed, for example, by writing setting data (configuration data) corresponding to a logical specification to be reconfigured into a dedicated memory. Dynamic reconfiguration means that the reconfigured logic specification is not fixedly used, but is reconfigured in accordance with the necessity of the arithmetic processing, the processing status, and the like.

  The storage means, acquisition means, determination means, and reconfiguration means are usually constructed using external devices (circuits, etc.) of reconfigurable circuits, but some or all of these are reconfigurable circuits. You may make it build. Further, an additional means for adding a partial logic specification for processing a new operation may be constructed using an external circuit or a reconfigurable circuit. Note that this arithmetic processing unit performs data processing or the like in cooperation with another arithmetic processing unit (which may be a reconfigurable arithmetic processing unit or a non-reconfigurable arithmetic processing unit). Alternatively, data processing or the like may be performed alone.

[First Embodiment]
First, the first embodiment will be illustrated with reference to FIGS. 1 to 7. FIG. 1 is a schematic diagram illustrating a configuration example of an image processing apparatus 10 according to the present embodiment. The illustrated image processing apparatus 10 is an apparatus having a single casing, and includes an internal bus 11 as an internal communication path. The internal bus 11 includes a CPU (Central Processing Unit) 12, a ROM (Read Only Memory) 14, a RAM (Random Access Memory) 16, an HDD (Hard Disc Drive) 18, a reconfigurable arithmetic unit 20, a UI (User Interface) 21, a scanner 22, The constituent elements of a printer 24, a CDD (Compact Disc Drive) 26, and a network interface 28 are connected.

  The CPU 12 is a device that controls each component of the image processing apparatus 10 and performs image processing according to a program stored in the ROM 14 or the like. The ROM 14 is a semiconductor memory (storage device) capable of long-term storage, and stores various programs and setting information. The RAM 16 is a semiconductor memory capable of temporary storage, and stores image data to be processed. The HDD 18 is a large-capacity storage device configured using a magnetic disk or the like, and is used for storing image data for a long period of time. The reconfigurable computing device 20 is a computing device capable of reconfiguring logic specifications, and performs arithmetic processing of image data and the like according to a program stored in the ROM 14 or the own device. The UI 21 includes a display device such as a liquid crystal display and a light emitting diode, and an input device such as a touch panel and a keyboard, and displays data to the user of the image processing apparatus 10 and receives an operation command from the user. The scanner 22 is a reading device that reads an image on a sheet surface and generates image data. The printer 24 is a printing device that performs printing on paper based on image data. The CDD 26 is a device that reads data recorded on a CD (compact disc) as a recording medium. For example, when the program for controlling the CPU 12 or the reconfigurable arithmetic device 20 is provided by the CDD 26, this program is executed. Used for reading. The network interface 28 is an interface for inputting / outputting data by connecting to a network 30 such as the Internet. For example, when a program for controlling the CPU 12 and the reconfigurable computing device 20 is provided through the network 30, Used to receive the data signal of this program.

  Here, the operation of the image processing apparatus 10 will be briefly described. In the image processing apparatus 10, typically, a user instructs an image data generation process by the scanner 22 or an image data print process by the printer 24 through the UI 21. In this case, the CPU 12 analyzes the instruction from the user according to the program, writes the image data generated by controlling the scanner 22 to the RAM 16, and prints based on the image data stored in the RAM 16 by controlling the printer 24. Or do. In this process, the reconfigurable arithmetic unit 20 reconfigures the logic circuit as necessary, and performs various image data processing such as enlargement / reduction, color conversion, and rotation.

  Then, the outline of the structural example of the reconfigurable arithmetic unit 20 is demonstrated using FIG. The reconfigurable computing device 20 includes a reconfiguration processor 34, a configuration memory 38, a control unit 40, an internal interface 42, and a memory interface 44. The reconfiguration processor 34 is a device as a reconfigurable circuit, and is connected to the configuration memory 38 and the internal interface 42. In the reconfigurable processor 34, processor elements (PE) as small circuits are arranged in an array. Each PE includes an ALU, a RAM, and the like, and is connected to other PEs and the internal interface 42. Each PE performs arithmetic processing on image data input from the internal interface 42 alone or in cooperation with other PEs, and outputs the result to the internal interface 42. The configuration memory 38 is a storage device including a semiconductor memory, and is connected to the reconfiguration processor 34 and the internal interface 42. The control unit 40 is an arithmetic device that controls the reconfigurable arithmetic device 20, and is connected to the internal interface 42. The memory interface 44 is a device connected to the internal interface 42, and transmits / receives data to / from the ROM 14, RAM 16, HDD 18, etc. via the internal bus 11 shown in FIG. 1 and transmits / receives control signals to / from the CPU 12. Or In FIG. 2, an output data storage unit 46 that stores data output from the reconfiguration processor 34, an input data storage unit 48 that stores data input to the reconfiguration processor 34, and a configuration memory. A state in which the configuration data storage unit 50 for storing the configuration data input to 38 is constructed is illustrated.

  Here, the operation of the reconfigurable computing device 20 will be briefly described. The control unit 40 determines a logical specification to be set in the reconfiguration processor 34, that is, a configuration according to the program. Then, configuration data for setting the configuration is input from the configuration data storage unit 50 to the configuration memory 38. Thereby, the operation of the semiconductor switch of the reconfiguration processor 34 is switched, and the reconfiguration processor 34 is reconfigured. That is, the internal logic of each PE, or the connection logic between PEs and the internal interface 42 is changed to a corresponding configuration (it can also be called a function module because it has a certain calculation function).

  Next, the control unit 40 shown in FIG. 2 will be described with reference to FIG. The control unit 40 is connected to a scheduler 60, an interrupt detection unit 70 connected to the scheduler 60, a scheduler table 72, and a layout load unit 74. The scheduler 60 is a device that controls reconfiguration of the configuration set in the reconfiguration processor 34. The scheduler 60 includes a priority / status determination unit 62, a layout determination unit 64, a process set unit 66, and a layout selection unit 68. Here, a process in which a series of operations to be executed (sometimes referred to as tasks) are a plurality of small operation units (for example, individual processes when tasks are pipelined) Each configuration will be described by taking as an example a case of consisting of (sometimes called).

  When an interrupt is received from the interrupt detection unit 70, the priority status determination unit 62 refers to the scheduler table 72 and the priority order (priority) of the task to be processed by the reconfiguration processor 34 and the process belonging to the task. Check the execution status (status). The layout determination unit 64 receives the determination result of the priority status determination unit 62, and if it is not set, the layout floor plan layout for executing each process, that is, which part of the reconfiguration processor It is determined whether to perform the calculation, and is registered in the scheduler table 72. This floor plan layout is data as a partial logical specification, and is determined based on, for example, configuration data for each operation stored in the configuration data storage unit 50 (which can also be regarded as data representing the partial logical specification). Is done. Further, the process set unit 66 temporarily sets the execution target processes in the tasks in the descending order of task priority as the process to be processed. Then, the layout selection unit 68 determines whether there is any overlap in the floor plan layout of the temporarily set process, and selects the floor plan layout to be actually set. The selection result is instructed to the layout load unit 74, and the layout load unit reads the configuration data stored in the configuration data storage unit 50 and transmits a load command signal to be input to the configuration memory 38 to the CPU 12.

  The interrupt detection unit 70 inputs an interrupt signal to the priority / status determination unit 62 when the CPU 12 issues a processing instruction for a new operation or when the operation being processed by the reconfiguration processor 34 is completed. The scheduler table 72 is a table in which the priority, status, floor plan layout used for the calculation, and the like are collected for the calculation that has received a processing instruction from the CPU 12.

  FIG. 4 is a diagram illustrating an example of configuration data for each calculation stored in the configuration data storage unit 50. FIG. 4 shows configuration data 80, 82, 84 for an operation named task A, configuration data 86, 88, 90 for another operation named task B, and another name named task C. The configuration data 92 for the calculation is shown. Here, it is assumed that tasks A and B are composed of three-stage processes (first to third processes) that are sequentially processed in series (in other words, pipeline processing is possible). Further, although it is assumed that the task C includes four stages of processes (first to fourth processes), the second to fourth processes are not shown.

  In the configuration data 80, a task that is a logic circuit for the first process in the PE arranged in the upper left area 1 of the four divided areas (this is an example of a small partition set in the reconfigurable circuit). A1 is set. In the configuration data 82, the task A2, which is the logic circuit for the second process, is set in the upper right area 2, and in the configuration data 84, the task A3, which is the logic circuit for the third process, is set in the lower left area 3. Is set. In the configuration data 86, a task B1, which is a logic circuit for the first process, is set in the left areas 1, 3 and in the configuration data 88, a task B2, which is a logic circuit for the second process, is set in the right areas 2, 4. In the configuration data 90, task B3, which is a logic circuit for the third process, is set in the lower areas 3 and 4. In the configuration data 92, a task C1, which is a logic circuit for the first process, is set in areas 1, 2, and 4 except for the lower left. An area where no logic circuit is set in these configuration data 80 to 92 is an area where PE is not scheduled to be used. The control unit 40 sets a final configuration data by combining a plurality of configuration data (determining a floor plan layout) so that logic circuits do not overlap.

  FIG. 5 is a diagram illustrating an example of the scheduler table 72. Here, the scheduler table 72 in the arithmetic processing process for the tasks A, B, and C described with reference to FIG. 4 is shown. Information on the task currently being processed is recorded in the top row 102 of the table. Specifically, the second process of task A and the first process of task B are currently being processed in parallel by the reconfiguration processor 34, and the second process of task A has a logic circuit in area 3. It is shown that a logic circuit is set in areas 2 and 4 for the first process of task B.

  Information about each task is recorded in the steps 104 and below. Specifically, in step 104, “task name”, “priority” indicating priority, “status” indicating a process being processed or completed, “number of processes” belonging to the task, “first process usage floor” Items of “plan layout”, “second process use floor plan layout”, “third process use floor plan layout”, and “fourth process use floor plan layout” are provided. In the levels 106, 108, and 110, values corresponding to the items in the level 104 are set for the tasks A, B, and C, respectively. For example, in task A, the priority is 1 (highest), the process being processed or processed is the second process, the total number of processes is 3, and the process for each process is shown in FIG. It is shown that the operation is performed with the use floor plan layout corresponding to the configuration data 80, 82, and 84 shown. Similarly, in task B, the priority is 2 (second highest), the process being processed or processed is the first process, the total number of processes is 3, and the process for each process Is performed with the use floor plan layout corresponding to the configuration data 86, 88, 90 shown in FIG. For task C, the priority is 3 (the third highest), the process being processed or processed is the 0th process (that is, the process has not yet been performed), and the total number of processes. Is 4, and the use floor plan layout corresponding to the configuration data 92 shown in FIG. 4 is used.

  Next, the operation of the reconfigurable computing device 20 will be described using the flowcharts of FIGS. FIG. 6 is a flowchart showing an overall process flow in the reconfigurable computing device 20, and FIG. 7 is a flowchart showing a process flow in the scheduler 60.

  As shown in FIG. 6, in the reconfigurable computing device 20, when a task processing request relating to image data is received from the CPU 12 (S10), the scheduler 60 of the control unit 40 makes a determination regarding the task contents, the processing order, etc. Perform (S12). Then, according to the floor plan layout determined by the scheduler 60, the configuration data is input to the configuration memory 38, and the configuration corresponding to the reconfiguration processor 34 is reconfigured (S14). The reconfiguration processor 34 executes a task based on this configuration (S16). When detecting the task processing, the interrupt detection unit 70 issues a task end signal to the scheduler 60 to interrupt (S18). Then, when there is another task in parallel processing, the scheduler 60 stops inputting input data (S20), updates the scheduler table 72 to determine the end content (S22), and then executes it. If there is a task, the processes after step S12 are repeated.

  Subsequently, the flow of processing of the scheduler 60 in steps S12 and S22 of FIG. 6 will be described in detail with reference to FIG. The scheduler 60 updates the status in the scheduler table 72 when there is a task execution request (S10) or when a task end signal is input (S18) (S30). Subsequently, the status of the task with the highest priority among unfinished tasks is checked (S32), and the floor plan layout of the process to be processed is set as the floor plan layout to be processed (S34). Then, it is determined whether the statuses of all tasks that have not been processed have been checked (S35). If there is an unchecked task, the status of the task with the next highest priority is checked (S36), and the floor plan layout of the process indicated by the status is referred to (S38). Logical AND. If the logical product is 0, the floor plan layout is set as the floor plan layout to be processed, and then the processes in and after step S34 are repeated. On the other hand, if the logical product does not become 0, that is, if there is an overlap with the floor plan layout set before that, the floor plan layout is not set for this task, and the processes in and after step S34 are repeated. When the status check of all tasks is completed in step S34, the configuration data corresponding to the set floor plan layout is sequentially configured from the configuration data storage unit 50 through the layout load unit 74 in the order of priority. The data is loaded into the memory 38 (S44, S46, S48).

  FIG. 8 is a diagram illustrating a specific example of a task processing mode. In the figure, how the tasks A, B, and C are processed under the configuration data shown in FIG. 4 and the scheduler table 72 shown in FIG. 5 is shown in time order. Before the start, as shown in the state 120, the statuses of the tasks A, B, and C are 0, and any processing is not performed. When the processing starts, first, as shown in a state 122, the first process of task A having a priority of 1 and the first process of task B having a priority of 2 and a floor plan layout that can be combined. Are processed in parallel. Then, the processing of the first process of task A ends first, and the scheduler 60 interrupts the processing of the first process of task B and performs the reconfiguration 124 of the configuration. As a result, as shown in the state 126, the parallel processing of the second process of the task A having the priority 1 and the first process of the task B having the priority 2 and the floor plan layout that can be combined is performed. Is called. Thereafter, when the processing of the first process of task B is completed, reconfiguration 128 is performed, and as shown in state 130, the second process of task A having a priority of 1, a priority of 2, and a floor The second process of task B that can be combined with the plan layout is processed in parallel. Similarly, the reconfiguration 132 is performed when the processing of the second process of task A is completed, and the parallel processing of the third process of task A and the second process of task B is performed as shown in state 134. Thus, the reconfiguration 136 is performed when the processing of the second process of the task B is completed, and the third process of the task A and the third process of the task B are performed in parallel as shown in the state 138. When the processing of the third process of task B is completed in state 138, the first process of task C having the next highest priority cannot be combined with the third process of task A having a priority of 1, Processing of the third process of task A is continued without reconfiguration. Eventually, when the process of the third process of task A is completed, reconfiguration 140 is performed, and as shown in state 142, the process of the first process of task C having the highest priority at that time is executed alone. This is because there is no other task that can be combined with the first process of task C. Then, when the first process of task C ends, reconfiguration 144 for processing the second process of task C is performed.

  In the example described above, scheduling is performed on the assumption that a plurality of processes belonging to the same task are not executed simultaneously. Then, it is assumed that intermediate data obtained by processing by the preceding process is appropriately stored in a memory and used in the subsequent process. However, parallel processing for a plurality of processes of the task with the highest priority (at that time) may be prioritized over processing of the task with the next highest priority. In this case, the subsequent process directly uses the intermediate data generated by the preceding process. When such a plurality of processes cannot be pipelined, a combination with another task process may be performed. Needless to say, even if the task is not divided into a plurality of processes, even if a lower-level process belongs to the process belonging to the task, it can be processed in the same manner.

  Further, in the above description, an example in which only the processing instructions for tasks A, B, and C are received has been shown. However, when a processing instruction for another task having the same or different priority is received during these processes. May update the scheduler table 72 as necessary to perform dynamic scheduling. Further, the overhead required for reconfiguration may be shortened by determining the next floor plan layout based on the scheduler table 72 in advance before an interrupt is applied. In the above description, the example of examining the floor plan layout by dividing the area of the reconfigurable processor 34 into four parts has been shown. However, the area may be set more finely so that resources can be used efficiently. Good.

[Second Embodiment]
Next, a second embodiment will be described with reference to FIGS. The second embodiment is a modification of the first embodiment, and the hardware configuration shown in FIGS. 1 to 3 is basically the same as that of the first embodiment. However, in the second embodiment, the number of configuration data to be prepared and the combination thereof are different from those in the first embodiment.

  FIG. 9 is a diagram corresponding to FIG. 4 and shows the configuration data stored in the configuration data storage unit 50 in the present embodiment. Here, four configuration data 152, 154, 156 and 158 are provided as the task A first process layout group 150 which is the configuration data for the first process of task A. Specifically, in the configuration data 152, a logic circuit is set in the upper left area 1 divided into four, in the configuration data 154, a logic circuit is set in the upper right area 2, and in the configuration data 156, the logic circuit is set in the lower left area 3. In the configuration data 158, a logic circuit is set in the lower right area 4. The task B first process layout group 160, which is configuration data for the first process of task B, is provided with six pieces of configuration data 162, 164, 166, 168, 170, 172. , Upper area 1, 2, left area 1, 3, right area 2, 4, lower area 3, 4, upper right and lower left area 2, 3, upper left and lower right area 1, 4 The circuit is set up. As described above, in this embodiment, a plurality of pieces of configuration data having different logic circuit setting positions are prepared for each process of each task. In particular, in the example shown in FIG. 9, configuration data corresponding to all combinations of areas is prepared for each process of each task.

  FIG. 10 corresponds to FIG. 5 and shows the scheduler table 178 in the present embodiment. In this example, the number of floorplan layout divided areas, which indicates how many areas are divided and the floorplan layout is set, is “4” in the top row 180, and is used depending on the configuration data in the set. It is recorded that the “number of used areas” is “2”. Specifically, the second process of task A and the first process of task B are set, the second process of task A has a logic circuit in area 1, and the first process of task B is area 2 and 4 are recorded as having logic circuits.

  Information about each task is recorded below the level 182. In level 182, "task name", "priority", "status", "number of processes", "number of first process floor plan layout used areas", "second process floor plan layout". The items “number of used areas” and “number of third process floor plan layout used areas” are provided. The number of used areas represents how many of the four divided areas are used to set the logic circuit. In steps 184, 186, and 188, values corresponding to the items in step 104 are set for tasks A, B, and C, respectively.

  FIG. 11 is a flowchart corresponding to FIG. 7 and shows the flow of processing in the scheduler 60. The scheduler 60 updates the status in the scheduler table 178 when there is a task execution request or when a task end signal is input (S50). Subsequently, the status of the task with the highest priority among the unfinished tasks is checked (S52), the process to be processed is set as the process to be processed (S54), and the number of used areas of the process is recorded. To do. Then, it is determined whether the statuses of all tasks that have not been processed have been checked (S56). If there is an unchecked task, the status of the task with the next highest priority is checked (S58), and the total number of used areas is obtained by referring to the number of used areas of the process to be executed (S60). Subsequently, it is verified whether the total number of used areas exceeds the number of floor plan layout division areas (S62). If not, the process is set as a process to be processed (S64). The added area number is subtracted from the total area number (S66).

  On the other hand, if the statuses of all tasks are checked in step S56, the floor plan layout of the first set process is selected. If there are a plurality of floor plan layouts for this process, one of them is selected. Next, it is confirmed whether or not the process is set (S70). If it is set, the floor plan layout of the process is selected (S72), and the logic with the floor plan layout selected before is selected. The product is taken (S74). As a result, if the logical product does not become 0, that is, if there is an overlap in the floor plan layout, another floor plan layout for the same process is selected (S72), and the same processing is repeated. On the other hand, when the logical product becomes 0, step S70 and subsequent steps are repeated. In step S70, if there is no next set process, the configuration data corresponding to each selected floor plan layout is sequentially loaded from the configuration data storage unit 50 to the configuration memory 38 (S76).

  In the above description, it is assumed that configuration data corresponding to all combinations of areas exists for each process of each task. However, if there is only configuration data corresponding to a combination of some areas, a floor plan layout that does not overlap may not be found. Therefore, in such a case, for example, floor plan layout setting combined with the first embodiment may be performed.

[Third Embodiment]
Subsequently, a third embodiment will be described with reference to FIGS. The third embodiment is a modification of the second embodiment, and the basic hardware configuration and processing mode are the same as those of the second embodiment. However, in the third embodiment, it is assumed that a reconfiguration processor 34 having a different physical structure from that of the reconfiguration processor 34 in the second embodiment (and the first embodiment) is used. .

  FIG. 12 is a diagram schematically illustrating the structure of the reconfiguration processor 200 according to the present embodiment. In the reconfiguration processor 200, a plurality of PEs are arranged in the same manner as the reconfiguration processor 34. However, the upper left area 1 is provided with a direct input port 202 through which a large amount of data from the scanner can be input without restriction. Since PEs that can sufficiently bring out the performance of the direct input port 202 are limited to PEs in area 1, a task called scan processing A for processing image data generated by scanning is arranged in area 1. Is desirable. In area 4, a JPEG accelerator 204 having a hardware structure capable of processing JPEG (Joint Photographic Expert Group) image data at high speed is embedded. Since the PEs that can sufficiently bring out the performance of the JPEG accelerator 204 are limited to the PEs in the area 4, it is desirable to place a task called JPEG processing B in the area 4.

  FIG. 13 is a diagram corresponding to FIG. 10 and represents the scheduler table 210 in the present embodiment. In the uppermost stage 212 of the scheduler table 210, as in the case of FIG. 10, it is recorded that “the number of floor plan layout divided areas” is “4” and “the number of used areas” is “2”. ing. In the uppermost stage 212, the second process of task A and the first process of task B are currently set. The second process of task A has a logic circuit in area 3, and the first process of task B It is recorded that the process has logic circuits in areas 1 and 2.

  Information about each task is recorded in the column 214 and subsequent items, and the basic items are the same as those in FIG. However, in the scheduler table 210, an item “processing property” describing a special process included in the task is provided in the stage 214. Then, “task property” is set to “none” in task A in step 216, “process property” is set to “scan (area 1)” in task B in step 218, and “process” is set in task C in step 220. “Property” is set to “JPEG (area 4)”.

  Next, the operation of the scheduler 60 when the reconfiguration processor 200 and the scheduler table 210 are used will be described with reference to FIG. The scheduler 60 updates the status in the scheduler table 210 when there is a task execution request or when a task end signal is input (S80). Subsequently, the processing property of the task with the highest priority among the unfinished tasks is referred to (S82), and it is confirmed whether or not special processing is included (S84). As a result, special processing is included, and when a specific area of the reconfigurable processor 200 is used, a floor plan layout to be processed in that area is selected (S86). On the other hand, if the special process is not included, the floor plan layout is selected so as not to overlap with the processing position of the task using the special area (S86). The above processing is repeated for all tasks until there is no free area in the area (S90). That is, in this embodiment, a specific area is locked (locked) so that special processing is arranged for the specific area.

It is a figure which shows the schematic structural example of the image processing apparatus concerning this Embodiment. It is a figure which shows the schematic structural example of a reconfigurable arithmetic unit. It is a figure which shows the schematic structural example of a control part. It is a figure which shows the example of configuration data. It is a figure which shows the example of a scheduler table. It is a flowchart explaining the flow of the process in a reconfigurable arithmetic unit. It is a flowchart explaining the flow of the process in a control part. It is a figure explaining the example of reconstruction. It is a figure which shows another example of configuration data. It is a figure which shows another example of a scheduler table. It is a flowchart explaining the modification of the flow of the process in a control part. It is a figure which shows the modification of a structure of a reconfiguration processor. It is a figure which shows another example of a scheduler table. It is a flowchart explaining the modification of the flow of the process which can be put in a control part.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Image processing apparatus, 11 Internal bus, 12 CPU, 14 ROM, 16 RAM, 18 HDD, 20 Reconfigurable arithmetic unit, 22 Scanner, 24 Printer, 26 CDD, 28 Network interface, 30 Network, 34 Reconfiguration processor, 38 Configuration memory, 40 control unit, 42 internal interface, 44 memory interface, 46 output data storage unit, 48 input data storage unit, 50 configuration data storage unit, 60 scheduler, 62 priority status determination unit, 64 layout determination unit, 66 process Set unit, 68 Layout selection unit, 70 Interrupt detection unit, 72 Scheduler table, 74 Layout load unit.

Claims (7)

A reconfigurable circuit having a plurality of small circuits and capable of reconfiguring a logic specification in a part or all of the small circuits;
Storage means for storing a partial logical specification for processing one or more operations in a part of the small circuits for each of the one or more operations;
Acquisition means for acquiring processing requests for a plurality of operations that can be processed independently of each other;
Determining means for determining a logical specification for parallel processing of two or more operations requested for processing based on a combination of the partial logical specifications in which the small circuits do not overlap;
Reconfiguring means for dynamically reconfiguring the logic specification determined by the determining means for the reconfigurable circuit;
An arithmetic processing apparatus comprising: The arithmetic processing device according to claim 1,
The storage means stores a plurality of partial logic specifications for which at least some of the one or more operations are different in a small circuit for processing the operation,
The determining means selects a partial logical specification that can be combined without overlapping small circuits from a plurality of partial logical specifications with different small circuits for processing operations, and determines the logical specifications. An arithmetic processing unit. The arithmetic processing device according to claim 1,
A plurality of sub-partitions that partition the reconfigurable circuit so as to include at least one of the sub-circuits;
The determination means determines the combination of the partial logic specifications that the small circuits do not overlap based on the overlap information of the small sections used for the calculation processing. The arithmetic processing device according to claim 1,
Some of the small circuits have different physical structures from other small circuits,
The determination processing unit determines the combination of the partial logic specifications based on a difference in physical structure of the small circuit. In the arithmetic processing unit according to any one of claims 1 to 4,
The acquisition means also acquires processing priority information for the requested processing,
The arithmetic processing apparatus, wherein the determining means determines the logical specification based on the priority information. In the arithmetic processing unit according to any one of claims 1 to 5,
A plurality of determination means determine the logical specifications based on the total processing time for a plurality of operations requested to be processed. A computer having a plurality of small circuits and including a reconfigurable circuit capable of reconfiguring a logic specification in a part or all of the small circuits.
Storage means for storing a partial logical specification for processing one or more operations in a part of the small circuits for each of the one or more operations;
Acquisition means for acquiring processing requests for a plurality of operations that can be processed independently of each other;
Determining means for determining a logical specification for parallel processing of two or more operations requested for processing based on a combination of the partial logical specifications in which the small circuits do not overlap;
Reconfiguring means for dynamically reconfiguring the logic specification determined by the determining means for the reconfigurable circuit;
An arithmetic processing program characterized by being made to function.

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