JP2005165435A - Data transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmission method for trasmitting configuration data in a simple mechanism to a plurality of progressing elements(PE) formed of reconstitutable circuit areas. <P>SOLUTION: Preliminarily, FF 61 corresponding to each of a plurality of PE 21 are serially connected so that a transfer path 51 can be formed, and a plurality of data areas 75 are sequentially and continuously transferred between the plurality of FF 61. When the data area 75 pertinent to the PE 21 is transferred, the data of the data area 75 are read, and the data are written in the data area 75 so that the data can be exchanged by using the transfer path 51. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method suitable for transferring data to or between a plurality of processing elements.

Japanese Patent Publication No. 10-505993 discloses several methods for supplying configuration data to an FPGA. In the configuration in which configuration data is supplied to the FPGA as serial data, the clock signal is supplied from the FPGA to select the PROM in the configuration mode, and the selection of the PROM is canceled when the configuration of the FPGA is completed. In the configuration in which the FPGA is connected to the parallel ROM, the FPGA outputs an address signal and receives a data signal in the configuration mode. Further, it is described that, in the configuration mode, the configuration data is received by addressing the EPROM using a microprocessor instead of the FPGA. Further, it is described that the configuration data is transmitted by setting the FPGA in the configuration mode on the memory side, and the transmission of the configuration data is stopped when it is indicated that the configuration is completed from the FPGA.
Japanese National Patent Publication No. 10-505993

  For FPGA (Field Programmable Gate Array), a processor (dynamic reconfigurable processor) for dynamically reconfiguring a circuit has been proposed. For example, International Publication WO02 / 095946 is cited. Can do. This International Publication No. WO02 / 095946 has a region called a matrix in which a plurality of elements are arranged two-dimensionally, and a plurality of elements can be switched by switching the connection of wiring groups arranged vertically and horizontally in the matrix. The data flow (data path) can be reconfigured flexibly. The dynamically reconfigurable configuration is not limited to this, and there is a configuration in which elements are connected in a tree shape, adjacent elements are connected, and the elements are used as communication paths.

  When a circuit composed of a plurality of elements is dynamically reconfigured, it is important that configuration data (configuration data) for controlling the function can be provided to each element in a timely manner. A data transmission method that consumes a large number of cycles to send and receive configuration data requires time for reconfiguration and is not suitable for a dynamic reconfiguration processor. Therefore, the data transmission method that requires many steps of changing the circuit side to the configuration mode, outputting the clock or address, obtaining the configuration data, and stopping the transmission of the configuration data when the configuration change is completed is dynamic. This is not a suitable method for reconfigurable processors.

  A method of transferring data in parallel by bus connection to a plurality of elements constituting a circuit instead of transferring serial data is excellent in that the data transfer time can be shortened. However, when a large-scale circuit is realized by a reconfigurable processor, the number of elements to which configuration data is transferred becomes enormous and the bus width increases. Therefore, hardware resources for transferring configuration data are increased, and the processor is large and expensive. By adopting a shared bus format, the hardware resource problem is somewhat improved. However, since it is necessary to transfer data while designating each element with an address and occupying the bus, the time required for the transfer increases. Instead of the shared bus format, there is also a transfer method called wormhole routing in which data packets are divided into small pieces called Fritz and a plurality of elements are connected in a daisy chain. However, if there is no available route to reach the data transmission destination element, it becomes a deadlock state and it is difficult to always transfer data under stable conditions.

  Furthermore, these data transmission methods require a procedure in which the sending side announces that the data transfer is ready to the receiving side, and the receiving side announces that the sending side is ready to receive data. It requires processing time or hardware. When a large-scale reconfigurable circuit is to be realized, there is a possibility that the time or hardware for pre-processing and post-processing for data transfer cannot be ignored.

  Therefore, an object of the present invention is to provide a transmission method and a data processing apparatus that can transfer data in a stable state with a simple configuration. It is another object of the present invention to provide a transmission method and a data processing apparatus that can omit the time or hardware required for pre- and post-processing of data transfer.

  In the present invention, a register of a register group including a plurality of registers corresponding to each of a plurality of processing elements is connected in series in advance to form a shift register type transfer path. Then, using the transfer path, a step of continuously transferring a plurality of data areas in order between the registers included in the register group, and a data area transferred to one register of the register group, If a processing element corresponding to a register is usable, the present invention provides a data transmission method including an input / output step of reading data in the data area and / or writing data in the data area. In the present invention, a register group including a plurality of processing elements and a plurality of registers corresponding to each of the plurality of processing elements, wherein the registers included in the register group form a transfer path in advance. And a register group that sequentially transfers a plurality of data areas between these registers. In this data processing device, if the data area transferred to the register corresponding to the processing element among the plurality of registers is usable in the processing element, the processing element reads the data in the data area, And / or input / output means for writing data into the data area.

  In this data transmission method and data processing apparatus, a transfer path is formed by a plurality of registers connected in series in advance. Also, the data area is transferred instead of the data itself. In this specification, the data area indicates an area allocated for storing data, and dummy data can be used even when data that can be used in a processing element such as configuration data or has meaningful data has already been stored. This includes the case where an area is reserved for future use by storing meaningless data. Therefore, since the data area is transferred in the transfer process, there is no need to check whether the data is ready or whether the data is acceptable, and the connected upstream register. The data area can be simply transferred in a cycle unit to the downstream register. Furthermore, since the transfer path is formed in advance, there is no need for routing. For this reason, the time and hardware spent for exchanging signals before and after data transfer can be omitted.

  It is also possible to arrange and wire such that the registers constituting the transfer path are concentrated and arranged to form a shift register and the shift register and the processing element are connected by appropriate wiring. The simplest arrangement and wiring without wiring delay is to connect a register arranged in an adjacent processing element in an appropriate direction to form a shift register type transfer path. The wiring consumed to form the transfer path is minimized, and even when the reception point is far from the transmission point, the latency for transferring the shift register type transfer path needs to be considered. Therefore, there is no need to consider the delay due to wiring. When the processing elements are physically separated from each other, a relay shift register can be inserted at an arbitrary place, and no control or hardware is added.

  In each processing element, in the input / output process, if the data area transferred to the register corresponding to the processing element among the plurality of registers included in the register group is usable in the processing element, the data area Read data and / or write data to the data area. This allows individual processing elements to receive data, such as messages addressed to individual processing elements, from the transfer path and to throw messages addressed to other processing elements or control units to the transfer path, between processing elements or control Data can be exchanged between units and processing elements. Therefore, input and / or output processing in each processing element is independent, and a control signal between elements is unnecessary.

  Properties including the availability of the data area can be controlled by the processing element. If a data area is addressed to its own processing element, data or messages in that data area can be downloaded, and if the data area is unused, it can be used to send its own data or message. . By setting the priority, it is possible to provide a data transmission method used for exchanging messages with a high degree of urgency even in a data area being used by another element. It is also possible for the control unit connected to the transfer path to determine the properties of a plurality of data areas. If the control unit is a data transmission source, it is possible to send out a data area in which a destination element is designated. When data is transferred from one element to another element, the traffic on the transfer path can be controlled by setting such a property in the data area and sending it out.

  It is effective that the transfer path is closed. If it is not closed, data can be sent only from the upstream element to the downstream element, but if it is closed, data can be transferred from the downstream element to the upstream element. When the control unit wants to obtain data from an element, the control unit can obtain a response from the element through a closed transfer path by setting and sending out the data area to be used by the element. Therefore, data indicating the process in the input / output process and the address to be processed can be set in the data area. In order to secure processing time of the processing element for the data area, a transfer path in which a plurality of registers are assigned to one processing element is also possible.

  A register having the same or larger capacity as the amount of data that can be transmitted and received is basically unnecessary. When one data amount is large, it is possible to transmit a data unit, which is processed independently for each processing element in the input / output process, by a plurality of continuous data areas. That is, by using the transfer path and the data area of the present invention, the data packet can be divided into register sizes and transferred in a daisy chain. By transmitting using a plurality of continuous data areas, it is possible to manage subsequent data areas by setting a transmission destination in the first data area. In the data transmission method of the present invention, even if a data packet becomes large, it is not necessary to temporarily buffer the entire data packet in order to transfer it. As the amount of shift registers connected in series increases, latency may increase, but delay due to buffering does not increase. Compared to the shared bus system, the entire packet does not need to be buffered once on the transmission / reception side, so the processing time is reduced accordingly.

  However, in a data processing apparatus having a large number of processing elements, when it is desired to reduce the latency, a plurality of transfer paths are provided, and the plurality of transfer paths are connected to the control unit by a distribution unit, and a plurality of data areas are connected to The data area can be allocated to the transfer path to which the usable processor element belongs. By providing this distribution step, the number of shift registers forming a transfer path reaching a desired processing element is reduced, so that the latency is reduced.

  Further, if the plurality of transfer paths are closed transfer paths having the same latency, the control unit receives the data areas sequentially sent to the plurality of transfer paths via the distribution unit without colliding with each other. be able to. Therefore, according to the present invention, it is possible to provide a data transmission method using a plurality of transfer paths, which does not require special control.

  A preferred embodiment to which the present invention is applied is a data processing apparatus having a plurality of processing elements, and by reconfiguring the function of the plurality of processing elements, the configuration of a circuit formed by connecting the plurality of processing elements is reconfigured It can be done. Each processing element includes a data path area whose function can be changed, and a memory that stores a plurality of configuration information for setting the data path area. By storing the configuration data in a data area that moves like a merry-go-round on the transmission path and transferring it to a desired processing element, the configuration data can be supplied in a timely manner with a simple mechanism. In the input / output process, data can be transferred from the data area to the memory, and a reconfigurable circuit area can be reconfigured. Further, the data can be sent to the control unit by sending the data area for output from the control unit and transferring the data from the memory of the desired processing element to the data area.

  Information stored in a plurality of data areas need not be plain information. An area for storing the encrypted data can be provided, and the case where the entire data area is encrypted is also included. In the input / output process and the input / output means, data in the data area can be read and decoded, and encrypted data can be written in the data area.

  In the present invention, a transfer path in which a plurality of registers corresponding to a plurality of processing elements are connected in series is used, and a data area that can be used by each processing element is circulated like a merry-go-round, between elements and between the element and the control unit. Exchange data between. Since the data area circulates through the shift register type transfer path and each element uses it, hardware for transferring data is simple, and flow control is also unnecessary. For this reason, in a data processing apparatus equipped with a large number of processing elements, for example, a reconfigurable LSI, hardware resources for supplying configuration information to the processing elements individually can be reduced, and the compact and low cost can be achieved. A reconfigurable LSI can be provided.

  FIG. 1 shows an example of a data processing apparatus. This data processing device 1 is a chip processing unit (PU), and includes a reconfigurable area 19, a function for reconfiguring the reconfigurable area 19, and a function for controlling input / output. And a fixed configuration area that supports the function.

  The reconfigurable circuit area 19 is divided into a plurality of segments 10 to 15 in FIG. 1, but a plurality of elements are two-dimensionally arranged in an array or matrix as shown in FIG. This is a configuration called a matrix. The matrix 19 of this example includes a plurality of processing elements (PE) 21 arranged two-dimensionally in the vertical and horizontal directions, wirings 22 arranged in a lattice pattern between them, and vertical and horizontal wirings 22 at connection points of the wirings 22. And a switching unit 23 that can freely switch the connection. The PE 21 may be a function that can be freely set by a lookup table or the like. In this example, there are some functional groups such as elements for arithmetic and logic operations, delay elements, memory elements, elements that generate addresses to input or output data, and elements that input or output data. The space efficiency of the matrix 19 is improved by arranging elements having internal configurations suitable for the respective processes. In addition, since the redundancy is reduced by arranging the elements divided into a certain number of function groups, there is an advantage that AC characteristics and processing speed can be improved.

  3 and 4 are examples of PE21. The PE 21 includes an internal data path area 29 whose function can be changed, and a setting unit 60 for setting the function of the internal data path area 29. The internal data path area 29a of the PE 21a shown in FIG. 3 includes an address generation circuit 28 composed of a counter and the like, and a selector SEL, and an address generated under the conditions set by the setting unit 60 is used as the output signal do. Output to the wiring 22. The output signal do is fed back to the PE 21a as an input signal dix or diy as it is or after being processed by another PE 21 via the row wiring and the column wiring. The address selected by the selector SEL under the conditions set by the setting unit 60 is output from the matrix 19 as an address for data input or output. The PE 21 a also includes a selector (not shown) for selecting input data from any of the wirings 22 and outputting the output data, and setting thereof is performed by the setting unit 60.

  The PE 21b shown in FIG. 4 has a configuration suitable for arithmetic operations and logical operations. The internal data path unit 29b includes a shift circuit SHIFT, a mask circuit MASK, and a logical operation unit ALU. Similarly to the PE 21a, the setting unit 60 sets the states of the shift circuit SHIFT, the mask circuit MASK, and the logical operation unit ALU. Therefore, the input data dix and diy can be added or subtracted, compared, or a logical sum or logical product can be calculated, and the result can be output to the wiring (bus) 22 as an output signal do.

  As shown in FIGS. 1 and 2, the matrix 19 of PU1 includes 368 PEs 21, and six segments 10 to 15 are formed in order to separately form transfer paths for supplying configuration data thereto. Is divided into forms. However, the PE 21 is not grouped into a plurality of segments by these segments 10 to 15 in that a data flow is constituted by a plurality of PEs 21 and input data is processed. Therefore, the PE 21 can be flexibly connected by the wiring group 22, and a data flow (data path) across a plurality of segments can be freely configured.

  Two types of interfaces for inputting / outputting data to be processed in a data path constituted by a plurality of PEs 21 are prepared in the matrix 19. One is direct inputs 31a to 31c and direct outputs 32a to 32c, and data can be directly input to and output from the PE 21 from the outside. A plurality of PU1s can be connected using the direct inputs 31a to 31b and the direct outputs 32a to 32c, and the real number of PEs 21 constituting the data path can be further increased. As a result, application processing in which circuit elements are insufficient in one chip (PU) 1 can be dealt with by linking a plurality of chips 1.

  The PU 1 further has a configuration for supplying data to the matrix 19 using an input buffer 33 and an output buffer 34 as another input method. The input buffer 33 includes four input elements LDB, and the configuration and control of the buffer 33 can be set by configuration data. Similarly, the output buffer 34 includes four output elements STB, and the configuration and control can be set by configuration data.

  Configuration data for the matrix 19 and the input / output buffers 33 and 34 is supplied from the RISC 35 or another PU 1 by the shift register type data transmission mechanism 50. In this example, the data transmission mechanism 50 includes a transfer control unit (TCU) 59 and transfer paths 51 to 58 that extend around each of the segments 10 to 15, the input buffer 33, and the output buffer 34. . The TCU 59 is connected to a bus switching unit (bus interface, BSU) 36, and the RISC 35 supplies configuration data to the TCU 59 via the BSU 36.

  As shown in FIG. 1, a plurality of components or interfaces are connected to the BSU 36, and configuration data can be sent to the matrix 19 using these components or interfaces, not limited to the RISC 35. First, an SDRAM interface 37 is connected to the BSU 36, and configuration data can be provided from an external memory. Further, since it is also connected to the PCI bus interface 38, configuration data can be supplied from an external processor connected to the PCI bus. As another component, a DMAC 39 is also connected to the BSU 36, and it is possible to control the supply of configuration data instead of the RISC 35. In addition, a general-purpose interface 40 such as an asynchronous communication device (UART) serving as a serial interface controller is connected to the BSU 36 via a bus bridge circuit 41. Furthermore, the input buffer 33 and the output buffer 34 of the matrix 19 are connected to the BSU 36, and data can be input / output to / from the matrix 19 through the interface described above.

  FIG. 5 shows more detailed routing of the transfer paths 51 to 58 of the data transmission mechanism 50. FIG. 6 shows a mechanism for inputting / outputting data using a transfer path in each element. Each of the transfer paths 51 to 56 is a wiring that serially connects 1-word (32-bit) registers (flip-flops) provided in the PE 21 included in each of the segments 10 to 15 shown in FIG. The transfer paths 51 to 56 are mainly configured by connecting a plurality of registers provided corresponding to each PE 21 in series. It is possible to connect independent registers between or before and after the registers of PE21, which is effective when the transfer path becomes long or the latency needs to be adjusted.

  With reference to FIG. 6, the configuration of each PE 21 will be described using the transfer path 51 as an example. The setting unit 60 of the PE 21 includes a 32-bit register (FF) 61, and is connected to the FF 61 of the PE 21 adjacent to the front and rear by a 32-bit transfer path 51. Therefore, in the transfer path 51, 1-word data 75 transmitted to the FF 61 of one PE 21 is transmitted to the FF 61 of the next PE 21 with a delay of one clock or one cycle.

  The setting unit 60 further sets the decoder 62 that decodes the data 75 stored in the FF 61, the background operation unit 63 that operates in the background to store the data 75, and the local data path area 29. And a foreground operation unit 64 in which configuration data is stored. The background operation unit 63 selects a background bank 65 of three banks, a selector 66 that distributes the data 75 stored in the FF 61 to a line that is directly output to each bank of the background memory 65, and a bank of the memory 65. And a selector 67 that can output data. The foreground operation unit 64 stores the setting data supplied to the data path area 29 to maintain the current configuration of the data path area 29 and the background memory 65 or the transfer to the foreground memory 68. A selector 69 is provided for selecting and supplying data from the FF 61 on the path 51. The selectors 67 and 69 for selecting configuration data (setting data) to be loaded into the foreground memory 68 are controlled by the second selectors 72 and 70 for selecting a selection signal, and the data set in the FF 61 by the transfer path 51 It can be controlled from the configuration data set in the foreground memory 68. The selectors 67 and 69 may be controlled by a signal directly supplied from the RISC 35.

  The setting unit 60 has an output selector 71 that can select the data 75 to be supplied to the FF 61 of the downstream PE 21 from any of the data of the FF 61 of its own PE 21, the data of the bank of the background memory 65, and the data of the foreground memory 68. I have. The decoder 62 analyzes the data 75 transferred to the FF 61 of its own PE 21 to switch the output selector 71 and select the data 75 to be transferred to the FF 61 of the downstream PE 21.

  FIG. 7 shows an outline of the processing of the decoder 62 that realizes the data transmission method using the transfer path 51. In step 81, it is determined whether or not the data 75 transferred to the FF 61 is data to be processed by its own PE 21. If the own PE 21 is not the data to be processed, the selector 71 is made through in step 87. Next, if it is determined that the data 75 transferred to the FF 61 is data to be processed by its own PE 21 and is control data in step 82, the decoder 62 selects the selector related to the foreground memory 68 in step 83. And the contents of the foreground memory 68 are updated. As a result, the configuration of the local data path area 29 is changed. In step 87, the selector 71 remains set to through.

  When the data 75 transferred to the FF 61 is not for control, it is a data area reserved by dummy data for writing data stored in the PE 21 or data of the PE 21. Therefore, if the data 75 transferred to the FF 61 is stored in the background memory 65 or the foreground memory 68 in step 84, the data read from the FF 61 is stored in the designated memory in step 85. In step 87, the selector 71 remains set to through.

  On the other hand, if the data 75 transferred to the FF 61 is a dummy in step 84, the selector 71 is switched in step 86 to transfer the contents of the background memory 65 or the foreground memory 68 to the FF 61 of the downstream PE 21. The contents of the foreground memory 68 indicate the processing state of the PE 21 and are used to check the processing state, determine the presence or absence of an error, etc. in the debug unit or the RISC 35. The content of the background memory 65 indicates the function assigned to the PE 21. For example, when an error occurs in the PE 21 or when it is necessary to reconfigure the data flow including the PE 21 And used when transferring configuration data to the alternative PE 21.

  In the data transmission mechanism 50 of this example, the transfer path 51 formed by connecting the FF 61 of each PE 21 is a shift register type transfer path in which data 75 is transferred from the upstream FF 61 to the downstream FF 61 in units of clocks or cycles. It is. There is no control mechanism for stopping or waiting for the transfer of the data 75 between the FFs 61, and the 32-bit data 75 is continuously transferred between the FFs in order. The data 75 transferred between the plurality of FFs 61 is basically not changed, and when there is a read request, the data 75 transferred to the downstream FF 61 is replaced with the output of the PE 21 memory. Therefore, the data 75 in units of words transferred between the FFs 61 is a data area that is released or set so that a certain PE 21 can be used exclusively, and can be read and written, but is transferred by the FF 61. The data area does not disappear, and the transfer path 51 is not released from the data area transfer.

  The data area may be dedicated to one specific PE 21 or may be dedicated to a plurality of PEs 21 that are the respective owners of the plurality of FFs 61 connected by the transfer path 51. Therefore, common data or messages can be sent to the plurality of PEs 21 using the transfer path 51. If the PE 21 connected by the transfer path 51 has a function for changing the properties of the data area 75 such as the destination (owner), reading, and writing, the property of the data area 75 that has achieved the purpose can be changed to change the other properties. Can be used for purposes. In this example, the properties of the data area 75 are collectively managed by the transmission control unit (TCU) 59 in order to simplify the function in the PE 21.

  FIG. 5 shows a schematic configuration of the TCU 59. The TCU 59 includes a data area management unit 91 and a delivery unit 92 that collects and delivers the data area 75 having the conditions set by the data area management unit 91 to the transfer paths 51 to 58. The data area management unit 91 includes a bus control unit 95 that manages data exchange with the BSU 36, a transmission unit 93, and a reception unit 94. The transmission unit 93 includes a buffer 96, an encryption processing circuit 97, and a parameter setting circuit 98. The encryption processing circuit 97 encrypts the data stored in the data area 75 if necessary, and conversely decrypts the encrypted data supplied from the BSU 36 if necessary. The parameter setting circuit 98 attaches a header to the data area 75 to be sent and sets the properties of the data area.

  In PU1, all the transfer paths 51 to 58 are closed, and the data area 75 sent from the TCU 59 returns to the TCU 59. Further, the reception unit 94 of the TCU 59 uses the read FIFO 99 for receiving the data area 75 returned from the transfer paths 51 to 58 and the data included in the received data area 75 to the bus control unit 95. A selector 105 that can select whether to output or supply to the transmission unit 93 and supply to another PE 21 through the same or different transfer paths 51 to 58 is provided.

  The delivery unit 92 includes a selector 101 that distributes and outputs the data area 75 output from the transmission unit 93 to any of the transfer paths 51 to 56 to which the destination PE 21 belongs. The PE 21 belongs to any one of the segments 10 to 15, and the data area 75 (at least the data area storing the header at the beginning of the data unit) 75 includes the segment information. You can choose. Further, in PU1, the input buffer 33 and the output buffer 34 are also controlled by the data transmission mechanism 50, and transfer paths 57 and 58 for connecting the respective elements are provided. The delivery unit 92 further includes a selector 102 that collects the data areas 75 returned from the transfer paths 51 to 58 and supplies them to the reception unit 94. In PU1, since the latencies of the transfer paths 51 to 58 are designed to be the same, the selector 102 for aggregation does not need to select the transfer paths 51 to 58, and makes a round of the transfer paths 51 to 58. The received data area 75 is recovered by the receiving unit 94 without colliding.

  The segments 10 to 15 are provided with substantially the same number of PEs 21, and FIFOs (registers) 61 corresponding to the PEs 21 included in the respective segments are used as register groups, and transfer paths 51 to 51 passing through these registers in series. The 56 latencies are arranged to be the same. That is, the number of FFs 61 in the register group constituting each of the shift register type transfer paths 51 to 56 is arranged to be equal. The number of FFs constituting each transfer path is determined so that the buffer transfer paths 57 and 58 also have the same segment and latency. Therefore, the data area 75 sent in order from the transmission unit 93 is transferred through the transfer paths 51 to 58 without breaking the order, and reaches the order sent to the selector 102 for aggregation. Therefore, when the receiving unit 94 sends the data in the data area 75 to the RISC 35 via the bus control unit 95 and the BSU 36 in the order of arrival, the RISC 35 can obtain the data in the order output by the sending unit 93. Therefore, the RISC 35 does not need to be aware of which position of which segment each PE 21 is physically located, and only outputs the data with the information indicating the segment and the address in the segment. Data can be supplied to the PE 21 and desired PE 21 data can be acquired.

  Data sent to the PE 21 is not limited to one word, and in many cases, it is several words or more. Therefore, it is unlikely that a single data area 75 can transmit a data unit in which independent processing is performed by the PE, that is, processing for reading and writing is performed, and a plurality of data areas are consumed. Although a header may be provided for each of the plurality of data areas 75, the area consumed by the headers is reduced. For this reason, in the PU 1 of this example, a data unit for which independent processing is performed in each PE 21 is transmitted by a plurality of continuous data areas 75, and data management information such as parameters is stored in the head data area 75. Data transfer efficiency is improved by storing as much as possible in the header. Therefore, a packet of one word or more is divided into a plurality and transferred through the FF 61 of the transfer path 51 in a daisy chain.

  FIG. 8A shows the configuration of the header. In this example, since one word is consumed in the header 76, the header 76 is stored in the data area 75 transmitted through the transfer path 51 first. The field 76a is a segment number, and the delivery unit 92 of the TCU 59 determines the transfer paths 51 to 58 to be distributed according to the value of the field 76a. The fields 76b and 76c are information indicating the X position and the Y position in the segment of the destination PE 21. Therefore, the fields 76a to 76c are address information for specifying the PE 21 that is the owner of the data area 75, and the setting unit 60 of the PE 21 decodes the information to determine whether the data area is addressed to itself. to decide. The field 76d is a field for discriminating between write access and read access. In the case of writing, data to be written to the memory of the PE 21 is stored in the subsequent data area 75. If it is a read, dummy data is stored in the subsequent data area 75, and the PE 21 outputs the specified memory information as the data area 75 instead of the dummy data, and sends it to the FF 61 of the subsequent PE 21. Become.

  A field 76e indicates that data is transferred by a plurality of data areas 75, and a field 76f indicates the number of data areas 75 that store data following the data area 75 that stores headers. Therefore, as shown in FIG. 8B, the PE 21 designated as the destination by the header follows the data area 75 of the header, and the data area of data (for example, configuration data) 77 continuously transferred to the FF 61 75 is determined to be a data area owned by itself by the number specified in the header, and data is input / output to / from these data areas 75. A field 76g indicates that a plurality of data areas 75, instead of one, are burst transferred following the header. The background memory 65 and the foreground memory 68 of the PE 21 are configured to allow continuous input / output by burst access. In burst access, a method of specifying the number of bursts or fixing the number of bursts can be adopted. Further, instead of designating the number of times, it is also possible to adopt a method of storing data one after another from designated addresses in the memory of the PE 21 and ending the burst access when writing up to a preset address. The same applies to reading. It is possible to simultaneously specify an address for inputting / outputting data and an amount of data to be input / output, thereby reducing the amount of header data.

  A field 76h indicates a bank number for storing or reading data in each PE 21. By designating the bank number, at the time of write access, the data 77 transferred by the data area 75 is written to the designated bank of the background memory 65 or the foreground memory 68. At the time of read access, the dummy data transferred to secure the data area 75 is replaced with the data of the designated bank and transferred to the next FF 61.

  The field 76i is for selection of encryption / non-encryption, and it is determined by this bit whether or not it is an encrypted packet. When encrypted data is sent, it is also encrypted and output when the data is read. The encryption / non-encryption separation can be freely set, and can be specified in chip units, segment units, element units, or bank units. The field 76j is used for designating a CRC. Thereby, the reliability of the data or message stored in the data area 75 can be improved.

  The header 76 can be set other than the above. For example, one can function as a control packet. The data area 75 can be used for broadcasting to provide data or messages to all the PEs 21 that circulate. It is suitable for segment unit control and can be powered down on a segment basis. Further, the control data can be used for setting the transmission unit 93 of the TCU 59. If the header for the control packet is output by the same procedure as the transfer of the header for the control packet to the PE 21 by the RISC 35, the control packet passes through the TCU 59 and can be used for setting the TCM 59. By specifying the bank number of the parameter setting circuit 98, the data transferred by all the data areas 75 thereafter can be set to be stored in the same bank.

  FIG. 9 shows examples of some packets that can be transmitted to the PE 21 via the transfer path 51. FIG. 9A shows a control packet. By storing the header 76 in the data area 75 and transmitting it alone, the PE 21 specified by the header 76 can be controlled. FIG. 9B shows a single write access packet, in which the data area 75 storing the write data is transferred following the data area 75 storing the header 76 through the FF 61 constituting the transfer path 51. FIG. 9C shows a burst write access packet, and a plurality of data areas 75 storing write data are transferred through the transfer path 51 following the data area 75 storing the header 76.

  FIG. 9D shows a single read access request packet. The data area 75 storing dummy data is transmitted through the transfer path 51 following the data area 75 storing the header 76. Then, as shown in FIG. 9E, the single read access response packet is returned by the transfer path 51 which is a closed circuit. As a single read access response packet, a data area 75 in which dummy data is replaced with read data 78 is transmitted in the target PE 21 following the data area 75 storing the header 76. FIG. 9F shows a burst read access request packet, and a plurality of data areas 75 storing dummy data are transmitted through the transfer path 51 following the data area 75 storing the header 76. Then, the burst read response packet shown in FIG. 9G is returned by the transfer path 51 of the closed circuit. Following the data area 75 storing the header 76, a plurality of data areas 75 in which dummy data is replaced with the read data 78 are transmitted as burst read response packets.

  If the RISC 35 is a control unit that performs communication management with respect to the PE 21 in the matrix 19, the RISC 35 sends the data to be written to the destination PE 21 to the TCU 59 as a packet having header data that identifies the PE 21, and the TCU 59 writes the data. The desired data is divided into data areas 75 and sent to a transfer path, for example, the transfer path 51. Then, when the PE 21 receives the data area 75 addressed to itself, the data contained in the data area 75 is written into the memory. Therefore, the RISC 35 can write data to the desired PE 21 without knowing the physical position of the PE 21.

  When the RISC 35 wants to read data from a desired PE 21, the RISC 35 sends a packet having header data that identifies the PE 21 and data that indicates the amount of data to be read to the TCU 59. The TCU 59 secures a data area 75 that can store the amount of data to be read using dummy data, and sends it to the transfer path 51. When the PE 21 receives the data area 75 addressed to itself, the PE 21 sends the designated data to the transfer path 51 instead of the dummy data. Therefore, data can be supplied from the local side to the RISC 35 via the transfer path 51 using the timing assigned in advance to the PE 21.

  In this shift register type data transmission mechanism 50, since the data area 75 used by the PE 21 belonging to the transfer path is reserved, the amount of data moving through the transfer path does not increase or decrease during data transmission / reception. There is no competition between input and output for different PEs 21. Therefore, the data area 75 can be continuously transferred in units of cycles between the FFs 61 forming the transfer path, and there is no need to stop the transfer of the data area 75 or wait. For this reason, hardware and software for managing the input / output timing of data in the middle of transmission are unnecessary, and data can be input to and read out from a desired PE 21 with an extremely simple configuration. The data area 75 to which the FF constituting the transfer path is transferred can be handled like a window of one word, and the RISC 35 can flow data through the transfer path by writing a packet in the window. In the PE 21, the self-addressed data area 75 is in a state where a window is opened, and data can be read from and written to the window. The data area 75 addressed to another PE is passed through the FF of the next PE 21 with the window closed.

  Further, in this data transmission mechanism 50, since the transfer path is constituted by a shift register, it is not necessary to buffer all the packet data output from the RISC 35. Data supplied from the RISC 35 to the TCU 59 can be output to the transfer path one word at a time. Therefore, even if it is influenced by the BSU 36 or the like, it is basically the speed output from the RISC 35, does not cause the RISC 35 to wait, and does not waste time in buffering data. 51 to 58 can be sent. Therefore, the data transmission mechanism 50 is a high-speed data transfer system with a simple configuration.

  Since data is transmitted through many FFs constituting the transfer path, there is a possibility that the timing at which the data reaches the desired PE 21 may be delayed. However, considering buffering of packet data by FIFO or the like, there is no difference in data arrival time except when the number of FFs constituting the transfer path is much larger than the number of words of packet data. In the case of a system that repeats buffering, the data transmission mechanism 50 of the present example also shortens the time for data to arrive first. Further, when the latency of the transfer path is large, it can be shortened by widening the bandwidth of the transfer path, but the hardware resources are considerably increased. On the other hand, like PU1 of this example, it is possible to design to reduce the latency of each transfer path by dividing the transfer path into segments. By dividing the transfer path for each segment, it is possible to prevent an increase in hardware resources, and it is not necessary to decode the segment in each PE, so that the configuration of the decoder 62 is simplified.

  The data processing device 2 shown in FIG. 10 is a large-scale reconfigurable data processing device including four matrices 19 having the same scale as the PU 1 described above. Even when the number of PEs increases in such a large scale, the transfer path is divided for each matrix, and the distribution circuit 5 that distributes the data area 75 to each matrix 19 is provided to prevent an increase in latency. be able to. By forming a group larger than the segment, for example, a macro segment and hierarchizing the transfer paths, the number of stages of shift registers included in each transfer path is reduced. For this reason, the latency is reduced by the layered transfer path, but on the other hand, information specifying the layered transfer path is increased and the header is increased. If the header becomes large, there is a possibility that transmission cannot be performed in one data area 75, and overhead increases and communication speed decreases. In this case, it is possible to output a control packet for setting the route of the distribution circuit and fix the transfer path selected by the distribution circuit. Since it is not necessary to output information specifying the transfer path until the transfer path is switched by the next control packet, header information can be reduced, and an increase in overhead can be prevented by transmitting the header information.

  In the above description, the configuration data of each PE 21 is updated from the RISC 35 via the data transmission mechanism 50. However, the configuration data is not limited to the RISC 35, and can be supplied from any component connected to the BSU 36. . The DMAC 39 can transfer configuration data from various memories (SDRAM, PCI bus) mapped in the RISC memory space to the TCU 59 and supply the configuration data to the PE 21. When configuration data is encrypted and supplied from an external memory, a decryption circuit is configured in the matrix 19, the encrypted configuration information is decrypted using the function of the matrix 19, and the configuration data is transmitted via the BSU 36. To the TCU 59. Then, the decrypted configuration data can be supplied to each PE 21 of the matrix 19. It is also effective to provide a RAM for temporarily storing configuration data in PU1. By storing the configuration data decoded by the matrix 19 or storing the configuration data supplied from the external memory, a plurality of configurations can be obtained regardless of the processing status of the matrix 19 and the processing status of the BSU 36. Data can be temporarily stored in RAM. For this reason, it can be reliably and timely supplied from the TCU 59 to the PE 21 by the configuration information replacement instruction.

  In the PE 21, it is desirable that the clock signals of the setting unit 60 and the data path unit 29 can be managed individually. In particular, the setting unit 60 has a function of stopping the clock signal of the data path unit 29 or delaying the frequency without stopping the clock signal to the circuit included in the data transmission mechanism 50 that transfers the data through the transfer path 51. It is desirable to have it. The power consumption of each PE 21 can be reduced without affecting the configuration data transfer, and fine power control can be performed.

  In the above description, an example in which data or a message is exchanged between the RISC 35 and the PE 21 has been described. However, data can be exchanged between the PEs 21 using the transfer path 51. Further, in the above, the TCU 59 is provided with a circuit 105 that can transfer the data area 75 from the downstream transfer path 51 to the upstream transfer path 51 or any of different transfer paths 52 to 56. Therefore, not only data can be supplied from the upstream PE 21 to the downstream PE 21 but also data can be supplied from the downstream PE 21 to the upstream PE 21, and data can be exchanged between the PEs 21 included in different transfer paths.

It is a figure which shows the outline | summary of a processing unit (PU). It is a figure which shows the outline | summary of a matrix. It is a figure which shows an example of a processing element (PE). It is a figure which shows the other example of PE. It is a figure which shows the state which connected PE by the transfer path. It is a figure which expands and shows the connection between PE. It is a flowchart which shows operation of the decoder of the setting unit of PE. FIG. 8A shows the configuration of header information, and FIG. 8B shows the configuration for transmitting packet data including header information. 9A is a control packet, FIG. 9B is a single write access packet, FIG. 9C is a burst write access packet, FIG. 9D is a single read access request packet, and FIG. ) Is a single read access response packet, FIG. 9 (f) is a burst read access request packet, and FIG. 9 (g) is a diagram showing the structure of a burst read access response packet. It is a figure which shows the example from which PU differs.

Explanation of symbols

1, 2 Data processing unit (PU)
10-15 Segment 19 Matrix 21 Processing Element (PE)
29 Internal data path area 50 Data transmission mechanism 51 to 58 Transfer path 59 Transfer control unit (TCU)
60 Setting unit 61 Flip-flop (FF, register)
75 Data transfer area

Claims (18)

Using a transfer path in which a register group including a plurality of registers corresponding to each of a plurality of processing elements is connected in series in advance, and sequentially transferring a plurality of data areas;
An input / output step of reading data in the data area and / or writing data in the data area, if a processing element corresponding to the register can use the data area transferred to one register of the register group A data transmission method comprising:   2. The data transmission method according to claim 1, further comprising a step in which a control unit connected to the transfer path determines properties of the plurality of data areas.   2. The data transmission method according to claim 1, wherein the transfer path is closed.   3. The transfer path according to claim 2, wherein a plurality of transfer paths are connected to the control unit via a distribution unit, and the plurality of data areas are assigned to the transfer paths to which processor elements that can use the respective data areas belong. A data transmission method further comprising a distribution step.   5. The data transmission method according to claim 4, wherein the plurality of transfer paths are closed transfer paths having the same latency. The processing element according to claim 1, comprising a data path area whose function can be changed, and a memory for storing a plurality of configuration information for setting the data path area.
In the input / output step, a data transmission method of transferring data from the data area to the memory or transferring data from the memory to the data area.   2. The data transmission method according to claim 1, wherein the data area includes data indicating processing in the input / output process and an address to be processed.   2. The data transmission method according to claim 1, wherein a data unit in which independent processing is performed for each processing element in the input / output step is transmitted by the plurality of continuous data areas.   2. The data area according to claim 1, wherein the plurality of data areas include an area for storing encrypted data, and in the input / output step, data in the data area is read and decoded and / or stored in the data area. A data transmission method for writing encrypted data. Multiple processing elements,
A register group including a plurality of registers corresponding to each of the plurality of processing elements, connected in series so as to form a transfer path in advance, and sequentially transferring a plurality of data areas in order Have
If the data area transferred to the register corresponding to the processing element among the plurality of registers is usable by the processing element, the processing element reads data in the data area and / or the data A data processing apparatus comprising input / output means for writing data to an area.   11. The data processing apparatus according to claim 10, further comprising a control unit that is connected to the transfer path and that determines properties of the plurality of data areas.   The data processing device according to claim 10, wherein the transfer path is closed.   12. The distribution according to claim 11, wherein the plurality of transfer paths and the plurality of transfer paths are connected to the control unit, and the plurality of data areas are distributed to the transfer paths to which processor elements that can use the respective data areas belong. A data processing apparatus further comprising a unit.   14. The data processing device according to claim 13, wherein the plurality of transfer paths are closed transfer paths having the same latency. The processing element according to claim 10, comprising: a data path area whose function can be changed; and a memory for storing a plurality of configuration information for setting the data path area.
The input / output means transfers data from the data area to the memory, or transfers data from the memory to the data area.   11. The data processing apparatus according to claim 10, wherein the data area includes data indicating processing of the input / output means and an address to be processed.   11. The data processing apparatus according to claim 10, wherein the input / output unit inputs / outputs a data unit for performing independent processing in the processing element to the plurality of continuous data areas.   11. The data area according to claim 10, wherein the plurality of data areas include an area for storing encrypted data, and the input / output means reads and decodes data in the data area and / or stores the data area in the data area. A data processing device that writes encrypted data.

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