JP2007272395A - Date flow graph generation device, setting data generation device of integrated circuit, processor, and integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reconfigure a DFG to a size which can be mapped to a reconfigurable circuit and reduce a use quantity of a memory necessary for data transfer among sub-DFGs. <P>SOLUTION: A data flow graph processing unit 31 includes a DFG dividing unit 60, a sub-DFG optimizing unit 61 and a DFG combining unit 62. The Dividing unit 60 divides a DFG generated from a compile unit 30 to generate a plurality of sub-DFGs. The optimizing unit 61 optimizes the sub-DFGs generated from the dividing unit 60. For example, if there is the case in which the data with the identical content is outputted from a plurality of nodes in the same sub-DFG to a memory, the optimizing unit 61 outputs data to the identical address of the memory from the plurality of nodes. The combining unit 62 generates DFGs in which the plurality of sub-DFGs optimized by the optimizing unit 61. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a technique for generating a data flow graph necessary for setting an operation of an integrated circuit.

  In recent years, development of reconfigurable processors capable of changing hardware operations in accordance with applications has been underway. As an architecture for realizing a reconfigurable processor, there are methods using a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array).

  An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource that connects the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high compared to an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).

  For example, in satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified to improve versatility, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has attracted attention to dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as cellular phones and PDAs (Personal Data Assistance) must be downsized, and if LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, Mounting area can be reduced.

  The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, in order to enable connection between all the basic cells, it is necessary to include a large number of switches and a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Further, since a complicated wiring pattern is used for the connection between the basic cells, the wiring tends to be long, and the delay increases because of the structure in which many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like. Furthermore, in the FPGA, it is necessary to send configuration information to a large number of basic cells of the LUT method, so that it takes a considerable time to configure the circuit. For this reason, the FPGA is not suitable for applications that require instantaneous switching of the circuit configuration.

  In order to solve these problems, in recent years, a reconfigurable processor using an ALU array in which multi-functional elements having a plurality of basic arithmetic functions called ALU (Arithmetic Logic Unit) are arranged in multiple stages has been studied. In the ALU array, processing flows in one direction from the top to the bottom, so wiring that connects the ALUs in the horizontal direction is basically unnecessary. Therefore, the circuit scale can be reduced as compared with the FPGA.

In the ALU array, the calculation function configuration of the ALU circuit and the wiring of the connection part connecting the preceding and succeeding ALUs are controlled by command data, and the expected calculation process can be executed. The command data is generally created based on the data flow graph (DFG: Data Flow Graph) created from a source program described in a high-level program language such as C language.
Since the size of the DFG that can be mapped on the ALU array at a time is limited by the circuit scale of the ALU array, it is necessary to divide a large DFG into a plurality of DFGs. Since the size of the combined DFG is directly affected by the number of circuit configurations executed in the ALU array, it is preferable to generate the DFG as small as possible.

  In view of such a situation, the present applicant has developed a technology that can efficiently process DFG necessary for operation setting of a reconfigurable circuit (see Patent Document 2).

The DFG processing method of Patent Document 2 is a method of reconfiguring a DFG so that the DFG mapped to the reconfigurable circuit whose function can be changed is less than the number of columns and the number of stages of the logic circuit of the reconfigurable circuit. It is about.
JP-A-10-256383 JP 2006-4345 A

  By the way, in the DFG processing method of Patent Document 2, output data from the divided sub-DFG mapped on the reconfigurable circuit is a memory connected to the reconfigurable circuit (as referred to in Patent Document 2). It is passed to another divided sub-DFG via the memory unit 29).

  However, according to such a DFG processing method, as the number of data exchanges between the sub-DFGs increases, so much memory is required. In some cases, the operation itself may be impossible due to a memory shortage.

  Therefore, in view of the above circumstances, the present invention reconfigures the DFG necessary for setting the operation of the reconfigurable circuit to a size that can be mapped to the reconfigurable circuit, and also requires the memory necessary for data transfer between the sub-DFGs. The purpose is to reduce the amount of use.

  The data flow graph generation apparatus of the present invention includes sub-DFG generation means for dividing a data flow graph (DFG) to generate two or more sub-DFGs. The sub-DFG generation unit generates a plurality of sub-DFGs such that data input / output between the sub-DFGs is performed via a memory, and data having the same content is transmitted from a plurality of nodes in the sub-DFG to different areas of the memory. When each is output, the output to the memory from any one of the plurality of nodes is deleted.

  According to this data flow graph generation device, it is possible to reduce the amount of memory used for data transfer between sub-DFGs obtained by dividing a DFG. In addition, power consumption can be reduced as the memory used is reduced.

  For example, when the plurality of nodes include a through node, the sub-DFG generation unit deletes the output from the through node to the memory. Alternatively, instead of deleting the memory output of the through node, the memory output from the input source node of the through node may be deleted.

  The data flow graph generation device according to an aspect of the present invention further includes DFG combining means for combining a plurality of sub DFGs generated by the sub DFG generating means. By providing both the sub-DFG generating means and the DFG combining means, the DFG (DFG before being divided into a plurality of sub-DFGs) can be reconfigured.

  By the way, the sub-DFG generation means outputs a memory from a partial node of the sub-DFG. Therefore, even if the sub-DFGs are combined as they are, the combined DFG cannot correctly perform the operation. Therefore, the DFG combining unit changes the input source of the node that has received the input from the memory that is no longer used by the processing in the sub-DFG generating unit. For example, when the different areas of the memory are A and B, the DFG combining means sets the input source of the node that has received the input from the memory area B that is no longer used due to the deletion of the memory output to the memory area A. Change it.

  A data flow graph generation apparatus according to an aspect of the present invention is used to generate a DFG mapped to an integrated circuit. This data flow graph generation apparatus includes a sub-DFG generation unit and a DFG combination unit as described above. Then, the input DFG is reconfigured into a DFG that can be mapped to the integrated circuit through processing in the sub-DFG generation means and the DFG combination means.

  Note that the DFG that can be mapped to the integrated circuit means, for example, a DFG that does not exceed the size of the integrated circuit or a DFG that satisfies the connection limit of the integrated circuit. An example of this integrated circuit is a reconfigurable circuit. In this case, the sub-DFG generation unit generates a sub-DFG such that the number of sub-DFG columns generated by division is equal to or less than the number of logic circuits per stage of the reconfigurable circuit. Furthermore, the generated sub-DFG also satisfies the connection restrictions imposed between the collections of logic circuits at each stage of the reconfigurable circuit.

  If the integrated circuit has a circuit delay, the calculation may not be performed correctly even if the DFG has a size that can be mapped to the integrated circuit. Therefore, the sub-DFG generation unit may generate the sub-DFG in consideration of the circuit delay of the integrated circuit. This is because the circuit delay problem can be solved by reducing the circuit scale.

  An integrated circuit setting data generation apparatus according to the present invention includes: a compiling unit that compiles a source program to generate a DFG; and the data flow graph generation apparatus that reconfigures the DFG generated by the compiling unit; And setting data generation means for generating setting data for configuring a desired circuit in the integrated circuit from the DFG reconfigured by the data flow graph generation device.

  An integrated circuit according to the present invention is configured based on the setting data supplied from the setting data generating device.

  A processing apparatus according to the present invention includes the setting data generation apparatus and the integrated circuit.

It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.

According to the present invention, not only can the DFG necessary for setting the operation of an integrated circuit such as a reconfigurable circuit be reconfigured to a size that can be mapped to the integrated circuit, but also a sub-DFG that constitutes the DFG. It is possible to reduce the amount of memory required for data transfer between the two. This can also reduce the possibility that the operation by the integrated circuit may not be executed due to a shortage of memory. In addition, power consumption can be reduced as the memory used is reduced.

  FIG. 1 is a configuration diagram of a processing apparatus 10 according to the embodiment. The processing device 10 includes an integrated circuit device 26. The integrated circuit device 26 has a function that makes it possible to reconfigure the circuit configuration. The integrated circuit device 26 is configured as one chip, and includes a reconfigurable circuit 12, a setting unit 14, a control unit 18, an output circuit 22, a memory unit 27, and path units 24 and 29. The reconfigurable circuit 12 can change the function by changing the setting.

  The setting unit 14 supplies setting data 40 for configuring a desired circuit to the reconfigurable circuit 12. The setting unit 14 may be configured as a command memory that outputs stored data based on the count value of the program counter. In this case, the control unit 18 controls the output of the program counter. In this sense, the setting data 40 may be called command data. The path units 24 and 29 function as feedback paths, and connect the output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12. The output circuit 22 is configured as a sequential circuit such as a data flip-flop (D-FF), for example, and receives the output of the reconfigurable circuit 12. The memory unit 27 is connected to the path unit 29. The reconfigurable circuit 12 is configured as a logic circuit such as a combinational circuit or a sequential circuit.

  The memory unit 27 has a storage area for storing a data signal output from the reconfigurable circuit 12 and / or a data signal input from the outside based on an instruction from the control unit 18. The memory unit 27 is configured as a RAM. In order to write data to the memory unit 27 and read the data, at least one clock time is required for each process. The data signal stored in the memory unit 27 is transmitted as an input to the reconfigurable circuit 12 through the path unit 29 based on an instruction from the control unit 18. The memory unit 27 can supply a data signal to the reconfigurable circuit 12 at a predetermined timing according to an instruction from the control unit 18. Note that the memory unit 27 may output a data signal according to an instruction from the setting unit 14. When the setting unit 14 is configured as a command memory, the setting unit 14 may have command data that instructs the output timing of the memory unit 27, and may output the command data to the memory unit 27 based on the count value from the control unit 18. . In this case, the setting unit 14 also functions as a control unit that controls the operation of the memory unit 27.

  The reconfigurable circuit 12 includes a logic circuit whose function can be changed. Specifically, the reconfigurable circuit 12 includes a configuration in which logic circuits capable of selectively executing a plurality of arithmetic functions are arranged in a plurality of stages, and further includes an output of a preceding logic circuit string and an input of a subsequent logic circuit string. The connection part which can set the connection relationship with is provided. A plurality of logic circuits included in each stage constitutes a collection of logic circuits. This connection unit also has a function of a state holding circuit (hereinafter also referred to as FF circuit) that holds the output of the preceding logic circuit row, that is, the internal state. The plurality of logic circuits are arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the storage unit 34. The program 36 shows an operation description describing the operation of processing in the circuit, and describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiling unit 30 compiles the program 36 stored in the storage unit 34, converts it into a data flow graph (DFG) 38 of the entire program, and stores the data flow graph (DFG) 38 in the storage unit 34. The DFG 38 expresses the dependency of the execution order between operations in the circuit, and shows the flow of operations of input variables and constants in a graph structure. In general, the DFG 38 is formed so that the calculation proceeds from top to bottom.

  The data flow graph processing unit 31 divides one or more DFGs generated by the compiling unit 30 into a plurality of sub-DFGs according to the number of logic circuits included in the set of logic circuits of the reconfigurable circuit 12. . Specifically, one or more DFGs are divided into a number of logic circuits per stage of the reconfigurable circuit 12, that is, a size that is equal to or less than the number of columns. When the reconfigurable circuit 12 is configured to include 6 columns × 3 stages of logic circuits, when the DFG exceeds 6 columns, the reconfigurable circuit 12 is divided into sub-DFGs having 6 or less columns.

  Then, the data flow graph processing unit 31 combines the plurality of divided sub-DFGs so as not to exceed the number of columns of the logic circuit. As a result, a combined DFG is generated in which the number of columns is equal to or less than the number of columns in the logic circuit aggregate.

  Here, if the generated combined DFG exceeds the number of logic circuit aggregates of reconfigurable circuits (the number of ALU stages constituting the logic circuit), the data flow graph processing unit 31 further divides the combined DFG. Generate a plurality of sub-joined DFGs. Specifically, the data flow graph processing unit 31 subdivides the combined DFG so as to be equal to or less than the number of stages of the reconfigurable circuit 12. When the reconfigurable circuit 12 is configured to include 6 columns × 3 stages of logic circuits, the combined DFG is subdivided into sub-joined DFGs of 3 stages or less. The plurality of divided sub-joined DFGs are stored in the storage unit 34. By repeatedly generating a circuit defined by a plurality of divided sub-coupled DFGs in the reconfigurable circuit 12, it is possible to express a desired circuit on the reconfigurable circuit 12.

  In addition, due to the configuration of the program 36, a plurality of DFGs may be generated at the time of compilation. For example, when compiling a plurality of programs 36 related to each other, or compiling a program 36 having a plurality of routine programs that are repeatedly called. In the processing apparatus 10, a plurality of DFGs are generated by the compiling unit 30, and the DFG generated by the compiling unit 30 is processed by the data flow graph processing unit 31 to generate a plurality of sub-joined DFGs. .

  The setting data generation unit 32 generates setting data 40 based on the DFG 38 determined by the data flow graph processing unit 31. The setting data 40 is data for mapping the DFG 38 to the reconfigurable circuit 12, and includes the functions of the logic circuit in the reconfigurable circuit 12, the connection relationship between the logic circuits, and constant data to be input to the logic circuit. Determine. Hereinafter, an example will be described in which the setting data generation unit 32 generates setting data 40 for a plurality of circuits obtained by dividing one target circuit to be generated.

  FIG. 2 is a diagram for explaining a plurality of circuits formed by dividing the target circuit 42. A circuit generated by dividing one target circuit 42 is referred to as a “divided circuit”. In this example, one target circuit 42 is divided into four divided circuits, that is, divided circuit A, divided circuit B, divided circuit C, and divided circuit D, in the vertical direction and the horizontal direction. The plurality of divided circuits are respectively coupled within the range of the number of columns of the reconfigurable circuit 12, and are regenerated as a substantially equivalent new target circuit.

  For example, when the number of nodes in the horizontal direction of the target circuit 42 to be generated is larger than the number of nodes in the horizontal direction (number of columns) of the reconfigurable circuit 12, the size can be mapped to the reconfigurable circuit 12. The DFG 38 of the target circuit 42 is divided in the left-right direction in the data flow graph processing unit 31. The node expresses the function of the logic circuit in the DFG 38. Further, when it is necessary to change the connection between the nodes in the vertical direction due to the number of columns of the reconfigurable circuit 12 or the input / output limitation between the ALUs, the DFG 38 of the target circuit 42 is divided in the vertical direction. The arrangement structure of the reconfigurable circuit 12 may be transmitted from the control unit 18 to the data flow graph processing unit 31 or may be recorded in the storage unit 34 in advance. In this embodiment, the DFG 38 expresses the dependency of the execution order between operations, and the data flow graph processing unit 31 divides the DFG according to the number of columns of the reconfigurable circuit 12 and divides the DFG. Is set as the sub-DFG.

  In addition, the data flow graph processing unit 31 investigates the connection relationship between the plurality of sub-DFGs. Similarly, when the data is divided only in the left-right direction, the data flow graph processing unit 31 needs to investigate the connection relationship. When the connection relationship is examined, the data flow graph processing unit 31 combines a plurality of sub-DFGs according to the connection relationship to generate one large combined DFG. The combined DFG is generated such that the number of columns is equal to or less than the number of columns of the reconfigurable circuit 12. When the combined DFG is larger than the number of stages of the reconfigurable circuit 12, the data flow graph processing unit 31 divides the combined DFG to generate a plurality of sub-combined DFGs.

  The setting data generation unit 32 generates setting data 40 of the combined DFG and stores it in the storage unit 34. The setting data 40 is expressed as data for mapping the combined DFG to the reconfigurable circuit 12. As described above, by reconfiguring the DFG according to the number of columns of the reconfigurable circuit 12 and generating the setting data 40 of the target circuit 42, it is possible to realize the processing device 10 with high versatility. .

  When a plurality of sub-joined DFGs are generated in the data flow graph processing unit 31, the setting data generating unit 32 generates setting data 40 for the plurality of sub-joined DFGs and stores them in the storage unit 34. The plurality of setting data 40 is expressed as data for mapping a plurality of sub-coupled DFGs divided into the number of stages or less of the reconfigurable circuit 12 to the reconfigurable circuit 12. As a result, a DFG larger than the circuit scale of the reconfigurable circuit 12 can be processed into a size that can be mapped to the reconfigurable circuit 12. That is, according to the processing apparatus 10, it is possible to reconfigure a desired circuit using the reconfigurable circuit 12 having a small circuit scale.

  FIG. 3 shows the configuration of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a plurality of logic circuit strings each including a logic circuit 50 that can selectively execute a plurality of arithmetic functions. Specifically, the reconfigurable circuit 12 is configured to include a multi-stage connection structure of logic circuit arrays and connection portions 52 provided in each stage. Here, multistage means that there are two or more stages. The connection unit 52 can set an arbitrary connection relationship between the output of the preceding logic circuit and the input of the subsequent logic circuit, or a connection relationship selected from a predetermined combination of connection relationships. The connection unit 52 can hold the output signal of the preceding logic circuit. In the reconfigurable circuit 12, the operation is advanced from the upper stage to the lower stage by the multi-stage connection structure of the logic circuits. Note that the reconfigurable circuit 12 may have a one-stage connection structure of a logic circuit array.

  The reconfigurable circuit 12 has an ALU (Arithmetic Logic Unit) as the logic circuit 50. The ALU is an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations, and can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting. Each ALU has a selector for setting a plurality of arithmetic functions. In the illustrated example, the ALU has two input terminals and two output terminals.

  As illustrated, the reconfigurable circuit 12 is configured as an X-stage Y-column ALU array in which X ALUs in the vertical direction and Y ALUs in the horizontal direction are arranged. Input variables and constants are input to the first-stage ALU11, ALU12,..., ALU1Y, and a set predetermined calculation is performed. The output of the calculation result is input to the second-stage ALU 21, ALU 22,..., ALU 2Y according to the connection set in the first-stage connection unit 52. In the first stage connection section 52, an arbitrary connection relationship between the output of the first ALU column and the input of the second ALU column or a combination of predetermined connection relationships is selected. The connection is configured so that the connection relationship can be realized, and the intended connection is enabled by setting. Hereinafter, the configuration is the same up to the connection part 52 of the Xth stage which is the final stage. The ALU column corresponds to an aggregate of ALUs.

  Note that the reconfigurable circuit 12 of FIG. 3 shows a configuration in which the connection units 52 are provided one by one alternately with the ALU column. By disposing the connection unit 52 at the lower stage of each ALU column, the reconfigurable circuit 12 is divided into X-stage reconfigurable units each including one ALU column. Specifically, the one-stage reconfigurable unit includes one-stage ALU row and one-stage connection unit 52. This division is in accordance with the FF circuit included in the connection unit 52. For example, a connection unit 52 is provided for each two-stage ALU column, and a connection unit having no FF circuit is connected between two ALU columns. In this case, it is divided into X / 2-stage reconfigurable units each composed of two ALU rows. In addition, by providing an FF circuit for each ALU column at a predetermined stage, a reconfigurable unit at a desired stage can be configured.

  Circuit configuration is performed in one clock. Specifically, the setting unit 14 maps the setting data to the reconfigurable circuit 12 every clock. The output of each ALU column is held in the connection unit 52 at the subsequent stage. Note that data is written to and read from the memory unit 27 in one clock. Therefore, in order to write data to the memory unit 27 and read the data, a time corresponding to at least two stages of processing of the ALU column is required.

  The connection unit 52 has a function of supplying variables and constants supplied from the outside and the memory unit 27 to the intended ALU. This function is called an intermediate input function. The connection unit 52 can also directly output the calculation result of the preceding ALU to the outside. This function is called an intermediate output function. With this configuration, various combinational circuits can be configured, and the degree of freedom in design is improved.

  FIG. 4 is a diagram for explaining the structure of the DFG 38. In the DFG 38, the flow of calculation of input variables and constants is expressed step by step in a graph structure. In the figure, operators are indicated by circles and represent nodes. The setting data generation unit 32 generates setting data 40 for mapping the DFG 38 to the reconfigurable circuit 12. In the embodiment, particularly when the DFG 38 cannot be mapped to the reconfigurable circuit 12, the DFG 38 is divided into a plurality of areas and combined, and further divided, thereby generating setting data 40 of the divided circuit. In order to realize the operation flow by the DFG 38 on the circuit, the setting data 40 specifies data that specifies a logic circuit to which an operation function is assigned, defines a connection relationship between the logic circuits, and further defines input variables, input constants, and the like. Become. Therefore, the setting data 40 includes selection information supplied to a selector that selects the function of each logic circuit 50, connection information for setting the connection of the connection unit 52, necessary variable data, constant data, and the like.

  Returning to FIG. 1, at the time of circuit configuration, the control unit 18 selects and reads a plurality of setting data 40 for configuring one target circuit 42 from the storage unit 34. When the setting unit 14 is configured as a command memory, the control unit 18 gives a program counter value to the setting unit 14, and the setting unit 14 reconfigures the setting data stored in accordance with the counter value as command data. Set to the configurable circuit 12. The setting unit 14 may include a cache memory and other types of memory. The control unit 18 may receive the setting data 40 from the storage unit 34 and supply the setting data 40 to the setting unit 14. However, the setting data is stored in the setting unit 14 in advance without using the control unit 18. You may keep it. In this case, the control unit 18 reads data from the setting unit 14 so that setting data corresponding to the target circuit 42 is supplied to the reconfigurable circuit 12 from among a plurality of setting data stored in advance in the setting unit 14. To control.

  The setting unit 14 sets the setting data 40 in the reconfigurable circuit 12 and sequentially reconfigures the circuit of the reconfigurable circuit 12. Thereby, the reconfigurable circuit 12 can execute a desired calculation based on the target circuit. The reconfigurable circuit 12 uses an ALU having a high-performance computing capability as a basic cell, and the reconfigurable circuit 12 and the setting unit 14 are configured on one chip, so that the configuration can be performed at a high speed, for example, It can be realized with one clock. The control unit 18 has a clock function, and the clock signal is supplied to the output circuit 22 and the memory unit 27. The control unit 18 may include a quaternary counter and supply a count signal to the setting unit 14.

  FIG. 5 is a diagram illustrating a connection relationship between ALUs in the reconfigurable circuit 12. In FIG. 5, illustration of the connecting portions 52 arranged between the ALU rows is omitted. The reconfigurable circuit 12 shown in FIG. 5 is configured as an ALU array in which four ALUs are arranged in the horizontal direction and six ALUs are arranged in the vertical direction. Input variables and constants are input to the first-stage ALU 11, ALU 12,..., ALU 14, and a set predetermined calculation is performed. The calculation result output is input to the second-stage ALU 21, ALU 22,..., ALU 24 according to the connection set in the first-stage connection unit 52. In the first stage connection section 52, a connection is configured so as to realize a connection relationship in which a certain connection restriction is imposed between the output of the first ALU string and the input of the second ALU string. Depending on the setting, the intended connection within that range becomes valid. The same applies to the second to fifth connection portions 52. The sixth stage ALU column, which is the last stage, outputs the final result of the operation. The connection unit 52 is configured to connect logic circuits arranged in close physical proximity between ALU stages. Thereby, the wiring length can be shortened and the circuit scale can be reduced. As a result, low power consumption and high processing speed are possible.

  In the reconfigurable circuit 12 shown in FIG. 5, there are 6 stages × 4 columns of ALUs, and wiring from one ALU in the upper stage is limited to three ALUs in the lower stage. As shown in the figure, the input of one ALU in the lower stage is limited to the ALU immediately above the upper stage and the left and right ALUs of the upper ALU, and the output of one ALU in the upper stage is directly below the ALU directly below the lower stage. It is limited to the left and right ALUs. For example, regarding the ALU 22, its input is limited to three directions of ALU 11, ALU 12, and ALU 13, and its output is limited to three directions of ALU 31, ALU 32, and ALU 33. If there is no ALU corresponding to the left or right, the input and output are limited to two directions, respectively. By using such a wiring, the number of wirings can be greatly reduced as compared with the case where all the upper and lower ALUs can be connected.

  FIG. 6 shows the configuration of the data flow graph processing unit 31. The data flow graph processing unit 31 includes a DFG dividing unit 60, a sub-DFG optimizing unit 61, and a DFG combining unit 62. The data flow graph processing function in the embodiment is realized by the CPU 10, the memory, the DFG processing program loaded in the memory, and the like in the processing device 10, and here, functional blocks realized by their cooperation are depicted. The DFG processing program may be built in the processing apparatus 10 or supplied from the outside in a form stored in a recording medium. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  The DFG dividing unit 60 divides the DFG to generate a plurality of sub-DFGs when the DFG generated by the compiling unit 30 corresponds to, for example, the following cases.

  (1) The number of DFG columns is larger than the number of logic circuits per stage of the reconfigurable circuit. That is, the number of DFG columns exceeds the number of columns in the ALU array of the reconfigurable circuit. For example, if the DFG is mapped to the reconfigurable circuit 12 as shown in FIG. 5, the number of DFG columns is 5 or more.

  (2) The DFG does not meet the connection limit of the reconfigurable circuit. For example, when the DFG is mapped to the reconfigurable circuit 12 as shown in FIG. 5, the wiring from one ALU is limited to the three ALUs in the lower stage, but the DFG to be mapped corresponds to four or more nodes. When you have a node that performs output.

  Note that, when the nodes between the sub-DFGs generated by division cannot be directly connected, the output data of the nodes is temporarily stored in the memory unit 27.

  The sub DFG optimizing unit 61 optimizes the sub DFG generated by the DFG dividing unit 60. For example, when there are many data transfers between the generated sub-DFGs, the usage amount of the memory unit 27 increases accordingly. In some cases, the data cannot be transferred between the sub-DFGs due to a memory shortage, and the operation itself may not be executed. Therefore, the sub-DFG optimizing unit 61 deletes the memory output from one of the nodes if, for example, the same data is output from a plurality of nodes in the same sub-DFG to the memory. To do. By doing so, it is possible to reduce the amount of memory used for data transfer between the sub-DFGs. As a result, the risk of computation errors due to insufficient memory can be reduced, and the power consumption of the integrated circuit device 26 including the reconfigurable circuit 12 can be reduced.

  The DFG combining unit 62 generates a DFG obtained by combining a plurality of sub DFGs optimized by the sub DFG optimizing unit 61.

  FIG. 7 shows a processing flow of the DFG 38 in the present embodiment. The compiling unit 30 compiles the program 36 (S10) and generates a DFG 38 (S12). The DFG dividing unit 61 of the data flow graph processing unit 31 divides the generated DFG 38 to generate a sub DFG (S14). The sub-DFG optimization unit 62 optimizes the divided sub-DFG (S16). The DFG combination unit 63 generates a DFG by combining the optimized sub-DFGs (S18). Then, the setting data generation unit 32 generates setting data 40 based on the combined DFG (S20).

  If the DFG combined with the sub-DFG exceeds the number of stages of the reconfigurable circuit in S18, the combined DFG is divided to generate a plurality of sub-coupled DFGs. Then, the setting data generation unit 32 generates a plurality of setting data 40 based on each sub-joined DFG.

(Example)
Hereinafter, the present invention will be described using examples.

  FIG. 8 shows a C source program input to the compiling unit 30. The compiling unit 30 compiles the program described in the C language to generate a DFG. FIG. 9 is a DFG output from the compiling unit 30. Such a DFG cannot be mapped to the reconfigurable circuit 12 with connection restrictions as shown in FIG. This is because the DFG in FIG. 9 includes nodes (first addition nodes) that output to the lower four nodes, whereas the DFG in FIG. This is because there is a restriction that only the lower three nodes or lower can be connected. Therefore, the DFG dividing unit 60 divides the DFG of FIG. 9 into two sub-DFGs as shown in FIG. 10, thereby eliminating the nodes that output to the four nodes at the lower stage.

  Note that in order to map the two sub-DFGs of FIG. 10 to the reconfigurable circuit, the reconfigurable circuit only needs to have an ALU of 6 stages × 3 columns. Since the reconfigurable circuit of FIG. 5 has an ALU of 6 stages × 4 columns, it is possible to map the DFG of FIG. Note that data transfer between two sub-DFGs mapped to the reconfigurable circuit is performed via memory areas A, B, and C allocated to the memory unit 29.

  Here, paying attention to the DFG in FIG. 10, it is noticed that the data output to the memory A and the data output to the memory B are connected via a through node (mov node). That is, the data output to the memory A and the data output to the memory B have the same contents. Therefore, either the output to the memory A or the output to the memory B can be deleted. Here, the output from the mov node to the memory B is deleted. As a result, the DFG of FIG. 10 can be replaced with a DFG as shown in FIG. As a result, the amount of memory used for data transfer between the sub-DFGs can be reduced.

  FIG. 12 shows a flowchart of the optimization process performed by the sub-DFG optimization unit 61. This flowchart shows a processing procedure for reducing the amount of memory used for data transfer between sub-DFGs. For example, FIG. 11 shows a procedure for generating a DFG as shown in FIG. 11 from the DFG shown in FIG.

  When the sub-DFG file is read, first, a mov node to be output to the memory is searched (S31). If there is a mov node that performs memory output (this node is referred to as node M), the process proceeds to step S32. If not, the optimization process by the sub-DFG optimization unit 61 is completed.

  In step S32, the input node of the node M is traced to search for a non-mov node (this node is called a node P). In step S33, it is checked whether or not the node P already has a memory output (this output variable is A). If it already has a memory output, the process proceeds to S38, and if not, the process proceeds to S34.

  In step S34, a memory output A is created at node P. In step S35, the memory output of node M (this output variable is set to B) is deleted. In step S36, a node having the output variable B as an input is searched. In step S37, the input B of the node found in S36 is changed to A.

  In step S38, it is determined whether the output variable A is the final output. Here, the final output is the output of the DFG before being divided into sub-DFGs. For example, it refers to ret1 and ret2 in FIGS. Not the final output means an output to a memory that transfers data to other sub-DFGs. For example, the output to the memories A, B, and C as shown in FIG.

  Here, a specific example of processing according to the above flowchart will be described. A procedure for generating the DFG of FIG. 11 from the DFG of FIG. 10 will be described.

  First, a DFG file as shown in FIG. 10 is read. In S31, a mov node M that performs output to the memory B is found. In S32, an addition node P that performs input to the mov node M is found (see “state 1” in FIG. 13). Since this node P already has the memory output A, it is determined yes in S33. However, this memory output A is an output to a memory that transfers data between sub-DFGs, and is not a final output. Therefore, it is determined No in S38, and the process proceeds to S35. Since this node P already has the memory output A, it is determined yes in S33.

  In S35, the memory output B of the node M is deleted. In S36, the node that has received the input from the memory B (the merge node in FIG. 10) is found. In S37, the input node to the merge node is changed from the memory B to the memory A.

Then, the process returns to S31 again, but the mov node that performs the memory output has disappeared due to the process in S35 (the memory output from the mov node has been deleted), so it is determined No in S31, and the sub-DFG optimization processing unit The optimization process by 61 is completed.
The present invention has been described based on the embodiments. It should be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications can be made to combinations of the respective components and processing processes, and such modifications are within the scope of the present invention.

  For example, the array of ALUs in the reconfigurable circuit 12 is not limited to a multistage array that allows connection only in the vertical direction, but may be a mesh-like array that allows connection in the horizontal direction. In the above description, the connection for connecting the logic circuits by skipping the stages is not provided, but the connection connection for skipping such stages may be provided.

  Further, FIG. 1 shows a case where the processing apparatus 10 has one reconfigurable circuit 12, but it may have a plurality of reconfigurable circuits 12. When there are a plurality of reconfigurable circuits 12, a plurality of DFGs can be processed at the same time, and the data processing time can be shortened.

  The embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  For example, in the above-described embodiment, the processing is related to the DFG mapped to the reconfigurable circuit. However, the concept disclosed in this specification of the application can be applied to others.

For example, when a DFG representing an operation is assigned to an integrated circuit having a circuit delay, the DFG may be divided into a plurality of small sub-DFGs and mapped to the integrated circuit in order to reduce the influence of the circuit delay. Similar to the above-described embodiment in the reconfigurable circuit, in this case, data exchange between the sub-DFGs is performed via a memory such as a D / FF (D-flip flop). The amount of memory used for delivery may be a problem. Even in such a case, as in the present invention, when the same content data is output from different nodes in the sub-DFG to different areas of the memory, the memory output from one of the nodes is deleted. , Memory usage can be reduced. As described above, the present invention is not limited to reconfigurable circuit design but can be widely applied to logic circuit design.

It is a block diagram of the processing apparatus which concerns on an Example. It is a figure for demonstrating the several circuit which can divide | segment a target circuit. 2 is a configuration diagram of a reconfigurable circuit 12. FIG. It is a figure for demonstrating the structure of DFG38. 3 is a diagram illustrating a connection relationship between ALUs in the reconfigurable circuit 12. FIG. It is a processing flowchart of DFG38 in a present Example. 3 is a configuration diagram of a data flow graph processing unit 31. FIG. This is a C source program input to the compiling unit 30. This is a DFG output from the compiling unit 30. FIG. 10 is a diagram illustrating two sub-DFGs generated by dividing the DFG shown in FIG. 9 by the DFG dividing unit 6. This is a sub-DFG optimized by the sub-DFG optimizing unit 61. It is a flowchart of the optimization process which the sub-DFG optimization part 61 performs. 2 shows a data flow graph in the middle of optimization processing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processing apparatus 12 Reconfigurable circuit 14 Setting part 18 Control part 22 Output circuit 24 Path | route part 26 Integrated circuit device 27 Memory part 29 Path | route part 30 Compile part 31 Data flow graph process part 32 Setting data generation part 34 Storage part 36 Program,
38 Data Flow Graph 40 Setting Data 50 Logic Circuit 52 Connection Unit 60 DFG Division Unit 61 Sub DFG Optimization Unit 62 DFG Coupling Unit

Claims (9)

Sub-DFG generation means for dividing a data flow graph (DFG) to generate two or more sub-DFGs,
The sub-DFG generating means generates a plurality of sub-DFGs such that data input / output between the sub-DFGs is performed via a memory, and data having the same content is transferred from a plurality of nodes in the sub-DFG to different areas of the memory. The data flow graph generation device, wherein when outputting each, the output to the memory from any one of the plurality of nodes is deleted.
The sub-DFG generation means includes:
2. The data flow graph generation device according to claim 1, wherein when the plurality of nodes include a through node, an output from the through node to a memory is deleted.
A DFG combining unit that combines the plurality of sub-DFGs generated by the sub-DFG generating unit;
When different areas of the memory are A and B,
The said DFG coupling | bond part changes the input origin of the node which received the input from the memory area B which will no longer be used by the said deletion of the memory output to the memory area A, The said Claim 1 or 2 characterized by the above-mentioned. Data flow graph generator.
A data flow graph generation device for generating a DFG mapped to an integrated circuit,
The sub-DFG generating means and the DFG combining means;
4. The data flow graph generation according to claim 3, wherein the input DFG is reconstructed into a DFG that can be mapped to the integrated circuit through processing in the sub-DFG generation unit and the DFG combination unit. apparatus.
The integrated circuit has a reconfigurable circuit,
The sub-DFG generation means includes:
The number of columns of sub-DFGs generated by division is less than or equal to the number of logic circuits per stage of reconfigurable circuit,
5. The data flow graph generating device according to claim 4, wherein the sub DFG generates a sub DFG such that the sub DFG satisfies a connection restriction imposed between a set of logic circuits at each stage of the reconfigurable circuit. .
The sub-DFG generation means includes:
6. The data flow graph generation device according to claim 4, wherein a sub DFG is generated in consideration of a circuit delay of the integrated circuit.
A compiling means for compiling a source program to generate a DFG;
The data flow graph generation device according to any one of claims 4 to 6, wherein the DFG generated by the compiling unit is reconfigured.
Setting data for integrated circuit, comprising setting data generation means for generating setting data for configuring a desired circuit in the integrated circuit from DFG reconfigured by the data flow graph reconstructing device Generator.
8. An integrated circuit configured based on setting data supplied from the setting data generating apparatus according to claim 7.
    A processing apparatus comprising the setting data generation apparatus according to claim 7 and the integrated circuit according to claim 8.

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