JP2004178105A - Clock switching device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform by hardware the switching control of a clock signal to be used without the intervention of a CPU. <P>SOLUTION: The frequency of an external clock signal OCLK is counted by an external oscillation detecting counter 2, and the frequency of an internal clock signal ICLK is counted by an internal oscillation detecting counter 3. When the external oscillation detecting counter 2 overflows, it is judged that the external clock signal OCLK is normal. Then, a switching circuit 8 is controlled to output an external clock signal OCLK as an operating clock HCKO on the basis of an overflow signal OFA. Thus, it is possible for a CPU to switch a clock signal to be outputted only by hardware without carrying out any processing. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock switching device, for example, in a semiconductor integrated circuit to which a first clock signal serving as a reference and a second clock signal different from the first clock signal are supplied, the second clock signal It is suitable for use in a clock switching device for switching a clock signal to be used in response.
[0002]
[Prior art]
2. Description of the Related Art Some semiconductor integrated circuits and the like can select an appropriate clock signal to be used for the operation of an internal circuit or the like from a plurality of supplied clock signals in accordance with an application or a use situation. For example, a clock signal generation source (oscillator or oscillation circuit) is built in a semiconductor integrated circuit, and a clock input terminal capable of inputting a clock signal from the outside is provided, so that the internally generated clock signal and an externally supplied clock signal are provided. Some clock signals can be selectively switched as needed.
[0003]
[Patent Document 1]
JP-A-11-95859
[Patent Document 2]
JP-A-2000-122749
[Patent Document 3]
JP 2001-142559 A
[Patent Document 4]
JP-A-7-6155
[0004]
[Problems to be solved by the invention]
However, in a conventional semiconductor integrated circuit and the like, as described in Patent Documents 1 to 4 and the like, selection of an appropriate clock signal from a plurality of clock signals is performed for clock signal selection control. This is performed by writing data from the CPU to software registers under software control or by instructions from the CPU under software control. That is, the selection and switching of the clock signal to be used require the intervention of the CPU at all times, and there is a problem that the processing load on the CPU increases.
[0005]
The present invention has been made in view of such a problem, and an object of the present invention is to make it possible to control switching of a clock signal to be used by hardware without intervening a CPU.
[0006]
[Means for Solving the Problems]
A clock switching device according to the present invention includes a first counter circuit and a switching circuit, wherein the first counter circuit counts the number of cycles of an input first clock signal, and the first counter circuit overflows. The output clock signal is switched from the second clock signal to the first clock signal by the switching circuit in response to the first overflow signal output when the clock signal occurs, and is output. As a result, the output clock signal can be switched and output without causing the CPU to perform any processing.
[0007]
An oscillation stop detecting circuit for detecting the stop of the oscillation of the first clock signal is further provided, and the output clock signal is changed from the first clock signal to the second clock signal in accordance with the detection result of the oscillation stop detecting circuit. In the case where the output is switched by the switching circuit, even if the oscillation of the first clock signal is stopped, the output clock signal can be switched and output without performing the processing interposed by the CPU. become able to.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a clock switching device according to a first embodiment of the present invention.
[0009]
The clock switching device shown in FIG. 1 uses an external clock signal OCLK externally supplied through an input terminal of a semiconductor integrated circuit or the like including the clock switching device, or a reference clock that is constantly generated inside the semiconductor integrated circuit or the like. One of the internal clock signals ICLK is output as an operation clock HCKO of the semiconductor integrated circuit or the like. The external clock OCLK and the internal clock signal ICLK are generated by an oscillator (not shown) (for example, a crystal oscillator or a ceramic oscillator) or an oscillation circuit.
[0010]
In FIG. 1, reference numeral 1 denotes a noise filter which removes a signal having a frequency higher than a predetermined frequency from the external clock signal OCLK and outputs the signal as an external clock signal HCLKN. That is, the noise filter 1 removes (blocks) high frequency external clock signal OCLK and high frequency noise due to abnormal oscillation or the like.
[0011]
Reference numeral 2 denotes an external oscillation detection counter, which is a 2-bit counter to which the external clock signal HCLKN is input and counts the number of cycles of the external clock signal HCLKN. Further, the external oscillation detection counter 2 outputs an overflow signal OFA when the count value overflows.
[0012]
Reference numeral 3 denotes an internal oscillation detection counter, which is a 6-bit counter for counting the number of cycles of the input internal clock signal ICLK. The internal oscillation detection counter 3 outputs an overflow signal OFB when the count value overflows.
[0013]
Reference numeral 4 denotes an edge detection circuit for detecting an edge of the reset signal RST when the externally input reset signal RST is activated. Reference numeral 5 denotes a logical sum operation circuit (OR circuit) for performing a logical sum operation of the output of the edge detection circuit 4 and the overflow signal OFB output from the internal oscillation detection counter 3 and resetting the operation result to the external oscillation detection counter 2 Output as a signal.
[0014]
Reference numeral 6 denotes an edge detection circuit that detects an edge of the overflow signal OFA output from the external oscillation detection counter 2 and outputs a detection result as a set signal HCCOUNT. Reference numeral 7 denotes a register which sets and holds a register value "1" in accordance with a set signal HCCOUNT output from the edge detection circuit 6, and outputs a clock selection signal XTAL corresponding to the register value.
[0015]
A switching circuit 8 receives an external clock signal OCLK, an internal clock signal ICLK, and a clock selection signal XTAL, and selectively operates one of the external clock signal OCLK and the internal clock signal ICLK according to the clock selection signal XTAL. Output as signal HCKO.
[0016]
Here, the internal oscillation detection counter 3 and the register 7 are reset (initialized) to a counter value “0” and a register value “0” by a reset signal RST supplied from the outside. The external oscillation detection counter 2 operates in synchronization with the external clock signal HCLKN (OCLK), and the edge detection circuits 4 and 6, the internal oscillation detection counter 3, and the register 7 operate in synchronization with the internal clock signal ICLK. I do.
[0017]
Next, the operation will be described.
FIG. 2 is a flowchart for explaining the outline of the operation of the clock switching device shown in FIG.
[0018]
First, the clock switching device performs an initialization operation of each circuit shown in FIG. 1 according to the input reset signal RST or the like (step S1). Since the register value of the register 7 becomes "0" by this initialization operation, the switching circuit 8 outputs the internal clock signal ICLK as the operation clock signal HCKO based on the clock selection signal XTAL output from the register 7.
[0019]
When the initialization operation is completed, the external oscillation detection counter 2 and the internal oscillation detection counter 3 start counting the number of cycles of the external clock signal HCLKN (OCLK) and the internal clock signal ICLK, respectively.
Thereafter, the clock switching device determines whether or not the count value overflows in the external oscillation detection counter 2 (Step S2).
[0020]
As a result of the above determination, when the count value overflows in the external oscillation detection counter 2 (when the external oscillation detection counter 2 overflows before the internal oscillation detection counter 3), the register value is stored in the register 7. 1 "is set (step S3). As a result, the switching circuit 8 selects the external clock signal OCLK based on the clock selection signal XTAL and outputs it as the operation clock signal HCKO.
[0021]
On the other hand, as a result of the determination, if the count value does not overflow in the external oscillation detection counter 2 (the internal oscillation detection counter 3 overflows before the external oscillation detection counter 2 causes the external oscillation detection counter 2 to overflow). If reset, the register 7 holds the register value "0" (step S4). Therefore, switching of operation clock signal HCKO is not performed, and switching circuit 8 outputs internal clock signal ICLK as operation clock signal HCKO.
[0022]
The operation of the clock switching device according to the above-described first embodiment will be described in detail with reference to FIGS. First, a case where the external clock signal OCLK is normal will be described with reference to FIG. 3, and then a case where the external clock signal OCLK is abnormal will be described with reference to FIGS.
FIG. 3 is a timing chart showing the operation of the clock switching device when the supplied external clock signal OCLK is normal (appropriate frequency range).
[0023]
Time T ₃₁ When the reset signal RST input from the outside is activated to a low level (hereinafter referred to as "L"), the internal oscillation detection counter 3 and the register 7 are reset. Further, a change in the reset signal RST is detected by the edge detection circuit 4, and the external oscillation detection counter 2 is reset based on the detection result.
[0024]
Time T ₃₁ At this time, the count values of the external oscillation detection counter 2 and the internal oscillation detection counter 3 become "0", respectively, and the register value of the register 7 is "0" (in FIG. 3, this is indicated by the clock selection signal XTAL). become. Therefore, switching circuit 8 selects and outputs internal clock signal ICLK as operation clock signal HCKO based on clock selection signal XTAL.
[0025]
Time T ₃₁ Is completed, the external oscillation detection counter 2 and the internal oscillation detection counter 3 start counting the number of cycles of the external clock signal HCLKN (OCLK) and the internal clock signal ICLK, respectively. As a result, the count values of the external oscillation detection counter 2 and the internal oscillation detection counter 3 increase with time. Here, for example, when the external clock signal HCLKN (OCLK) and the internal clock signal ICLK have substantially the same frequency, the respective count values increase at substantially the same speed.
[0026]
And time T ₃₂ In this case, when the external oscillation detection counter 2 whose count value is smaller than the internal oscillation detection counter 3 overflows, the external oscillation detection counter 2 sets the overflow signal OFA to a high level (hereinafter referred to as “H”). And output. The overflow signal OFA is set to, for example, “H” during a period of four cycles of the external clock signal HCLKN in order to detect the overflow signal OFA using the internal clock signal ICLK whose frequency may be different from the external clock signal HCLKN.
[0027]
Next, at time T ₃₃ , The change of the overflow signal OFA from "L" to "H" is detected by the edge detection circuit 6, so that the set signal HCCOUNT becomes "H". Further, the time T ₃₄ , The register value of the register 7 is set to “1” based on the set signal HCCOUNT, and the clock selection signal XTAL output from the register 7 becomes “H”.
[0028]
When the clock selection signal XTAL becomes “H”, the switching circuit 8 switches the output clock signal. At this time, regardless of the phases of the external clock signal OCLK and the internal clock signal ICLK, if the clock signal is switched at the time when the clock selection signal XTAL becomes “H”, a high-frequency signal as the operation clock HCKO is temporarily supplied. Or a noise called mustache may occur.
[0029]
Therefore, when the clock selection signal XTAL becomes “H”, the switching circuit 8 first fixes the operation clock signal HCKO to “H”, waits for the external clock signal OCLK to become “H”, and switches the clock signal. Perform (time T ₃₅ ). The switching of the clock signal is performed in this manner, and the switching circuit 8 selects and outputs the external clock signal OCLK as the operation clock signal HCKO.
[0030]
FIG. 4 is a timing chart showing the operation of the clock switching device when the supplied external clock signal OCLK is abnormal (low frequency or no clock).
[0031]
Time T ₄₁ When the input reset signal RST is activated to "L", the time T shown in FIG. ₃₁ Similarly, the external oscillation detection counter 2, the internal oscillation detection counter 3, and the register 7 are reset. As a result, the internal clock signal ICLK is output from the switching circuit 8 as the operation clock signal HCKO.
[0032]
Time T ₄₁ After the initialization operation in, the external oscillation detection counter 2 and the internal oscillation detection counter 3 start counting the number of cycles of the external clock signal HCLKN and the internal clock signal ICLK, respectively. However, when the supplied external clock signal OCLK has an abnormally low frequency, the rate at which the count value of the external oscillation detection counter 2 increases as shown in FIG. Significantly slower than the speed of
[0033]
As a result, the time T ₄₂ In this case, before an overflow occurs in the external oscillation detection counter 2, the internal oscillation detection counter 3 overflows, and the overflow signal OFB becomes "H". Further, when the overflow signal OFB becomes “H”, the external oscillation detection counter 2 is reset, and the counter value becomes “0”.
[0034]
Time T ₄₃ , The internal oscillation detection counter 3 sets the overflow signal OFB to “L”. Thereafter, since the internal oscillation detection counter 3 overflows before the external oscillation detection counter 2 overflows, the switching of the operation clock signal HCKO is not performed, and the internal clock signal ICLK is continuously output from the switching circuit 8 as the operation clock signal HCKO. .
[0035]
FIG. 5 is a timing chart showing the operation of the clock switching device when the supplied external clock signal OCLK is abnormal (high frequency).
Time T ₅₁ When the input reset signal RST is activated to "L", the external oscillation detection counter 2, the internal oscillation detection counter 3, and the register 7 are reset in the same manner as at the time T31 shown in FIG. . As a result, the internal clock signal ICLK is output from the switching circuit 8 as the operation clock signal HCKO.
[0036]
Here, when the supplied external clock signal OCLK has an abnormally high frequency, the external clock signal OCLK is cut off by the noise filter 1, and the external clock signal HCLKN is a signal having a fixed signal level. Therefore, the count value of the external oscillation detection counter 2 holds “0” and does not increase.
[0037]
As a result, no overflow occurs in the external oscillation detection counter 2 and only the internal oscillation detection counter 3 whose counter value increases with the passage of time overflows. Therefore, as in the case shown in FIG. 4, the operation clock signal HCKO is not switched, and the internal clock signal ICLK is continuously output from the switching circuit 8 as the operation clock signal HCKO.
[0038]
As described above in detail, according to the present embodiment, the external oscillation detection counter 2 counts the number of cycles of the external clock signal OCLK, and the internal oscillation detection counter 3 counts the number of cycles of the internal clock signal ICLK. When the external oscillation detection counter 2 overflows, it is determined that the external clock signal OCLK is in a normal frequency range, and the external clock signal OCLK is output as the operation clock HCKO based on the overflow signal OFA. The switching circuit 8 is switched and controlled.
[0039]
On the other hand, if the internal oscillation detection counter 3 overflows before the external oscillation detection counter 2, it is determined that the external clock signal OCLK is abnormal, and the external oscillation detection counter 2 is reset. Thus, it is possible to prevent the clock signal output as the operation clock signal HCKO from being switched to the abnormal external clock signal.
[0040]
Therefore, the switching of the clock signal output as the operation clock HCKO can be controlled according to the state of the supplied external clock signal OCLK by controlling only the hardware without causing the CPU to perform any processing. Can be reduced.
[0041]
In the first embodiment described above, an input terminal or the like is provided so that the timing at which the switching circuit 8 switches the clock signal output as the operation clock signal HCKO from the internal clock signal ICLK to the external clock signal OCLK can be externally controlled. You may do it. In this case, more appropriate selection of the clock signal and control of the switching timing can be performed.
[0042]
In the first embodiment described above, the switching circuit 8 first fixes the operation clock signal HCKO to “H” as shown in FIG. 3, and waits until the external clock signal OCLK becomes “H”. The clock signal is switched (at time T ₃₅ ), The operation clock signal HCKO may be fixed to “L” and the clock signal may be switched after the external clock signal OCLK becomes “L”. Even in this case, it is possible to prevent a signal of a high frequency from being temporarily output as the operation clock HCKO and the occurrence of noise called a mustache when the clock signal is switched.
[0043]
(Second embodiment)
Next, a second embodiment will be described.
FIG. 6 is a block diagram showing one configuration example of the clock switching device according to the second embodiment of the present invention. 6, blocks and the like having the same functions as the blocks and the like shown in FIG. 1 are denoted by the same reference numerals, and overlapping description will be omitted.
[0044]
As shown in FIG. 6, the clock switching device according to the second embodiment is different from the clock switching device according to the first embodiment shown in FIG. 1 in that external clock stop detection for detecting oscillation stop of the external clock signal OCLK is performed. A circuit 14 is further provided.
The external oscillation stop detection circuit 14 includes first and second latch circuits 9 and 10, a determination circuit 11, a logical sum operation circuit (OR circuit) 12, and an external oscillation stop detection counter 13, and operates with the internal clock signal ICLK. I do.
[0045]
The first latch circuit 9 acquires and holds the count value CNT from the external oscillation detection counter 2 (in the second embodiment, a 3-bit counter) in synchronization with the internal clock signal ICLK, and holds the count value CNT. That is, the count value held one cycle before is output. Similarly, the second latch circuit 10 captures and holds the output (count value) of the first latch circuit 9 in synchronization with the internal clock signal ICLK, and outputs the held count value. Here, the first and second latch circuits 9 and 10 are reset (initialized) by the clock selection signal XTAL output from the register 7.
[0046]
The determination circuit 11 determines whether the output of the first latch circuit 9 matches the output of the second latch circuit 10. Further, the determination circuit 11 generates and outputs one of the signal SA (match) and the signal SB (mismatch) based on the determination result. The OR circuit 12 performs a logical OR operation on the signal SB output from the determination circuit 11 and the clock selection signal XTAL output from the register 7, and outputs the operation result to the external oscillation stop detection counter 13 as a reset signal.
[0047]
The external oscillation stop detection counter 13 is a 4-bit counter that counts the number of cycles of the internal clock signal ICLK according to the signal SA output from the determination circuit 11. When the count value overflows, the external oscillation stop detection counter 13 outputs a clear signal XTALCLR to the register 7 and resets the register value of the register 7 to “0”.
[0048]
As shown by the dotted line in FIG. 6, when an overflow of the count value occurs, the external oscillation stop detection counter 13 outputs an externally output oscillation stop detection signal DTC for notifying the stop of the oscillation of the external clock signal OCLK. At least one of an interrupt signal INT for requesting execution of interrupt processing and the like and an internal reset signal IRST may be output.
[0049]
Further, when the control circuit 15 is provided and the oscillation of the internal clock signal ICLK is stopped according to the setting by the CPU or the like, the operation inhibition signal ODS causes the external oscillation stop detection circuit 14 (the external oscillation stop detection counter 13) to operate. The operation may be prohibited. The control circuit 15 may be provided in the external oscillation stop detection circuit 14 as shown in FIG. 6, or may be provided separately (externally) from the external oscillation stop detection circuit 14.
[0050]
Next, the operation will be described.
FIG. 7 is a flowchart for explaining the outline of the operation of the clock switching device shown in FIG. In FIG. 7, steps S11, S12, S13, and S14 correspond to steps S1, S2, S4, and S3 shown in FIG. 2, respectively, and are performed according to the state of the external clock signal OCLK. Since the operation similar to the operation shown in (1) is performed, the description is omitted.
[0051]
In step S14, when the register value is set to "1" in the register 7, the reset states of the first and second latch circuits 9, 10 and the external oscillation stop detection counter 13 in the external oscillation stop detection circuit 14 are released. Then, each operation starts. Thus, the determination circuit 11 determines whether or not the outputs of the first and second latch circuits 9 and 10 match, and the external oscillation stop detection counter 13 determines whether the output of the external oscillation stop counter 13 The number of cycles of the clock signal ICLK is counted.
[0052]
Next, the clock switching device determines whether or not the count value overflows in the external oscillation stop detection counter 13 (Step S15).
As a result of the determination, when the count value overflows in the external oscillation stop detection counter 13 (when the count value of the external oscillation detection counter 2 is continuously the same for a predetermined period), the clock switching device Then, an internal reset signal and the like are generated to perform an initialization operation of each circuit (step S11). As a result, the operation clock signal HCKO is switched, and the switching circuit 8 outputs the internal clock signal ICLK as the operation clock signal HCKO.
[0053]
It is sufficient to reset the register value of the register 7 to “0” by the clear signal XTALCLR without performing the initialization operation of each circuit in the clock switching device, and the operation clock signal HCKO is switched and the operation is performed. It is possible to output internal clock signal ICLK as clock signal HCKO.
[0054]
On the other hand, as a result of the determination, when the count value does not overflow in the external oscillation stop detection counter 13, the external clock signal OCLK (HCLKN) oscillates as shown in FIG. Was reset (time T ₉₂ reference. ), The process returns to step S14, and the register 7 holds the register value “1”. Therefore, switching of operation clock signal HCKO is not performed, and switching circuit 8 outputs external clock signal OCLK as operation clock signal HCKO.
[0055]
The operation of the clock switching device according to the second embodiment when the oscillation of the external clock signal OCLK is stopped will be described in detail with reference to FIG.
FIG. 8 is a timing chart showing the operation of the clock switching device when the external clock signal OCLK is no longer supplied due to the stop of the oscillation of the external clock signal OCLK. In FIG. 8, it is assumed that the operation clock signal HCKO is switched after the initialization operation is completed, and that the external clock signal OCLK is output from the switching circuit 8 as the operation clock signal HCKO.
[0056]
Time T ₈₁ When the oscillation of the supplied external clock signal OCLK stops, the external oscillation detection counter 2 stops counting the number of cycles of the external clock signal OCLK, and the counter value CNT is fixed at a predetermined value (see FIG. 8). 3 "(hexadecimal notation)).
[0057]
At this time, since operation is performed by the internal clock signal ICLK and the register value (clock selection signal XTAL) of the register 7 is “1” (“H”), the external oscillation stop detection circuit 14 compares the count value CNT. An external oscillation stop detection operation is being performed.
[0058]
Specifically, the count value CNT is taken into the first latch circuit 9 in synchronization with the internal clock signal ICLK, and the taken count value is taken into the second latch circuit at the next (one cycle later) clock. 10 and a new count value CNT is captured by the first latch circuit 9. The fetched count value CNT is output from the first and second latch circuits 9 and 10 to the determination circuit 11, respectively, and the determination circuit 11 determines whether or not the count values CNT match.
[0059]
As a result of the determination, if the count values CNT do not match, a signal SB is output from the determination circuit 11, and the counter value of the external oscillation stop detection counter 13 is reset. On the other hand, if the count values CNT match as a result of the determination, the determination circuit 11 outputs a signal SA as shown in FIG. 8 (for example, “H” during a period in which the count values CNT match). In response to the signal SA, the external oscillation stop detection counter 13 counts the number of cycles of the internal clock signal ICLK, and the counter value of the external oscillation stop detection counter 13 increases.
[0060]
In FIG. 8, time T ₈₁ Thereafter, since the counter value CNT of the external oscillation detection counter 2 does not change, the counter value of the external oscillation stop detection counter 13 increases. And time T ₈₂ When the counter value of the external oscillation stop detection counter 13 reaches the maximum value (when it overflows), the external oscillation stop detection counter 13 outputs the clear signal XTALCLR for one cycle in synchronization with the fall of the internal clock signal ICLK. Only "L".
[0061]
Further, the time T ₈₃ , The register value of the register 7 becomes “0” based on the clear signal XTALCLR, and the clock selection signal XTAL output from the register 7 becomes “L”. Thus, the operation clock signal HCKO is switched, and the internal clock signal ICLK is output from the switching circuit 8 as the operation clock signal HCKO. When the clock selection signal XTAL becomes "L", the operation of the external oscillation stop detection circuit 14 stops.
[0062]
On the other hand, as shown in FIG. ₉₁ After the external oscillation stop counter 13 starts counting the number of cycles of the internal clock signal ICLK, the external clock signal OCLK is oscillated (at time T). ₉₂ ), The counter value CNT of the external oscillation detection counter 2 changes. As a result, different (unmatched) counter values CNT are output from the latch circuits 9 and 10 to the determination circuit 11, and the determination circuit 11 outputs the signal SB as the determination result (sets the signal SA to "L" and sets the signal SB to To “H”). Therefore, the counter value of the external oscillation stop counter 13 is reset to “0”. Thereafter, the external oscillation stop counter 13 starts counting the number of cycles of the internal clock signal ICLK again.
[0063]
As described above, according to the second embodiment, in addition to the effects obtained by the above-described first embodiment, by providing the external oscillation stop detection circuit 14, it is assumed that the oscillation of the external clock signal OCLK is stopped. Also, switching can be controlled by the clear signal XTALCLR from the external oscillation stop detection counter 13 so that the internal clock signal ICLK is output as the operation clock HCKO. Therefore, even if the oscillation of the external clock signal OCLK is stopped, the switching control of the clock signal output as the operation clock HCKO can be performed by the control of only the hardware without performing any processing interposed by the CPU. Can be reduced.
[0064]
Further, unlike the conventional charge / discharge analog circuit as disclosed in Patent Document 2, in the second embodiment, the oscillation of the external clock signal OCLK is detected by a digital circuit. In comparison, current consumption and power consumption of the circuit can be reduced.
Further, the stop of the oscillation of the external clock signal OCLK can be reliably detected by controlling only the hardware, and the time required from the stop of the circuit to the return thereof can be reduced as compared with the case where the conventional charge / discharge analog circuit is used. Can be.
[0065]
In the first and second embodiments described above, the clock switching device has been described by taking the external clock OCLK and the internal clock ICLK as an example. However, the present invention is not limited to the external clock OCLK and the internal clock ICLK, The present invention can be applied to switching control between a reference clock signal, which is a reference always oscillated when the switching device is operating, and another arbitrary clock signal different from the reference clock.
[0066]
Further, the other arbitrary clock signal (external clock signal OCLK) is not limited to one, and may be a plurality of clock signals. In this case, priorities may be assigned to the plurality of clock signals, and the switching circuit 8 may control the switching of the clock signal output as the operation clock signal HCKO with reference to the priorities.
[0067]
In the first and second embodiments described above, the counters included in the clock switching device are all increment counters in which the counter value increases by one. However, a decrement counter in which the counter value decreases by one may be used. It can be configured similarly. The size (number of bits) of each counter shown in the first and second embodiments is an example, and the size of the counter is arbitrary as long as the required magnitude relationship between the counters is satisfied. is there.
[0068]
It should be noted that each of the above-described embodiments is merely an example of a concrete embodiment for carrying out the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features.
Various aspects of the present invention are shown below as supplementary notes.
[0069]
(Supplementary Note 1) A first counter circuit that counts the number of cycles of the input first clock signal and outputs a first overflow signal when an overflow occurs,
A switching circuit to which the first clock signal and a second clock signal different from the first clock signal are input, and which selectively outputs one of the first and second clock signals;
A clock switching device, wherein the switching circuit switches a clock signal to be output from the second clock signal to the first clock signal in response to the first overflow signal.
(Supplementary Note 2) A second counter circuit that counts the number of cycles of the second clock signal and outputs a second overflow signal when an overflow occurs,
2. The first counter circuit according to claim 1, wherein the maximum value of the count value is smaller than the maximum value of the count value of the second counter circuit, and the first counter circuit is initialized by the second overflow signal. Clock switching device.
(Supplementary Note 3) A filter circuit for removing a high-frequency signal is further provided,
3. The clock switching device according to claim 1, wherein the first clock signal is input to the first counter circuit via the filter circuit.
(Supplementary Note 4) The first clock signal is a plurality of clock signals,
4. The clock switching device according to any one of supplementary notes 1 to 3, further comprising the first counter circuit corresponding to each of the plurality of clock signals.
(Supplementary Note 5) Different priorities are given to the plurality of clock signals of the first clock signal,
5. The clock switching device according to claim 4, wherein the switching circuit outputs the first clock signal in accordance with the first overflow signal and the priority.
(Supplementary Note 6) The first counter circuit outputs the first overflow signal during a period of a plurality of cycles of the first clock signal, wherein the first counter circuit outputs the first overflow signal. Clock switching device.
(Supplementary Note 7) When switching the clock signal to be output from the second clock signal to the first clock signal, the switching circuit outputs a high-level or low-level signal having a fixed signal level, and 7. The clock switching device according to claim 1, wherein the clock signal is switched after the signal level of the clock signal becomes the same as the fixed signal level.
(Supplementary note 8) The clock switching device according to any one of Supplementary notes 1 to 7, further comprising a register capable of determining which clock signal is output from the switching circuit.
(Supplementary note 9) The clock switching device according to supplementary note 8, wherein a value is set in the register based on the first overflow signal.
(Supplementary note 10) The semiconductor device according to Supplementary note 1, further comprising an input terminal for inputting a signal for controlling timing for switching a clock signal output from the switching circuit from the second clock signal to the first clock signal. 10. The clock switching device according to any one of claims 9 to 9.
(Supplementary note 11) The clock switching device according to supplementary note 2, wherein the first and second counter circuits are increment counters.
(Supplementary note 12) The clock switching device according to supplementary note 2, wherein the first and second counter circuits are decrement counters.
(Supplementary note 13) The clock switching device according to any one of Supplementary notes 1 to 12, wherein the second clock signal is always oscillated when the clock switching device is operating. .
(Supplementary Note 14) An oscillation stop detection circuit for detecting the stop of the oscillation of the first clock signal is further provided.
The switching circuit switches an output clock signal from the first clock signal to the second clock signal in accordance with a detection result of the oscillation stop detection circuit. A clock switching device according to the item.
(Supplementary Note 15) The oscillation stop detection circuit includes: a determination circuit that compares and determines the count values of the first counter circuit at different points in time;
A third counter circuit that operates in accordance with a result of the determination by the determination circuit and that outputs a third overflow signal when an overflow occurs;
15. The clock switching device according to claim 14, wherein the switching circuit switches an output clock signal from the first clock signal to the second clock signal in response to the third overflow signal.
(Supplementary note 16) The supplementary note 15, wherein the determination circuit compares and determines whether or not the counter values of the first counter circuit, which are continuously output in a time series, in the adjacent periods coincide with each other. Clock switching device.
(Supplementary Note 17) The oscillation stop detection circuit outputs at least one of a detection signal that can be output to the outside, an internal reset signal, and an interrupt signal when the oscillation stop of the first clock signal is detected. The clock switching device according to any one of supplementary notes 14 to 16, characterized in that:
(Supplementary note 18) The clock switching device according to any one of Supplementary notes 14 to 17, further comprising a control circuit that inhibits the operation of the oscillation stop detection circuit.
(Supplementary Note 19) The first clock signal is a plurality of clock signals,
19. The clock switching device according to any one of appendices 14 to 18, further comprising the oscillation stop detection circuit corresponding to each of the plurality of clock signals.
(Supplementary Note 20) The first clock signal is an external clock signal that is supplied to the semiconductor arithmetic device having the clock switching device from the outside via an input terminal.
20. The clock switching device according to any one of supplementary notes 1 to 19, wherein the second clock signal is an internal clock signal generated by an oscillation circuit included in the semiconductor arithmetic device.
[0070]
【The invention's effect】
As described above, according to the present invention, the number of cycles of the input first clock signal is counted by the first counter circuit, and the first clock signal and the second clock signal different from the first clock signal are counted. The switching circuit to which the clock signal is input switches the clock signal to be output from the second clock signal to the first clock signal according to the first overflow signal output from the first counter circuit. Accordingly, the CPU can switch and output the clock signal to be output only by controlling the hardware without performing any processing, and the processing load on the CPU can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a clock switching device according to a first embodiment.
FIG. 2 is a flowchart illustrating an outline of an operation of the clock switching device according to the first embodiment.
FIG. 3 is a timing chart showing the operation of the clock switching device when the external clock signal is normal.
FIG. 4 is a timing chart showing the operation of the clock switching device when the external clock signal is abnormal (low frequency).
FIG. 5 is a timing chart showing the operation of the clock switching device when the external clock signal is abnormal (high frequency).
FIG. 6 is a block diagram illustrating a configuration example of a clock switching device according to a second embodiment.
FIG. 7 is a flowchart illustrating an outline of an operation of the clock switching device according to the second embodiment.
FIG. 8 is a timing chart showing the operation of the clock switching device when the oscillation of the external clock signal stops.
FIG. 9 is a timing chart showing an external oscillation stop detection operation.
[Explanation of symbols]
1 Noise filter
2 External oscillation detection counter
3 Internal oscillation detection counter
4, 6 edge detection circuit
5,12 OR operation circuit
7 Register
8 Switching circuit
9, 10 Latch circuit
11 Judgment circuit
13 External oscillation stop detection counter
14 External oscillation stop detection circuit

Claims (10)

A first counter circuit that counts the number of cycles of the input first clock signal and outputs a first overflow signal when an overflow occurs;
A switching circuit to which the first clock signal and a second clock signal different from the first clock signal are input, and which selectively outputs one of the first and second clock signals;
A clock switching device, wherein the switching circuit switches a clock signal to be output from the second clock signal to the first clock signal in response to the first overflow signal. A second counter circuit that counts the number of cycles of the second clock signal and outputs a second overflow signal when an overflow occurs;
2. The first counter circuit according to claim 1, wherein the maximum value of the count value is smaller than the maximum value of the count value of the second counter circuit, and the first counter circuit is initialized by the second overflow signal. Clock switching device. It further comprises a filter circuit for removing high-frequency signals,
3. The clock switching device according to claim 1, wherein the first clock signal is input to the first counter circuit via the filter circuit. The first clock signal is a plurality of clock signals,
The clock switching device according to claim 1, further comprising the first counter circuit corresponding to each of the plurality of clock signals. The switching circuit, when switching the clock signal to be output from the second clock signal to the first clock signal, outputs a high-level or low-level signal having a fixed signal level, and outputs the signal of the first clock signal. The clock switching device according to any one of claims 1 to 4, wherein the clock signal is switched after the level becomes the same as the fixed signal level. The clock switching device according to any one of claims 1 to 5, further comprising a register capable of determining which clock signal is output from the switching circuit. An oscillation stop detection circuit that detects an oscillation stop of the first clock signal;
7. The switching circuit according to claim 1, wherein the switching circuit switches an output clock signal from the first clock signal to the second clock signal in accordance with a detection result of the oscillation stop detection circuit. 2. The clock switching device according to claim 1. A determination circuit for comparing and determining the count values of the first counter circuit at different times from each other;
A third counter circuit that operates in accordance with a result of the determination by the determination circuit and that outputs a third overflow signal when an overflow occurs;
The clock switching device according to claim 7, wherein the switching circuit switches a clock signal to be output from the first clock signal to the second clock signal in response to the third overflow signal. The oscillation stop detection circuit outputs at least one of a detection signal that can be output to the outside, an internal reset signal, and an interrupt signal when the oscillation stop of the first clock signal is detected. The clock switching device according to claim 7. The first clock signal is an external clock signal externally supplied to the semiconductor arithmetic device having the clock switching device via an input terminal,
10. The clock switching device according to claim 1, wherein the second clock signal is an internal clock signal generated by an oscillation circuit included in the semiconductor arithmetic device.

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