JP2964704B2 - Clock stop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock circuit, and more particularly to a circuit for stopping an external clock supplied to a large-scale integrated circuit (hereinafter abbreviated as LSI).

[0002]

2. Description of the Related Art In recent years, band devices such as handy terminals and electronic notebooks have been developed with the progress of LSIs such as microcomputers. These devices need to be lightweight and operate for a long time because of their applications, and LSIs mounted on these devices also require low power consumption electrodes. In order to reduce the power consumption, many LSIs have a function of temporarily stopping a clock when the LSI is not operating due to a key input or the like.

[0003] As a method of stopping the clock, LS
As one of the internal instructions for operating I, there is a software stop which has a stop instruction and executes this instruction to stop the clock. There is also a hardware stop in which an external stop terminal is provided to stop the clock by an external signal. As another clock stop method, there is a method of stopping the external clock directly.

[0004]

The conventional LSI clock stop circuit has a problem that the LSI cannot be stopped at an arbitrary timing from the outside by software stop. In the hardware stop, the LSI can be stopped at an arbitrary timing from the outside, but there is a disadvantage that one external terminal is added.

In the method of directly stopping the clock, the following problem occurs. LSIs such as microcomputers
Uses a lot of dynamic circuits inside to reduce the number of transistors and reduce the chip size. Thus, the cost of the LSI is reduced. However, in a dynamic circuit, if the clock is stopped at the sampling timing, the stored charge is released by a leak current, and data and the like are destroyed.

To avoid this, a static circuit may be used for the internal circuit of the LSI. However, the static circuit requires almost twice the number of transistors as compared to the dynamic circuit, and the cost increases due to an increase in chip size. Become. In addition, there are timings in the bus cycle and the machine cycle in the LSI where the clock cannot be stopped halfway due to functional restrictions. Further, in a sense amplifier, a charge pump or the like, a predetermined procedure is required before and after the clock is stopped, and the clock cannot be directly stopped.

An object of the present invention is to detect that the external clock signal has stopped and output a stop signal, and at the same time, automatically generate a clock signal necessary for the internal circuit of the microcomputer to shift to the stop state. It is an object of the present invention to provide a clock stop circuit for causing a clock stop.

[0008]

A clock stop circuit according to the present invention detects a stop of an external clock, receives an output signal of the detect circuit, and generates an internal clock after the stop of the external clock. An internal clock generation circuit, and counts the number of generated internal clocks to a predetermined number.
A means is provided for stopping the generation of the internal clock when it has reached, and a selection circuit for switching and outputting the external clock or the internal clock output from the internal clock generation circuit. Or the clock stop circuit of the present invention
Is a detection circuit that detects that the external clock has stopped,
Stop the external clock by inputting the output signal of the detection circuit
An internal clock generation circuit that generates an internal clock later,
The number of occurrences of the internal clock is counted and reaches a predetermined number.
Means for stopping the generation of the internal clock,
OR gate for inputting an internal clock and the internal clock
And is configured.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows a clock stop circuit of a microcomputer according to an embodiment of the present invention. The clock stop circuit includes a clock stop detection circuit 1 for inputting an external clock CKE.
And an internal clock generation circuit 6 which receives the output signal STP of the detection circuit 1 and generates the internal clock CKI for a certain period (T2 to T3) after the external clock CKE is stopped, and an external clock CKE or an internal clock generation circuit 6 And a selection circuit 5 for switching and outputting the internal clock CKI output by the selector.

Next, the operation will be described. First, an external clock signal CKE is input to an external terminal of the microcomputer. The external clock signal CKE is input to the clock stop detection circuit 1. The clock stop detection circuit 1 has the SN741
23N, etc., is constituted by a retrigger monostable multi, and outputs a high level when the period of the rising edge of the external clock signal CKE is within the operation time Tm, and outputs a low level when the rising edge does not come within the operation time Tm. Output. The output of the clock stop detection circuit 1 is output to the inside of the microcomputer as a row active stop signal STP, and performs a transition process to a stop state.

The stop signal STP is input to a reset / set flip-flop 2 (hereinafter abbreviated as R / SFF2) and is set at the rising edge. R / SF
The output signal RSF of F2 is input to the strobe input S of the free-running multi 3 and oscillates when the output signal RSF of R / S FF2 is at a high level. Self-running multi 3 outputs internal clock signal CKI.

The internal clock signal CKI is input to the counter 4. The counter 4 is a quaternary counter and outputs a counter output signal CT. The counter output signal CT is R / S · F
The signal is input to F2 and the R / S FF2 is reset at the rising edge.

The external clock signal CKE and the internal clock signal CKI are input to a selection circuit 5, and a selection input S of the selection circuit 5 receives a stop signal STP. Selection circuit 5
Indicates an external clock signal CKE when the stop signal STP is at a high level, and an internal clock signal CK when the stop signal STP is at a low level.
I is selected and the clock signal CLK is output as a clock signal to the inside of the microcomputer.

Next, the operation of the clock stop circuit of FIG. 1 will be described with reference to the timing chart of FIG. Until timing T1, the microcomputer is in a normal operating state, and the external clock signal CKE is
Since the falling edge periodically comes within the operation time Tm, the stop signal STP outputs a high level, and the selection circuit 5 selects and outputs the external clock signal CKE as the clock signal CLK.

At timing T1, the external clock signal CKE
Stops. Clock stop detection circuit 1 at timing T2
And the stop signal STP goes low. Therefore, the R / S FF 2 is set, and the self-running multi 3 starts oscillating. The selection circuit 5 switches and outputs the internal clock signal CKI from the external clock signal CKE as the clock signal CLK.

At timing T3, the internal clock signal CKI
Outputs the fourth clock, the counter output signal CT stops oscillating, and a low level is output as the clock signal CLK.

The internal circuit of the microcomputer enters the stop state after completing the transition processing to the stop state by the four clock signals CLK output while the stop signal STP is at the low level (low active). At timing T4, the external clock signal CKE restarts.

At timing T5, the external clock signal CKE
The stop signal STP goes high, the stop state is released, and the microcomputer returns to the normal operation state due to the falling edge of the clock stop detection circuit 1.

FIG. 3 shows a clock stop circuit according to a second embodiment of the present invention. The generation circuit of the clock signal CLK uses an OR gate 6 instead of the selection circuit 5 of FIG. 1 and receives an external clock signal CKE and an internal clock signal CKI as inputs. The other circuit configuration is the same as that of the clock stop circuit of FIG. 1, and the operation thereof is the same when the external clock signal CKE is stopped at the low level, and the description is omitted.

[0020]

As described above, according to the present invention, when the external clock signal CKE of the microcomputer is stopped and the stop signal STP is output, the internal circuit of the microcomputer shifts to the stop state. The internal clock generator circuit automatically generates the necessary clock signals to stop the microcomputer at any timing without using special external terminals. Can use a circuit that cannot directly stop the external clock signal, so that there is also an effect of reducing costs.

[Brief description of the drawings]

FIG. 1 is a clock stop circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the clock stop circuit of FIG. 1;

FIG. 3 is a clock stop circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 clock stop detection circuit 2 flip-flop 3 self-running multi 4 counter 5 selection circuit 6 OR gate CKE external clock signal CKI internal clock signal STP stop signal CT counter output signal CLK clock signal RSF R / S · FF2 output signal T1 to T5 Timing Tm Operating time of clock stop detection circuit 1

Claims (2)

(57) [Claims] A detection circuit as claimed in claim 1] external clock to detect that it has stopped, the internal clock generation circuit which receives the output signal of the detection circuit for generating an internal clock after the external clock stop, the number of occurrences of the internal clock Count and place
Means for stopping generation of the internal clock when a constant is reached
And a selection circuit for switching and outputting the external clock or the internal clock output from the internal clock generation circuit. (2) A detection that detects that the external clock has stopped
Output circuit, and an output signal of the detection circuit.
Internal clock generation that generates an internal clock after lock is stopped
Counting the number of generations of the raw clock and the internal clock
Means for stopping generation of the internal clock when a constant is reached
And inputting the external clock and the internal clock
A clock stop circuit having an OR gate
Road.