JP3144811B2 - Monitoring timer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring timer circuit for detecting runaway of a program.

[0002]

2. Description of the Related Art In a conventional monitoring timer circuit, as shown in FIG. 3, a counter 32 which performs a count-up operation by a clock signal, and a counter by a logical sum of a hit signal output from a microcomputer and a hard reset signal. Is set to the initial value, and the counter is set to the initial value by a hard reset signal or a hit signal, and thereafter counts up.

[0003]

However, in the case of the above-described conventional circuit configuration, it is necessary to output a hit signal periodically in order to detect this as a normal operation even during the initial processing of the program. It was necessary to incorporate a hit signal output function at the stage. Also,
In the case where the monitoring timer circuit is stopped at the debugging stage of the program development, there is a disadvantage that a device for forcibly stopping the monitoring timer circuit on hardware is required.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a monitoring timer circuit which operates by an initial hit signal.

[0005]

To achieve the above object, a monitoring timer circuit according to the present invention comprises a counter means for counting up by a clock signal, the counter means being set to an initial value, and a reset every hit signal. A logic processing means, wherein the logic processing means resets by inputting a hard reset signal, and outputs a set signal by inputting a hit signal; and an inverted output of the counter means. A first AND circuit for activating the counter circuit by an AND operation with a set signal output from a storage circuit, and a second AND circuit for performing an AND operation on an output of the first AND circuit and a hit signal The counter is set to an initial value by the logical sum of the logical product of the second logical product and the output of the second logical product and the hard reset signal A counter means for counting up the clock signal and a Liwa means sets the counter means to an initial value, in which a logic element means for resetting each hit signal.

[0006]

Therefore, the counter means stops the count-up operation until the hit signal is output after the hard reset, and starts the count operation from the first hit signal, thereby facilitating program development. Having.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a monitoring timer circuit according to the present invention. FIG. 2 is an operation timing chart in FIG.

In FIG. 1, reference numeral 1 denotes an SR flip-flop of storage means for outputting a set signal by detecting the presence or absence of a hit signal from a microcomputer or the like; , An n-ary counter of counter means for outputting
The AND circuit of the first AND means for controlling the counter operation of the n-ary counter 2 by taking the logical product of the output of the R flip-flop and the inverted output of the n-ary counter 2, and 4 is the logic of the output of the AND circuit 3 and the hit signal A of the second AND means for taking the product
ND circuits 5 and 5 are OR circuits of logical OR means for calculating the logical sum of the output of the AND circuit 4 and the hard reset signal and setting the n-ary counter 2 to an initial value. Here, the output of the AND circuit 3 is supplied to the ENA terminal of the n-ary counter 2, and the hard reset signal is supplied to the CL terminal of the SR flip-flop 1 and the CL terminal of the n-ary counter 2.

Next, a specific circuit operation will be described with reference to an operation timing chart of FIG.

The clock signal is a reference clock of the n-ary counter 2 output from an oscillation circuit or the like that oscillates at a predetermined frequency. After the power supply is started, the hard reset signal is "high" for a fixed time until a certain time t1. As a result, the SR flip-flop 1 is reset and its output becomes "
low ", and the n-ary counter 2 is set to the initial state.
The output of the ND circuit 3 keeps "low", and the n-ary counter 2 keeps the counter operation stopped. Next, at time t2
When a hit signal is input, the SR flip-flop 1
Is set to "high", and the n-ary counter 2 starts the counter operation. After that, even if a hit signal is input, the output of the SR flip-flop 1 remains "high".
h "is maintained, the output of the AND circuit 4 passes the hit signal input during the n-ary counting operation such as the hit signal input at the time t3 with the count number 5, and the n-ary counter 2 returns to the initial value. It is reset, but at time t3
If a hit signal is not input during the n-ary counter operation of the n-ary counter 2 as in the period from to the time t4, the output of the n-ary counter 2 becomes "
high ", and the output of the AND circuit 3 to which the inverted output is inputted becomes" low ", so that the hit signal inputted thereafter is stopped by the OR circuit 5, and thereafter, n
The hex counter 2 is never set to the initial value. Therefore, the output of the n-ary counter 2 is held "high" until a hard reset signal is input, and an abnormality is notified to an external circuit.

[0011]

As described above, according to the present invention, since the monitoring timer circuit is activated by the first hit signal, there is no need to provide a function of outputting a hit signal at the time of initial processing of a program. It is only necessary to insert the function into the main processing routine. Further, the debugging efficiency in the program development stage can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is an operation timing chart of the present embodiment.

FIG. 3 is a circuit diagram of a conventional monitoring timer circuit.

[Brief description of reference numerals]

 REFERENCE SIGNS LIST 1 SR flip-flop (storage means) 2 n-ary counter (counter means) 3 AND circuit (first logical product means) 4 AND circuit (second logical product means) 5 OR circuit (logical sum means)

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-27038 (JP, A) JP-A-2-120943 (JP, A) JP-A-2-68637 (JP, A)

Claims (1)

(57) [Claims] 1. A monitoring timer circuit comprising: counter means for counting up by a clock signal; and logic processing means for setting the counter means to an initial value and resetting for each hit signal. Storage means for resetting by input of a reset signal and outputting a set signal by input of a hit signal ; and said counter means by a logical product of an inverted output of said counter means and a set signal outputted from said storage means. a first logical product means operable state, the logical product of the output and the hit signal of said first logical aND means, said counter hand
A second AND means for setting the stage to an initial value .