JP2002300781A - Large current push-pull step-up circuit - Google Patents

Large current push-pull step-up circuit

Info

Publication number
JP2002300781A
JP2002300781A JP2001096620A JP2001096620A JP2002300781A JP 2002300781 A JP2002300781 A JP 2002300781A JP 2001096620 A JP2001096620 A JP 2001096620A JP 2001096620 A JP2001096620 A JP 2001096620A JP 2002300781 A JP2002300781 A JP 2002300781A
Authority
JP
Japan
Prior art keywords
plate
electrode
electrodes
push
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001096620A
Other languages
Japanese (ja)
Other versions
JP4346253B2 (en
Inventor
Junichi Hoshina
淳一 保科
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sawafuji Electric Co Ltd
Original Assignee
Sawafuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sawafuji Electric Co Ltd filed Critical Sawafuji Electric Co Ltd
Priority to JP2001096620A priority Critical patent/JP4346253B2/en
Publication of JP2002300781A publication Critical patent/JP2002300781A/en
Application granted granted Critical
Publication of JP4346253B2 publication Critical patent/JP4346253B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a push-pull step-up power supply circuit which has a large capacity with the secondary side output. SOLUTION: This large current push-pull step-up circuit has a first plate-like electrode 1 of an approximately rectangular shape having a region disposing a push-pull transformer 20 in the center and terminal parts each mounting capacitors on both sides, a pair of second plate-like electrodes 2 and 3 each of an approximately rectangular shape having approximately a half area of the first plate-like electrode and having each a terminal connecting field-effect transistors and Zener diodes on one side, a third plate-like electrode 4 of an approximately rectangular shape having approximately same area of the upper plate part of the first plate-like electrode and having terminal parts each connecting to field-effect transistors, capacitors, and Zener diodes on both sides, and electric-insulation sheets 8. The first, the second and the third plate-like electrodes are electrically insulated between each other by the electric-insulation sheet 8 and integrally fixed with locking elements.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、直流低電圧を直流
高電圧に昇圧する昇圧回路で使用されるプッシュプルタ
イプ昇圧回路の板状電極構造に関する。
The present invention relates to a plate-like electrode structure of a push-pull type booster circuit used in a booster circuit for boosting a low DC voltage to a high DC voltage.

【0002】[0002]

【従来の技術】プッシュプルタイプ昇圧回路は、二次側
における高電圧出力を確保するため、低電圧一次側は大
電流が流れることとなる。このため、本願出願人による
特許出願2000−218151号等の従来構成におい
ては、一次側電流回路の大きなインダクタンスに起因し
て、スイッチング素子のオフ時に生じる逆起電力に起因
するスパイク電圧が大きくなり、スイッチング損失の増
加、スナバ回路の必要容量の増大、一次入力及び二次出
力間の変換効率の低下が発生し、全体としての昇圧電源
回路のパフォーマンス低下が生じていた。
2. Description of the Related Art In a push-pull type booster circuit, a large current flows on a low voltage primary side in order to ensure a high voltage output on a secondary side. For this reason, in a conventional configuration such as Japanese Patent Application No. 2000-218151 filed by the present applicant, a spike voltage caused by a back electromotive force generated when the switching element is turned off increases due to a large inductance of the primary side current circuit, The switching loss increases, the required capacity of the snubber circuit increases, the conversion efficiency between the primary input and the secondary output decreases, and the performance of the booster power supply circuit as a whole has deteriorated.

【0003】[0003]

【発明が解決しようとする課題】本願発明は、プッシュ
プルタイプ昇圧回路において、大電流となる一次側電流
経路を最小化し、一次側電流回路のインダクタンスを最
小化し、スイッチング素子のオフ時に生じる逆起電力に
起因するスパイク電圧を削減し、スイッチング損失を削
減し、スナバ回路の必要容量を削減し、一次入力及び二
次出力間の変換効率を向上し、全体としての昇圧電源回
路のパフォーマンスを向上し、二次側出力の大容量化を
課題とする。
SUMMARY OF THE INVENTION The present invention relates to a push-pull type booster circuit, which minimizes a primary current path which causes a large current, minimizes an inductance of the primary current circuit, and generates a counter electromotive force generated when a switching element is turned off. Reduce power-induced spike voltage, reduce switching loss, reduce required capacity of snubber circuit, improve conversion efficiency between primary input and secondary output, and improve overall boost power supply circuit performance. Another object is to increase the capacity of the secondary side output.

【0004】[0004]

【課題を解決するための手段】上記の課題を解決するた
めに、請求項1の発明では、中央にプッシュプルトラン
スを配置する領域及び両側部にコンデンサーを装着する
端子部を備えほぼ矩形形状の第一の板状電極、一側部に
電解効果トランジスタ、及びツェナーダイオードを接続
する端子部を備えほぼ矩形形状であり第一の板状電極の
ほぼ半分の面積を備える一対の第二の板状電極、両側部
に電解効果トランジスタ、コンデンサー、及びツェナー
ダイオードを接続する端子部を備えほぼ矩形形状であり
第一の板状電極の板上部とほぼ等しい面積を備える第三
の板状電極、及び電気絶縁シートを備え、第一の板状電
極の下部に一対の第二の板状電極を配置し、第二の板状
電極の下部に第三の板状電極を配置し、これら第一、第
二、第三の各板状電極間は電気絶縁シートにより電気的
に絶縁され、締結要素によりこれら第一、第二、第三の
板状電極を一体に固定することを特徴とする大電流プッ
シュプルタイプ昇圧回路の板状電極構造とし、
In order to solve the above-mentioned problems, the invention according to claim 1 has a substantially rectangular shape having a centrally disposed area for arranging a push-pull transformer and terminal parts for mounting capacitors on both sides. A first plate-like electrode, a pair of second plate-like members each having a terminal portion for connecting a field effect transistor and a Zener diode on one side and having a substantially rectangular shape and an area approximately half the area of the first plate-like electrode. A third plate-like electrode having an electrode, a terminal portion for connecting a field effect transistor, a capacitor, and a zener diode on both sides, having a substantially rectangular shape, and having an area approximately equal to the upper portion of the first plate-like electrode; An insulating sheet is provided, a pair of second plate-like electrodes is arranged below the first plate-like electrode, and a third plate-like electrode is arranged below the second plate-like electrode. 2nd and 3rd plates The plates are electrically insulated by an electric insulating sheet, and the first, second, and third plate electrodes are integrally fixed by a fastening element. Structure and

【0005】請求項2の発明では、前記第一、第二、第
三の板状電極構造に配置される電子素子は、幾何学的対
象位置に配置されることを特徴とし、
According to a second aspect of the present invention, the electronic elements arranged in the first, second, and third plate-like electrode structures are arranged at geometrically symmetric positions.

【0006】請求項3の発明では、前記第一、第二、第
三の板状電極を固定する締結要素は、電気絶縁性材から
形成されることを特徴とする。
According to a third aspect of the present invention, the fastening element for fixing the first, second, and third plate electrodes is formed of an electrically insulating material.

【0007】[0007]

【発明の実施の形態】以下に述べる実施の形態は一実施
例であり、本技術分野で通常の技術を有する技術者によ
れば、本願発明の技術範囲を逸脱することなく他の実施
の形態を実施することは容易である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment described below is an example, and according to a person having ordinary skill in the art, other embodiments may be used without departing from the technical scope of the present invention. Is easy to implement.

【0008】図1は本発明によるプッシュプルタイプ昇
圧電源回路を示す。図1において、点線で囲まれる一次
側回路100は、プッシュプルトランス20の一次側巻
線20−2、一次側巻線の中間引き出し部B+に接続す
る12Vバッテリー等の電源30、B+ラインに関して
電源30の両端に各々並列にm個(合計2m個)接続さ
れる電解コンデンサー7を備える。更に、一次回路10
0は、一次巻線のC1ライン及びB+ライン間に、電解
効果トランジスタ5及びツェナーダイオード6がn個並
列に接続される。電界効果トランジスタ5のソースSは
B+ラインに、ドレインDはC1ラインに、及びゲート
Gは図示しない制御回路に接続され、ツェナーダイオー
ド6のカソードはC1ラインに、アノードはB+ライン
に各々接続される。図示されるように、一次巻線のC2
ライン及びB+ライン間も同様である。なお、プッシュ
プルトランス20のコアー20−1を介した二次側巻線
20−3の出力は、整流素子及びコンデンサーからなる
整流平滑回路40を経由して負荷50に供給される。
FIG. 1 shows a push-pull type booster power supply circuit according to the present invention. In FIG. 1, a primary circuit 100 surrounded by a dotted line includes a primary winding 20-2 of the push-pull transformer 20, a power supply 30 such as a 12 V battery connected to an intermediate lead portion B + of the primary winding, and a power supply for the B + line. An electrolytic capacitor 7 is connected to both ends of the capacitor 30 in parallel with each other in number m (total 2 m). Further, the primary circuit 10
0 indicates that n field effect transistors 5 and zener diodes 6 are connected in parallel between the C1 line and the B + line of the primary winding. The source S of the field effect transistor 5 is connected to the B + line, the drain D is connected to the C1 line, the gate G is connected to a control circuit (not shown), the cathode of the Zener diode 6 is connected to the C1 line, and the anode is connected to the B + line. . As shown, the primary winding C2
The same applies between the line and the B + line. The output of the secondary winding 20-3 via the core 20-1 of the push-pull transformer 20 is supplied to the load 50 via the rectifying and smoothing circuit 40 including a rectifying element and a capacitor.

【0009】合計2m個の電解コンデンサー7は、バッ
テリー電源30の内部インピーダンスを下げると共にノ
イズ吸収を行い、大電流に対応するため2m個に分割さ
れる。実施例では、m=9である。合計2n個のツェナ
ーダイオード6は、スナバー回路を構成する。更に、合
計2n個の電界効果トランジスタ5は、図示しない制御
回路により制御されスイッチングを行う。ツェナーダイ
オード6及び電界効果トランジスタ5は、共に大電流に
対応するため2n個に分割される。実施例では、n=8
である。
A total of 2 m electrolytic capacitors 7 are divided into 2 m capacitors to reduce the internal impedance of the battery power supply 30 and absorb noise, and to cope with large currents. In the embodiment, m = 9. A total of 2n Zener diodes 6 constitute a snubber circuit. Further, a total of 2n field effect transistors 5 are controlled by a control circuit (not shown) to perform switching. Each of the Zener diode 6 and the field effect transistor 5 is divided into 2n pieces to cope with a large current. In the embodiment, n = 8
It is.

【0010】図2及び図3は、電源回路構造を示す。図
2及び図3を合わせて参照し説明する。電源回路を構成
する板状電極構造は、上部板状電極1、一対の中間板状
電極2、3、及び下部板状電極4から構成される。各板
状電極間は、エポキシ樹脂等の電気絶縁シート8により
絶縁され、アクリル樹脂等で形成される複数の絶縁ボル
ト10により一体に固定される。一対の中間板状電極
2、3は、一側部の端子部2−1、3−1が板状電極の
左右に露出するように配置される。
FIGS. 2 and 3 show a power supply circuit structure. A description will be given with reference to FIGS. The plate electrode structure of the power supply circuit includes an upper plate electrode 1, a pair of intermediate plate electrodes 2 and 3, and a lower plate electrode 4. The plate electrodes are insulated by an electric insulating sheet 8 made of epoxy resin or the like, and are integrally fixed by a plurality of insulating bolts 10 made of acrylic resin or the like. The pair of intermediate plate electrodes 2 and 3 are arranged such that the terminal portions 2-1 and 3-1 on one side are exposed to the left and right of the plate electrode.

【0011】電源30は、上部板状電極1を+電位、下
部板状電極4を−電位とするように各端子部1−1及び
4−2に、各端子部の孔部によりネジ等を使用し電気的
及び機械的に接続される。プッシュプルトランス20
は、一対のE型フェライトコアを対向し組み合わせ、中
央部に一次巻線を巻層し、一次巻線の外周部を絶縁シー
ト等で絶縁し、絶縁シート等の上層部に二次巻線を巻層
する構成である。一次巻線の巻き線端部C1、C2は、
各々ネジ止めが可能な端子が電気的及び機械的に接続さ
れる。一次巻線の中間引き出し部B+は、ネジ止めが可
能な端子が電気的及び機械的に接続される。二次巻線の
引き出し部20−3は、図示しない二次側平滑回路に電
気的及び機械的に接続される。プッシュプルトランス2
0は、一次巻線の中間引き出し部B+をボルトにより上
部板状電極1の所定位置に電気的及び機械的に接続さ
れ、一次巻線の一端部C1はネジにより中間板状電極2
の所定位置に電気的及び機械的に接続され、一次巻線の
他端部C2も同様に中間板状電極3の所定位置に電気的
及び機械的に接続される。
The power source 30 is provided with screws and the like in the terminal portions 1-1 and 4-2 so that the upper plate electrode 1 has a positive potential and the lower plate electrode 4 has a negative potential. Used and electrically and mechanically connected. Push-pull transformer 20
Is a pair of E-type ferrite cores facing each other, a primary winding is wound in the center, the outer periphery of the primary winding is insulated with an insulating sheet or the like, and a secondary winding is placed on the upper layer of the insulating sheet or the like. It is a configuration in which the layers are wound. The winding ends C1, C2 of the primary winding are:
Terminals each capable of being screwed are electrically and mechanically connected. The terminal that can be screwed is electrically and mechanically connected to the intermediate lead portion B + of the primary winding. The lead portion 20-3 of the secondary winding is electrically and mechanically connected to a secondary-side smoothing circuit (not shown). Push-pull transformer 2
No. 0 electrically and mechanically connects the intermediate lead portion B + of the primary winding to a predetermined position of the upper plate electrode 1 with a bolt, and one end C1 of the primary winding is connected to the intermediate plate electrode 2 with a screw.
The other end C2 of the primary winding is also electrically and mechanically connected to a predetermined position of the intermediate plate electrode 3 in the same manner.

【0012】図4は上部板状電極1の単体状態を、図5
は一対の中間板状電極2、3の単体状態を、図6は下部
板状電極4の単体状態を各々示す。上部板状電極1は、
一側部に端子部1−1を備えると共に、トランス20の
各一次巻線の端子部B+を電気的及び機械的に固定する
ネジ孔及び端子部C1、C2を挿通する矩形形状の貫通
孔、三個の板状電極1、2、3を一体化固定するための
ネジ孔等の円形及び矩形の貫通孔或いはネジ孔(ネジ
部)を備える。一対の中間板状電極2或いは3は、共に
同一形状であり、一側部に端子部2−1或いは3−1を
備え、同様の貫通孔或いはネジ孔(ネジ部)を備える。
下部板状電極4は、一側部に端子部4−2、及び両側部
に端子部4−1を備え、同様の貫通孔或いはネジ孔(ネ
ジ部)を備える。
FIG. 4 shows a single state of the upper plate-like electrode 1, and FIG.
6 shows a single state of the pair of intermediate plate electrodes 2 and 3, and FIG. 6 shows a single state of the lower plate electrode 4. The upper plate-like electrode 1
A terminal portion 1-1 on one side, a screw hole for electrically and mechanically fixing the terminal portion B + of each primary winding of the transformer 20, and a rectangular through hole through which the terminal portions C1 and C2 are inserted; A circular or rectangular through-hole or screw hole (screw portion) such as a screw hole for integrally fixing the three plate-like electrodes 1, 2, and 3 is provided. The pair of intermediate plate-shaped electrodes 2 or 3 have the same shape, are provided with terminal portions 2-1 or 3-1 on one side, and are provided with similar through holes or screw holes (screw portions).
The lower plate-shaped electrode 4 has a terminal portion 4-2 on one side and a terminal portion 4-1 on both sides, and has a similar through hole or screw hole (screw portion).

【0013】さて、図2及び図3に戻り説明する。先ず
第2図において、板状電極の左右に配置する各端子は、
左右共に図面に向かい上方より、下部板状電極端子4−
1、中間板状電極2或いは3の端子2−1或いは3−1
が交互に配列する。第2図、第3図に示される回路構造
において、各端子及び以後に説明する各電子素子の配置
は、左右対象に配置される(電界効果トランジスタ5の
ソースS、ドレインD、ゲートGの各足配置に起因し
て、図面に向かい、電子素子の配置が左右で上下に端子
1個分ずれているが、本質的な問題ではなく左右対象配
置と見なしうる)。以下の電子素子の配置接続は、第2
図に向かい右側についてのみ説明するが、左側について
も同様である。
Returning to FIG. 2 and FIG. First, in FIG. 2, the terminals arranged on the left and right of the plate-like electrode are:
Left and right lower plate electrode terminals 4-
1. Terminal 2-1 or 3-1 of intermediate plate electrode 2 or 3
Are alternately arranged. In the circuit structures shown in FIGS. 2 and 3, the terminals and the electronic elements described below are arranged symmetrically (the source S, the drain D, and the gate G of the field-effect transistor 5). Due to the foot arrangement, the arrangement of the electronic elements is shifted left and right by one terminal up and down in the drawing, but this is not an essential problem and can be regarded as a left and right symmetric arrangement.) The following electronic device arrangement connection
Only the right side facing the figure will be described, but the same applies to the left side.

【0014】電界効果トランジスタ5は、板状電極の端
子2−1、4−1の外部に配置され、ドレインDが中間
板状電極2の端子2−1に、ソースSが下部板状電極4
の端子4−1にハンダ等により電気的に接続されると共
に機械的にも接続される。ゲートGは、図示しない制御
回路に接続される。ツェナーダイオード6は、端子2−
1及び4−1上に配置され、カソードがドレインDと共
に端子2−1にハンダ付け等により電気的及び機械的に
接続され、アノードはソースSと共に端子4−1に同様
に接続される。電解コンデンサー7は、上部板状電極4
上に配置され、上部板状電極4及び下部板状電極端子4
−1間に同様に接続される。なお、電界効果トランジス
タ5は、冷却のため、シリコン等の電気絶縁性且つ熱導
電性樹脂を介して、ヒートシンクに接触及び/或いは固
定される。
The field effect transistor 5 is disposed outside the terminals 2-1 and 4-1 of the plate electrode, the drain D is connected to the terminal 2-1 of the intermediate plate electrode 2, and the source S is connected to the lower plate electrode 4.
The terminal 4-1 is electrically connected to the terminal 4-1 by solder or the like and mechanically connected. The gate G is connected to a control circuit (not shown). The Zener diode 6 is connected to the terminal 2-
1 and 4-1. The cathode is electrically and mechanically connected to the terminal 2-1 together with the drain D by soldering or the like, and the anode is similarly connected to the terminal 4-1 together with the source S. The electrolytic capacitor 7 has an upper plate electrode 4
An upper plate electrode 4 and a lower plate electrode terminal 4
-1 is similarly connected. The field-effect transistor 5 is contacted and / or fixed to a heat sink via an electrically insulating and thermally conductive resin such as silicon for cooling.

【0015】以上の説明より明らかなように(特に図2
に示されるよう)、三個の板状電極は、左右対象に構成
され、また装着される複数の各電子素子は、電極中央に
配置されるトランス20に対して対象に配置される。従
ってほぼ矩形形状の平板電極上に配置される複数の各電
子素子及びトランスの一次巻線間の幾何学的距離(例え
ば、端子C1と右側の複数の各電子素子間の距離)を最
小とする配置構成である。
As is clear from the above description (particularly in FIG.
), The three plate-shaped electrodes are arranged symmetrically to the left and right, and the plurality of mounted electronic elements are arranged symmetrically with respect to the transformer 20 arranged at the center of the electrodes. Therefore, the geometric distance between the plurality of electronic elements and the primary winding of the transformer arranged on the substantially rectangular plate electrode (for example, the distance between the terminal C1 and the plurality of right electronic elements) is minimized. It is an arrangement configuration.

【0016】[0016]

【発明の効果】以上の説明から明らかなように、請求項
1の発明によれば、プッシュプルタイプ昇圧回路の一次
側電流経路を上部板状電極1、一対の中間板状電極2或
いは3、及び下部板状電極4からなる三個の板状電極
(ブスバー)からなる積層構造とし、左右対象に各電子
素子を配置することにより、一次電流経路が最小とな
り、一次電流回路に付随するインダクタンスが最小とな
り、スイッチング素子のオフ時スパイク電圧が削減さ
れ、スイッチング損失が削減され、効率が改善される。
スナバー回路は、電界効果トランジスタ5のソースS、
ドレインD間にツェナーダイード6を接続するのみで充
分な効果を発揮し、従来構成の抵抗及びダイオードの並
列接続にコンデンサーを直列接続する回路を電界効果ト
ランジスタ5のソースS、ドレインD間に接続する構成
は不要となる。この結果スナバー回路での電力消費は、
著しく削減され、特に低負荷時での一次及び二次回路間
の電力変換効率(全体としてのパフォーマンス)が改善
される。また請求項2の発明によれば、電子素子は幾何
学対象性を持って配置され、インダクタンスを含む回路
解析を容易に行うことが出来、回路設計の自由度が増加
する。更にまた、請求項3の発明によれば、電気絶縁性
材から形成される締結要素により三個の板状電極を固定
することにより、特別な固定要素及び板状電極間の電気
的絶縁を考慮することなく、組み付け作業が容易に行
え、連続製造ラインでの組み付けが可能となる。
As is apparent from the above description, according to the first aspect of the present invention, the primary current path of the push-pull type booster circuit is formed by the upper plate electrode 1, the pair of intermediate plate electrodes 2 or 3, And a three-layered electrode (bus bar) composed of the lower plate-shaped electrode 4 and the left and right symmetrical arrangement of the electronic elements, thereby minimizing the primary current path and reducing the inductance associated with the primary current circuit. This minimizes the switching element off-spike voltage, reduces switching losses, and improves efficiency.
The snubber circuit includes a source S of the field effect transistor 5,
A sufficient effect is obtained only by connecting the Zener diode 6 between the drains D, and a circuit in which a capacitor is connected in series with the parallel connection of the resistor and the diode of the conventional configuration is connected between the source S and the drain D of the field effect transistor 5. This configuration is unnecessary. As a result, the power consumption in the snubber circuit is
Significant reduction is achieved, and the power conversion efficiency (overall performance) between primary and secondary circuits, especially at low loads, is improved. According to the second aspect of the present invention, the electronic elements are arranged with geometric symmetry, and a circuit analysis including an inductance can be easily performed, thereby increasing the degree of freedom in circuit design. Furthermore, according to the third aspect of the present invention, by fixing the three plate-shaped electrodes by the fastening element formed of an electrically insulating material, a special fixing element and electrical insulation between the plate-shaped electrodes are considered. Without the need for assembly, assembly work can be easily performed, and assembly on a continuous production line becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示すプッシュプルタイプ昇
圧電源回路の模式図である。
FIG. 1 is a schematic diagram of a push-pull type booster power supply circuit showing one embodiment of the present invention.

【図2】本発明の一実施例を示す、プッシュプルタイプ
昇圧電源の構成図である。
FIG. 2 is a configuration diagram of a push-pull type step-up power supply showing one embodiment of the present invention.

【図3】図2で示される構成図の部分断面図である。FIG. 3 is a partial sectional view of the configuration diagram shown in FIG. 2;

【図4】上部板状電極の正面図である。FIG. 4 is a front view of an upper plate electrode.

【図5】中間板状電極の正面図である。FIG. 5 is a front view of an intermediate plate electrode.

【図6】下部板状電極の正面図である。FIG. 6 is a front view of a lower plate-like electrode.

【符号の説明】[Explanation of symbols]

100 プッシュプルタイプ昇圧電源回路の一次側回路 1 上部板状電極 2、3 中間板状電極 4 下部板状電極 5 電界効果トランジスタ 6 ツェダイオード 7 電解コンデンサー 8 電気絶縁シート 10 電気絶縁性締結要素 Reference Signs List 100 Primary circuit of push-pull type booster power supply circuit 1 Upper plate electrode 2, 3 Intermediate plate electrode 4 Lower plate electrode 5 Field effect transistor 6 Tse diode 7 Electrolytic capacitor 8 Electrical insulating sheet 10 Electrical insulating fastening element

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 中央にプッシュプルトランス(20)を
配置する領域及び両側部にコンデンサーを装着する端子
部を備えほぼ矩形形状の第一の板状電極(1)、一側部
に電解効果トランジスタ、及びツェナーダイオードを接
続する端子部を備えほぼ矩形形状であり第一の板状電極
のほぼ半分の面積を備える一対の第二の板状電極
(2)、(3)、両側部に電解効果トランジスタ、コン
デンサー、及びツェナーダイオードを接続する端子部を
備えほぼ矩形形状であり第一の板状電極の板上部とほぼ
等しい面積を備える第三の板状電極(4)、及び電気絶
縁シート(8)を備え、第一の板状電極(1)の下部に
一対の第二の板状電極(2)、(3)を配置し、第二の
板状電極の下部に第三の板状電極(4)を配置し、これ
ら第一、第二、第三の各板状電極間は電気絶縁シート
(8)により電気的に絶縁され、締結要素によりこれら
第一、第二、第三の板状電極を一体に固定することを特
徴とする大電流プッシュプルタイプ昇圧回路の板状電極
構造。
1. A substantially rectangular first plate-like electrode (1) having a central area where a push-pull transformer (20) is arranged and terminals for mounting capacitors on both sides, and a field effect transistor on one side. , And a pair of second plate-like electrodes (2) and (3) each having a substantially rectangular shape having a terminal portion for connecting the Zener diode and having an area approximately half that of the first plate-like electrode. A third plate-shaped electrode (4) having a terminal portion for connecting a transistor, a capacitor, and a Zener diode and having a substantially rectangular shape and having an area approximately equal to the upper portion of the first plate-shaped electrode; ), A pair of second plate-like electrodes (2) and (3) are disposed below the first plate-like electrode (1), and a third plate-like electrode is disposed below the second plate-like electrode. (4) is arranged, these first, second and third plates A large current push-pull type booster circuit characterized in that the first, second and third plate-like electrodes are electrically insulated from each other by an electric insulating sheet (8) and the first, second and third plate-like electrodes are integrally fixed by a fastening element. Plate-shaped electrode structure.
【請求項2】 請求項1において、前記第一、第二、第
三の板状電極構造に配置される電子素子は、幾何学的対
象位置に配置されることを特徴とする。
2. The electronic device according to claim 1, wherein the electronic elements arranged in the first, second, and third plate-like electrode structures are arranged at geometrically targeted positions.
【請求項3】 請求項1において、前記第一、第二、第
三の板状電極を固定する締結要素は、電気絶縁性材から
形成されることを特徴とする。
3. The device according to claim 1, wherein the fastening element for fixing the first, second, and third plate-shaped electrodes is formed of an electrically insulating material.
JP2001096620A 2001-03-29 2001-03-29 High current push-pull type booster circuit Expired - Fee Related JP4346253B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001096620A JP4346253B2 (en) 2001-03-29 2001-03-29 High current push-pull type booster circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001096620A JP4346253B2 (en) 2001-03-29 2001-03-29 High current push-pull type booster circuit

Publications (2)

Publication Number Publication Date
JP2002300781A true JP2002300781A (en) 2002-10-11
JP4346253B2 JP4346253B2 (en) 2009-10-21

Family

ID=18950518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001096620A Expired - Fee Related JP4346253B2 (en) 2001-03-29 2001-03-29 High current push-pull type booster circuit

Country Status (1)

Country Link
JP (1) JP4346253B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62296770A (en) * 1986-04-08 1987-12-24 エムハート インコーポレーテッド Mode changing source
JPH05268767A (en) * 1992-03-17 1993-10-15 Toyota Autom Loom Works Ltd Push-pull dc-dc converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62296770A (en) * 1986-04-08 1987-12-24 エムハート インコーポレーテッド Mode changing source
JPH05268767A (en) * 1992-03-17 1993-10-15 Toyota Autom Loom Works Ltd Push-pull dc-dc converter

Also Published As

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