JPS63157677A - Bridge type inverter - Google Patents
Bridge type inverterInfo
- Publication number
- JPS63157677A JPS63157677A JP61303349A JP30334986A JPS63157677A JP S63157677 A JPS63157677 A JP S63157677A JP 61303349 A JP61303349 A JP 61303349A JP 30334986 A JP30334986 A JP 30334986A JP S63157677 A JPS63157677 A JP S63157677A
- Authority
- JP
- Japan
- Prior art keywords
- side wiring
- wiring conductor
- semiconductor switching
- mos
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000012212 insulator Substances 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 239000011889 copper foil Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Landscapes
- Inverter Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はブリッジ形インバータ装置に係わり、更に詳し
くは小形化、高効率化、低価格化を可能にした半導体ス
イッチング素子を用いたインバータ装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bridge type inverter device, and more particularly to an inverter device using semiconductor switching elements that enables miniaturization, high efficiency, and low cost. .
周知の通り、近年パワーエレクトロニクス、半導体スイ
ッチング素子の進歩により、インバータ装置も高周波、
大電力化が進められ、従来の真空管式高周波電源の分野
にも半導体スイッチング素子を用いたインバータ式高周
波電源が採用されてきている。As is well known, in recent years, advances in power electronics and semiconductor switching elements have led to inverter devices that operate at high frequencies and
BACKGROUND OF THE INVENTION As power generation continues to increase, inverter-type high-frequency power supplies using semiconductor switching elements are being adopted in the field of conventional vacuum tube-type high-frequency power supplies.
この半導体スイッチング素子を用いたインバータ式高周
波電源の１つの例を挙げれば、第３図の通りである。こ
の第３図の例は、半導体スイッチング素子であるＭＯＳ
−ＦＥＴを用いたブリッジ形インバータ装置を簡略的
に示したもので、即ち通常ＭＯ５・ＦＥＴに接続されて
いる還流ダイオード、逆阻止ダイオード、及び電圧形イ
ンバータ装置に於ける直流電源バイパスコンデンサ、電
流形インバータ装置に於ける直列リアクトル等を省いて
示したもので、直流電源１に接続された４組のＭＯＳ・
ＦＥＴ２〜５から成り、ＭＯＳ −ＦＥＴ２，５と、Ｍ
ＯＳ −ＦＥＴ３．４は交互にオン・オフ動作を行ない
交流出力端子６．７に交流電力を発生するものである。An example of an inverter type high frequency power supply using this semiconductor switching element is shown in FIG. The example shown in Fig. 3 is a MOS, which is a semiconductor switching element.
- This is a simplified diagram of a bridge type inverter device using FETs, that is, a freewheeling diode, a reverse blocking diode, which is normally connected to an MO5 FET, and a DC power supply bypass capacitor in a voltage source inverter device, and a current type This figure excludes the series reactor in the inverter device, and shows four sets of MOS/MOS connected to the DC power supply 1.
Consists of FETs 2 to 5, MOS-FETs 2 and 5, and M
The OS-FET 3.4 alternately performs on/off operations to generate AC power at the AC output terminal 6.7.
所がこの種タイプのインバータ装置に於いては、ＭＯＳ
−ＦＥＴを高速でオン・オフ動作させると、電圧形ブ
リッジインバータ装置では主に配線８〜１１．１４〜１
９の浮遊インダクタンスＬに蓄えられたエネルギーによ
るサージ電圧ｅＬ（ｅｔ＝Ｌ＠ｄｉ／ｄｔ）がＭＯ３Φ
ＦＥＴの両端に発生し、又電流形ブリッジインバータ装
置では主に配線９〜１８の浮遊インダクタンスＬによる
サージ電圧が同様に発生する。そしてこのサージ電圧が
短時間でもＭＯＳ ＠ＦＥＴの耐電圧値を越えると、Ｍ
ＯＳ・ＦＥＴは劣化あるいは破壊に至る場合がある。そ
こで従来は、第３図インバータ装置に更に大容量のスナ
バ回路を各ＭＯ３−ＦＥＴの両端に並列に設け、サージ
電圧を吸収するようにしていた。However, in this type of inverter device, MOS
- When FETs are operated on and off at high speed, in a voltage bridge inverter device, the main wires 8 to 11, 14 to 1
The surge voltage eL (et=L@di/dt) due to the energy stored in the stray inductance L of 9 is MO3Φ
A surge voltage is generated at both ends of the FET, and in the current source bridge inverter device, a surge voltage is also generated mainly due to the stray inductance L of the wiring lines 9 to 18. If this surge voltage exceeds the withstand voltage value of MOS @FET even for a short time, M
The OS/FET may deteriorate or be destroyed. Therefore, in the past, a snubber circuit with a larger capacity was provided in parallel to both ends of each MO3-FET in the inverter device shown in FIG. 3 to absorb the surge voltage.
このように大容量のスナバ回路を設けた半導体スイッチ
ング素子を用いたインバータ装置では、サージ電圧発生
抑制手段として、配線の浮遊インダクタンスに蓄えられ
たエネルギーによるサージ電圧をスナバ回路と半導体ス
イッチング素子に吸収消費させる手段をとっているので
次のような問題点があった。In an inverter device that uses semiconductor switching elements equipped with a large-capacity snubber circuit, the surge voltage generated by the energy stored in the stray inductance of the wiring is absorbed and consumed by the snubber circuit and the semiconductor switching element as a means of suppressing surge voltage generation. However, the following problems arose as the method was used to
即ち■上記吸収消費されるエネルギーはブリッジ形イン
バータ装置の動作周波数に比例して増大するので、ブリ
ッジ形インバータ装置を高周波で動作させた場合、損失
が大きくなる。従ってインバータ装置の効率を大きく低
下させる。又■大容量のスナバ回路を必要とする分イン
バータ装置全体の価格が高価となり、低価格化に障害と
なる。That is, (1) the absorbed and consumed energy increases in proportion to the operating frequency of the bridge type inverter device, so when the bridge type inverter device is operated at a high frequency, the loss increases. Therefore, the efficiency of the inverter device is greatly reduced. In addition, the need for a large-capacity snubber circuit increases the price of the entire inverter device, which becomes an obstacle to price reduction.
更に■スナバ回路の取付スペースの為に小形化が難しく
なる等々である。Furthermore, it becomes difficult to miniaturize the snubber circuit due to the installation space.
従って本発明の目的とする所は、サージ電圧発生抑制手
段としてスナバ回路を用いることなく、即ちサージ電圧
発生の原因である浮遊インダクタンスの発生を小ならし
め、もってサージ電圧の発生を抑制して半導体スイッチ
ング素子を保護することにより、もって高効率、安価、
小型化が図れるブリッジ形インバータ装置を提供するに
ある。Therefore, an object of the present invention is to reduce the generation of stray inductance, which is a cause of surge voltage generation, without using a snubber circuit as a means for suppressing surge voltage generation, thereby suppressing the generation of surge voltage and By protecting the switching elements, high efficiency, low cost,
An object of the present invention is to provide a bridge type inverter device that can be downsized.
上記目的を達成する為に本発明は次の技術的手段を有す
るものである。即ち本発明はブリッジ形に接続された４
組の半導体スイッチング素子を具備してなるブリッジ形
インバータ装置に於いて；前記半導体スイッチング素子
の各々に対して接続される直流側配線導体と交流側配線
導体間に絶縁物を介在させ、且つ半導体スイッチング素
子接続部を除いて相互に近接配線することを特徴とする
ブリッジ型インバータ装置である。In order to achieve the above object, the present invention has the following technical means. That is, the present invention provides four
In a bridge type inverter device comprising a set of semiconductor switching elements; an insulator is interposed between a DC side wiring conductor and an AC side wiring conductor connected to each of the semiconductor switching elements; This is a bridge type inverter device characterized in that the wiring is close to each other except for the element connection portions.
上記構成によると、各半導体スイッチング素子に於ける
直流側配線導体と交流側配線導体に流れる電流は互いに
反対方向となり、而も直流側配線導体と交流側配線導体
を絶縁物を介して近接配線しているから、浮遊インダク
タンスが夫々打消されるので、浮遊インダクタンスを極
力抑えることができ、それ故にサージ電圧の発生を抑制
できる。従ってスナバ回路の如き回路を要することがな
いから、インバータ装置の高効率化、小型化。According to the above configuration, the currents flowing in the DC side wiring conductor and the AC side wiring conductor in each semiconductor switching element are in opposite directions, and the DC side wiring conductor and the AC side wiring conductor are wired close to each other through an insulator. Since the stray inductances are canceled out, the stray inductances can be suppressed as much as possible, and therefore the generation of surge voltage can be suppressed. Therefore, since there is no need for a circuit such as a snubber circuit, the inverter device can be made more efficient and smaller.
低価格化が可能とされる。It is believed that lower prices are possible.
次に添付図面第１図、第２図に従い本発明の好適な実施
例を詳細上説明する。Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings FIGS. 1 and 2. FIG.
第１図は斜視図、第２図は１つのＭＯＳ・ＦＥＴに着目
し、それに接続される直流側配線導体と交流側配線導体
の相互配線関係及びそれに基く浮遊インダクタンスの発
生抑制メカニズムを説明する為の説明図である。Figure 1 is a perspective view, and Figure 2 focuses on one MOS/FET to explain the mutual wiring relationship between the DC side wiring conductor and AC side wiring conductor connected to it, and the mechanism for suppressing the generation of stray inductance based on this. FIG.
第１図に於ける附号１〜１９は、第３図で示した従来技
術の附号１−１９と各々対応し、同−附号は同一構成要
素を示している。Numbers 1 to 19 in FIG. 1 correspond to numbers 1 to 19 of the prior art shown in FIG. 3, respectively, and the numbers 1 to 19 indicate the same components.
即ち、１は直流電源、２〜５は半導体スイッチング素子
であるＭＯＳ・ＦＥＴ、６，７は交流出力端子、８〜１
９は配線を各々示し、上記配線の内、９．１０及び１７
．１８は直流側配線導体を示し、１１、１４．１５．１
８は交流側配線導体を示している。That is, 1 is a DC power supply, 2 to 5 are MOS/FET semiconductor switching elements, 6 and 7 are AC output terminals, and 8 to 1 are
9 indicates each wiring, and among the above wirings, 9.10 and 17
．． 18 indicates the DC side wiring conductor, 11, 14.15.1
8 indicates an AC side wiring conductor.
以上は従来一般のＭＯＳ−ＦＥＴを用いたブリッジ形イ
ンバータ装置を示し、本発明は首記した目的を達成する
為に次のようにしたものである。 即ち、１つのＭＯＳ
・ＦＥＴ２に着目した場合、この直流側配線導体９と交
流側配線導体１１の間に絶縁物を介在させ且つ互いに近
接配置するものであり、又もう１つのＭＯＳ ＠ＦＥＴ
３に着目した場合も、この直流側配線導体１０と交流側
配線導体１４の間に絶縁物を介在させ且つ互いに近接配
置するものであり、同様にＭＯＳ・ＦＥＴ４に着目した
場合、その直流側配線１７と交流側配線１５の間に絶縁
物を介在させ且つ互いに近接配置するものであり、ＭＯ
Ｓ・ＦＥＴ５に着目した場合、その直流側配線導体１８
と交流側配線導体１Ｂの間に絶縁物を介在させ且つ直接
配置するものである。The above describes a bridge type inverter device using a conventional general MOS-FET, and the present invention is made as follows to achieve the above-mentioned object. That is, one MOS
- When focusing on the FET 2, an insulator is interposed between the DC side wiring conductor 9 and the AC side wiring conductor 11 and they are placed close to each other, and is another MOS @FET.
3, an insulator is interposed between the DC side wiring conductor 10 and the AC side wiring conductor 14, and they are placed close to each other. Similarly, when focusing on the MOS/FET 4, the DC side wiring 17 and the AC side wiring 15, an insulator is interposed between them and they are placed close to each other.
When focusing on the S-FET 5, its DC side wiring conductor 18
An insulator is interposed between the AC side wiring conductor 1B and the AC side wiring conductor 1B, and the insulation material is directly placed between the AC side wiring conductor 1B and the AC side wiring conductor 1B.
この場合、各ＭＯＳ −ＦＥＴの接続部を除いて近接配
線される。これらを可能にする為に本実施例では、両面
プリント回路基板２Ｇ 、 ２１を準備する。In this case, the MOS-FETs are wired in close proximity except for the connection portions of the MOS-FETs. In order to make these possible, double-sided printed circuit boards 2G and 21 are prepared in this embodiment.
一方の両面プリント回路基板２０は片側の銅ハク２０ａ
、絶縁物２０ｂ、もう片側の銅ハク２Ｑｃより成り、同
様に他方の両面プリント回路基板２１は片側の銅ハク２
１ａ、絶縁物２１ｂ、もう片側の銅ハク２１Ｃより成る
。そして、一方の両面プリント回会路基５板２０（７）
片側の銅ハク２ＱａにＭＯＳ ＠ＦＥＴ２及び３の各々
の直流側端子を接続し、もう一方の片側の銅ハク２Ｑｃ
にこれらＭＯＳ・ＦＥＴ２及び３の各々の交流側端子を
スルーホールを通して接続する。これによって、ＭＯ３
φＦＥＴ２及び３に関しては、それらの直流側配線導体
９又は１０が両面プリント回路基板２０の片側の銅ハタ
２０ａによって構成され、それらの交流側配線導体１１
又は１４が両面プリント回路基板２０のもう片側の銅ハ
ク２０ｃによって構成され、而もこれらの間には絶縁物
２０ｂが介在し、且つ銅ハク２０ａと２０ｃが近接して
いることにより上記直流側配線導体９又は１０と交流側
配線導体１１又は１４とが近接するものでる。One double-sided printed circuit board 20 has a copper plate 20a on one side.
, an insulator 20b, and a copper foil 2Qc on the other side.Similarly, the other double-sided printed circuit board 21 is made of a copper foil 2Qc on one side.
1a, an insulator 21b, and a copper plate 21C on the other side. And one double-sided printed circuit board 5 board 20 (7)
Connect the DC side terminals of each of MOS @FETs 2 and 3 to the copper plate 2Qa on one side, and connect the copper plate 2Qc on the other side.
The AC side terminals of each of these MOS-FETs 2 and 3 are connected through through holes. By this, M.O.3
Regarding φFETs 2 and 3, their DC side wiring conductor 9 or 10 is constituted by the copper group 20a on one side of the double-sided printed circuit board 20, and their AC side wiring conductor 11
Or, 14 is constituted by the copper foil 20c on the other side of the double-sided printed circuit board 20, and since the insulator 20b is interposed between them, and the copper foils 20a and 20c are close to each other, the above-mentioned DC side wiring The conductor 9 or 10 and the AC side wiring conductor 11 or 14 are close to each other.
同じように、他方の両面プリント回路基板２１の片側の
銅ハタ２１ａにＭＯＳ −ＦＥＴ４及び５の各々の直流
側端子を接続し、もう一方の片側の銅ハク２１ｃに、こ
れらＭＯＳ −ＦＥＴ４及び５の各々の交流、側端子を
スルーホールを通して接続する。Similarly, the DC side terminals of each of the MOS-FETs 4 and 5 are connected to the copper plate 21a on one side of the other double-sided printed circuit board 21, and the DC side terminals of these MOS-FETs 4 and 5 are connected to the copper plate 21c on the other side. Connect each AC side terminal through a through hole.
これによってＭＯＳ・ＦＥＴ４及び５に関しては、それ
らの直流側配線導体１７又は１８が両面プリント回路基
板２１の片側の銅ハク２１ａによって構成され、それら
の交流側配線導体１５又は１６が両面プリント回路基板
２１のもう片側の銅ハタ２１ｃによって構成され、而も
これらの間には絶縁物２１ｂが介在し、且つ銅ハク２１
ａと２１ｃが近接していることにより上記直流側配線導
体１７又は１８と交流側配線導体１５又は１６とが近接
するものである。As a result, regarding the MOS/FETs 4 and 5, their DC side wiring conductor 17 or 18 is constituted by the copper foil 21a on one side of the double-sided printed circuit board 21, and their AC side wiring conductor 15 or 16 is constituted by the double-sided printed circuit board 21. It is composed of the copper plate 21c on the other side, with an insulator 21b interposed between them, and the copper plate 21c.
Since a and 21c are close to each other, the DC side wiring conductor 17 or 18 and the AC side wiring conductor 15 or 16 are close to each other.
而して上記銅ハク２０ｃ、２１ｃは、その中央に於ける
切断部で導電体ブスバー２２ 、２３により機械的且つ
電気的に接続されるもので、この導電体ブスバー２２及
び２３は交流側配線導体１１．１４．１５．１８の一部
を兼ねると共に交流出力側配線１２．１３と交流出力端
子６．７を構成しているものである。The copper strips 20c and 21c are mechanically and electrically connected by conductive busbars 22 and 23 at the cut point in the center, and these conductive busbars 22 and 23 are connected to the AC side wiring conductor. 11, 14, 15, and 18, and constitutes the AC output side wiring 12.13 and the AC output terminal 6.7.
上記構成に基づくと、各ＭＯ５＠ＦＥＴに於ける直流側
配線導体と交流側配線導体に流れる電流は互いに反対方
向となる。第２図に於けるＭＯＳ−ＦＥＴに着目してこ
れを述べると、ＭＯ３＠ＦＥＴに流れる電流ｉは破線で
示す経路となるので、図から明らかにように直流側配線
導体９と交流側配線導体１１に流れる電流は互いに反対
方向となり、而も直流側配線導体９と交流側配線導体１
１は絶縁物を介して近接配置されているから、浮遊イン
ダクタンスは相互に打消しあって微少となる。それ故に
サージ電圧の発生を極力制御できるものである。Based on the above configuration, the currents flowing through the DC side wiring conductor and the AC side wiring conductor in each MO5@FET are in opposite directions. Describing this by focusing on the MOS-FET in Figure 2, the current i flowing through the MO3@FET follows the path shown by the broken line, so as is clear from the figure, the DC side wiring conductor 9 and the AC side wiring conductor The currents flowing through 11 are in opposite directions to each other, and the DC side wiring conductor 9 and the AC side wiring conductor 1
1 are placed close to each other with an insulator in between, so the stray inductances cancel each other out and become very small. Therefore, the generation of surge voltage can be controlled as much as possible.
而して上記実施例に於いては、プリント回路基板を用い
た例を示したが、銅板の如き板状導電体と絶縁板を用い
て上記のように構成してもよく、この場合には板状導電
体をＭＯＳ −ＦＥＴのような半導体スイッチング素子
の放熱板機能を兼用させることもできる。又、上記実施
例に於いては。In the above embodiment, an example using a printed circuit board was shown, but the above structure may also be constructed using a plate-shaped conductor such as a copper plate and an insulating plate. The plate-shaped conductor can also serve as a heat sink for a semiconductor switching element such as a MOS-FET. Also, in the above embodiment.
導電体ブスバー２２ 、２３間に何等絶縁物を介在させ
ない例を示したが、絶縁物を介在させ且つそれらを互い
に近接配置すれば更に浮遊インダクタンスを減少できる
。Although an example has been shown in which no insulating material is interposed between the conductor bus bars 22 and 23, stray inductance can be further reduced by interposing an insulating material and arranging them close to each other.
加えて、上記の実施例では導電体ブスバーの片端のみを
引出し交流出力端子６．７としたが、両端を引き出し出
力端子を複数として用いてもよく、この低導電体ブスバ
ーの代りに銅板の如き板状導電体を用いてもよいもので
ある。In addition, in the above embodiment, only one end of the conductor busbar is drawn out to provide an AC output terminal 6.7, but both ends may be drawn out and a plurality of output terminals may be used. A plate-shaped conductor may also be used.
更に、本発明を半導体スイッチング素子を用いた電圧形
のブリッジインバータ装置に適用する場合には、上記実
施例に於ける両面プリント回路基板２０．２１の近くに
直流電源バイパスコンデンサを１ケ所以上設け、プラス
側配線導体２０ａとマイナス側配線導体２１ａ間に電気
的に接続することで、直流電源ｌからインバータ回路へ
の配線８．１９の浮遊インダクタンスを等価回路的に減
少させることもでき、同じように半導体スイッチング素
子を複数並列に接続して使用する場合、両面プリント基
板２０．２１を貫通する穴あるいは切欠きを開け、これ
を通して直流電源バイパスコンデンサに電気的に接続し
ても同じ効果を生ずるものである。Furthermore, when the present invention is applied to a voltage type bridge inverter device using semiconductor switching elements, one or more DC power supply bypass capacitors are provided near the double-sided printed circuit board 20, 21 in the above embodiment, By electrically connecting between the positive side wiring conductor 20a and the negative side wiring conductor 21a, the stray inductance of the wiring 8.19 from the DC power supply l to the inverter circuit can be reduced in terms of an equivalent circuit, and in the same way. When using multiple semiconductor switching elements connected in parallel, the same effect can be obtained by making a hole or cutout through the double-sided printed circuit board 20, 21 and electrically connecting it to the DC power supply bypass capacitor through this. be.
以上詳述した如くこの発明によれば、サージ電圧発生抑
制手段としてスナバ回路を用いることなく、即ちサージ
電圧発生の原因である浮遊インダクタンスの発生を小な
らしめ、もってサージ電圧の発生を抑制して半導体スイ
ッチング素子を保護できるので、高効率、安価、小型化
が図れるブリッジ形インバータ装置を提供できるもので
ある。As detailed above, according to the present invention, the generation of the surge voltage can be suppressed by reducing the generation of stray inductance, which is the cause of the generation of the surge voltage, without using a snubber circuit as a means for suppressing the generation of the surge voltage. Since the semiconductor switching elements can be protected, it is possible to provide a bridge type inverter device that is highly efficient, inexpensive, and compact.
【図面の簡単な説明】
添付図面第１図、第２図は本発明の実施例を示し、第１
図は斜視図、第２図は１つのＭＯＳ・ＦＥＴに着目し、
それに接続される直流側配線導体と交流側配線導体の相
互配線関係及びそれに甚く浮遊インダクタンスの発生制
御メカニズムを説明する為の図、及び第３図は従来技術
であり、図中１は直流電源、２〜５はＭＯＳ−ＦＥＴ、
６．７は交流出力端子、 ８，１９は直流電源ｌからイ
ンバータ回路への配線、 ９ 、１０．１７．１８は
直流側配線導体、 １１．１４，１５．１６は交流側配
線導体、 １２．１３は交流出力側配線、 ２０．２１
は両面プリント回路基板、 ２０ａ 、 ２Ｑｃ 、
２１ａ 、 ２１ｃは銅ハタ、 ２０ｂ、２１ｂは絶縁
物、２２ 、２３は導電体ブスバーを各々示している。
ヌ １ δ
２１医
メ ２７７７
粛 ３８[BRIEF DESCRIPTION OF THE DRAWINGS] The attached drawings, FIGS. 1 and 2, show embodiments of the present invention.
The figure is a perspective view, and the second figure focuses on one MOS/FET.
A diagram for explaining the mutual wiring relationship between the DC side wiring conductor and the AC side wiring conductor connected thereto, and the mechanism for controlling the generation of stray inductance, and Figure 3 are related to the prior art, and 1 in the figure is a DC power source. , 2 to 5 are MOS-FETs,
6.7 is an AC output terminal, 8 and 19 are wiring from the DC power supply l to the inverter circuit, 9, 10.17.18 are DC side wiring conductors, 11.14 and 15.16 are AC side wiring conductors, 12. 13 is AC output side wiring, 20.21
is a double-sided printed circuit board, 20a, 2Qc,
21a and 21c are copper wires, 20b and 21b are insulators, and 22 and 23 are conductor busbars, respectively. Nu 1 δ 21 Medical Me 2777 Su 38
Claims (1)
を具備してなるブリッジ形インバータ装置に於いて；前
記半導体スイッチング素子の各々に対して接続される直
流側配線導体と交流側配線導体間に絶縁物を介在させ、
且つ半導体スイッチング素子接続部を除いて相互に近接
配線することを特徴とするブリッジ型インバータ装置。In a bridge type inverter device comprising four sets of semiconductor switching elements connected in a bridge configuration; an insulator is provided between the DC side wiring conductor and the AC side wiring conductor connected to each of the semiconductor switching elements; intervene,
Furthermore, a bridge type inverter device is characterized in that the wirings are arranged in close proximity to each other except for the semiconductor switching element connecting portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61303349A JPS63157677A (en) | 1986-12-19 | 1986-12-19 | Bridge type inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61303349A JPS63157677A (en) | 1986-12-19 | 1986-12-19 | Bridge type inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63157677A true JPS63157677A (en) | 1988-06-30 |
Family
ID=17919905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61303349A Pending JPS63157677A (en) | 1986-12-19 | 1986-12-19 | Bridge type inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63157677A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001178151A (en) * | 1999-12-20 | 2001-06-29 | Murata Mfg Co Ltd | Capacitor module for inverter, inverter and capacitor module |
| JP2001352767A (en) * | 2000-06-07 | 2001-12-21 | Toshiba Corp | Power unit for power converter |
| WO2002028155A1 (en) * | 2000-09-29 | 2002-04-04 | American Superconductor Corporation | Low-inductance connector for printed-circuit board |
| WO2002015651A3 (en) * | 2000-08-11 | 2002-08-29 | American Superconductor Corp | Low inductance transistor module with distributed bus |
| JP2008054495A (en) * | 2006-08-25 | 2008-03-06 | Semikron Elektronik Gmbh & Co Kg | Low inductance power semiconductor module for power circuit subjected to current application |
| KR20170090135A (en) * | 2016-01-28 | 2017-08-07 | 엘지이노텍 주식회사 | Inverter package |
| WO2017140579A1 (en) * | 2016-02-18 | 2017-08-24 | Siemens Aktiengesellschaft | Vertical structure of a half-bridge |
| WO2020078967A1 (en) * | 2018-10-17 | 2020-04-23 | Mahle International Gmbh | Inverter device having a half bridge module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59153476A (en) * | 1983-02-17 | 1984-09-01 | Fuji Electric Co Ltd | Inverter device |
| JPS6125092B2 (en) * | 1978-01-26 | 1986-06-13 | Komatsu Mfg Co Ltd |
-
1986
- 1986-12-19 JP JP61303349A patent/JPS63157677A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6125092B2 (en) * | 1978-01-26 | 1986-06-13 | Komatsu Mfg Co Ltd | |
| JPS59153476A (en) * | 1983-02-17 | 1984-09-01 | Fuji Electric Co Ltd | Inverter device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001178151A (en) * | 1999-12-20 | 2001-06-29 | Murata Mfg Co Ltd | Capacitor module for inverter, inverter and capacitor module |
| US6570774B1 (en) | 1999-12-20 | 2003-05-27 | Murata Manufacturing Co., Ltd. | Capacitor module for use in inverter, inverter, and capacitor module |
| JP2001352767A (en) * | 2000-06-07 | 2001-12-21 | Toshiba Corp | Power unit for power converter |
| WO2002015651A3 (en) * | 2000-08-11 | 2002-08-29 | American Superconductor Corp | Low inductance transistor module with distributed bus |
| US6459605B1 (en) | 2000-08-11 | 2002-10-01 | American Superconductor Corp. | Low inductance transistor module with distributed bus |
| WO2002028155A1 (en) * | 2000-09-29 | 2002-04-04 | American Superconductor Corporation | Low-inductance connector for printed-circuit board |
| US6472613B1 (en) | 2000-09-29 | 2002-10-29 | American Superconductor Corporation | Low-inductance connector for printed-circuit board |
| JP2008054495A (en) * | 2006-08-25 | 2008-03-06 | Semikron Elektronik Gmbh & Co Kg | Low inductance power semiconductor module for power circuit subjected to current application |
| KR20170090135A (en) * | 2016-01-28 | 2017-08-07 | 엘지이노텍 주식회사 | Inverter package |
| WO2017140579A1 (en) * | 2016-02-18 | 2017-08-24 | Siemens Aktiengesellschaft | Vertical structure of a half-bridge |
| WO2020078967A1 (en) * | 2018-10-17 | 2020-04-23 | Mahle International Gmbh | Inverter device having a half bridge module |
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