JP2002272136A - Interconnected system inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interconnected system inverter in which utility of a reactor is improved. SOLUTION: This interconnected system converter, which supplies power from a DC power source 11 to a system 17, is equipped with a step-up and step-down converter 13 for converting a DC voltage supplied from the DC power source 11 into a plusating current, and an inverter 15 for converting the plusating current into AC. The converter 13 is provided with a first transistor Q1 and a second transistor Q2, which are connected in series between both terminals of the DC power source 11, a third transistor Q3 and a fourth transistor Q4 which are connected in series between input terminals of the inverter 15, and a reactor L1 which is connected between a node of the first and second transistors Q1, Q2 and a node of the third and fourth transistors Q3, Q4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a grid-connected inverter, and more particularly, to a grid-connected inverter with improved reactor utilization efficiency.

[0002]

2. Description of the Related Art Conventionally, a grid-connected inverter is known as a circuit for linking DC power supplied from a DC power supply such as a solar cell or a fuel cell to a system and converting the AC power into AC power. As an example of a grid-connected inverter, see JP-A-200
No. 0-152651.

FIG. 3 is a circuit diagram of a conventional grid-connected inverter disclosed in the publication.

[0004] As shown in FIG. 3, the conventional system interconnection inverter described in the publication discloses a boost converter 2 for boosting a DC voltage supplied from an input power supply 1 and shaping a waveform, and a boost converter. , An inverter 4 for shaping the output current Io into a sine wave, and a filter 5 for smoothing the output voltage.
And a control circuit 6 for controlling the operation of the boost converter 2 and the inverter 4. The control circuit 6 switches the boost converter 2 at a high frequency when the voltage of the input power supply 1 is lower than the system voltage. At the same time, the inverter 4 is switched at a low frequency in accordance with the polarity of the system voltage, and when the voltage of the input power supply 1 is higher than the system voltage, the switching of the boost converter 2 is stopped and the inverter 4 is switched at a high frequency. .

Thus, when the voltage of the input power supply 1 is lower than the system voltage, boosting and waveform shaping are performed by the boost converter 2, and when the voltage of the input power supply 1 is higher than the system voltage, the inverter By 4, waveform shaping is performed.

At this time, when the voltage of input power supply 1 is lower than the system voltage, the reactor included in boost converter 2 functions substantially as a smoothing reactor, and the voltage of input power supply 1 is higher than the system voltage. In
The reactor included in the filter 5 functions substantially as a smoothing reactor. Therefore, both the reactor included in boost converter 2 and the reactor included in filter 5 are required to have a sufficient size required for the smoothing reactor.

[0007]

However, in the above-described conventional system interconnection inverter, when the voltage of input power supply 1 is lower than the system voltage, the reactor included in boost converter 2 is substantially a smooth reactor. Therefore, the reactor included in the filter 5 may be a very small reactor, and may be deleted in some cases. Therefore, when the voltage of the input power supply 1 is lower than the system voltage, the reactor included in the filter 5 has an unnecessarily large size or may be useless in some cases.

On the other hand, when the voltage of input power supply 1 is higher than the system voltage, the reactor included in filter 5 functions substantially as a smoothing reactor,
The reactor included in boost converter 2 may be deleted. Therefore, when the voltage of input power supply 1 is higher than the system voltage, it can be said that the reactor included in boost converter 2 is useless.

As described above, in the above-described conventional grid-connected inverter, the utilization efficiency of the reactor is poor.
In addition to an increase in product cost and an increase in the size of the circuit, there is a problem that the loss generated in each reactor is large.

Therefore, an object of the present invention is to provide a grid-connected inverter with improved reactor utilization efficiency.

[0011]

SUMMARY OF THE INVENTION The object of the present invention is as follows.
A system interconnection inverter that supplies power from a DC power supply to a system, wherein the converter converts a DC voltage supplied from the DC power supply into a pulsating current, and converts the pulsating current supplied from the converter into an AC current. An inverter, wherein the converter comprises: first and second transistors connected in series between both ends of the DC power supply; and third and fourth transistors connected in series between input terminals of the inverter. , And a reactor connected between the nodes of the first and second transistors and the nodes of the third and fourth transistors.

According to the present invention, when the DC voltage is higher or lower than the absolute value of the voltage of the system, the nodes of the first and second transistors and the third and fourth nodes are connected.
Since the reactor connected between the node of the transistor of the above substantially functions as a smoothing reactor,
High utilization efficiency of reactor. Therefore, not only can the product cost be reduced, but also the circuit can be miniaturized and the conversion efficiency can be increased.

In a preferred embodiment of the present invention, when the DC voltage is higher than the absolute value of the voltage of the system, the first and second transistors are PWM-driven, and the DC voltage is the voltage of the system. If the absolute value of the third and fourth transistors is lower than the absolute value, a control circuit for driving the third and fourth transistors by PWM is further provided.

In a further preferred aspect of the present invention, when the DC voltage is higher than the absolute value of the voltage of the system, the control circuit turns on one of the third and fourth transistors and turns off the other. When the DC voltage is lower than the absolute value of the voltage of the system, one of the first and second transistors is turned on and the other is turned off.

In a further preferred aspect of the present invention, the control circuit compares the control signal wave generated based on at least a value of a current flowing through the reactor with the first and second carrier waves. First to fourth
ON / OFF of the transistor is controlled.

In a further preferred aspect of the present invention, the first carrier has a waveform in which a DC component having substantially the same amplitude as that of the second carrier is superimposed on the second carrier.

In a further preferred aspect of the present invention, the control circuit controls on / off of the third and fourth transistors by comparing the control signal wave with the first carrier wave, By comparing the control signal wave with the second carrier wave, the first and second carrier waves are compared.
ON / OFF of the transistor is controlled.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the present invention will be described in detail. The grid-connected inverter according to the present embodiment is a circuit that converts DC power supplied from a DC power supply to AC power by linking the DC power to the system, and is not particularly limited. Examples of the DC power supply include a solar cell and a fuel cell. Power supply can be used.

FIG. 1 is a circuit diagram of a system interconnection inverter 10 according to a preferred embodiment of the present invention.

As shown in FIG. 1, a system interconnection inverter 10 according to this embodiment includes an input capacitor 12 connected between both ends of a DC power supply 11 and a DC power supply 11 connected between both ends of the DC power supply 11. A step-up / step-down converter 13 for stepping up or stepping down the voltage and shaping the waveform, an intermediate capacitor 14 connected between the output terminals of the step-up / step-down converter 13, and an output current Io An inverter 15 for switching the polarity so as to form a sine wave;
And a control circuit 16 for controlling the operation of the inverter 5. An output of the inverter 15 is connected to a system power supply 17.

The buck-boost converter 13 includes a first transistor Q1 and a second transistor Q2 connected in series.
And a second arm consisting of a third transistor Q3 and a fourth transistor Q4 connected in series.
And an energy storage reactor L1 connected between the nodes of the first and second transistors Q1, Q2 and the nodes of the third and fourth transistors Q3, Q4.
And diodes D1 to D4 connected in parallel to the first to fourth transistors Q1 to Q4, respectively. Figure 1
As shown in FIG. 1, the first and second transistors Q1,
The first arm composed of Q2 is connected between both ends of the DC power supply 11. Further, the third and fourth transistors Q
The second arm consisting of Q3 and Q4 is a buck-boost converter 1
3 output terminal. Further, the buck-boost converter 13 is provided with a reactor current monitor M1 for detecting a reactor current IL flowing through the reactor L1, and the detected value is supplied to the control circuit 16.

As will be described in detail below, the buck-boost converter 13
Performs a boosting operation, the third transistor Q3 and the fourth transistor Q4 are alternately turned on while the first transistor Q1 is kept on and the second transistor Q2 is kept off. On the other hand, when the buck-boost converter 13 performs the step-down operation, the third transistor Q
The first transistor Q1 and the second transistor Q2 are alternately turned on while the transistor 3 is kept on and the fourth transistor Q4 is kept off.

The intermediate capacitor 14 forms a filter together with the reactor L1 included in the buck-boost converter 13. As the capacitance value, a value sufficient to absorb the ripple current generated when the buck-boost converter 13 performs the boosting operation is required.
When reactor L1 of about mH is used, several tens of μF
It may be set to about several hundred μF.

The inverter 15 is a so-called full bridge circuit, and includes a fifth transistor Q5 connected in series.
And a third arm comprising a sixth transistor Q6;
A fourth arm composed of a seventh transistor Q7 and an eighth transistor Q8 connected in series;
To D8 to D8 connected in parallel with the eighth to eighth transistors Q5 to Q8. As shown in FIG. 1, the third arm including the fifth and sixth transistors Q5 and Q6 and the seventh and eighth transistors Q7 and Q8
The fourth arm is composed of a buck-boost converter 1
3 and a system power supply 17 is connected between the nodes of the fifth and sixth transistors Q5 and Q6 and the nodes of the seventh and eighth transistors Q7 and Q8.

Note that, as shown in FIG.
Although a reactor L2 for removing noise is connected between the nodes of the transistors Q5 and Q6 and one end of the system power supply 17, in this embodiment, the voltage applied to both ends of the reactor L2 is extremely small. A very small reactor, for example, a reactor having an inductance of about several hundred μH may be used. That is, the reactor L2
Since the Et product is very small in, a reactor having a very small core shape can be used. However, this reactor L2 is not a reactor indispensable for the conversion operation or the step-up / step-down operation by the grid interconnection inverter 10, but merely for the purpose of removing noise. I do not care.

Further, an output current monitor M2 for detecting the output current Io is provided at the other end of the system power supply 17, and the detected value is supplied to the control circuit 16.

The control circuit 16 has an inverter control signal c5
To c8, an inverter control signal generation circuit 21 for generating
An inverter drive circuit 22 that receives the inverter control signals c5 to c8 and generates inverter drive signals C5 to C8;
A carrier generation circuit 23 for generating a first carrier S1 and a second carrier S2, and buck-boost converter control signals c1 to c
Step-up / step-down converter control signal generation circuit 24 that generates
And a buck-boost converter drive circuit 25 that receives buck-boost converter control signals c1 to c4 and generates buck-boost converter drive signals C1 to C4.

The inverter control signal generation circuit 21 detects the polarity of the output voltage Vo, and generates inverter control signals c5 to c8 based on the detected polarity. More specifically, when the polarity of the output voltage Vo is positive, the inverter control signals c5 and c8 are at a high level, the inverter control signals c6 and c7 are at a low level, and conversely, the polarity of the output voltage Vo is negative. In this case, the inverter control signals c6 and c7 are set to the high level, and the inverter control signals c5 and c8 are set to the low level.

The inverter drive circuit 22 amplifies the inverter control signals c5 to c8 and amplifies the inverter drive signals C5 to c8.
C8, which are connected to the fifth to eighth transistors Q5
This is a circuit for driving the inverter 15 by supplying it to the gates of Q8 to Q8. Therefore, the inverter control signals c5 to c5
receiving c8 and outputting inverter drive signals C5 to C8 4
One buffer circuit is included.

The first signal generated by the carrier generation circuit 23
Each of the second carrier waves S1 and S2 is a triangular wave having the same cycle as the switching cycle of the buck-boost converter 13, as described later. The first carrier S1 has a waveform in which a DC component having substantially the same amplitude as that of the second carrier S2 is superimposed on the second carrier S2.
1 and the peak voltage of the second carrier S2 substantially coincide with each other.

Step-up / step-down converter control signal generation circuit 24
Are the input voltage Vin, the output voltage Vo, and the reactor current I
L, the detected value of the output current Io, the first carrier S1
And the second carrier wave S2, and generates buck-boost converter control signals c1 to c4 based on these. More specific operation will be described later.

The buck-boost converter drive circuit 25 amplifies the buck-boost converter control signals c1 to c4 to generate buck-boost converter drive signals C1 to C4.
To drive the step-up / step-down converter 13 by supplying them to the gates of the transistors Q1 to Q4, respectively. Therefore, the buck-boost converter drive circuit 25 includes
The circuit includes four buffer circuits that receive the buck-boost converter control signals c1 to c4 and output the buck-boost converter drive signals C1 to C4, respectively.

Next, the operation of the system interconnection inverter 10 according to this embodiment will be described.

FIG. 2 is an operation waveform diagram of the system interconnection inverter 10 according to the present embodiment.

As shown in FIG. 2, the operation of the system interconnection inverter 10 according to the present embodiment is performed during a period when the input voltage Vin from the DC power supply 11 is higher than the absolute value of the voltage of the system power supply 17 (time t0 to time t0). t1, time t2 to t4, time t5
To t6) and a period in which the input voltage Vin from the DC power supply 11 is lower than the absolute value of the voltage of the system power supply 17 (time t1 to t6).
2. A different operation is performed between times t4 and t5).

More specifically, first, the buck-boost converter control signal generation circuit 24 generates the input voltage Vin based on the input voltage Vin, the output voltage Vo, the detected value of the reactor current IL, and the detected value of the output current Io. During a period higher than the absolute value of the voltage of the power supply 17, a step-down command value wave indicating a target value of the reactor current IL to be passed through the reactor L1 is internally generated, and the input voltage Vin is
7 during a period lower than the absolute value of the voltage of the reactor L.
Internally generates a boost command value wave indicating a target value of reactor current IL to be passed to 1. The waveforms of the step-down command value wave and the step-up command value wave are shown in FIG. Of these step-down command value waves and step-up command value waves, the command value wave having a higher value in each time zone is the current command value wave. The waveform of the current command value wave is shown in FIG. As shown in FIG. 2 (l), the step-down command value wave is a sine wave absolute value waveform, and the step-up command value wave is (system power supply 1).
Absolute value of voltage of step 7 × step-down command value wave) / (input voltage Vi)
This is the waveform derived in n).

As shown in FIGS. 2 (l) and (m),
During a period when the input voltage Vin is higher than the absolute value of the voltage of the system power supply 17, the step-down command value wave shows a higher value than the step-up command value wave, and the input voltage Vin is higher than the absolute value of the voltage of the system power supply 17. Also, during the low period, the step-up command value wave shows a higher value than the step-down command value wave. Therefore, the current command value wave has the step-down voltage during the period when the input voltage Vin is higher than the absolute value of the voltage of the system power supply 17. During the period in which the input voltage Vin coincides with the command value wave and is lower than the absolute value of the voltage of the system power supply 17, it coincides with the boost command value wave. Although the comparison between the input voltage Vin and the absolute value of the voltage of the system power supply 17 is shown in FIG. 2K, the waveform shown in FIG. This is for explaining the operation of No. 10, and such a comparison is not performed in the control circuit 16.

Next, the buck-boost converter control signal generation circuit 24 compares the current command value wave with the detected value of the reactor current IL, and based on this, the waveform of the reactor current IL matches the current command value wave. Thus, a control signal wave is generated.

Further, the buck-boost converter control signal generation circuit 24 generates the control signal wave and the first and second carrier waves S1 and S2.
, And based on this, the buck-boost converter control signals c1 to c4 are generated. Specifically, the buck-boost converter control signal c4 is set to a high level during a period when the control signal wave is higher than the first carrier wave S1, and conversely, during a period when the control signal wave is lower than the first carrier wave S1. The pressure converter control signal c3 is set to a high level. Further, during a period when the control signal wave is higher than the second carrier wave S2, the buck-boost converter control signal c1 is set to a high level, and conversely,
During a period in which the control signal wave is lower than the second carrier wave S2, the buck-boost converter control signal c2 is set to a high level.

Thus, the buck-boost converter control signal c
Since 1 and c2 have opposite phase signals, and the buck-boost converter control signals c3 and c4 have opposite phase signals, the first to fourth transistors Q1 to Q4 are PWM-driven. However, between the step-up / step-down converter control signals c1 and c2 and so that the first transistor Q1 and the second transistor Q2 are not simultaneously turned on, and the third transistor Q3 and the fourth transistor Q4 are not simultaneously turned on. A dead time is inserted between the buck-boost converter control signals c3 and c4.

As described above, the first carrier S1 is a waveform in which a DC component substantially equal to the amplitude of the second carrier S2 is superimposed on the second carrier S2.
Has substantially no overlap with the carrier S2 of
Therefore, during the period when the first and second transistors Q1 and Q2 are switching at a high frequency, the switching operation of the third and fourth transistors Q3 and Q4 is stopped, and the third and fourth transistors Q3 and Q3 are switched. During the period when Q4 is switching at a high frequency, the first and second
The switching operation of the transistors Q1 and Q2 is stopped.

Here, at the timing when the input voltage Vin and the absolute value of the voltage of the system power supply 17 coincide with each other, the control signal wave includes the region where the waveform of the first carrier S1 exists and the waveform of the second carrier S2. 2 (b) to 2 (e), the input voltage Vin is higher than the absolute value of the voltage of the system power supply 17 as shown in FIGS. , The first and second transistors Q1 and Q2 are PWM driven, and the input voltage Vin
Is lower than the absolute value of the voltage of the system power supply 17, the third and fourth transistors Q3 and Q4 are PWM-driven.

When the first and second transistors Q1 and Q2 are driven by PWM, the input voltage Vin is reduced, and the third
When the fourth transistors Q3 and Q4 are PWM-driven, the input voltage Vin is boosted. As a result, the voltage waveform between the output terminals of the step-up / step-down converter 13 becomes a pulsating waveform and substantially matches the absolute value of the voltage of the system power supply 17. 17 is supplied.

In the above operation, first to fourth
Of the transistors Q1 to Q4 are determined by comparing the control signal wave with the first carrier wave S1 and the second carrier wave S2.
, The switching between the step-down operation and the step-up operation is automatically performed. Reactor L1 functions as a common smoothing reactor both in the case where step-up / step-down converter 13 is performing the step-down operation and in the case where the step-up / step-down converter 13 is performing the step-up operation, and utilization efficiency is greatly increased. You can see that.

As described above, according to the system interconnection inverter 10 of the present embodiment, the reactor L1 is common to both the case where the step-up / step-down converter 13 performs the step-down operation and the case where the step-up / step-down converter 13 performs the step-up operation. Since it functions as a smoothing reactor, the usage efficiency of the reactor is high. Therefore, not only can the product cost be reduced, but also the circuit can be miniaturized and the conversion efficiency can be increased.

Further, according to the system interconnection inverter 10 of the present embodiment, the step-down operation and the step-up operation by the step-up / step-down converter 13 are performed by comparing the control signal wave with the first carrier wave S1 and the second carrier wave S2. Is automatically switched, the control by the control circuit 16 can be easily performed.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. It goes without saying that it is a thing.

[0048]

As described above, according to the present invention,
It is possible to provide a grid-connected inverter with improved reactor utilization efficiency.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a system interconnection inverter 10 according to a preferred embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the system interconnection inverter 10 according to a preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional system interconnection inverter.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 grid-connected inverter 11 DC power supply 12 input capacitor 13 buck-boost converter 14 intermediate capacitor 15 inverter 16 control circuit 17 system power supply 21 inverter control signal generation circuit 22 inverter drive circuit 23 carrier wave generation circuit 24 buck-boost converter control signal generation circuit 25 up / down Pressure converter drive circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuyuki Ito 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDC Corporation F-term (reference) 5H007 BB02 CA02 CB04 CB05 CC03 CC12 DA06 DB01 DC02 DC05 EA02 5H730 AS04 AS05 BB13 BB14 BB57 BB83 BB86 DD04 DD32 FD21 FG05

Claims (6)

[Claims] 1. A system interconnection inverter for supplying power from a DC power supply to a system, comprising: a converter for converting a DC voltage supplied from the DC power supply into a pulsating flow; and a pulsating current supplied from the converter. And an inverter for converting AC to AC. The converter includes first and second transistors connected in series between both ends of the DC power source, and third and second transistors connected in series between input terminals of the inverter. A system interconnection inverter comprising: a fourth transistor; and a reactor connected between a node of the first and second transistors and a node of the third and fourth transistors. . 2. When the DC voltage is higher than the absolute value of the voltage of the system, the first and second transistors are PWM-driven, and when the DC voltage is lower than the absolute value of the voltage of the system. The system interconnection inverter according to claim 1, further comprising: a control circuit that performs PWM driving of the third and fourth transistors. 3. The control circuit according to claim 2, wherein the control circuit is configured to control the third and fourth control signals when the DC voltage is higher than an absolute value of the voltage of the system.
One of the transistors is turned on and the other is turned off, and when the DC voltage is lower than the absolute value of the voltage of the system, one of the first and second transistors is turned on and the other is turned off. The grid-connected inverter according to claim 2. 4. The control circuit according to claim 1, wherein the control circuit compares a control signal wave generated based on at least a value of a current flowing through the reactor with first and second carrier waves to thereby control the first to fourth transistors. The system interconnection inverter according to claim 3, wherein on / off is controlled. 5. The system interconnection according to claim 4, wherein the first carrier has a waveform in which a DC component substantially equal to the amplitude of the second carrier is superimposed on the second carrier. System inverter. 6. The control circuit controls on / off of the third and fourth transistors by comparing the control signal wave with the first carrier wave, and controls the control signal wave and the second transistor. The system interconnection inverter according to claim 5, wherein the on / off of the first and second transistors is controlled by comparing the first and second carriers with a carrier wave.