JP2003088140A - Step-up/down converter and system interconnection inverter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a step-up/down converter which can step up and step down the voltage through simplified control. SOLUTION: This step-up/down converter is capable of converting a DC voltage 11 supplied across the input terminals to the ripple current and is composed of the first and second transistors Q1, Q2 connected in series across the input terminals, third and fourth transistors Q3, Q4 connected in series across the output terminals, a reactor L1 connected between a node of the first and second transistors Q1, Q2 and a node of the third and fourth transistors Q3, Q4, and a control circuit 16 for PWM control of arm consisting of the third and fourth transistors Q3, Q4 while the PWM drive of the arm consisting of the first and second transistors Q1, Q2. Accordingly, the step-up/down operations may be controlled easily by adequately setting the duties of these arms.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buck-boost converter and a system interconnection inverter using the buck-boost converter, and more particularly to a buck-boost converter capable of performing a boosting operation and a bucking operation by simple control and the buck-boost converter. Regarding the grid-connected inverter used.

[0002]

2. Description of the Related Art Conventionally, a system interconnection inverter has been known as a circuit for converting DC power supplied from a DC power source such as a solar cell or a fuel cell into AC power by converting it to AC power. As an example of a grid interconnection inverter, Japanese Patent Laid-Open No.
No. 0-152651.

FIG. 7 is a circuit diagram of a conventional grid interconnection inverter described in the publication.

As shown in FIG. 7, the conventional grid-connected inverter described in the publication includes a boost converter 2 that boosts a DC voltage supplied from an input power source 1 and performs waveform shaping, and a boost converter. Intermediate stage capacitor 3 for smoothing the output of, the inverter 4 for shaping the output current Io into a sine wave, and the filter 5 for smoothing the output voltage.
And a control circuit 6 for controlling the operations of the boost converter 2 and the inverter 4. The control circuit 6 switches the boost converter 2 at a high frequency when the voltage of the input power supply 1 is lower than the system voltage. At the same time, the inverter 4 is switched at a low frequency according to the polarity of the system voltage, and when the voltage of the input power supply 1 is higher than the system voltage, the switching of the boost converter 2 is stopped and the inverter 4 is switched at a high frequency. .

Thus, when the voltage of the input power supply 1 is lower than the system voltage, the boost converter 2 performs boosting and waveform shaping, and when the voltage of the input power supply 1 is higher than the system voltage, the inverter is used. Waveform shaping is performed according to 4.

In the conventional grid-connected inverter shown in FIG. 7, the output of the step-up converter 2 is direct current, and its voltage needs to be sufficiently stabilized. Therefore, the intermediate stage capacitor 3 has a very large capacitance. (About 5000μF)
Is required. Therefore, an electrolytic capacitor is generally used as the intermediate stage capacitor 3.

[0007]

However, since electrolytic capacitors are generally large in size and have a shorter life than other capacitors, the use of such components not only increases the size of the entire grid interconnection inverter. However, there is a problem that reliability is lowered. Here, it is effective to use a plurality of electrolytic capacitors in parallel in order to prolong the life of the electrolytic capacitors and improve the reliability, but in this case, the size is further increased.

Further, in the above-mentioned conventional grid-connected inverter, the operation when the voltage of the input power source 1 is lower than the system voltage (step-up operation) and the operation when the voltage of the input power source 1 is higher than the system voltage. (Step-down operation) is very different from that of the control method, and there is a problem that the control is complicated and the output waveform is easily disturbed when the operation is switched.

Therefore, an object of the present invention is to provide a step-up / down converter capable of performing step-up operation and step-down operation by simple control and a grid interconnection inverter using the same.

Another object of the present invention is to provide a step-up / down converter capable of smoothly switching between step-up operation and step-down operation, and a grid interconnection inverter using the same.

Still another object of the present invention is to provide a grid interconnection inverter which does not need to use an electrolytic capacitor as an intermediate stage capacitor.

[0012]

The object of the present invention is to:
A system interconnection inverter that supplies electric power from a DC power source to at least one of an AC load and a system, a converter that converts a DC voltage supplied from the DC power source into a pulsating flow, and the pulse supplied from the converter. An inverter for converting the flow into an alternating current; an intermediate capacitor provided between the converter and the inverter; and a control circuit for controlling the operation of the converter, wherein the converter is connected in series to the DC power supply. First and second transistors, third and fourth transistors connected in series between the input terminals of the inverter, nodes of the first and second transistors, and the third and fourth transistors And a reactor connected between the first and second nodes, and the control circuit PWM-drives the arm composed of the first and second transistors. While, the arm consisting of the third and fourth transistors is achieved by the system interconnection inverter, characterized in that the PWM drive.

According to the present invention, the arms formed of the first and second transistors are PWM-driven and the third and fourth arms are driven.
Since the arm composed of transistors is driven by PWM, it is possible to easily perform the step-up / down operation by appropriately setting the duty, and to smoothly switch between the step-up operation and the step-down operation. it can. Further, according to the present invention, since the capacitance value required for the intermediate capacitor is small, it is possible to reduce the size of the entire device.

In a preferred embodiment of the present invention, the intermediate capacitor is a film capacitor.

According to the preferred embodiment of the present invention, the reliability of the entire apparatus can be improved.

[0016] In a further preferred aspect of the present invention, the capacitance value of the intermediate capacitor is set to several µF to several tens µF.

In a preferred aspect of the present invention, the control circuit is configured such that when the DC voltage is lower than the absolute value of the voltage of the system, the duty of the first transistor is the duty of the third transistor. The converter is controlled to be larger than the above.

In a further preferred aspect of the present invention, the control circuit is configured such that when the DC voltage is higher than an absolute value of the voltage of the system, the duty of the first transistor is equal to that of the third transistor. The converter is controlled so as to be smaller than the duty.

[0019] In a further preferred aspect of the present invention, the control circuit controls ON / OFF of the first and second transistors by comparing a first control signal with a carrier wave, and a second control circuit controls the ON / OFF of the first and second transistors. The ON / OFF of the third and fourth transistors is controlled by comparing a control signal with the carrier wave.

[0020] In a further preferred aspect of the present invention, the first control signal has a substantially sinusoidal waveform.

[0021] In a further preferred aspect of the present invention, the second control signal is substantially a DC waveform.

The above object of the present invention is also a step-up / down converter for converting a DC voltage supplied between the input terminals into a pulsating current, wherein first and second transistors connected in series between the input terminals. A third and a fourth transistor connected in series between the output terminals, and a reactor connected between the node of the first and the second transistor and the node of the third and the fourth transistor. And a control circuit that PWM-drives the arm composed of the first and second transistors while PWM-driving the arm composed of the third and fourth transistors. To be achieved.

According to the present invention, the arms formed of the first and second transistors are PWM-driven and the third and fourth arms are driven.
Since the arm composed of transistors is driven by PWM, it is possible to easily perform the step-up / down operation by appropriately setting the duty, and to smoothly switch between the step-up operation and the step-down operation. it can.

[0024] In a preferred aspect of the present invention, the control circuit is configured such that, during a boosting operation, the duty of the first transistor is larger than the duty of the third transistor. Control the transistor.

[0025] In a further preferred aspect of the present invention, the control circuit is configured such that, in a step-down operation, the first
So that the duty of the second transistor is smaller than the duty of the third transistor.
Control the transistor.

[0026] In a further preferred aspect of the present invention, the control circuit controls ON / OFF of the first and second transistors by comparing a first control signal with a carrier wave, and a second control circuit controls the ON / OFF of the first and second transistors. The ON / OFF of the third and fourth transistors is controlled by comparing a control signal with the carrier wave.

[0027]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of the present invention will be described in detail. The grid-connected inverter according to the present embodiment is a circuit that links DC power supplied from a DC power supply to a grid and converts the power into AC power, and is not particularly limited, but a DC power supply is a solar cell or a fuel cell. The power source can be used.

FIG. 1 is a circuit diagram of a grid interconnection inverter 10 according to a preferred embodiment of the present invention.

As shown in FIG. 1, the grid interconnection inverter 10 according to this embodiment receives a DC power from a DC power supply 11, converts the DC power into an AC, and supplies the AC load 18 and a grid 19 with the DC power. And a step-up / down converter 13 connected between both ends of the DC power supply 11 for stepping up or down the voltage of the DC power supply 11 and performing waveform shaping, and an intermediate capacitor 14 connected between the output ends of the step-up / step-down converter 13.
And an inverter 15 connected between the output terminals of the step-up / down converter 13 to switch the polarity so that the output current Io becomes a sine wave, and a smoothing circuit connected between the output of the inverter 15 and the AC load 18 and the grid 19. 17 and a control circuit 16 for controlling the operations of the step-up / down converter 13 and the inverter 15. The output of the smoothing circuit 17 is connected to the AC load 18 and the grid 19.

The step-up / down converter 13 includes a first transistor Q1 and a second transistor Q2 connected in series.
And a second arm composed of a third transistor Q3 and a fourth transistor Q4 connected in series.
Energy storage reactor L1 connected between the first arm and the node of the first and second transistors Q1 and Q2 and the node of the third and fourth transistors Q3 and Q4.
And diodes D1 to D4 connected in parallel to the first to fourth transistors Q1 to Q4, respectively. Figure 1
, The first and second transistors Q1,
The first arm made up of Q2 is connected between both ends of the DC power supply 11. Also, the third and fourth transistors Q
The second arm composed of Q3 and Q4 is a buck-boost converter 1
3 output terminal.

The buck-boost converter 13 will be described in detail below.
Indicates that the input voltage Epv from the DC power supply 11 is the system power supply 19
When the voltage Vo is lower than the absolute value of the voltage Vo, the boosting operation is performed and the input voltage Epv from the DC power supply 11 is
When the voltage Vo is higher than the absolute value of the voltage Vo, the step-down operation is performed.

The intermediate capacitor 14 constitutes a filter together with the reactor L1 included in the step-up / down converter 13. As the capacitance value, a value sufficient to absorb the ripple current generated when the buck-boost converter 13 performs the boost operation is required, and specifically, the inductance is 5
When the reactor L1 of about μH is used, several μF to
It may be set to about several tens of μF. Therefore, the intermediate capacitor 14 is not particularly limited, but a film capacitor is preferably used. Since the film capacitor has a very long life as compared with the electrolytic capacitor, the reliability of the grid interconnection inverter 10 according to the present embodiment is not impaired. Further, since the required capacitance value is relatively small, the grid interconnection inverter 10 is prevented from becoming large.

The inverter 15 is a so-called full bridge circuit, which is a fifth transistor Q5 connected in series.
And a third arm composed of a sixth transistor Q6,
A fourth arm composed of a seventh transistor Q7 and an eighth transistor Q8 connected in series, and a fourth arm
~ Eighth transistors Q5 to Q8 and diodes D5 to D8 connected in parallel. As shown in FIG. 1, a third arm composed of fifth and sixth transistors Q5 and Q6 and seventh and eighth transistors Q7 and Q8.
Each of the fourth arms is composed of a buck-boost converter 1
The smoothing circuit 17 is connected between the output terminals of the third and third nodes, and between the nodes of the fifth and sixth transistors Q5 and Q6 and the nodes of the seventh and eighth transistors Q7 and Q8.

The smoothing circuit 17 comprises a reactor L2 for removing noise and a capacitor CO.

Further, an output current monitor M for detecting the output current Io is provided between the smoothing circuit 17, the AC load 18, and the system 19, and the detected value is the control circuit 16.
Is supplied to.

The control circuit 16 is a buck-boost converter control circuit 21 for controlling the operation of the buck-boost converter 13.
And an inverter control circuit 22 for controlling the operation of the inverter 15.

FIG. 2 is a block diagram schematically showing the configuration of the step-up / down converter control circuit 21.

As shown in FIG. 2, the buck-boost converter control circuit 21 includes a full-wave rectifier 31, a peak voltage detection circuit 32, a subtractor 33, a compensator 34, and an adder 35.
, Sine wave generator 36, multiplier 37, and subtractor 38
, Compensator 39, adder 40, and carrier generation circuit 41
, A gate circuit 42, and a buck-boost converter drive circuit 43
With.

The full-wave rectifier 31 is a circuit that receives the detected value m of the output current monitor M and rectifies it, and its output is supplied to the peak voltage detection circuit 32. Full wave rectifier 31
For example, a full bridge circuit using a diode can be used.

The peak voltage detection circuit 32 includes the full-wave rectifier 3
The peak value of the AC voltage supplied from the full-wave rectifier 31 is calculated by converting the output from 1 into DC and multiplying the DC voltage by π / 2. The obtained peak value is supplied to the subtractor 33.

The subtractor 33 is a circuit for subtracting the output value of the filter 31 from the target value Ipeak of the peak value of the output current, and its output is supplied to the compensator 34. The target value Ipeak of the peak value of the output current is given from the outside according to the operating condition of the grid interconnection inverter 10 according to the present embodiment.

The compensator 34 is a circuit for improving and stabilizing the control performance, and for example, an amplifier can be used.

The adder 35 is a circuit for adding the output value of the compensator 34 and the voltage Epvn at the maximum power of the DC power supply 11, and the output of the control signal S3 is the gate circuit 42.
Is supplied to. The control signal S3 is a DC signal obtained by correcting the voltage Epvn at the maximum power of the DC power supply 11 based on the current detected value m of the output current and the target value Ipeak of the peak value of the output current.

The sine wave generator 36 is a circuit for generating a sine wave sin, and its frequency is substantially matched with the frequency of the system power supply 19.

The multiplier 37 outputs the sine wave sin output from the sine wave generator 36 and the target value Ipea of the peak value of the output current.
The target value m ′ of the output current, which is the output of the circuit, is supplied to the subtractor 38.

The subtractor 38 is a circuit for subtracting the detected value m of the output current monitor M from the target value m ′ of the output current output from the multiplier 37, and its output is supplied to the compensator 39.

The compensator 39 is a circuit for improving and stabilizing the control performance, and for example, an amplifier can be used.

The adder 40 is a circuit for adding the output value of the compensator 39 and the detected value of the output voltage Vo, and the control signal S1 which is the output thereof is supplied to the gate circuit 42. The control signal S1 changes the voltage waveform of the system power supply 19 into the detected value m of the current output current and the target value Ip of the peak value of the output current.
It is a sine wave signal corrected based on eak.

The carrier wave generation circuit 41 is a circuit for generating a carrier wave S2, and the carrier wave S2 is supplied to the gate circuit 42. The frequency of the carrier wave S2 is set sufficiently higher than the frequency of the system power supply 19, and although not particularly limited, it is preferably set to about 16 KHz.

The gate circuit 42 receives the control signal S1, the control signal S3 and the carrier wave S2, and receives the control signal S1 and the carrier wave S2.
By comparing two, the buck-boost converter control signal c
1 and c2, and a circuit that generates the step-up / down converter control signals c3 and c4 by comparing the control signal S3 with the carrier wave S2. The details will be described later.

The step-up / step-down converter drive circuit 43 amplifies the step-up / step-down converter control signals c1 to c4 to generate step-up / step-down converter drive signals C1 to C4, which are applied to the gates of the first to fourth transistors Q1 to Q4. It is a circuit that drives the step-up / down converter 13 by supplying each. Therefore, the buck-boost converter drive circuit 43 has
It includes four buffer circuits that receive the step-up / down converter control signals c1 to c4 and output the step-up / down converter drive signals C1 to C4, respectively.

FIG. 3 is a block diagram schematically showing the configuration of the inverter control circuit 22.

As shown in FIG. 3, the inverter control circuit 22 receives the output voltage Vo and receives the inverter control signal c.
Inverter control signal generation circuit 51 for generating 5 to c8
And an inverter drive circuit 52 that receives the inverter control signals c5 to c8 and generates the inverter drive signals C5 to C8.
With.

The inverter control signal generation circuit 51 detects the polarity of the output voltage Vo and generates the inverter control signals c5 to c8 based on this. More specifically, when the polarity of the output voltage Vo is positive, the inverter control signals c5 and c8 are set to high level, the inverter control signals c6 and c7 are set to low level, and conversely, the polarity of the output voltage Vo is negative. If so, the inverter control signals c6 and c7 are set to high level, and the inverter control signals c5 and c8 are set to low level.

The inverter drive circuit 52 amplifies the inverter control signals c5 to c8 and outputs the inverter drive signals C5 to C5.
C8 is generated and these are added to the fifth to eighth transistors Q5.
Is a circuit for driving the inverter 15 by supplying each to the gates of Q8 to Q8. Therefore, the inverter drive circuit 52 has the inverter control signals c5 to c5.
Receives c8 and outputs inverter drive signals C5 to C8 4
Two buffer circuits are included.

Next, the operation of the grid interconnection inverter 10 according to this embodiment will be described.

As described above, the step-up / down converter 13 included in the system interconnection inverter 10 according to the present embodiment is used when the input voltage Epv from the DC power supply 11 is lower than the absolute value of the voltage Vo of the system power supply 19. The boosting operation is performed, and the input voltage Epv from the DC power supply 11 is the voltage V of the system power supply 19.
When it is higher than the absolute value of o, the step-down operation is performed. The step-up control and the step-down control for the step-up / down converter 13 are the first
Is controlled by controlling the ratio of the duty d1 of the transistor Q1 and the duty d3 of the third transistor Q3. The following formula is a formula for explaining this.

E _B = (Epv × d1) / d3 (1) In Expression (1), e _B is the output voltage of the step-up / down capacitor 13, that is, the voltage across the intermediate capacitor 14.

As is clear from the equation (1), the output voltage e _B of the step-up / down capacitor 13 is equal to the first transistor Q1.
Of the first transistor Q1 and the duty d3 of the third transistor Q3, and when the duty d1 of the first transistor Q1 is larger than the duty d3 of the third transistor Q3, the boosting operation is performed. When the duty d3 of the transistor Q3 is larger than the duty d1 of the first transistor Q1, the step-down operation is performed.

Next, a method of determining the duty d1 of the first transistor Q1 and the duty d3 of the third transistor Q3 will be described.

FIG. 4 is a timing chart showing the operation of the gate circuit 42 when the level of the control signal S1 is higher than the level of the control signal S3. The input voltage Epv from the DC power supply 11 is the voltage Vo of the system power supply 19. This is the case when it is lower than the absolute value of. Since FIG. 4 shows a very short period in an enlarged manner, the level of the control signal S1 which is substantially a sine wave is shown linearly.

As shown in FIG. 4, the gate circuit 42
Compares the control signal S1 with the carrier wave S2,
Is higher than the carrier wave S2, the buck-boost converter control signal c1 is set to high level, and conversely, the control signal S1
During the period when is lower than the carrier wave S2, the buck-boost converter control signal c2 is set to the high level. Further, the gate circuit 42 compares the control signal S3 with the carrier wave S2, sets the buck-boost converter control signal c3 to the high level in the period when the control signal S3 is higher than the carrier wave S2, and conversely, the control signal S3 is higher than the carrier wave S2. In the low period, the buck-boost converter control signal c4 is set to the high level.

As a result, the buck-boost converter control signal c
1 and c2 are opposite-phase signals to each other, and the step-up / down converter control signals c3 and c4 are opposite-phase signals to each other, so that the arm formed of the first and second transistors Q1 and Q2 and the third and fourth transistors Q3. , Q4 are simultaneously PWM-driven. However, the first transistor Q1 and the second transistor Q2
Are not turned on at the same time, or the third transistor Q3 and the fourth transistor Q4 are not turned on at the same time, there is dead between the buck-boost converter control signals c1 and c2 and between the buck-boost converter control signals c3 and c4. The time is inserted.

Since such an operation is performed, when the level of the control signal S1 is higher than the level of the control signal S3, the duty d of the first transistor Q1 is increased.
1 is inevitably larger than the duty d3 of the third transistor Q3, and the buck-boost converter 13 performs a boosting operation. When the step-up / step-down converter 13 performs the boosting operation, as shown in FIG. 4, the first to fourth transistors Q1 to Q4 are turned on and the first transistor Q1 and the third transistor Q3 are turned on. State (state 1), state in which the first transistor Q1 and the fourth transistor Q4 are on (state 3), and state in which the second transistor Q2 and the fourth transistor Q4 are on (state 4) Will be repeated. Buck-boost converter 1
3 performs the boosting operation, the second transistor Q2
The state (state 2) in which the third transistor Q3 is on does not exist.

FIG. 5 is a timing chart showing the operation of the gate circuit 42 when the level of the control signal S1 is lower than the level of the control signal S3. The input voltage Epv from the DC power supply 11 is the voltage Vo of the system power supply 19. This is the case when it is higher than the absolute value of. It should be noted that since FIG. 5 shows a very short period in an enlarged manner, the level of the control signal S1 that is substantially a sine wave is shown linearly.

As shown in FIG. 5, when the level of the control signal S1 is lower than the level of the control signal S3, the duty d3 of the third transistor Q3 is the first.
Inevitably becomes larger than the duty d1 of the transistor Q1 and the step-up / down converter 13 performs the step-down operation. When the step-up / step-down converter 13 performs the step-down operation, as shown in FIG. 5, the first to fourth transistors Q1 to Q4 are turned on and the first transistor Q1 and the third transistor Q3 are turned on. State (state 1), state in which the second transistor Q2 and the third transistor Q3 are on (state 2), and state in which the second transistor Q2 and the fourth transistor Q2
The state (state 4) in which the transistor Q4 is turned on is repeated. When the step-up / down converter 13 performs a boosting operation, there is no state (state 3) in which the first transistor Q1 and the fourth transistor Q4 are on.

6A to 6D show states 1 to 1, respectively.
7 is an equivalent circuit diagram of the grid interconnection inverter 10 in state 4. FIG.

As is apparent from FIG. 6, state 1 and state 3
Is repeated, the output voltage of the buck-boost converter 13 becomes higher than the input voltage Epv from the DC power supply 11 (step-up operation), and when the states 1 and 2 are repeated, the output voltage of the buck-boost converter 13 is the DC power supply. It becomes lower than the input voltage Epv from 11 (step-down operation).

By the operation described above, the voltage waveform between the output ends of the step-up / down converter 13 becomes a pulsating waveform and substantially matches the absolute value of the voltage of the system power supply 19, which is converted into a sine wave by the inverter 15. System power 19
Is supplied to.

As described above, according to this embodiment, the first to fourth transistors Q constituting the step-up / down converter 13 are formed.
Since ON / OFF of 1 to Q4 is determined by comparing the control signals S1 and S3 with the carrier wave S2, the buck-boost converter 13 automatically switches between the step-down operation and the step-up operation. Therefore, it is possible to smoothly switch between the step-up operation and the step-down operation.

Further, in the present embodiment, the intermediate capacitor 14 has only to absorb the ripple current generated when the step-up / down converter 13 performs the boosting operation, so that the capacitance value thereof is about several μF to several tens μF. And a small film capacitor can be used. This allows
It is possible to downsize the entire grid interconnection inverter 10. Further, as described above, the life of the film capacitor is much longer than that of the electrolytic capacitor, so that the reliability of the grid interconnection inverter 10 according to this embodiment is significantly improved.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. It goes without saying that it is a thing.

For example, when the grid interconnection inverter 10 according to the above embodiment is operated independently, the output voltage Vo is used in place of the detection value m of the output current monitor M supplied to the buck-boost converter control circuit 21, The target value of the output voltage may be used instead of the output voltage Vo.

[0074]

As described above, according to the present invention,
It is possible to provide a step-up / down converter capable of performing a step-up operation and a step-down operation by simple control, and a system interconnection inverter using the step-up / step-down converter. Further, according to the present invention, it is possible to provide a small-sized and highly reliable grid interconnection inverter.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a grid interconnection inverter 10 according to a preferred embodiment of the present invention.

FIG. 2 is a block diagram schematically showing a configuration of a step-up / down converter control circuit 21.

FIG. 3 is a block diagram schematically showing a configuration of an inverter control circuit 22.

FIG. 4 is a timing chart showing an operation of the gate circuit when the level of the control signal S1 is higher than the level of the control signal S3.

FIG. 5 is a timing chart showing an operation of the gate circuit when the level of the control signal S1 is lower than the level of the control signal S3.

6 (a) to 6 (d) are equivalent circuit diagrams of the grid interconnection inverter 10 in states 1 to 4, respectively.

FIG. 7 is a circuit diagram of a conventional grid interconnection inverter.

[Explanation of symbols]

10 grid-connected inverter 11 DC power supply 13 Buck-Boost Converter 14 Intermediate capacitor 15 inverter 16 Control circuit 17 Smoothing circuit 18 AC load 19 system power supply 21 Buck-Boost Converter Control Circuit 22 Second Buck-Boost Converter Control Circuit 31 Full-wave rectifier 32 Peak voltage detection circuit 33 Subtractor 34 Compensator 35 adder 36 Sine wave generator 37 Multiplier 38 Subtractor 39 Compensator 40 adder 41 Carrier wave generation circuit 42 gate circuit 43 Buck-Boost Converter Drive Circuit 51 control signal generation circuit 52 Inverter drive circuit

Continued front page    F-term (reference) 5H007 AA06 BB07 CA02 CB05 CC07                       CC09 CC12 DA03 DA06 DB01                       DC02 DC05 EA01 EA02 EA15                 5H730 AA15 BB13 BB14 BB81 BB86                       DD04 EE59 FD01 FD31 FF02                       FG05 FG16

Claims (12)

[Claims] 1. A grid interconnection inverter that supplies electric power from a DC power supply to at least one of an AC load and a grid, and a converter that converts a DC voltage supplied from the DC power supply into a pulsating current, and from the converter. An inverter for converting the supplied pulsating flow into an alternating current, and an intermediate capacitor provided between the converter and the inverter,
A control circuit for controlling the operation of the converter, wherein the converter is connected in series to the DC power supply;
And a second transistor, a third and a fourth transistor connected in series between the input terminals of the inverter, a node of the first and the second transistor, and a node of the third and the fourth transistor. And a reactor connected between the first and second transistors, and the control circuit performs PWM driving of the arm including the first and second transistors while
And a system interconnection inverter characterized by PWM-driving an arm made up of a fourth transistor. 2. The grid interconnection inverter according to claim 1, wherein the intermediate capacitor is a film capacitor. 3. The capacitance value of the intermediate capacitor is several μF to
The grid-connected inverter according to claim 1, wherein the grid-connected inverter is several tens of μF. 4. The control circuit sets the duty of the first transistor to be larger than the duty of the third transistor when the DC voltage is lower than the absolute value of the voltage of the system. The grid-connected inverter according to any one of claims 1 to 3, which controls a converter. 5. The control circuit sets the duty of the first transistor smaller than the duty of the third transistor when the DC voltage is higher than the absolute value of the voltage of the system. The grid-connected inverter according to any one of claims 1 to 4, which controls a converter. 6. The control circuit controls ON / OFF of the first and second transistors by comparing a first control signal with a carrier wave, and compares the second control signal with the carrier wave. The grid-connected inverter according to any one of claims 1 to 5, wherein ON / OFF of the third and fourth transistors is controlled by performing the operation. 7. The grid-connected inverter according to claim 6, wherein the first control signal has a substantially sinusoidal waveform. 8. The grid-connected inverter according to claim 6, wherein the second control signal has a substantially DC waveform. 9. A step-up / down converter for converting a DC voltage supplied between input terminals into a pulsating current, wherein a first and a second transistor connected in series between the input terminals and an output terminal are provided. A third and a fourth transistor connected in series,
While PWM driving the reactor connected between the node of the first and second transistors and the node of the third and fourth transistors and the arm composed of the first and second transistors, A step-up / step-down converter having a control circuit for PWM-driving an arm made up of a third transistor and a fourth transistor. 10. The control circuit controls the first to fourth transistors such that the duty of the first transistor is larger than the duty of the third transistor during a boosting operation. The buck-boost converter according to claim 9, which is characterized in that. 11. The control circuit controls the first to fourth transistors such that the duty of the first transistor is smaller than the duty of the third transistor during the step-down operation. The buck-boost converter according to claim 9 or 10. 12. The control circuit controls ON / OFF of the first and second transistors by comparing a first control signal with a carrier wave, and compares the second control signal with the carrier wave. The buck-boost converter according to any one of claims 9 to 11, wherein ON / OFF of the third and fourth transistors is controlled by doing so.