CN113595364B - PWM modulation method and device - Google Patents

PWM modulation method and device Download PDF

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CN113595364B
CN113595364B CN202110857902.7A CN202110857902A CN113595364B CN 113595364 B CN113595364 B CN 113595364B CN 202110857902 A CN202110857902 A CN 202110857902A CN 113595364 B CN113595364 B CN 113595364B
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CN113595364A (en
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易龙强
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Kehua Data Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
    • H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
    • H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
    • H02M5/22—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M5/275—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M5/293—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/20—Active power filtering [APF]

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  • Power Engineering (AREA)
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Abstract

The invention discloses a PWM (pulse-width modulation) method and a device, when the pulse width of the current action level is greater than the preset pulse width, a first PWM signal is generated based on a sinusoidal signal, and a multi-level power topology circuit is controlled based on the first PWM signal; and when the pulse width of the current action level is not more than the preset pulse width, generating a second PWM signal through a positive level and a negative level or through the positive level, a zero level and the negative level so as to control the multi-level power topology circuit. Because the two PWM signals meet the volt-second principle, when the three-level power topological circuit is controlled, the two PWM signals have the same action and effect; and because the pulse width of the current action level in the second PWM signal is larger than that of the current action level in the first PWM signal, the conditions of higher harmonics, incomplete switching-on of a switching tube, overlarge reverse peak and zero-crossing distortion caused by the overlow pulse width can be avoided when the multi-level power topology circuit is controlled.

Description

PWM modulation method and device
Technical Field
The present invention relates to the field of signal modulation, and in particular, to a PWM modulation method and apparatus.
Background
Currently, a three-level Power topology circuit is generally used in a new energy Power generation system, or a Power conversion Power Supply such as an Uninterruptible Power Supply (UPS), a Static Var Generator (SVG), an Active Power Filter (APF), or the like. Specifically, the three-level power topology circuit can invert direct current into alternating current, and can also rectify the alternating current into alternating current. Referring to fig. 1, fig. 1 is a schematic circuit diagram of a three-level power topology circuit in the prior art, in which an SPWM (Sinusoidal Pulse Width Modulation) Modulation method is generally used to control each switching tube in the three-level power topology circuit, fig. 2 is a schematic PWM waveform generated based on the SPWM Modulation method in the prior art. Specifically, the Pulse Width of the PWM (Pulse Width Modulation) signal is in positive correlation with the amplitude of the sinusoidal signal, that is, the larger the amplitude of the sinusoidal signal is, the wider the corresponding Pulse Width of the positive level or the negative level is. Therefore, the pulse width near the zero-crossing point of the sinusoidal signal becomes small, and when the pulse width is too small, there are four problems as follows: 1) the pulse with smaller pulse width may have higher harmonic due to higher frequency, which causes interference to the topology circuit; 2) because the pulse width is small, the time of acting on the switching tube is short, the switching tube can be incompletely switched on, and further the loss of the switching tube is large and the heating is serious; 3) when the pulse width is small, a switching tube in the topological circuit can carry out follow current on the inductor, and the switching tube can be damaged due to overlarge reverse peak when the switching tube is turned off; 4) when the pulse width is small, the pulse with the small pulse width may not be emitted due to the action of the suppression system, so that the pulse loss causes the output waveform of the topology circuit to be distorted at the zero-crossing point.
Disclosure of Invention
The invention aims to provide a PWM (pulse-width modulation) method and a device, which can avoid the generation of higher harmonic waves, incomplete switching-on of a switching tube, overlarge inverse peak and zero-crossing point distortion caused by over-small pulse width when a multilevel power topological circuit is controlled.
In order to solve the above technical problem, the present invention provides a PWM modulation method, including:
judging whether the pulse width of the current action level is larger than a preset pulse width, wherein the pulse width of the current action level is the pulse width of a positive level or a negative level in a first PWM signal obtained by calculation based on a sinusoidal signal, the positive half cycle of the sinusoidal signal in the first PWM signal is the positive level and the zero level, and the negative half cycle of the sinusoidal signal is the negative level and the zero level;
if yes, controlling a multi-level power topology circuit based on the first PWM signal;
and if not, generating a second PWM signal based on a positive level and a negative level or based on the positive level, a zero level and the negative level, so that the pulse width of the current action level in the second PWM signal is larger than that of the current action level in the first PWM signal, the first PWM signal and the second PWM signal meet the volt-second balance principle, and controlling the multi-level power topology circuit based on the second PWM signal.
Preferably, generating the second PWM signal based on a positive level and a negative level or based on a positive level, a zero level and a negative level comprises:
controlling an on-time of a positive level and a negative level to generate the second PWM signal when the second PWM signal is generated based on the positive level and the negative level, a sum of the on-time of the positive level and the negative level being equal to a sum of an on-level and a zero level of the first PWM signal;
when the second PWM signal is generated based on a positive level, a zero level, and a negative level, the action times of the positive level, the zero level, and the negative level are controlled to generate the second PWM signal, and the sum of the action times of the positive level, the zero level, and the negative level is equal to the sum of the action times of the first PWM signal and the zero level.
Preferably, the current active level in the second PWM signal includes: when the current action level is in the positive half cycle of the sinusoidal signal, the positive level is the current action level, and the negative level is the second level; when in the negative half cycle of the sinusoidal signal, the negative level is the current active level and the positive level is the second level.
Preferably, generating the second PWM signal based on the positive level and the negative level or based on the positive level, the zero level and the negative level includes:
controlling the action time of the zero level to be tau 0 The action time of the action level is tau 1 And the second level has an action time of tau 2 ；
The above-mentioned tau 0 The above-mentioned [ tau ] P1 And said τ being 2 The expression of (c) is:
Figure BDA0003184715030000031
wherein, T s K is an integer not less than 2 for the current control period of the PWM signal, and τ is the pulse width of the current active level in the first PWM signal.
Preferably, the second PWM signal comprises a time sequence of action time τ 2 Second level of (d), action time of tau 0 Zero level and action time of 1 The action level of (c).
Preferably, the second PWM signal includes doing in chronological orderThe time of use is
Figure BDA0003184715030000032
A second level, with an action time of
Figure BDA0003184715030000033
Zero level of (d), time of action τ 1 Has an action level and an action time of
Figure BDA0003184715030000034
Has a zero level and an action time of
Figure BDA0003184715030000035
To the second level of (c).
Preferably, the second PWM signal comprises a time sequence of action times
Figure BDA0003184715030000036
Zero level, action time of
Figure BDA0003184715030000037
A second level, with an action time of
Figure BDA0003184715030000038
Zero level of (d), time of action τ 1 Has an action level and an action time of
Figure BDA0003184715030000039
Zero level, action time of
Figure BDA00031847150300000310
A second level and an action time of
Figure BDA00031847150300000311
Is zero level.
In order to solve the above technical problem, the present invention further provides a PWM modulation apparatus, including:
a memory for storing a computer program;
a processor for implementing the steps of the PWM modulation method described above when executing the computer program.
The application provides a PWM (pulse-width modulation) method and a device, when the pulse width of a current action level is larger than a preset pulse width, a first PWM signal is generated based on a sinusoidal signal, and a multi-level power topology circuit is controlled based on the first PWM signal; and when the pulse width of the current action level is not more than the preset pulse width, generating a second PWM signal through a positive level and a negative level or through the positive level, a zero level and the negative level so as to control the multi-level power topology circuit. Because the two PWM signals meet the volt-second principle, when the three-level power topological circuit is controlled, the two PWM signals have the same action and effect; and because the pulse width of the current action level in the second PWM signal is larger than that of the current action level in the first PWM signal, the conditions of higher harmonics, incomplete switching-on of a switching tube, overlarge reverse peak and zero-crossing distortion caused by the overlow pulse width can be avoided when the multi-level power topology circuit is controlled.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a circuit schematic of a prior art three-level power topology;
FIG. 2 is a schematic diagram of a PWM waveform generated based on an SPWM modulation method in the prior art;
fig. 3 is a schematic flow chart of a PWM modulation method according to the present invention;
FIG. 4 is a schematic diagram of a first level mode of operation provided by the present invention;
FIG. 5 is a schematic diagram of a second mode of operation of the present invention;
FIG. 6 is a diagram illustrating a second level mode of operation in accordance with the present invention in comparison to a conventional mode;
FIG. 7 is a schematic diagram of a third mode of operation according to the present invention;
FIG. 8 is a schematic diagram comparing the level effect in the same coordinate system provided by the present invention;
fig. 9 is a block diagram of a PWM modulation apparatus according to the present invention.
Detailed Description
The core of the invention is to provide a PWM method and a device, which can avoid the generation of higher harmonic wave, incomplete switching-on of a switch tube, overlarge inverse peak and zero crossing point distortion caused by the undersize pulse width when controlling a multilevel power topology circuit.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 3, fig. 3 is a schematic flow chart of a PWM modulation method according to the present invention, the method includes:
s11: judging whether the pulse width of the current action level is larger than a preset pulse width, wherein the pulse width of the current action level is the pulse width of a positive level or a negative level in a first PWM signal obtained by calculation based on a sinusoidal signal, the positive half cycle of the sinusoidal signal in the first PWM signal is the positive level and the zero level, and the negative half cycle of the sinusoidal signal is the negative level and the zero level;
s12: if yes, controlling the multi-level power topology circuit based on the first PWM signal;
s13: and if not, generating a second PWM signal based on the positive level and the negative level or based on the positive level, the zero level and the negative level, so that the pulse width of the current action level in the second PWM signal is larger than that of the current action level in the first PWM signal, the first PWM signal and the second PWM signal meet the volt-second balance principle, and controlling the multi-level power topology circuit based on the second PWM signal.
When the PWM signal generated based on the sinusoidal signal in the prior art is used to control the multilevel power topology circuit, when the pulse width of the PWM signal is relatively small, there may be higher harmonics caused by too small pulse width, incomplete switching of the switching tube, too large inverse peak, and distortion of the zero crossing point.
In order to solve the technical problem, the design idea of the present application is to increase the pulse width of the PWM signal as much as possible without changing the effect on the multilevel power circuit, so as to avoid the occurrence of higher harmonics caused by too small pulse width, incomplete switching on of the switching tube, too large inverse peak, and zero crossing distortion.
It should be noted that, for the PWM signal generated by sinusoidal signal modulation, since the pulse width of the PWM signal is in positive correlation with the amplitude of the sinusoidal signal, the pulse width of the PWM signal is generally too small and appears near the zero crossing point, and therefore, in other embodiments, it may be determined whether the input sinusoidal signal is in a zero crossing point interval (the preset pulse width is the same as the pulse width corresponding to the interval boundary value in the zero crossing point interval), and if the sinusoidal signal is not in the zero crossing point interval, that is, if the pulse width of the current action level of the first PWM signal generated based on the sinusoidal signal is large, the first PWM signal is generated directly based on the sinusoidal signal, and the control is performed based on the first PWM signal. If the sinusoidal signal is in the zero-crossing point interval, that is, the pulse width of the current action level of the first PWM signal generated based on the sinusoidal signal is small, if the multilevel power topology circuit is still controlled based on the first PWM signal at this time, the situation caused by the small pulse width may occur. Therefore, when the sinusoidal signal crosses zero, a second PWM signal is generated based on the positive level and the negative level or based on the positive level, the negative level and the zero level, wherein the pulse width of the current action level in the second PWM signal is larger than the pulse width of the current action in the first PWM signal, the first PWM signal and the second PWM signal meet the volt-second balance principle, and then when the multi-level power topology circuit is controlled based on the second PWM signal, the action effect is unchanged, and the generation of higher harmonics, incomplete switching-on of a switching tube, overlarge peak reversal and zero crossing distortion caused by the undersize pulse width can be avoided.
It should be noted that the first PWM signal generated according to the sinusoidal signal includes a positive level and a zero level when the positive half cycle of the corresponding sinusoidal signal is positive, and the positive level is the current action level; the first PWM signal includes a negative level and a zero level at a time corresponding to a negative half cycle of the sinusoidal signal, and the negative level is a currently active level. When the second PWM signal corresponds to the positive half cycle of the sine signal, the second PWM signal comprises a positive level, a negative level or comprises a positive level, a zero level and a negative level, and the positive level is a current action level; the second PWM signal comprises a negative level, a positive level, or comprises a negative level, a zero level, and a negative level when corresponding to the negative half cycle of the sinusoidal signal, and the negative level is the current active level.
When the multi-level power topology circuit is a three-level power topology circuit as shown in fig. 1, the positive level of the first PWM signal or the second PWM signal corresponds to the positive level of the positive half cycle of the sine signal to control the transistors Q1 and Q2 in fig. 1, and the negative level of the first PWM signal or the second PWM signal corresponds to the negative level of the negative half cycle of the sine signal to control the transistors Q3 and Q4 in fig. 1.
In particular, the volt-second equilibrium principle can be colloquially explained as: when the sine signal is in positive half cycle, the difference value obtained by subtracting the pulse width of the negative level from the pulse width of the current action level (namely, the positive level) of the second PWM signal is equal to the pulse width of the current action level (positive level) in the first PWM signal; when the sine signal is in a negative half cycle, the difference value obtained by subtracting the pulse width of the positive level from the pulse width of the current action level (namely, the negative level) of the second PWM signal is equal to the pulse width of the current action level (the negative level) in the first PWM signal.
Therefore, in the application, when the current action level is not greater than the preset pulse width, namely near the zero crossing point of the sinusoidal signal, the multilevel power topology circuit is controlled based on the second PWM signal, so that the generation of higher harmonics, incomplete switching-on of a switching tube, excessive inverse peak and zero crossing point distortion caused by too small pulse width can be avoided.
On the basis of the above-described embodiment:
as a preferred embodiment, the determining whether the current sinusoidal signal is in the zero-crossing point interval includes:
judging whether the absolute value of the amplitude of the current sinusoidal signal is larger than a preset amplitude, wherein the preset amplitude is the amplitude of the sinusoidal signal corresponding to the boundary value of the zero crossing point interval;
controlling a multi-level power topology circuit based on a first PWM signal, comprising:
when the absolute value of the amplitude of the current sinusoidal signal is larger than a preset amplitude, controlling the multilevel power topology circuit based on the first PWM signal;
generating a second PWM signal based on the positive and negative levels or based on the positive, zero, and negative levels, comprising:
and when the absolute value of the amplitude of the current sinusoidal signal is not less than the preset amplitude, generating a second PWM signal based on the positive level and the negative level or based on the positive level, the zero level and the negative level.
The embodiment aims to provide a specific implementation manner for judging whether a sinusoidal signal is in a zero point interval, and specifically, when a first PWM signal is generated based on the sinusoidal signal, a pulse width of a current action level is calculated based on an amplitude of the sinusoidal signal, and then a corresponding first PWM signal is generated based on the calculated pulse width. Therefore, whether the absolute value of the amplitude of the current sinusoidal signal is greater than a preset amplitude can be judged through the amplitude of the sinusoidal signal so as to judge whether the sinusoidal signal is in a zero crossing point interval, and when the absolute value of the amplitude of the current sinusoidal signal is greater than the preset amplitude (corresponding to the situation that the sinusoidal signal is not in the zero crossing point interval), the multilevel power topology circuit is controlled based on the first PWM signal; when the absolute value of the amplitude of the current sinusoidal signal is not greater than the preset amplitude (the corresponding sinusoidal signal is in the zero-crossing interval), a second PWM signal is generated based on the positive level and the negative level or based on the positive level, the zero level and the negative level, and the multi-level power topology circuit is controlled based on the second PWM signal.
Since the amplitude of the sinusoidal signal is a positive value at the positive half cycle and a negative value at the negative half cycle, the determination in the present application is made based on the absolute value of the amplitude of the sinusoidal signal. In addition, to ensure that the operation effect of the present embodiment is the same as that of the above embodiment, the absolute value of the amplitude of the sinusoidal signal corresponding to the interval boundary value in the zero-crossing interval in the present embodiment is preset to be the same.
Therefore, whether the sinusoidal signal is in the zero crossing point interval can be judged by the method in the embodiment, and the implementation method is simple and reliable.
In other modulation modes, if the pulse width of the current action level is smaller than the preset pulse width and does not correspond to the zero crossing point interval, the method is also applicable, the mode of generating the second PWM signal based on the positive level and the negative level or based on the positive level, the zero level and the negative level can be adopted as long as the pulse width is lower than the set value, and the original small pulse width signal is changed into a larger pulse width signal, so that the generation of higher harmonics, incomplete switching-on of a switching tube, overlarge inverse peak and zero crossing point distortion caused by the overlow pulse width is avoided.
As a preferred embodiment, generating the second PWM signal based on the positive level and the negative level or based on the positive level, the zero level and the negative level includes:
controlling the action time of the positive level and the negative level to generate a second PWM signal when the second PWM signal is generated based on the positive level and the negative level, the sum of the action time of the positive level and the negative level being equal to the sum of the action level of the first PWM signal and a zero level;
in generating the second PWM signal based on the positive level, the zero level, and the negative level, the action times of the positive level, the zero level, and the negative level are controlled to generate the second PWM signal, and the sum of the action times of the positive level, the zero level, and the negative level is equal to the sum of the action times of the first PWM signal and the zero level.
Specifically, the present embodiment is intended to explain that the second PWM signal is generated by controlling the action times of the positive level and the negative level or by controlling the action times of the positive level, the zero level, and the negative level, and in particular, when the second PWM signal is generated based on the positive level and the negative level or the positive level, the zero level, and the negative level, the control period of the second PWM signal should be ensured to be the same as the control period of the first PWM signal and satisfy the volt-second balance.
The corresponding volt-second equilibrium principle at this time can be interpreted as: at the positive half cycle of the sinusoidal signal, the action time of the current action level (positive level) in the first PWM signal is equal to the difference between the action time of the positive level and the action time of the negative level in the second PWM signal. At the negative half cycle of the sinusoidal signal, the action time of the current action level (negative level) in the first PWM signal is equal to the difference between the action time of the negative level and the action time of the positive level in the second PWM signal.
In summary, the second PWM signal with the pulse width of the current action level larger than that of the first PWM signal can be generated by controlling the action time, and the control method is simple and easy to implement.
As a preferred embodiment, the current active level in the second PWM signal includes: when the sine signal is in the positive half cycle, the positive level is the current action level, and the negative level is the second level; when in the negative half cycle of the sinusoidal signal, the negative level is the current active level and the positive level is the second level.
The present embodiment aims to define the current active level in the second PWM signal, specifically, in the positive half cycle of the sinusoidal signal, the current active level is a positive level, and a negative level is taken as the second level; in the negative half cycle of the sinusoidal signal, the currently applied level is a negative level, and the positive level is taken as the second level.
As a preferred embodiment, generating the second PWM signal based on the positive level and the negative level or based on the positive level, the zero level and the negative level includes:
controlling the action time of zero level to be tau 0 The action time of the action level is tau 1 And the second level has an action time of tau 2 ；
τ 0 、τ 1 And τ 2 The expression of (a) is:
Figure BDA0003184715030000091
wherein, T s K is an integer not less than 2 for the current control period of the PWM signal, and τ is the pulse width of the current active level in the first PWM signal.
Specifically, when the second PWM signal is generated based on the positive level and the negative level, τ is set to be larger than τ 0 、τ 1 And τ 2 Where k may be set to 2 or an integer greater than 2; when the second PWM signal is generated based on the positive level, the zero level, and the negative level, τ is described above 0 、τ 1 And τ 2 May be set to 3 or an integer greater than 3, e.g., 4, 5, 6, 8, etc. It should be noted that the k value should be set reasonably to avoid making the pulse width of the zero level and the second level too small, i.e. τ 2 、τ 0 The value is too small.
The present embodiment aims to provide an implementation for generating the second PWM signal based on a positive level, a zero level and a negative level. In particular, the action time of the action level and the negative level are respectively
Figure BDA0003184715030000092
For reference, the action time of the control action level is
Figure BDA0003184715030000093
Controlling the duration of the second level to
Figure BDA0003184715030000094
It can be seen that above the reference value, the time to effect the level is increased
Figure BDA0003184715030000095
Thereby increasing the time and pulse width of the active level. And satisfies the zero level action time tau 0 The action time of the action level is tau 1 And the second level has an action time of tau 2 The sum of which is equal to the current control period of the first PWM signal, satisfies the volt-second balance principle.
Wherein, the specific calculation formula of τ is: τ ═ T s M is sin (ω t), wherein M is a modulation ratio, and M is not less than 0 and not more than 1.
Further, in consideration that the action time cannot be a negative value, therefore, in the above expression
Figure BDA0003184715030000096
Thus, it is possible to provide
Figure BDA0003184715030000097
At τ is greater than
Figure BDA0003184715030000098
In time, the traditional modulation mode is directly adopted, namely the control is carried out based on the first PWM signal. At a value of tau close to
Figure BDA0003184715030000099
During this time, the action time of the second level approaches to 0, the pulse width of the second level will become very small, and a high-frequency signal and the like may be introduced at this time due to the problem caused by the excessively small pulse width, which deviates from the original intention in the present application, and therefore, a value can be taken according to actual needs in actual engineering, and specifically, when the second PWM signal is generated based on the positive level, the zero level, and the negative level, k is preferably taken as 3. When k is 3, the action time of zero level is
Figure BDA00031847150300000910
The action time of the action level is
Figure BDA00031847150300000911
Figure BDA00031847150300000912
The second level has an action time of
Figure BDA00031847150300000913
At this time in order to
Figure BDA00031847150300000914
For example, at τ greater than
Figure BDA00031847150300000915
Generating a first PWM signal and controlling the multi-level power topology circuit based on the first PWM signal when tau is less than
Figure BDA00031847150300000916
And generating a second PWM signal, and controlling the multi-level power topology circuit based on the second PWM signal. When the second PWM signal is generated based on a positive level and a negative level, k preferably takes a value of 2. When k is 2, the action time of the action level is
Figure BDA0003184715030000101
The second level has an action time of
Figure BDA0003184715030000102
Also in the same way
Figure BDA0003184715030000103
For example, at τ greater than
Figure BDA0003184715030000104
Generating a first PWM signal and controlling the multi-level power topology circuit based on the first PWM signal when tau is less than
Figure BDA0003184715030000105
And generating a second PWM signal, and controlling the multi-level power topology circuit based on the second PWM signal.
Take k-3 as an example, when according to volt-seconds principle:
Figure BDA0003184715030000106
wherein, V 1 Voltage value, V, being the level of action in the PWM signal 2 Is the voltage value of the second level in the PWM signal.
It can be seen that, at the action time, the first PWM signal generated based on the sinusoidal signal is completely equivalent in effect, and each vector acts for the action time
Figure BDA0003184715030000107
Is a base number and is expanded in action time.
Various modes of action can be formed according to the modulation scheme:
as a preferred embodiment, the second PWM signal comprises a time sequence of action times tau 2 Second level of (d), action time of tau 0 Zero level and action time of 1 The action level of (c).
Referring to fig. 4, fig. 4 is a schematic diagram of a first level mode of operation according to the present invention. The second PWM signal is in the sine signal positive half cycle, the positive level is the action level, the negative level is the action level, the action level starts with the negative level, then the zero level, stops with the positive level, the action time is in turn: tau is 2 ～τ 0 ～τ 1 (ii) a In the negative half cycle of the sine signal, the negative level is an action level, the positive level is a second level, starting with the positive level, then the zero level, ending with the negative level, and the action time is sequentially as follows: tau is 2 ～τ 0 ～τ 1 。
As can be seen from fig. 4, the pulse width of the positive level at the positive half cycle is larger than the corresponding pulse width of the positive level in the conventional mode, and the pulse width of the negative level at the negative half cycle is larger than the corresponding pulse width of the negative level in the conventional mode. It can be seen that the implementation manner in the present embodiment can implement a function of increasing the action pulse width. Of course, the order of application of the levels may be reversed or other sequences of application times, such as: the action time is as follows: tau is 1 ～τ 0 ～τ 2 Or τ 1 ～τ 2 ～τ 0 And the like. In this embodiment, the action level, the zero level, and the second level are asymmetrically distributed.
As a preferred embodiment, the second PWM signal includes a time sequence of action times
Figure BDA0003184715030000111
A second level, with an action time of
Figure BDA0003184715030000112
Zero level of (d), time of action τ 1 Has an action level and an action time of
Figure BDA0003184715030000113
Has a zero level and an action time of
Figure BDA0003184715030000114
To the second level of (c).
Referring to fig. 5 and fig. 6, fig. 5 is a schematic diagram illustrating a second level mode of operation provided by the present invention, and fig. 6 is a schematic diagram illustrating a comparison between the second level mode of operation provided by the present invention and a conventional mode. Specifically, each level is applied with symmetrical time in each half cycle, specifically, the second PWM signal starts with a negative level and ends with a positive level in a positive half cycle of the sinusoidal signal, and the specific action sequence is: negative level-zero level-positive level-zero level-negative level, the action time is as follows:
Figure BDA0003184715030000115
in the negative half cycle of the sine signal, starting with a positive level and ending with a negative level, the specific action sequence is as follows: positive level-zero level-negative level-zero level-positive level, the action time is as follows:
Figure BDA0003184715030000116
as can be seen from fig. 5, the pulse width of the positive level at the positive half cycle is larger than the corresponding pulse width of the positive level in the conventional mode, and the pulse width of the negative level at the negative half cycle is larger than the corresponding pulse width of the negative level in the conventional mode. Fig. 6 is a schematic diagram showing the comparison between the second level-action mode and the conventional mode after filtering the high frequency of the PWM signal, and it can be seen from the diagram that the second level-action mode is smoother than the conventional mode near the zero crossing of the modulation wave. It can be seen that the implementation in this embodiment can also implement the function of increasing the action pulse width. In this embodiment, the action level, the zero level, and the second level are symmetrically distributed.
As a preferred embodiment, the second PWM signal includes a time-dependent signalIn sequence, the action time is
Figure BDA0003184715030000117
Zero level, action time of
Figure BDA0003184715030000118
A second level, with an action time of
Figure BDA0003184715030000119
Zero level of (d), time of action τ 1 Has an action level and an action time of
Figure BDA00031847150300001110
Zero level, action time of
Figure BDA00031847150300001111
A second level and an action time of
Figure BDA00031847150300001112
Is zero level.
Referring to fig. 7, fig. 7 is a schematic diagram of a third level mode of operation according to the present invention. In each half cycle, the action time of each level is symmetrical, specifically, the second PWM signal starts with zero level and ends with zero level in the positive half cycle of the sinusoidal signal, and the specific action sequence is: zero level-negative level-zero level-positive level-zero level-negative level-zero level, the action time is as follows:
Figure BDA00031847150300001113
in the negative half cycle of the sine signal, starting with zero level and ending with zero level, the specific action sequence is as follows: zero level-positive level-zero level-negative level-zero level-positive level-zero level, the action time is as follows in sequence:
Figure BDA0003184715030000121
as can be seen from fig. 7, the pulse width of the positive level at the positive half cycle is larger than the corresponding pulse width of the positive level in the conventional mode, and the pulse width of the negative level at the negative half cycle is larger than the corresponding pulse width of the negative level in the conventional mode. It can be seen that the implementation manner in the present embodiment can implement a function of increasing the action pulse width. And the PWM signals in the embodiment are connected through a zero level, so that sudden change between direct connection from a positive level to a negative level or direct connection from the negative level to the positive level is avoided, and overlarge impact is avoided.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating comparison of level effects in the same coordinate system according to the present invention. Fig. 8 includes three PWM signals, wherein the uppermost PWM signal is a PWM signal generated based on the amplitude of the sinusoidal signal in the prior art, and it can be seen that the pulse width is smaller in the zero-crossing point interval. In fig. 8, the middle PWM signal and the lowest PWM signal are PWM signals generated by using the positive level, the zero level and the negative level in the present application in the period of the zero-crossing point interval, respectively, the middle PWM signal is a PWM signal generated in the second level operation mode, and the lowest PWM signal is a PWM signal generated in the third level operation mode. In the zero-crossing point interval, the pulse width of the PWM signal is larger than that of the traditional mode. Therefore, the control mode in the application can increase the pulse width of the action level in the zero crossing point interval of the sinusoidal signal to a certain extent.
Referring to fig. 9, fig. 9 is a block diagram of a PWM modulation apparatus according to the present invention, the apparatus includes:
a memory 91 for storing a computer program;
a processor 92 for implementing the steps of the PWM modulation method described above when executing the computer program.
For solving the above technical problem, the present application further provides a structural block diagram of a PWM modulation apparatus, and please refer to the above embodiments for the introduction of the structural block diagram of the PWM modulation apparatus, which is not described herein again.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A PWM modulation method, comprising:
judging whether the pulse width of the current action level is larger than a preset pulse width, wherein the pulse width of the current action level is the pulse width of a positive level or a negative level in a first PWM signal obtained by calculation based on a sinusoidal signal, the positive half cycle of the sinusoidal signal in the first PWM signal is the positive level and the zero level, and the negative half cycle of the sinusoidal signal is the negative level and the zero level;
if yes, controlling a multi-level power topology circuit based on the first PWM signal;
and if not, generating a second PWM signal based on a positive level and a negative level or based on the positive level, a zero level and the negative level, so that the pulse width of the current action level in the second PWM signal is larger than that of the current action level in the first PWM signal, the first PWM signal and the second PWM signal meet the volt-second balance principle, and controlling the multi-level power topology circuit based on the second PWM signal.
2. The PWM modulation method according to claim 1, wherein generating the second PWM signal based on a positive level and a negative level or based on a positive level, a zero level and a negative level comprises:
controlling an on-time of a positive level and a negative level to generate the second PWM signal when the second PWM signal is generated based on the positive level and the negative level, a sum of the on-time of the positive level and the negative level being equal to a sum of an on-level and a zero level of the first PWM signal;
when the second PWM signal is generated based on a positive level, a zero level, and a negative level, the action times of the positive level, the zero level, and the negative level are controlled to generate the second PWM signal, and the sum of the action times of the positive level, the zero level, and the negative level is equal to the sum of the action times of the first PWM signal and the zero level.
3. The PWM modulation method according to claim 2, wherein the current active level in the second PWM signal comprises: when the current action level is in the positive half cycle of the sinusoidal signal, the positive level is the current action level, and the negative level is the second level; when in the negative half cycle of the sinusoidal signal, the negative level is the current active level and the positive level is the second level.
4. The PWM modulation method according to claim 3, wherein generating the second PWM signal based on a positive level and a negative level or based on a positive level, a zero level and a negative level comprises:
controlling the action time of the zero level to be tau 0 The action time of the action level is tau 1 And the second level has an action time of tau 2 ；
The above-mentioned tau 0 The above-mentioned [ tau ] 1 And said τ being 2 The expression of (a) is:
Figure FDA0003184715020000021
wherein, T s K is an integer not less than 2 for the current control period of the PWM signal, and τ is the pulse width of the current active level in the first PWM signal.
5. The PWM modulation method according to claim 4, wherein the second PWM signal includes an action time τ in time order 2 Second level of (d), action time of tau 0 Zero level and action time of 1 The action level of (c).
6. The PWM modulation method according to claim 4, wherein the second PWM signal includes a time sequence of an action time of
Figure FDA0003184715020000022
A second level, with an action time of
Figure FDA0003184715020000023
Zero level of (d), time of action τ 1 Has an action level and an action time of
Figure FDA0003184715020000024
Has a zero level and an action time of
Figure FDA0003184715020000025
To the second level of (c).
7. The PWM modulation method according to claim 4, wherein the second PWM signal includes a time sequence of an action time of
Figure FDA0003184715020000026
Zero level, action time of
Figure FDA0003184715020000027
A second level, with an action time of
Figure FDA0003184715020000028
Zero level of (d), time of action τ 1 Has an action level and an action time of
Figure FDA0003184715020000029
Zero level, action time of
Figure FDA00031847150200000210
The second level and the action time of
Figure FDA00031847150200000211
Is zero level.
8. A PWM modulation apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the PWM modulation method according to any one of claims 1 to 7 when executing the computer program.
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