JP2000262070A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a single-phase or multiple-phase power converter, capable of obtaining a plurality of output levels easily and of effecting power factor improvement easily. SOLUTION: A series circuit of first and second switches Q1, Q2, a series circuit of third and forth switches Q3, Q4, a series circuit of fifth and sixth switches Q5, Q6 and a capacitor C are connected parallel to each other. One terminal 4 of an AC power supply 3 is connected to the mid point of the first and second switches Q1, Q2 via a first reactor L1. A load 11 is connected between the middle point of the fifth and sixth switches Q5, Q6 and the other terminal 5 of the AC power supply 3 via a second reactor L2. The middle point of the third and forth switches Q3, Q4 are connected to the terminal 5 of the AC power supply 3. The control of the first to sixth switches Q1-Q6 is changed over to obtain a non-conversion mode, in which an output voltage V0 is equalized to an input AC voltage Vin, a step-down mode in which V0 is made lower than the Vin, and a step-up mode, in which V0 is made higher than the Vin. A resonance circuit for soft switching is connected between DC lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching type single-phase or multi-phase power converter for selectively obtaining an AC output having a plurality of output voltage values based on an AC input.

[0002]

2. Description of the Related Art An AC-DC-AC converter is composed of a half-bridge type AC-DC converter and a half-bridge type DC-DC converter.
It is publicly known to be configured by a combination with an AC inverter. Further, a first mode for controlling the converter and the inverter switch so that the input voltage and the output voltage of the power converter are substantially the same, and a second mode for controlling the switch so that the output voltage is lower than the input voltage. A mode and a third mode for controlling a switch so as to increase the output voltage higher than the input voltage can be selectively obtained, and in order to improve efficiency, a pair of half-bridge type converters is used. PWM switch or one or both of a pair of switches of a half-bridge inverter
It has been proposed in Japanese Patent Application Laid-Open No. 8-126352 of the present applicant to turn on / off at a cycle of the power supply voltage without control.

[0003]

The above publication does not describe details of the switch control circuit. Further, there is no description about improvement of power loss based on a parasitic capacitance of a switch or a parallel capacitor.

Accordingly, a first object of the present invention is to provide a single-phase or multi-phase power converter capable of easily obtaining a plurality of output levels and easily improving a power factor. is there. A second object of the present invention is to provide a single-phase or multi-phase power converter capable of easily obtaining a plurality of output levels and reducing power loss due to a parasitic capacitance of a switch or a parallel capacitor. A third object of the present invention is to reduce switching loss in a single-phase or multi-phase power converter having a series circuit of a pair of switches that are turned on and off in opposite directions.

[0005]

The present invention for solving the above problems and achieving the above object comprises a power conversion circuit and a control circuit for the conversion circuit, wherein the power conversion circuit is connected to one end of an AC power supply. A first AC power supply terminal connected to the second AC power supply terminal connected to the other end of the AC power supply;
And a first series circuit in which the second switch is connected in series, and a third series circuit in which the third and fourth switches are connected in series and connected in parallel to the first series circuit. Two
A third series circuit connected to the first and second series circuits in parallel with the first and second series circuits; and 2nd and 3rd
A capacitor or a DC power supply connected in parallel to the series circuit, and an output means, a connection midpoint of the first and second switches is connected to the first AC power supply terminal, A connection midpoint between the third and fourth switches is connected to the second AC power supply terminal, and the output means is provided between the connection midpoint between the fifth and sixth switches and the second AC power supply terminal. For connecting a load, the control circuit is configured to perform a non-conversion mode in which an AC output voltage substantially equal to a voltage of the AC power supply is supplied to the load, and an AC output voltage lower than the voltage of the AC power supply to the load. The first, second, and third modes to selectively obtain at least two modes of a step-down mode for supplying to the load and a step-up mode for supplying an AC output voltage higher than the voltage of the AC power supply to the load. To control the fourth, fifth and sixth switches. Power converter,
Phase difference signal forming means for forming a signal indicating a phase difference between an input current on the power supply side of the first and second switches and an input voltage between the first and second AC power supply terminals; and And a switch control circuit for controlling the third and fourth switches so as to reduce the phase difference based on a signal indicating the following.

It is desirable to configure a circuit for power factor improvement and DC voltage control. It is desirable to provide a soft switching circuit as described in claim 3. Further, as described in claim 4, the soft switch circuit preferably has, for example, the configuration shown in FIG. Further, as described in claim 5, the soft switching circuit can be configured using a transformer having a primary winding and a secondary winding. Claim 6
As shown in (1), when the boost mode is provided, it is desirable to connect a reactor to the input stage. Further, as shown in claims 7 and 8, the soft switching circuits of claims 4 and 5 can be applied to various power converters including a series circuit of a pair of switches.

[0007]

According to the first and second aspects of the present invention, the power factor can be easily improved using the third and fourth switches. According to the third to sixth aspects of the present invention, a plurality of output levels can be easily obtained, and the efficiency can be improved. Further, according to the invention of claims 7 and 8, noise and loss can be reduced in various power converters including a pair of switches.

[0008]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

FIG. 1 shows a power converter for obtaining an AC output of a plurality of voltage levels based on an AC input according to an embodiment of the present invention. This power conversion device roughly includes a conversion circuit 1 and a control circuit 2.

The conversion circuit 1 includes first and second AC power supply terminals 4 and 5 connected to a commercial AC power supply 3 of, for example, 50 Hz.
, A first, a second, a third, a fourth, a fifth and a sixth switch Q1, Q2, Q3, Q4, Q5, Q6, a conversion capacitor C, a first reactor L1 of the input stage and an output. The second reactor L2 in the stage and the third reactor L3 in the middle stage
, An input-stage filter capacitor C11, an output-stage filter capacitor C12, and first and second AC output terminals 6, 7.

The first to sixth switches Q1 to Q6 are insulated gate type (MOS type) field effect transistors each having a source connected to a bulk (substrate), and include first, second, third and third switches. Fourth, fifth and sixth FET switches S1, S2, S3, S4, S5, S6 and first, second, third, fourth, fifth and sixth diodes D1 connected in anti-parallel thereto. , D2, D3, D4, D5, D6. The diodes D1 to D6 are connected to the switches Q1 to Q6.
It can be made into individual components without being built in. Also,
FET switches S1 to S6 are bipolar transistors,
It can be a semiconductor switch such as an IGBT.

A first series circuit comprising a series connection of first and second switches Q1, Q2; a second series circuit comprising a series connection of third and fourth switches Q3, Q4; A third series circuit composed of a series connection of sixth switches Q5 and Q6 and a conversion capacitor C are connected in parallel with each other.

The midpoint of the first series circuit, that is, the midpoint 8 between the first and second switches Q1, Q2 is connected to the input stage reactor L.
1 is connected to the first AC power supply terminal 4. The midpoint of the second series circuit, ie the third and fourth switches Q3,
The connection midpoint 9 of Q4 is connected to the second AC power supply terminal 5 via the reactor L3. The middle point of the third series circuit, that is, the middle point 10 between the fifth and sixth switches Q5 and Q6 is connected to the first AC output terminal 6 via the output stage reactor L2. The load 11 is connected between the first and second AC output terminals 6 and 7 as output means. The second AC power supply terminal 5 and the second AC output terminal 7 are ground terminals and are commonly connected to each other.

The first filter capacitor C11 is connected between the first and second AC power supply terminals 4 and 5 for removing high frequency components of the input current. The second filter capacitor C12 is connected between the first and second AC output terminals 6 and 7 for removing high frequency components of the output voltage.

In order for the control circuit 2 to control the first to sixth switches Q1 to Q6, the control circuit 2 and the first to sixth switches
Are connected to the gates (control terminals) of the switches Q1 to Q6 by lines 12, 13, 14, 15, 16, and 17, respectively. The first and second AC power terminals 4 and 5 are connected by lines 18 and 19, and the first AC output terminal 6 is connected by line 20 so that the control circuit 2 generates control signals for the switches Q1 to Q6. , And both ends of the capacitor C by lines 21 and 22, and the reactor L1
A current detector 23 for detecting a current flowing through the control circuit 2 is connected to the control circuit 2 by a line 24. The current detector 23 can be connected between the filter capacitor C1 and the power supply terminal 4. In the present application, both the current before smoothing by the capacitor C1 and the current after smoothing are referred to as input currents.

Before describing the details of the control circuit 2 of FIG. 1 with reference to FIG. 2, the operation of the conversion circuit 1 of FIG. 1 will be described. The conversion circuit 1 operates in the first, second, and third modes in the same manner as in the above-described Japanese Patent Application Laid-Open No. 8-126352. The first mode is a voltage non-conversion mode in which an output voltage Vo substantially equal to the voltage Vin (for example, 100 V) of the power supply 3 is obtained between the first and second AC output terminals 6 and 7. The second mode is a step-down mode in which an output voltage V0 lower than the power supply voltage Vin (100 V) is obtained. The third mode is a boost mode in which an output voltage V0 higher than the power supply voltage Vin is obtained. In either mode, the first and second switches Q1, Q
2 and one or both of the fifth and sixth switches Q5 and Q6 are prohibited from turning on and off the high frequency, and the low frequency (5
0 Hz), a loss reduction effect is produced.

[0017]

[Non-Conversion Mode] In the non-conversion mode in which an output voltage V0 substantially equal to the input AC voltage Vin is obtained, the control signals shown in FIGS. 4B to 4G are applied to the first to sixth switches Q1 to Q6. Supplied. That is, the first and fifth switches Q1 and Q5 are turned on intermittently at 180-degree intervals by a 50 Hz square wave pulse, and the second and sixth switches Q2 and Q6 are turned on at Q1.
, Q5. The third and fourth switches Q3 and Q4 are controlled to be turned on and off at a frequency (for example, 20 kHz) sufficiently higher than the frequency of the AC power supply voltage Vin shown in FIG. In the non-conversion mode, the third and fourth switches Q3 and Q4 can be kept off. However, in this embodiment, they are turned on / off as in the other modes to improve the power factor. As shown in FIG.
When the input AC voltage Vin is in the positive half-wave period (t0 to t1), the AC power supply 3, the first reactor L1, the first switch Q1, the fifth switch Q5, the second
A positive current flows through the reactor L2 and the closed circuit of the load 11. Further, during a period in which the input AC voltage Vin is a negative half-wave (t1 to t2), the AC power supply 3, the load 11, the second reactor L2, the sixth switch Q6, and the second switch Q
2 and a negative current flows in the closed circuit of the first reactor L1. In this non-conversion mode, the input AC voltage Vin becomes the output voltage V0 with a slight voltage drop. In this case, the first, second, fifth and sixth switches Q1, Q2, Q5,
Since Q6 is not turned on / off at a high frequency (for example, 20 kHz), the number of times of switching per unit time is reduced, and the decrease in efficiency due to switching loss is reduced. The accuracy of the output voltage V0 in the non-conversion mode is -10
It is about +10.

[0018]

[Step-down mode] Output voltage V lower than input AC voltage Vin
In the case of the step-down mode for obtaining 0, control signals shown in FIGS. 5B to 5G are supplied to the first to sixth main switches Q1 to Q6. That is, the first and second switches Q1 and Q2 are at the same low frequency (50 Hz) as the power supply voltage Vin in FIG.
And the third to sixth switches Q3 to Q6 are turned on and off by a high-frequency (for example, 20 kHz) PWM pulse. The positive half-wave period t0 of the input AC voltage Vin shown in FIG.
At time t1 and when the fifth switch Q5 is on,
AC power supply 3, first reactor L1, first switch Q
1, a positive current flows through the closed circuit of the fifth switch Q5, the second reactor L2 and the load 11. Further, during the period t0 to t1 of the positive half-wave of the input AC voltage Vin and the period when the sixth switch Q6 is ON, that is, when the fifth switch Q5 is OFF, the AC power source 3, the first reactor L1, The first switch Q1, the capacitor C, the sixth switch Q6, the second
A positive current flows through the reactor L2 and the closed circuit of the load 11.

The period of the negative half-wave of the input AC voltage Vin in the step-down mode is from t1 to t2, and the sixth switch Q6
Is on, the AC power supply 3, the load 11, the second reactor L2, the sixth switch Q6, the second switch Q2
A negative current flows in the closed circuit of the first reactor L1. Further, the period of the negative half-wave of the input AC voltage Vin, t1 to
At time t2 and when the fifth switch Q5 is on, that is, when the sixth switch Q6 is off, the AC power source 3, the load 11, the second reactor L2, the fifth switch Q5, the capacitor C, the second A negative current flows in the closed circuit of the switch Q2 and the first reactor L1. Input AC voltage Vin
Is interrupted at a high frequency by the fifth and sixth switches Q5 and Q6, so that an output voltage V0 lower than the input AC voltage Vin is obtained.

In the buck mode, the capacitor C is
It is charged by a circuit passing through the second, fifth and sixth switches Q1 Q2, Q5, Q6. For this reason, if the voltage Vc of the capacitor C is not controlled, this voltage Vc gradually increases. Therefore, the third and fourth switches Q3 and Q4 are turned on and off at a high frequency (for example, 20 kHz) to discharge the electric charge of the capacitor C, thereby controlling the voltage Vc. The discharge circuit of the capacitor C is formed as follows. First,
When the input AC voltage Vin is a positive half-wave period t0 to t1 and the fourth switch Q4 is on, the capacitor C, the first switch Q1, the first reactor L1, the power source 3, the third The discharge current of the capacitor C flows in a closed circuit including the reactor L3 and the fourth switch Q4. At this time, energy is stored in the first and third reactors L1, L3. Next, when the input AC voltage Vin is a positive half-wave period t0 to t1 and the third switch Q3 is on, the first reactor L1, the power supply 3, the third reactor L3, and the third switch The energy of the reactors L1 and L3 is released in a closed circuit including Q3 and the first switch Q1, and the energy of the reactors L1 and L3 is fed back to the power supply 3. The third and fourth switches Q3 and Q4 are turned on and off by a PWM pulse at a frequency sufficiently higher than the voltage Vin of the power supply 3, as shown in FIGS.
The discharge period of the capacitor C is controlled by controlling the width of the M pulse, and the voltage Vc of the capacitor C is kept substantially constant. During the period when the input AC voltage Vin is in the negative period t1 to t2 and the third switch Q3 is on, the capacitor C, the third switch Q3, the third reactor L3, the power supply 3, the first reactor The charge of the capacitor C is discharged in a closed circuit including L1 and the second switch Q2. Also,
When the input AC voltage Vin is in the negative period t1 to t2 and
During the ON period of the switch Q4, the first reactor L1
, A second switch Q2, a fourth switch Q4, a third reactor L3, and a power supply 3 in a closed circuit.
1, L3 energy is released. In this embodiment, the third and fourth switches Q3 and Q4 are turned on so as to improve the input power factor. Controlled off

[0021]

[Step-up mode] Output voltage V higher than input AC voltage Vin
In the step-up mode for obtaining 0, the first to sixth switches Q1 to Q6 are on / off controlled by the control signals shown in FIGS. That is, the first to fourth switches Q1 to Q1
Q4 is turned on / off at a high frequency, and the fifth and sixth switches Q5 and Q6 are turned on / off at a power supply frequency (50 Hz). In FIG. 6, the input AC voltage Vin is a positive half-wave period t0.
At time t1 and during the ON period of the first switch Q1, a closed circuit composed of the power supply 3, the first reactor L1, the first switch Q1, the fifth switch Q5, the second reactor L2, and the load 11 is used. A current in the direction of 1 flows. At this time, the energy charged in the previous cycle is released to the first reactor L1, and the sum of the voltage Vin of the power supply 3 and the voltage of the first reactor L1 is output, and the amplitude is higher than the input AC voltage Vin. Is obtained. In the step-up mode, the power supply 3 is connected to the input AC voltage Vin during the positive half-wave period t0 to t1 and the ON period of the second switch Q2.
A current in the first direction flows through a closed circuit including the first reactor L1, the second switch Q2, the capacitor C, the fifth switch Q5, the second reactor L2, and the load 11, and flows through the first reactor L1. Energy is stored. At this time, the voltage Vc of the capacitor C is added to the input AC voltage Vin to become the output voltage V0.

In the boost mode, the input AC voltage Vin is in a negative half-wave period t1 to t2 and the second switch Q
While the switch 2 is on, a current in the second direction flows through a closed circuit including the power supply 3, the load 11, the second reactor L2, the sixth switch Q6, the second switch Q2, and the first reactor L1. . At this time, the voltage of the first reactor L1 is added to the input AC voltage Vin to become the output voltage V0. Also, during the period when the input AC voltage Vin is a negative half-wave period t1 to t2 and the first switch Q1 is on, the power
Load 11, second reactor L2, sixth switch Q6
, A capacitor C, a first switch Q1 and a first reactor L1, a current flows in a second direction in a closed circuit. At this time, the voltage Vc of the capacitor C is added to the input AC voltage Vin to become the output voltage V0. During this period, energy is stored in the first reactor L1.

In the boost mode, discharge of the capacitor C occurs, and this voltage decreases. Therefore, the third and fourth switches Q3 and Q4 are connected to the fifth and sixth switches Q5 and Q6.
The voltage Vc of the capacitor C is controlled to be substantially constant by interrupting at a higher frequency (for example, 20 kHz). The detailed operation will be described below. The input AC voltage Vin is a positive half-wave period t0 to t1 and the fourth switch Q
4, the power supply 3, the first reactor L1, the first switch Q1, the capacitor C, the third reactor L
3. A closed circuit comprising a fourth switch Q4 and a capacitor C
Charge. At this time, the first and third reactors L1,
Since the stored energy of L3 is released, the capacitor C
Is charged by the sum of the voltage Vin of the power supply 3 and the voltages of the first reactors L1 and L3. That is, the capacitor C is charged with a voltage higher than the output voltage V0. Input AC voltage Vin
During the positive half-wave period t0 to t1 and during the ON period of the third switch Q3, the power supply 3, the first reactor L1,
A current flows through a closed circuit of the first switch Q1, the third switch Q3, and the third reactor L3, and energy is stored in the first and third reactors L1, L3. During the period when the input AC voltage Vin is a negative half-wave period t1 to t2 and the third switch Q3 is ON, the power supply 3, the third reactor L3, the third switch Q3, the capacitor C, the second A current flows through a closed circuit including the switch Q2 and the first reactor L1, and the capacitor C is charged by the sum of the voltage Vin of the power supply 3 and the voltages of the first and third reactors L1 and L3.
The power supply 3, the third reactor L3, the fourth switch Q4, and the second switch Q are provided during the period t1 to t2 when the input AC voltage Vin is a negative half-wave and when the fourth switch Q4 is on.
A current flows through a closed circuit including the second and first reactors L1, and energy is stored in the first and third reactors L1 and L3. In this boost mode, the third and fourth switches Q3 and Q4 operate to improve the input power factor.

FIG. 3 is an equivalent circuit showing that the conversion circuit 1 of FIG. 1 obtains a non-conversion mode, a step-down mode, and a step-up mode. The input stage energy storage element 30 corresponds to the first reactor L1, and the output stage energy storage element 34.
Corresponds to the second reactor L2, the first power supply 31 of the voltage V1 corresponds to the first and second switches Q1, Q2,
The second power supply 32 of the voltage V2 is connected to the third and fourth switches Q
3 and Q4, and the third power supply 33 at the voltage V3 corresponds to the fifth and sixth switches Q5 and Q6. In the non-conversion mode, the voltages V1, V3 of the first and third power supplies 31, 33 are used.
, And the first, second, fifth and sixth switches Q1, Q2, Q5 and Q6 are controlled. In the step-down mode, the first, second, fifth and sixth switches Q1, Q2, Q5 are set so that the voltage V1 of the first power supply 31 is set to zero and the voltage V3 of the third power supply 33 is set to a negative value. , Q6.
In the step-up mode, the first, second, fifth and sixth switches Q1, Q2, Q5, and Q5 are set so that the voltage V1 of the first power supply 31 becomes a positive value and the voltage V3 of the third power supply 33 becomes zero.
Control Q6. The voltage V2 of the second power supply 32 is controlled to improve the input power factor.

Next, details of the control circuit 2 will be described with reference to FIG. The control circuit 2 includes an input voltage detection circuit 41, a DC voltage detection circuit 42, an output voltage detection circuit 43, a DC voltage and power factor improvement command value generation unit 44, an output stage voltage command value generation unit 45, a square wave generator 46, First to fourth mode selection switches 48, 49, 50, 51, triangular wave generator 52, first, second, and third comparators 53, 54, 55, first, second, and third negative-phase signals Forming circuits 56, 57 and 58;

The input voltage detecting circuit 41 is connected to the lines 18, 1
9 is connected to the first and second AC power supply terminals 4 and 5 to detect the voltage Vin of the power supply 3 and generate a reference sine wave. The DC voltage detection circuit 42 is connected to both ends of the capacitor C by the lines 21 and 22, and outputs a detection signal indicating the voltage Vc of the capacitor C. Output voltage detection circuit 4
3 is connected to the first and second AC output terminals 6 and 7 by lines 20 and 19, and outputs a detection signal indicating the output voltage V0. Each of the detection circuits 41, 42, and 43 has a power supply voltage V
In, a voltage lower than the actual values of the capacitor voltage Vc and the output voltage V0 are output, but for the sake of easy understanding, it is assumed that the same value as the actual voltage is output here. Note that this command value Vrc is equal to the first and second switches Q1, Q2.
And a command value for setting the voltage Vconv between the interconnection midpoint 8 of the third and fourth switches Q3 and Q4 to a desired value.

DC voltage and power factor improvement command value generating means 44
Is a DC reference voltage source 59, first and second subtractors 60,
63, two proportional integration (PI) circuits 61 and 64, and a multiplier 62. The first subtractor 60 is connected to the reference voltage source 5
9 outputs an error signal indicating the difference between the reference voltage and the detection output of the DC voltage detection circuit 42. This error signal is input to a multiplier 62 via a proportional integration circuit 61,
The reference sine wave obtained from 1 (for example, a sine wave having an effective value of 100 V) is multiplied. The output of the multiplier 62 is a capacitor C
Is an input current command value including information for maintaining the voltage Vc at a desired value. The second subtracter 63 is connected to the output of the multiplier 62 (input current command value) and the line 2 connected to the current detector 23.
And outputs a signal indicating a difference from the detection value (detection current value).
Functions as a phase difference signal forming circuit. The output of the subtractor 63 is output via a proportional integration circuit 64. The output of the proportional integration circuit 64 becomes a DC voltage and a power factor improvement command value Vrc.
The command value Vrc is a sine wave synchronized with the power supply voltage Vin, and includes information for controlling the voltage of the capacitor C to a predetermined value and information for improving the input power factor. Note that the command value Vrc is a desired value of the voltage Vconv between the interconnection midpoint 8 between the first and second switches Q1 and Q2 and the interconnection midpoint 9 between the third and fourth switches Q3 and Q4. It functions as a command value for

The output stage voltage command value generating means 45 comprises a reference output voltage command value generator 66, a subtracter 67, and a proportional-integral-derivative (PID) circuit 68. The reference output voltage command value generator 66 generates a command value indicating V01 = Vin−a which is a volt lower than the power supply voltage Vin in the step-down mode, and V02 which is b volts higher than the power supply voltage Vin in the step-up mode.
= Vin + b. These reference voltage command values V01, V
02 is a sine wave synchronized with the power supply voltage Vin. Subtracter 67
Outputs a signal indicating the difference between the output of the reference voltage command value generator 66 and the output of the output voltage detection circuit 43. This subtractor 6
7 is output via a proportional-integral-derivative (PID) circuit 68 and becomes an output stage voltage command value Vri. Vri is a sine wave synchronized with the power supply voltage Vin, and the connection point 9 of the third and fourth switches Q3 and Q4 and the fifth and sixth switches Q5 and
It functions as a command value for setting the voltage Vinv between Q6 and the interconnection midpoint 10 to a desired value.

A square wave generator 46 and four switches 48, 49, 50, 51 are provided for selectively setting the step-down mode, the step-up mode, and the non-conversion mode.

The square wave generator 46 includes an amplifier 69 and a limiter 70. The amplifier 69 includes the input voltage detection circuit 41
7A is amplified to a voltage whose peak is sufficiently higher than the maximum value of the triangular wave voltage Vt. The limiter 70 includes the triangular wave generator 5
The amplifier output is limited between + Vs equal to the maximum value and -Vs equal to the minimum value of the output triangular wave of No. 2 and a square having alternating high levels of + Vs and low levels of -Vs shown in FIG. A wave voltage Vs is generated.

The first mode selection switch 48 is connected between the output stage voltage command value generation means 45 and the first comparator 53, and is turned on only in the boost mode. No. 2
The mode selection switch 49 is connected between the square wave generator 46 and the first comparator 53, and is turned on only in the non-conversion mode and the step-down mode. The third mode selection switch 50 is connected between the output stage voltage command value generation means 45 and the third comparator 55, and is turned on only in the step-down mode. The fourth mode selection switch 51 is connected between the square wave generator 46 and the third comparator 55, and is turned on only in the non-conversion mode and the boost mode.

The triangular wave generator 52 has a frequency (for example, 20 Hz) that is sufficiently higher than the frequency (50 Hz) of the voltage Vin of the power supply 3.
A triangular-wave voltage Vt (kHz), that is, a sawtooth wave is generated as shown in FIGS. The maximum value of this triangular wave voltage Vt is + V
s, the minimum value is −Vs, which is a sawtooth voltage that gradually decreases after rising sharply. Of course, triangular wave generator 5
2 can be configured to generate a triangle wave that rises gradually and rises rapidly, and a triangle wave that rises and falls gradually. In FIG. 2, one triangular wave generator 52 is connected to the first, second and third comparators 53, 54 and 55, but the first, second and third comparators 53, 54 and 55 A dedicated triangular wave generator can be provided. Also,
One triangular wave generator 52 can also generate three types of triangular waves.

The first comparator 53 compares a comparator input signal Vr1 composed of one of the outputs of the first and second mode selection switches 48 and 49 with the triangular wave voltage Vt and outputs a first switch Q1 to the line 12. Is output in a binary format.

The second comparator 54 is connected to the DC voltage and power factor improvement command value generating means 44 and the triangular wave generator 52, and converts the capacitor voltage and the comparator input signal Vr2 and the triangular wave voltage Vt as the power factor improvement command value. By comparison, an on / off control signal for the third switch Q3 is output to the line 14 in a binary form. The second comparator 54 constitutes a voltage control of the capacitor C and a power factor improvement control circuit.

The third comparator 55 compares the comparator input signal Vr3 consisting of the outputs of the third and fourth mode selection switches 50 and 51 with the triangular wave voltage Vt and outputs a signal from the line 16 to the line 16.
The ON / OFF control signal for the fifth switch Q5 is output in binary form.

The first negative-phase signal forming circuit 56 comprises a NOT circuit, that is, a negative circuit, is connected to the first comparator 53, and comprises a second negative-phase signal of the on / off control signal of the first switch Q1. An on / off control signal for the switch Q2 is output on line 13.

The second negative-phase signal forming circuit 57 is composed of a NOT circuit, is connected to the second comparator 54, and is connected to the fourth switch Q4 which is the reverse phase signal of the ON / OFF control signal of the third switch Q3. Line 15 on / off control signal
Output to

The third negative-phase signal forming circuit 58 is composed of a NOT circuit, is connected to the third comparator 55, and is connected to the sixth switch Q6 which is a negative-phase signal of the on / off control signal of the fifth switch Q5. Outputs on / off control signal.
The first, second and third comparators 53, 54,
55, the first, second and third anti-phase signal forming circuits 56 and 5
7, 58 can be built in. Further, the first, second and third inverted-phase signal forming circuits 56, 57, 58
Is formed by three negative-phase signal comparators without being formed by a NOT circuit, and the three negative-phase signal comparators are connected in the same manner as the positive-phase signal comparators 53, 54, and 55, and only the polarity of the input is positive. Signal comparators 53, 54, 55
Can be reversed.

[0039]

[Mode Switching] Next, how the mode switching can be performed by the circuit of FIG. 2 will be described with reference to FIGS.

[0040]

[Non-conversion mode] In the non-conversion mode, the second and fourth mode selection switches 49 and 51 are turned on, and the input signal Vr1 of the first and third comparators 53 and 55 during the positive half-wave period of the power supply voltage Vin. , Vr3 become + Vs, which coincides with the maximum value + Vs of the triangular wave voltage Vt as shown in FIG.
Do not cross. As a result, the outputs of the first and third comparators 53 and 55 during the period of the positive half-wave of the power supply voltage Vin are continuously at a high level. In addition, since the inputs of the first and third comparators 53 and 55 become -Vs during the negative half-wave period of the power supply voltage Vin in the non-conversion mode, the output continuously becomes low. Thus, in the non-conversion mode, FIG.
(B) As shown in (C), (F) and (G), the first and second switches Q1, Q2 and the fifth and sixth switches Q5, Q6
Is controlled on and off at a low frequency of 50 Hz. The input signal Vr2 of the second comparator 54 during the positive half-wave period of the power supply voltage Vin in the non-conversion mode takes a value between 0 and + Vs. Further, Vr2 during the negative half-wave period of the power supply voltage Vin is 0 to
−Vs. Accordingly, as shown in FIG. 9, in the second comparator 54, the input signal Vr2 is
Across t, a high-frequency on / off control signal (PWM pulse) is supplied to the third and fourth switches Q3 and Q4 as shown in FIGS. In this embodiment, since the mode selector switch is connected to the input signal line of the second comparator 54, the third and fourth switches Q3 and Q4
Turns on / off in each mode.

[0041]

[Step-down mode] In the step-down mode, the second and third mode selection switches 49 and 50 are turned on. Therefore, during the positive half-wave period of the power supply voltage, as shown in FIG. 10, the input signal Vr1 of the first comparator 53 becomes + Vs and does not cross the triangular wave voltage Vt. Therefore, the output of the first comparator 53 goes high. In a negative half wave of the power supply voltage Vin, Vr1 becomes -Vs, and the output of the first comparator 53 becomes low. Therefore, in the step-down mode, the first and second switches Q1 and Q2 are on / off controlled at a low frequency as shown in FIGS. 5B and 5C. Power supply voltage Vin in step-down mode
Input signal Vr3 of the third comparator 55 during the positive half-wave period
Takes a value between 0 and + Vs, and crosses the triangular wave voltage Vt as shown in FIG. During the negative half-wave period of the power supply voltage Vin, V
r3 takes a value between 0 and -Vs and crosses the triangular wave voltage Vt. Accordingly, in the step-down mode, the fifth and sixth switches Q5 and Q6 are controlled by a high-frequency on / off control signal, that is, a PWM pulse, as shown in FIGS. The formation of the PWM pulse in the third comparator 55 is performed as shown in FIG. In the step-down mode, the input signal Vr2 of the second comparator 54 has a value between 0 and + Vs, and crosses the triangular wave voltage Vt as shown in FIG. In the negative half-wave period, Vr2 takes a value between 0 and -Vs,
Crosses the triangular wave voltage Vt. As a result, a high-frequency on / off control signal is supplied to the third and fourth switches Q3 and Q4 as shown in FIGS.

[0042]

[Boost mode] In the boost mode, the first and fourth selection switches 48 and 51 are turned on. Therefore, the output stage voltage command value Vri between 0 and + Vs becomes the input signal Vr1 of the first comparator 53, and crosses the triangular wave voltage Vt as shown in FIG. In the negative half-wave period, Vr1 takes a value between 0 and -Vs and crosses the triangular wave voltage Vt. As a result, the first and second switches Q1 and Q2 are controlled by a high-frequency on / off control signal, that is, a PWM pulse, as shown in FIGS. Third comparator 5 in boost mode
The input signal Vr3 of No. 5 becomes a square wave + Vs and does not cross the triangular wave voltage Vt as shown in FIG. In the negative half-wave period, Vr3 becomes -Vs, and does not cross the triangular wave voltage Vt.
As a result, the fifth and sixth switches Q5 and Q6 are
(F) As shown in (G), it becomes a low frequency on / off control signal. In the boost mode, the input signal Vr2 of the second comparator 54 is between 0 and + Vs as in the other modes.
It crosses the triangular wave voltage Vt as shown in FIG. As a result, the third and fourth switches Q3 and Q4 are on / off controlled at a high frequency as shown in FIGS.

As is clear from the above, this embodiment has the following effects. (1) The non-conversion mode, the step-down mode, and the step-up mode can be obtained with a relatively simple circuit configuration. (2) In the non-boost mode, the first, second, fifth and sixth switches Q1, Q2, Q5 and Q6 are turned on / off at a low frequency (50 Hz), and in the buck mode the first and second switches are turned on and off. Q
1, Q2 is turned on / off at low frequency, and 5th in boost mode
And the sixth switches Q5 and Q6 are turned on / off at a low frequency, so that the number of switching times per unit time is reduced,
The total switching loss is reduced, efficiency is improved,
Also, switching noise is reduced. (3) Since the power factor is improved by the third and fourth switches Q3 and Q4, efficiency is improved and high frequency components are reduced. (4) The third and fourth switches Q3 and Q4 are capacitors C
Since it also has a function of controlling the voltage of the power supply, the power factor can be improved without providing a special switch.

[0044]

Second Embodiment Next, a power converter according to a second embodiment of the present invention will be described with reference to FIGS. However, in FIG. 12 to FIG. 22 and FIG. 23 to FIG.

The power converter of the second embodiment shown in FIG. 12 is different from the power converter of FIG. 1 in that a resonance inductor Lr, a resonance capacitor Cr, and seventh and eighth switches Q7 and Q8.
And the parasitic capacitances C1 -C of the first through sixth switches Q1 -Q6.
6 except that the modified control circuit 2a is provided and the modified control circuit 2a is provided. However, FIG.
In the figure, the illustration of the filter capacitors C11 and C12 is omitted. The series circuit of the resonance inductor Lr, the resonance capacitor Cr, and the seventh switch Q7 has parasitic capacitances C1 to C6.
To reduce the loss based on the first and second switches Q1, Q2
2 are connected in parallel to the series circuit of the second, third and fourth switches Q3 and Q4, and the series circuit of the fifth and sixth switches Q5 and Q6. The eighth switch Q8 is connected in series with the conversion capacitor C. In this embodiment, the conversion capacitor C also forms a loss reduction circuit together with the resonance inductor Lr and the resonance capacitor Cr. Parasitic capacitance C1 of the first to sixth switches Q1 to Q6
C6 is a parasitic capacitance between a pair of main terminals (between the drain and the source) and is connected in parallel to each of the switches Q1 to Q6, and contributes to zero volt switching at the time of turn-off and noise reduction. An individual capacitor can be connected in parallel to each of the switches Q1 to Q6 if necessary. The seventh and eighth switches Q7 and Q8 are composed of insulated gate type FETs similarly to the first to sixth switches Q1 to Q6, and have diodes D7 and Q7 in addition to the FET switches S7 and S8.
D8. The seventh and eighth switches Q7, Q8
This gate (control terminal) is connected to the control circuit 2a by lines 25 and 26 in order to control ON / OFF of the control circuit 2a.

The seventh and eighth switches Q7 and Q8 are for performing soft switching when the first to sixth switches Q1 to Q6 are turned on. Immediately before turning on at least one of the first to sixth parasitic capacitances C1 to C6,
One of the first to sixth switches Q1 to Q6 is to release zero energy to the drain-source voltage of at least one of the first to sixth switches Q1 to Q6.

FIG. 13 shows details of the control circuit 2a of FIG. The control circuit 2a of FIG. 13 includes first, second, and third timing adjustment circuits 71, 72, and 7 in addition to the control circuit 2 of FIG.
The configuration is the same as that of FIG. 2 except that a control circuit 74, switches Q7 and Q8, a control circuit 74, and fifth and sixth mode selection switches 75 and 76 are added. The first timing adjustment circuit 71 includes a first comparator 53 and a negative-phase signal forming circuit 56.
18 is connected to the control lines 12 and 13 of the first and second switches Q1 and Q2.
(B) (C) or FIG. 19 (F) (G) or FIG. 20 (B)
An on / off control signal similar to (C) is transmitted. The second timing adjusting circuit 72 is connected to the second comparator 54, the second negative-phase signal forming circuit 57, and the DC voltage detecting circuit 42, and controls the control lines 14 and 15 of the third and fourth switches Q3 and Q4. 18 (D) (E) or FIG. 20 (B)
An on / off control signal similar to (C) is transmitted. The third timing adjusting circuit 73 is connected to the third comparator 55, the third negative-phase signal forming circuit 58, and the DC voltage detecting circuit 42, and controls the control lines 16 and 17 of the fifth and sixth switches Q5 and Q6. 18 (F) (G) or FIG. 20 (B)
The on / off control signal of (C) is transmitted.

FIG. 14 shows the first timing adjustment circuit 71 of FIG. 13 in detail. The first timing adjusting circuit 71 includes first and second OR gates 77 and 78, a DC voltage zero detector 79, and a timer 80.
8 (B) (C) or a low frequency on / off control signal as shown in FIGS. 19 (F) (G) and a high frequency on / off control signal similar to FIGS. 20 (B) (C). And sends it to the first and second switches Q1 and Q2. In FIG. 14, the zero voltage detector 79 is connected to the DC voltage detection circuit 42, and FIG. 19D shows a signal indicating the point in time when the voltage between the DC lines to which the capacitor C is connected becomes zero. So happens. Since FIG. 19 shows the step-down mode, the fifth and sixth switches Q5 and Q6 are turned on and off at a high frequency, and the zero voltage detector 79 outputs the signal from FIG. Pulse is generated. The time when the zero voltage detection pulse is generated corresponds to the time t3 in FIG. Timer 80 responds to the output of zero voltage detector 79 to generate a pulse having a time width Tx shown in FIG. FIG.
The generation period of the 9 (E) pulse corresponds to the period from t3 to t5 in FIG. The first OR gate 77 in FIG. 14 adds the output of the timer 80 to the output of the comparator 53, for example, as shown in FIG.
9 (F) is output. Second OR
The gate 78 provides a timer 80 to the output of the negative-phase signal forming circuit 56.
And outputs, for example, an on / off control signal shown in FIG. In the first embodiment, the first and second switches Q1 and Q2 are not turned on / off at a high frequency but turned on / off at a low frequency in the step-down mode. On the contrary,
In the second embodiment, an on-period for zero-volt switching at the time of turning on the third to sixth switches Q3 to Q6 at the time of high-frequency on / off is intermittently provided. The second and third timing adjustment circuits 72 in FIG.
73 is formed similarly to the first timing adjustment circuit 71. The first to third timing adjustment circuits 71 to 71
At 73, the zero voltage detection circuit 79 and the timer 80 shown in FIG.
Can be shared. Further, instead of providing the zero voltage detection circuit 79, a timer for measuring a time corresponding to, for example, from t2 to t3 in FIG. it can.

In FIG. 13, switches Q7 and Q8 control circuit 74 is connected to input voltage detection circuit 41 by line 81, and triangular wave generator 52 is connected by line 82.
And sends control signals for the seventh and eighth switches Q7 and Q8 to the lines 25 and 26.

FIG. 15 shows the Q7 and Q8 control circuits 74 shown in FIG.
It is shown. The Q7 and Q8 control circuit 74 is 50 Hz
, A high frequency on / off mode pulse forming circuit 84 of, for example, 20 kHz, and mode changeover switches 85, 86, 87, 88. Low frequency on / off mode pulse forming circuit 83
FIG. 18 is based on the input voltage detection signal on line 81.
(H) As shown in (I), a pulse synchronized with the power supply voltage Vin is formed and supplied to the control terminals of the seventh and eighth switches Q7 and Q8. The high frequency on / off mode pulse forming circuit 84 forms pulses shown in FIGS. 20D and 20E based on the triangular wave voltage Vt of the line 82, that is, the carrier wave, and supplies the pulses to the seventh and eighth switches Q7 and Q8. I do. The mode changeover switches 85 and 86 in FIG. 15 are turned on in the non-conversion mode. The mode changeover switches 87 and 88 are turned on in both the step-down mode and the step-up mode. The mode changeover switches 85, 86, 87 and 88 are omitted, and the low frequency
The output of the off-mode pulse forming circuit 83 and the high-frequency
Both the output of the off-mode pulse forming circuit 84 and the output of the off-mode pulse forming circuit 84 can be supplied to the lines 25 and 26.

FIG. 16 shows details of the low frequency on / off mode pulse forming circuit 83 of FIG. This low frequency on
The off-mode pulse forming circuit 83 includes two comparators 89 and 90, two reference voltage sources 91 and 92,
It comprises a gate 93 and three timers 94, 95, 96. The comparator 89 compares the 50 Hz sine wave of the line 81 with the reference voltage Va of the reference voltage source 91, and
A pulse indicating the point in time when the sine wave voltage of the line 81 becomes higher than a is generated at time t1 in FIG. The comparator 90 compares the sine wave of the line 81 with the reference voltage Vb of the reference voltage source 92, and generates a pulse indicating the time when the sine wave becomes lower than the reference voltage Vb at time t6 in FIG. The reference voltages Va and Vb are set near the zero level of the sine wave as shown in FIG. The comparators 89 and 90 include a trigger signal forming circuit (differentiating circuit) at the output stage, and generate a trigger pulse at times t1 and t6 in FIG. The OR gate 93 in FIG. 16 sends the outputs of the two comparators 89 and 90 to timers 94 and 95. The timer 94 generates a pulse having a time width Ta shown in FIG. 18H in response to trigger pulses generated from the two comparators 89 and 90. The time width Ta is set so as to include the time points at which the first to sixth switches Q1 to Q6 are turned on. The output of the timer 94 shown in FIG.
Is used as a control pulse for the switch Q7. The timer 95 responds to the output trigger pulses of the comparators 89 and 90 to form a pulse having a time width Tb indicating the period from t1 to t2 and the period from t6 to t7 in FIG. The timer 96 generates a low-level pulse having a time width Tc indicating the period from t2 to t4 and the period from t7 to t9 in FIG. The output of the timer 96 becomes a control signal for the eighth switch Q8. As apparent from FIG. 18, FIG. 18H includes the turn-on times t3 and t8 of the first to sixth switches Q1 to Q6.
The control pulses Q7 and Q8 of (I) are formed. The operation and effect of the seventh and eighth switches Q7 and Q8 will be described later in detail.

FIG. 17 shows the details of the high frequency on / off mode pulse forming circuit 84 of FIG. This high frequency
The off-mode pulse forming circuit 84 includes first to fourth timers 97, 98, 99, and 100. First timer 9
7 measures a predetermined time T0 somewhat shorter than one cycle of the triangular wave voltage Vt in response to the rising time t0 of the sawtooth triangular wave voltage Vt supplied by the line 82 shown in FIG. A trigger pulse is generated at the time. Since the triangular wave voltage Vt rapidly rises vertically and then gradually decreases, when the high-frequency on / off control pulse is transmitted from the first to third comparators in FIG. Can be aligned. The second timer 98 in FIG. 17 generates a pulse having a time width Ta in the period from t1 to t6 shown in FIG. . In response to the output of the first timer 97, the third timer 99 responds to the output of the first timer 97 by a time width T corresponding to the period t1 to t2 in FIG.
Generate b pulse. The fourth timer 100 generates a low-level pulse having a time width Tc during a period from t2 to t5 shown in FIG. Supply. In this embodiment, the second, third and fourth timers 98, 99,
100 functions substantially similarly to the timers 94, 95, 96 of FIG. However, the timers 98, 99, 1 in FIG.
The time width of 00 may be set to a value different from the time widths of the timers 94, 95, and 96 in FIG. Timer 97
To 100 may be variable timers whose output pulse widths change according to the magnitude of the input or output current or voltage of the conversion circuit 1a.

The mode switching switch 75 shown in FIG. 13 selectively sends the DC voltage and the power factor improvement command value Vrc to the second comparator 54. The mode switch 76 selectively sends the output of the square wave generator 46 to the second comparator 54. In this embodiment, the switch 75 is turned on in the step-down mode and the step-up mode, and the switch 76 is turned on in the non-conversion mode.

The basic operation of the power converter of the second embodiment is the same as that of the first embodiment, and a non-conversion mode, a step-down mode, and a step-up mode can be selectively obtained.
In the second embodiment, the DC voltage and the power factor improvement command value Vrc can be input to the second comparator 54 in FIG. 13 via the mode switch 75, and the square wave voltage can be input via the mode switch 76. Vs can be input. When the switch 75 is on, the second comparator 54 generates an output similar to that of the first embodiment. On the other hand, when the switch 76 is on, the second comparator 54 generates an on / off control signal for the third switch Q3 in the same cycle as the input voltage as shown in FIG. In the step-down mode of the second embodiment, the first, second, and third comparators 53, 54, and 55 and the first, second, and third opposite-phase signal forming circuits 56, 57, and 58 are used as shown in FIG.
Outputs similar to (B) to (G) are obtained. In the boost mode, the first, second, and third comparators 53,
54, 55 and first, second, and third negative-phase signal forming circuits 5
6, 57, and 58, outputs similar to those shown in FIGS.

Next, the zero volt switching operation of the first to sixth switches Q1 to Q6 and the operation of reducing the loss due to the parasitic capacitances C1 to C6 according to the second embodiment will be described with reference to FIG. FIG. 21 shows the on / off states of the first to eighth switches Q1 to Q8, the voltages Vq1 to Vq8, and the resonance current Icr flowing through the inductor Lr during a partial period in the step-down mode. In FIG. 21, the ON periods of the first to eighth switches Q1 to Q8 are indicated by oblique lines. In FIG. 21, t1, t2, t3, t5, t6,
At time t7, t1, t2, t3, t4, t5, t in FIG.
It corresponds to 6 time points. Hereinafter, the operation of each section in FIG. 21 will be described in detail. Note that the current path may be indicated only by the symbol of the circuit element.

[0056]

[T0-t1 Section] The operation in the step-down mode shown in FIG. 21 is a modification of a part of the operation shown in FIG. t0 to t1
In the section, the first, fourth, sixth, and eighth switches Q1, Q4, Q6, and Q8 are on, and the second, third, fifth, and seventh switches Q2, Q3, Q5, and Q7 are on. Is off. Therefore, 3-L1-Q1-Q8-C-Q6-L2
A positive current flows to the load 11 through the path of −11. Also,
The energy release circuit of the third reactor L3 is L3 -Q4
It occurs on the route of -Q6 -L2-11.

[0057]

[Section t1 to t2] In the section t1 to t2, the seventh switch Q7 is newly turned on. As a result, 3-L1-Q1-Lr-Cr-Q7-
The current in the path of Q6-L2-11 also flows. That is, Lr Cr
The current Icr of the resonant circuit starts to flow as shown in FIG. Since the current Icr gradually increases, the seventh switch Q7 turns on with zero current switching.

[0058]

[T2 to t3 section] At time t2, the eighth switch Q8 is turned off. Since the parasitic capacitances C2, C3, C5 of the second, third and fifth switches Q2, Q3, Q5 during the off period are connected in parallel to the LrCr resonance circuit, the parasitic capacitances C2, C3, C5 Discharge occurs. That is, C2 -Q1-
Discharge of C2 occurs on the path of Lr-Cr-Q7, and C3-L
Discharge of C3 occurs in the path of r-Cr-Q7-Q4, and C5
Discharge of C5 occurs on the path of -Lr -Cr -Q7 -Q6. As a result, the second, third and fifth switches Q2, Q
3. The voltages Vq2, Vq3, and Vq5 of Q5 are as shown in FIGS.
As shown in (E), the temperature gradually decreases from time t2, and becomes almost zero at time t3. When the eighth switch Q8 is turned off at the time t2, charging of the parasitic capacitance (not shown) of the eighth switch Q8 starts, and the voltage Vq8 is changed to the level shown in FIG.
And gradually increases as shown in FIG.

[0059]

[T3 to t4 section] At time t3, the second, third and fifth switches Q2, Q3 and Q5 are turned on. Therefore, in the section from t3 to t4, the first to seventh switches Q1 to Q
All of 7 are turned on. The second, third and fifth switches Q2, Q3, Q5 are connected to these voltages Vq2, Vq3, Vq5.
Is turned on with zero at zero, thereby achieving zero volt switching. Also, the parasitic capacitances C2 and C3
, C5 is transferred to the LrCr resonant circuit,
Since the second, third and fifth switches Q2, Q3, Q5 are controlled to be turned on, no loss of stored energy in the parasitic capacitances C2, C3, C5 occurs. In the section from t3 to t4, the circuit of 3-L1-Q1-Q5-L2-11,
A current flows through the circuit of -L1 -Q1 -Lr -Cr -Q7 -Q6 -L2-11 and the circuit of L3 -Q4 -Q6 -L2-11. In this embodiment, the time between t2 and t3 in FIG. 21 is determined by calculation. Instead, it is detected that the voltage between the DC lines P1 and P2 becomes zero at t3, and the switches Q2, Q3 and Q5 are turned on. It may be controlled.

[0060]

[T4 to t5 section] Each switch Q1 to t4 to t5 section
The state of Q8 is the same as the previous section from t3 to t4. FIG.
As shown in (I), the direction of the resonance current Icr is reversed at time t4.

[0061]

[T5 to t6 section] At time t5, the second, fourth and sixth switches Q2, Q4 and Q6 are turned off. In addition,
In the section from t5 to t6, the first, third and fifth switches Q1,
Q3 and Q5 are kept on as in the previous section between t4 and t5.
When the second, fourth and sixth switches Q2, Q4 and Q6 are turned off, the parasitic capacitances C2, C4 and C6 are charged, and the second, fourth and sixth switches Q2 and Q4 are charged.
, Q6 of FIG. 21 (B) (D)
As shown in (F), the voltage gradually rises in the interval from t5 to t6, and zero volt switching is achieved. Also, a noise reduction effect is produced. At the time of this turn-off, Lr-Q1-C
A C2 charging circuit composed of 2-Q7-Cr, Lr-Q3-
C4 charging circuit consisting of C4 -Q7 -Cr, Lr -Q5
A C6 charging circuit consisting of -C6 -Q7 -Cr results.
When the voltages of the second, fourth, and sixth parasitic capacitances C2, C4, and C6 gradually increase in the section from t5 to t6, the voltage Vq8 based on the parasitic capacitance of the eighth switch Q8 is increased as shown in FIG.
As shown in (H), it gradually decreases and becomes almost zero at t6.

[0062]

[Section t6 to t7] At time t6, the eighth switch Q8 is turned on. In the section from t6 to t7, the first to seventh switches Q1 to Q7 are kept in the same state as in the previous section from t5 to t6. Since the voltage Vq8 of the eighth switch Q8 is substantially zero at time t6, zero volt switching is achieved. In the section from t6 to t7, 3-L1 -Q1 -Q5-
A current flows in the circuit of L2-11.

[0063]

[Section after t7] The seventh switch Q7 is turned off in synchronization with the time point t7 when the resonance current Icr becomes zero.
This achieves zero current switching of the seventh switch Q7. After t7, the seventh switch Q7
The other switches are kept in the same state as in the section from t6 to t7.

In this embodiment, the soft switching control by the resonance circuit is not executed at time t7 in FIG. Accordingly, during the positive half-wave period of the step-down mode, the third and fifth switches Q3 and Q5 perform zero volt switching at the time of turning on. Further, the second switch Q2, which can be kept off originally, is controlled to be turned on and off at a high frequency. In the period of the negative half-wave of the AC power supply voltage Vin, the same operation as in the period of the positive half-wave shown in FIG. 21 occurs.

In the boost mode, the first and second
Switches Q1 and Q2 are turned on and off at high frequency,
And the sixth switches Q5 and Q6 are turned on / off at a low frequency. Therefore, during the period corresponding to the period t0 to t7 in FIG. 21, the first to eighth switches Q1
Q8 and the resonance current Icr change. That is, in the boost mode of FIG. 22, the first and second switches Q1, Q2
Are the fifth and sixth switches Q5 in the step-down mode of FIG.
The transistor is turned on / off at a high frequency similarly to Q6, and the fifth and sixth switches Q5 and Q6 in FIG. 22 operate similarly to the first and second switches Q1 and Q2 in FIG. In the step-up mode, the seventh and eighth switches Q7 and Q8 are controlled to be turned on and off in the same manner as in the step-down mode, and all of the first to sixth switches Q1 to Q6 are simultaneously turned on during the period from t3 to t5. Thus, zero volt switching is achieved.

In the non-conversion mode shown in FIG.
8 (H) and (I), the seventh and eighth switches Q
7 and Q8 are on / off controlled, so that the same effects as in the step-down mode and the step-up mode can be obtained when the first to sixth switches Q1 to Q6 are turned on and off.

In the second embodiment, as described above, the first to sixth switches Q1 to Q6 can be soft-switched, thereby reducing power loss and noise. In the case of the non-conversion mode, as shown in FIG.
As in the embodiment, the number of switching times per unit time is reduced, and the efficiency is improved. Also, in the step-down mode, the half-wave period of the first and second switches Q1, Q2 as shown in FIGS. 19 (F) and (G). The period is a low-frequency operation, and the number of times of switching is reduced and the loss is reduced as compared with the conventional device in which all switches are controlled to be turned on and off with a PWM pulse in all periods.

[0068]

Third Embodiment FIG. 23 shows a power converter according to a third embodiment in which a switching loss and noise reduction circuit is modified. The power conversion circuit 1b of the power conversion device includes seventh, eighth, and ninth power conversion circuits to form a soft switching circuit.
Switches Q7, Q8, Q9, a transformer Tr having a primary winding N1 and a secondary winding N2, and two diodes D
11 and D12. The eighth switch Q8 is connected in series with the conversion capacitor C as in the second embodiment. One end of the primary winding N1 functioning as an inductor is connected to one DC line P1, and the other end is connected to the other DC line P2 via a seventh switch Q7.
One end of the ninth switch Q9 is connected to a connection point between the primary winding N1 and the seventh switch Q7, and the other end is connected to a connection point between the eighth switch Q8 and the capacitor C. One end of a secondary winding N2 electromagnetically coupled to the primary winding N1 is connected to the interconnection point of the seventh and ninth switches Q7 and Q9,
This other end is connected between the diodes D11 and D12. The diode D11 is connected between the other end of the secondary winding N2 and one end of the capacitor C. The diode D12 is connected between the other end of the capacitor C and the other end of the secondary winding N2.

The control circuit 2b of FIG. 23 is different from the control circuit 2 of FIG. 2 in that the seventh, eighth and ninth switches Q7,
The control signal forming circuit 74a of Q8 and Q9 is added. Q7, Q8, Q9 The control signal forming circuit 74a is shown in FIG.
The third, Q7, Q8 control circuit 74 is formed on the same principle as the first, second, third, and fourth timers for forming the control signals shown in FIGS. 101, 10
2, 103 and 104. The first timer 101
The triangular wave voltage V of the same one as the triangular wave generator 52 of FIG.
In response to t, the time width T11 from t0 to t1 in FIG. 25 is measured. The second timer 102 generates a pulse having a time width T12 in a period from t1 to t3 shown in FIG. 25D in response to the trailing edge of the output pulse from the first timer 101. Third timer 10
Numeral 3 generates a negative pulse having a time width T3 in the period from t1 to t4 shown in FIG. 25E in response to the trailing edge of the output pulse from the first timer 101. The fourth timer 104 is the second timer 1
In response to the trailing edge of the output pulse 02, a pulse having a time width T14 in the period t3 to t4 shown in FIG. Outputs of the second, third and fourth timers 102, 103 and 104 are supplied to control terminals of seventh, eighth and ninth switches Q7, Q8 and Q9. First to sixth switches Q1 to Q
6 is ON / OFF controlled in each mode similarly to the first embodiment or the second embodiment.

FIG. 25 shows a first example of a positive half-wave period when the power converter of the third embodiment is operated in the boost mode.
And the control signals for the first, second, seventh, eighth, and ninth switches Q1, Q2, Q7, Q8, and Q9. In the third embodiment shown in FIG.
The on / off control of the second switch Q2 is performed by the positive-phase signal of the comparator 53 shown in FIG.
On / off control of the first switch Q1 based on the output of the first switch Q1. When the seventh switch Q7 is controlled to turn on the seventh switch Q7 and the eighth switch Q8 is controlled to be turned off before the turn-on time t2 of the second switch Q2, 3-L1-Q1-N1-Q7-Q6 -L2 -1
A voltage is applied to the primary winding N1 by the circuit (1). Since the secondary winding N2 is electromagnetically coupled to the primary winding N1, a voltage is generated here and a current flows through the circuit of N2-D11-C-Q7. The secondary winding N2 is equivalently short-circuited by the capacitor C, and the voltage of the primary winding N1, that is, the voltage between the pair of DC lines P1 and P2 also becomes substantially zero. Among the first to sixth switches Q1 to Q6, for example, the energy of C2 in the parasitic capacitances C1 to C6 of the switches during the off period is C2 -Q1.
The voltage is released in a closed circuit of -N1 -Q7, fed back to the capacitor C, and the voltage Vq2 of the second switch Q2 becomes zero. FIG.
At 5, the second switch Q2 is turned on at time t2 when this voltage goes to zero. This achieves zero volt switching of the second switch Q2.
Simultaneously with or after turning on the second switch Q2, the ninth switch Q9 is turned on as shown in FIG. 25F, and the seventh switch Q7 is turned off. T3 of FIG.
During the period t4, 3-L1 -Q2 -D7 -N2 -Q5 -L2
In the circuit of −11, a voltage is applied to the primary winding N1 and N2 −
The capacitor C is charged by the circuit of Q9-CD12. As a result, the voltage Vc of the capacitor C gradually increases, and conversely, the voltage Vq8 of the eighth switch Q8 gradually decreases and becomes almost zero at time t4 in FIG. Therefore, t4 in FIG.
At this point, the eighth switch Q8 is turned on. As a result, zero volt switching of the eighth switch Q8 is achieved.

During a negative cycle of the power supply voltage Vin,
Zero volt switching is achieved when the first switch Q1 is turned on. Also, the third and fourth switches Q
3, the zero volt switching when Q4 is turned on is performed in the same manner as the first and second switches Q1 and Q2. In the step-down mode, the fifth and sixth switches Q5,
The zero volt switching of Q6 is performed similarly to the first and second switches Q1 and Q2 in the boost mode. Therefore, the third embodiment can provide the same effects as those of the second embodiment.

[0072]

Fourth Embodiment A power converter according to a fourth embodiment is the same as that of the first embodiment except that the control circuit 2 of the first embodiment is modified to a control circuit 2C shown in FIG. It is what was constituted. The control circuit 2C of FIG. 11 includes first, second, and third switches instead of the changeover switches 48, 49, 50, and 51 of the control circuit 2 of FIG.
Arithmetic circuits 47a, 48a, 49a and first and second limiters
The configuration is the same as that of FIG. 2 except that 50a and 51a are provided.

The first arithmetic circuit 47a is connected to the converter voltage command value generating means 44, the inverter stage voltage command value generating means 45, and the square wave generator 46.
The operation of Vs-Vri is executed. That is, the first arithmetic circuit 4
7a includes an adder and a subtractor, and subtracts the inverter voltage command value Vri from a value obtained by adding the square wave voltage Vs to the converter voltage command value Vrc. Note that the order of addition and subtraction can be reversed to Vrc−Vri + Vs. The first arithmetic circuit 47a has a function of automatically selecting the high-frequency on / off operation or the low-frequency on / off operation of the first and second switches Q1, Q2 in response to a change in the inverter voltage command value Vri. Having.

The second arithmetic circuit 48a includes a converter voltage command value generating means 44 and an inverter voltage command value generating means 45
And a square wave generator 46, and Vri + Vs−
Execute the calculation of Vrc. That is, the second arithmetic circuit 48a includes an adder and a subtractor, and subtracts the converter voltage command value Vrc from the value obtained by adding the square wave voltage Vs to the inverter voltage command value Vri. It should be noted that the order of addition and subtraction is reversed so that V
It can also be ri−Vrc + Vs. The second arithmetic circuit 48a has a function of automatically selecting the high-frequency on / off operation or the low-frequency on / off operation of the fifth and sixth switches Q5 and Q6 in response to a change in the inverter voltage command value Vri. Have.

The first limiter 50a is connected to the first arithmetic circuit 4
7a is limited to the range of the high level + Vs and the low level -Vs of the square wave voltage Vs, and the first switch control command value V
Outputs r1. Vr1 is the input stage switch Q1, Q2
Of the generated voltage command value.

The second limiter 51a is connected to the second arithmetic circuit 4
8a is limited to the range of the high level + Vs and the low level -Vs of the square wave voltage Vs, and the second switch control command value V
Outputs r3. Note that Vr3 can also be referred to as a generated voltage command value of the output stage switches Q5 and Q6.

The third arithmetic circuit 49a is connected to the inverter voltage command value generating means 45 and the second limiter 51,
The calculation of Vr3-Vri is executed. That is, the third arithmetic circuit 4
9a is a subtractor, which is a second switch control command value Vr3.
Is subtracted from the inverter voltage command value Vri to generate a capacitor voltage and power factor improvement command value Vr2. Note that Vr2 can also be referred to as a generated voltage command value of the intermediate switches Q3 and Q4. The voltage of the fundamental wave at the interconnection point 8 of the first and second switches Q1 and Q2 is set to V1 'and the third and fourth switches Q with reference to a half of the voltage Vc of the capacitor C.
The voltage of the fundamental wave at the interconnection point 9 between the third and Q4 is V2 ′, the fifth
V1 ′, V2 ′, V
The relationship between 3 ′ and the switch control command values Vr1, Vr2, Vr3 is as follows: V1 ′ = (Vc / 2) Vr1, V2 ′ = (Vc / 2) Vr2, V3 ′ = (Vc / 2) Vr3, Vinv = V3 '-V2', Vconv = V1'-V2 '.

The first comparator 53 is connected to the first limiter 50a and the triangular wave generator 52. The first comparator 53 compares the command value Vr1 with the triangular wave voltage Vt. Is output in binary format.

The second comparator 54 is connected to the third arithmetic circuit 49a and the triangular wave generator 52, compares the command value Vr2 with the triangular wave voltage Vt, and controls the line 14 to turn on / off the third switch Q3. Output the signal in binary format.

The third comparator 55 is connected to the second limiter 51a and the triangular wave generator 52. The third comparator 55 compares the command value Vr3 with the triangular wave voltage Vt, and outputs on line 16 the ON / OFF control signal for the fifth switch Q5. Is output in binary format.

According to the embodiment shown in FIG. 26, the mode can be easily switched. The control circuit 2a of the second embodiment shown in FIG.
The control circuit 2b of the third embodiment is replaced with the control circuit 2c of FIG.
It can also be transformed as follows.

[0082]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) In each embodiment, as shown in FIGS. 27D and 27E, in the non-conversion mode, the third and fourth switches Q3
, Q4 can be kept off. FIG.
(D) As shown by the dotted line in (E), in the non-conversion mode, the third and fourth switches Q3 and Q4 are the same as the first, second, fifth and sixth switches Q1, Q2, Q5 and Q6. Can be turned on and off at a low frequency (50 Hz). (2) The power conversion circuit 1 of FIG. 1, 12, or 23,
A plurality (for example, three) of 1a or 1b can be connected in parallel to form a multi-phase (for example, three-phase) power converter. (3) Inductor Lr and capacitor Cr and 2 shown in FIG.
A soft switching circuit comprising two switches Q7 and Q8, that is, a DC link circuit
Switches Q7, Q8, Q9 and diodes D11, D12
A soft switching circuit consisting of
It is connected between the output DC lines of the C-DC converter or between the input DC lines of the inverter, and the switch of the converter or the inverter can be soft-switched. That is, the soft switching circuit shown in FIG. 13 or FIG. 23 can be provided between a pair of DC lines of a general half-bridge type or full-bridge type converter or inverter. (4) When the parasitic capacitance between the first to sixth switches Q1 to Q6 or the pair of lines P1 and P2 is large in the power conversion circuit 1 of FIG. 1, the individual capacitor C is omitted and the parasitic capacitance is used as a capacitor. Can be. (5) In the power conversion circuits 1a and 1b of FIGS. 12 and 23, external capacitors are connected in parallel to the switches Q1 to Q6 instead of or in addition to the parasitic capacitances C1 to C6.
It can be used to reduce noise and switching loss at turn-off. (6) It is not configured to obtain all of the non-conversion mode, the step-down mode, and the step-up mode, but is configured to obtain two of the non-conversion mode and the step-down mode. To obtain two of
In addition, it can be configured to obtain two modes, a step-down mode and a step-up mode. (7) Many parts of the control circuits 2, 2a, 2b can be constituted by digital circuits. (8) In the first embodiment, between the ON periods of the first and second switches Q1 and Q2, the ON periods of the third and fourth switches Q3 and Q4, and the fifth and sixth switches Q
5. A dead time (pause period) may be provided between the ON periods of Q6 to prevent a short circuit due to storage.
Further, in the second embodiment, it is possible to provide a dead time between a pair of switches at the time of turn-on and turn-off in which all the switches Q1 to Q6 are not simultaneously turned on. (9) Any one or two of the reactors L1, L2, L3 can be omitted. (10) The conversion capacitor C can be used as a DC power supply. (11) Seventh to ninth switches of the second and third embodiments
The ON / OFF timing of Q7 to Q9 can be determined based on a comparison between the triangular wave voltage Vt and the voltage level crossing the triangular wave voltage Vt, without being determined by a timer or a variable timer.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a power converter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a control circuit of FIG. 1;

FIG. 3 is an equivalent circuit diagram of the conversion circuit of FIG.

FIG. 4 is a waveform diagram showing a power supply voltage in a non-conversion mode and ON / OFF states of first to sixth switches.

FIG. 5 is a waveform diagram showing a power supply voltage in a step-down mode and ON / OFF states of first to sixth switches.

FIG. 6 is a waveform diagram showing a power supply voltage in a boost mode and ON / OFF states of first to sixth switches.

FIG. 7 is a waveform diagram showing inputs and outputs of the square wave generator of FIG. 2;

8 is a waveform diagram showing an input of a third comparator of FIG. 2 and an on / off state of fifth and sixth switches in a step-down mode.

FIG. 9 is a waveform diagram showing a relationship between a triangular wave voltage and an input of each comparator in a non-conversion mode.

FIG. 10 is a waveform chart showing a relationship between a triangular wave voltage and an input of each comparator in a step-down mode.

FIG. 11 is a waveform chart showing a relationship between a triangular wave voltage and an input of each comparator in a boost mode.

FIG. 12 is a circuit diagram illustrating a power converter according to a second embodiment.

FIG. 13 is a block diagram showing the control circuit of FIG. 12 in detail.

FIG. 14 is a block diagram illustrating a timing adjustment circuit connected to the comparator and the negative-phase signal forming circuit of FIG. 13;

FIG. 15 is a block diagram showing a switch Q7, Q8 control circuit of FIG. 13;

FIG. 16 is a block diagram showing a low-frequency on / off pulse forming circuit of FIG. 15;

FIG. 17 is a block diagram showing a high-frequency on / off pulse forming circuit of FIG. 15;

FIG. 18 is a waveform chart showing an input voltage and control signals of first to eighth switches in a non-conversion mode according to the second embodiment.

FIG. 19 is a waveform diagram showing an input voltage in a step-down mode according to the second embodiment and the state of each part in FIG. 14;

FIG. 20 is a waveform chart showing inputs of a third comparator and control signals of fifth to eighth switches in a step-down mode according to the second embodiment.

FIG. 21 is a diagram illustrating a time t1 in FIG. 20 in the step-down mode according to the second embodiment.
FIG. 9 is a waveform diagram showing voltage changes and resonance currents of the switches Q1 to Q8 from to t7.

FIG. 22 shows each switch Q in the boost mode of the second embodiment.
FIG. 22 is a waveform chart showing 1 to Q8 and a resonance current in the same manner as in the period from t1 to t7 in FIG. 21.

FIG. 23 is a circuit diagram showing a power converter according to a third embodiment.

FIG. 24 shows a switch Q included in the control circuit of FIG. 23;
7 is a block diagram showing a Q8, Q9 control circuit. FIG.

FIG. 25 shows the input of the first comparator and the switches Q2, Q1, Q7, and Q8 in the boost mode of the third embodiment.
, And Q9 are control signal waveforms.

FIG. 26 is a block diagram illustrating a control circuit according to a fourth embodiment.

FIG. 27 is a waveform diagram showing an input voltage and control signals of switches Q1 to Q6 in a modified example of the power converter of the first embodiment.

[Explanation of symbols]

 1, 1a, 1b Power conversion circuit 2, 2a, 2b Control circuit Q1 to Q9 Switch C capacitor L1 to L3 Reactor Lr Resonance inductor Cr Resonance capacitor

Claims (8)

[Claims] 1. A power conversion circuit comprising a power conversion circuit and a control circuit for the conversion circuit, wherein the power conversion circuit is connected to one end of an AC power supply.
AC power supply terminal and a second terminal connected to the other end of the AC power supply.
2 AC power terminal, a first series circuit in which first and second switches are connected in series, and a circuit in which third and fourth switches are connected in series, and the first series circuit A second series circuit connected in parallel to the second circuit, a fifth and a sixth switch are circuits connected in series, and a second series circuit connected in parallel to the first and second series circuits. 3, a capacitor or a DC power supply connected in parallel to the first, second, and third series circuits, and an output unit, while the first and second switches are connected. A point is connected to the first AC power supply terminal, a connection midpoint between the third and fourth switches is connected to the second AC power supply terminal, and the output unit is connected to the fifth and sixth switches. For connecting a load between a connection midpoint and the second AC power supply terminal, wherein the control circuit comprises: A non-conversion mode for supplying an AC output voltage substantially equal to a voltage to the load, a step-down mode for supplying an AC output voltage lower than the voltage of the AC power supply to the load, and an AC output higher than the voltage of the AC power supply. The first and second modes for selectively obtaining at least two modes of a boost mode for supplying a voltage to the load.
In the power conversion device for controlling the second, third, fourth, fifth and sixth switches, the input current and the first and second AC on the power supply side of the first and second switches. Phase difference signal forming means for forming a signal indicating a phase difference with an input voltage between power supply terminals, and controlling the third and fourth switches so as to reduce the phase difference based on the signal indicating the phase difference And a switch control circuit. 2. A power conversion circuit comprising: a power conversion circuit; and a control circuit for the conversion circuit, wherein the power conversion circuit is connected to one end of an AC power supply.
AC power supply terminal and a second terminal connected to the other end of the AC power supply.
2 AC power terminal, a first series circuit in which first and second switches are connected in series, and a circuit in which third and fourth switches are connected in series, and the first series circuit A second series circuit connected in parallel to the second circuit, a fifth and a sixth switch are circuits connected in series, and a second series circuit connected in parallel to the first and second series circuits. 3, a capacitor or a DC power supply connected in parallel to the first, second, and third series circuits, and an output unit, while the first and second switches are connected. A point is connected to the first AC power supply terminal, a connection midpoint between the third and fourth switches is connected to the second AC power supply terminal, and the output unit is connected to the fifth and sixth switches. For connecting a load between a connection midpoint and the second AC power supply terminal, wherein the control circuit comprises: A non-conversion mode for supplying an AC output voltage substantially equal to a voltage to the load, a step-down mode for supplying an AC output voltage lower than the voltage of the AC power supply to the load, and an AC output higher than the voltage of the AC power supply. The first and second modes for selectively obtaining at least two modes of a boost mode for supplying a voltage to the load.
2, a third, fourth, fifth and sixth switches for controlling a DC voltage detection circuit for detecting the voltage of the capacitor or DC power supply, a reference voltage source for generating a reference voltage, A first subtractor that forms a signal corresponding to a difference between the DC voltage and the reference voltage, an input voltage detection circuit that detects an input voltage between the first and second AC power supply terminals, and the input voltage detection. A multiplier for multiplying an output of the first subtractor by an input voltage detected by a switch; a current detector for detecting an input current flowing to an input stage of the first and second switches; and A second subtractor for forming a signal indicating the difference between the output of the multiplier and the output of the multiplier; a triangular wave generator for generating a triangular wave voltage with a period sufficiently shorter than the period of the input voltage; The third switch is obtained by comparing the output of the subtractor with the triangular wave voltage. A comparator for forming an on / off control signal of the switch, and an anti-phase signal forming circuit for forming a signal having an opposite phase to the on / off control signal of the third switch for on / off control of the fourth switch. A power conversion device comprising: 3. A power conversion circuit comprising: a power conversion circuit; and a control circuit for the conversion circuit, wherein the power conversion circuit is connected to one end of an AC power supply.
AC power supply terminal and a second terminal connected to the other end of the AC power supply.
2 AC power terminal, a first series circuit in which first and second switches are connected in series, and a circuit in which third and fourth switches are connected in series, and the first series circuit A second series circuit connected in parallel to the second circuit, a fifth and a sixth switch are circuits connected in series, and a second series circuit connected in parallel to the first and second series circuits. 3, a conversion capacitor or a DC power supply connected in parallel to the first, second and third series circuits,
A parasitic capacitance or a capacitor connected in parallel to each of the first, second, third, fourth, fifth and sixth switches, and an output unit, and connection of the first and second switches. A middle point is connected to the first AC power supply terminal, a connection middle point of the third and fourth switches is connected to the second AC power supply terminal, and the output means is connected to the fifth and sixth switches. A load between the connection midpoint of the second AC power supply terminal and the second AC power supply terminal, wherein the control circuit supplies the load with an AC output voltage substantially equal to the voltage of the AC power supply. And a step-down mode in which an AC output voltage lower than the voltage of the AC power supply is supplied to the load, and a step-up mode in which an AC output voltage higher than the voltage of the AC power supply is supplied to the load. To selectively obtain the first and second
A power conversion device configured to control a second, a third, a fourth, a fifth, and a sixth switch, wherein a soft switching switch is connected in series to the conversion capacitor or the DC power supply; A soft switching circuit for selectively setting the voltage between both ends of the second and third series circuits to zero or almost zero is provided, wherein the first, second, third, fourth, fifth and sixth circuits are provided. A circuit for controlling the soft-switching switch to be in an off state for a predetermined period from immediately before the turn-on time of at least one of the switches to a predetermined time immediately after the turn-on time. Power converter. 4. A power conversion circuit comprising: a power conversion circuit; and a control circuit for the conversion circuit, wherein the power conversion circuit is connected to one end of an AC power supply.
AC power supply terminal and a second terminal connected to the other end of the AC power supply.
2 AC power terminal, a first series circuit in which first and second switches are connected in series, and a circuit in which third and fourth switches are connected in series, and the first series circuit A second series circuit connected in parallel to the second circuit, a fifth and a sixth switch are circuits connected in series, and a second series circuit connected in parallel to the first and second series circuits. 3, a conversion capacitor or a DC power supply connected in parallel to the first, second, and third series circuits, output means, and the first, second, third, fourth A parasitic capacitance or a capacitor connected in parallel to the fifth and sixth switches, and a connection midpoint between the first and second switches is connected to the first AC power supply terminal; And a connection midpoint of the fourth switch is connected to the second AC power supply terminal, and the output unit is configured to connect the fifth and sixth switches. A non-conversion mode for connecting a load between a point and the second AC power supply terminal, wherein the control circuit supplies the load with an AC output voltage substantially the same as the voltage of the AC power supply; At least two modes are selectively selected from a step-down mode in which an AC output voltage lower than the voltage of an AC power supply is supplied to the load and a step-up mode in which an AC output voltage higher than the voltage of the AC power supply is supplied to the load. In order to get the first, second
In a power converter configured to control the second, third, fourth, fifth and sixth switches, a seventh switch is provided in parallel with the first, second and third series circuits. A series circuit of a resonance inductor and a resonance capacitor is connected through the switch, an eighth switch is connected in series to the conversion capacitor, and the first, second, third, fourth, fifth, and fifth switches are connected to each other. The seventh switch is turned on for a predetermined period from immediately before the turn-on time of at least one of the six switches to a predetermined time immediately after the turn-on time. Turning off the eighth switch between the turn-on time of one switch and the turn-on control of the eighth switch after the turn-on time of the at least one switch; and Power converter, wherein the switch control circuit is provided to turn off control 7 of the switch. 5. A power conversion circuit comprising: a power conversion circuit; and a control circuit for the conversion circuit.
AC power supply terminal and a second terminal connected to the other end of the AC power supply.
2 AC power terminal, a first series circuit in which first and second switches are connected in series, and a circuit in which third and fourth switches are connected in series, and the first series circuit A second series circuit connected in parallel to the second circuit, a fifth and a sixth switch are circuits connected in series, and a second series circuit connected in parallel to the first and second series circuits. 3, a conversion capacitor or a DC power supply connected in parallel to the first, second, and third series circuits, output means, and the first, second, third, fourth A parasitic capacitance or a capacitor connected in parallel to the fifth and sixth switches, and a connection midpoint between the first and second switches is connected to the first AC power supply terminal; And a connection midpoint of the fourth switch is connected to the second AC power supply terminal, and the output unit is configured to connect the fifth and sixth switches. A non-conversion mode for connecting a load between a point and the second AC power supply terminal, wherein the control circuit supplies the load with an AC output voltage substantially the same as the voltage of the AC power supply; At least two modes are selectively selected from a step-down mode in which an AC output voltage lower than the voltage of an AC power supply is supplied to the load and a step-up mode in which an AC output voltage higher than the voltage of the AC power supply is supplied to the load. In order to get the first, second
A power converter configured to control the second, third, fourth, fifth and sixth switches, wherein a transformer having primary and secondary windings, and first, second and third transformers;
Soft switching switch, first and second soft switching diodes, and a switch control circuit are provided, and one end of the primary winding is connected to one end of the first, second, and third series circuits. The first soft-switching switch is connected between the other end of the primary winding and the other end of the first, second, and third series circuits; and The switch is the first,
The third soft switching switch is connected between one end of the second and third series circuits and one end of the conversion capacitor or the DC power supply, and the third soft switching switch is connected to one end of the conversion capacitor or the DC power supply and the secondary winding. And the second soft switching diode is connected between the other end of the secondary winding and one end of the conversion capacitor or the DC power supply. Is connected between the other end of the conversion capacitor or the DC power supply and the other end of the secondary winding, the switch control circuit, the first, second, third, fourth, fourth
Turning on the first soft-switching switch for a first predetermined period from a predetermined time before a turn-on time of at least one of the fifth and sixth switches to a predetermined time at the turn-on time; The second soft switching switch is off-controlled during a second predetermined period from a substantially same time as the start of the first predetermined period to a time after the first predetermined period, and the first predetermined Power for controlling the third soft-switching switch to be turned on during a third predetermined period between the end of the period and the end of the second predetermined period. Conversion device. 6. The conversion circuit includes a reactor between a connection midpoint between the first and second switches and the first AC power supply terminal, and the control circuit controls the boost mode. The power conversion device according to claim 1, 2, 3, 4, or 5. 7. An AC / DC converter comprising a series circuit of first and second switches which are turned on and off in opposite directions and a conversion capacitor or a DC power supply connected in parallel to the series circuit.
A power converter for DC conversion or DC / AC conversion, comprising a parasitic capacitance or a capacitor connected in parallel to the first and second switches, and a first soft switching switch in parallel with the series circuit. A series circuit of a resonance inductor (Lr) and a resonance capacitor (Cr) is connected via (Q7), and a second circuit is connected in series with the conversion capacitor or the DC power supply (C).
And a switch (Q8) for soft switching is connected, and the first switch is turned on during a predetermined period from immediately before a turn-on time of at least one of the first and second switches to a predetermined time immediately after the turn-on time. A soft-switching switch (Q7) is turned on, and the second soft-switching switch (Q8) is turned on between the time when the first soft-switching switch (Q7) is turned on and the time when the at least one switch is turned on. ), A switch for turning off the second soft-switching switch (Q8) and turning off the first soft-switching switch (Q7) after turning on of the at least one switch. A power conversion device provided with a control circuit. 8. An AC / DC power supply having a series circuit of first and second switches that are turned on and off in opposite directions and a capacitor or a DC power supply (C) connected in parallel to the series circuit.
In a power converter for DC conversion or DC / AC conversion, a transformer (Tr) having primary and secondary windings (N1, N2)
And first, second and third soft switching switches (Q7, Q8, Q9), first and second soft switching diodes (D11, D12), and a switch control circuit, One end of a primary winding (N1) is connected to one end of the series circuit, and the first soft switching switch (Q7)
The second soft switching switch (Q8) is connected between the other end of the next winding (N1) and the other end of the series circuit, and the second soft switching switch (Q8) is connected to one end of the series circuit and the conversion capacitor or DC power supply (C ), And the third soft switching switch (Q9) is connected between one end of the conversion capacitor or DC power supply (C) and one end of the secondary winding (N2). The first soft switching diode (D11) is connected between the other end of the secondary winding (N2) and one end of the conversion capacitor or DC power supply (C), The switching diode (D12) is connected between the other end of the conversion capacitor or the DC power supply (C) and the other end of the secondary winding (N2), and the switch control circuit includes the first and second switches. When at least one of the two switches is turned on First from an earlier predetermined time to a predetermined time of turn-on time
The first soft start switch (Q
7) is turned on, and a second soft-switching switch (a second soft-switching switch (b) is provided in a second predetermined period from substantially the same time as the beginning of the first predetermined period to a time later than the first predetermined period. Q8) is turned off, and the third soft switching switch (Q9) is turned off in a third predetermined period between the end of the first predetermined period and the end of the second predetermined period.
Characterized in that it is configured to turn on the power.