CN105406747A - NPC three-level inner tube lossless voltage-sharing clamping circuit - Google Patents
NPC three-level inner tube lossless voltage-sharing clamping circuit Download PDFInfo
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- CN105406747A CN105406747A CN201510985364.4A CN201510985364A CN105406747A CN 105406747 A CN105406747 A CN 105406747A CN 201510985364 A CN201510985364 A CN 201510985364A CN 105406747 A CN105406747 A CN 105406747A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
Abstract
The invention discloses an NPC three-level inner tube lossless voltage-sharing clamping circuit. The clamping circuit comprises a power frequency first half period and a power frequency second half period consisting of an IGBT, a diode, a capacitor and a resistor with a symmetrical structure; the IGBT comprises a first IGBT, a second IGBT, a third IGBT and a fourth IGBT, wherein the first IGBT and the second IGBT are in the power frequency first half period; the third IGBT and the fourth IGBT are in the power frequency second half period; the first IGBT and the fourth IGBT are connected with a bus separately; when the second IGBT is in a breakover state, the first IGBT is in an instant switch-on state, the third IGBT is switched off, and the third IGBT and the fourth IGBT bear all bus voltage Vin; when the second IGBT is a breakover state, the first IGBT is in a switch-off state; and one diode and one IGBT are in the breakover state in each of the power frequency first half period and/or the power frequency second half period to form zero level. According to the NPC three-level inner tube lossless voltage-sharing clamping circuit, two inner tubes can be dynamically clamped to enable the voltage of the two inner tubes not to exceed +10% of half of the bus voltage, so as to achieve the purpose of restraining the switch-off voltage peak of the inner tube in a lossless manner.
Description
Technical field
The invention belongs to power electronics tri-level inversion clamper resist technology field, especially design the clamp circuit of pipe in a kind of three level two.
Background technology
Existing NPC tri-level circuit only has two outer tube Q1, Q4 has done clamper protection, it is that when utilizing inner and outer pipes parameter more consistent, two outer tubes first turn off and first bear more back-pressure, and turn off after pipe in two, interior pipe nature bears less voltage stress than outer tube so need not clamper protect, but the parameter of inner and outer pipes is always variant in actual motion, especially along with the operation of equipment, device aging, this species diversity can be increasing, to such an extent as to there is abnormal due to voltage spikes when turning off in the interior pipe not doing clamper protection, the due to voltage spikes that time serious, this turns off reaches the puncture voltage of IGBT pipe, IGBT is caused to puncture, thus burn whole IGBT module.
Summary of the invention
In view of the above-mentioned problems in the prior art, main purpose of the present invention is to provide pipe in a kind of NPC three level can't harm and all presses clamp circuit, solves the defect that in NPC tri-level circuit, pipe is protected without clamper, increases the reliability of product.When NPC tri-level circuit inner and outer pipes parameter has larger difference, manage in dynamic clamp two, make it be no more than+10% of the half of busbar voltage, reach the object of pipe shutoff voltage spike in harmless the suppression.
The technical solution used in the present invention is as follows:
In a kind of NPC three level, pipe is harmless all presses clamp circuit, comprise the power frequency upper half and the power frequency lower half that are made up of symmetrical configuration IGBT, diode, electric capacity and resistance, IGBT comprises an IGBT, the 2nd IGBT, the 3rd IGBT and the 4th IGBT, wherein, one IGBT and the 2nd IGBT is in power frequency upper half, 3rd IGBT and the 4th IGBT is in power frequency lower half, and an IGBT and the 4th IGBT is connected to bus; " the interior pipe shutoff peak voltage absorbing circuit " of shared two electric capacity is also comprised, " energy can't harm feedback loop " and " initial pre-charge circuit " in power frequency upper half and power frequency lower half; When the 2nd IGBT conducting, when an IGBT is in moment opening state, the 3rd IGBT turns off, and the 3rd IGBT and the 4th IGBT bears whole busbar voltage Vin; When the 2nd IGBT conducting, when an IGBT is in off state, power frequency upper half is or/and all have a diode and an IGBT conducting to form zero level in power frequency lower half.
Further, interior pipe turn off peak voltage absorbing circuit by diode seven D7, electric capacity three C3 of power frequency upper half and electric capacity four C4 of power frequency lower half and diode nine D9 in series; Diode eight D8, electric capacity three C3, electric capacity four C4 and diode ten D10 energy in series can't harm feedback loop; Resistance one R1, electric capacity three C3, electric capacity four C4 and resistance two R2 initial pre-charge circuit in series;
Further, power frequency upper half specifically comprises electric capacity one C1 being connected to bus input one, bus input one is also connected with an IGBT, diode one D1, diode eight D8 and resistance one R1, concrete, one IGBT is connected with bus high level end BUS+ by its collector electrode C, and diode one D1 is all connected with bus input one by its negative pole with diode eight D8; The free end of electric capacity one C1 is also connected with diode five D5 and diode seven D7 in turn, concrete, and in the same way, and diode five D5's diode five D5 and diode seven D7 is connected with the free end of electric capacity one C1 by its positive pole; The emitter E of the one IGBT and the positive pole of diode one D1 are all connected between diode five D5 and diode seven D7, form the common port A1 of an IGBT, diode one D1, diode five D5 and diode seven D7, the positive pole of diode eight D8 and the free end of resistance one are all connected to the negative pole of diode seven D7, form the common port B1 of diode seven D7, diode eight D8 and resistance one R1; Common port A1 is also connected with diode two D2 and the 2nd IGBT, concrete, and the 2nd IGBT is connected with the emitter E of an IGBT by its collector electrode C, and diode two D2 is connected to common port A1 by its negative pole; Common port B1 is also connected with electric capacity three C3, and the positive pole of the free end of electric capacity three C3 and the emitter E of the 2nd IGBT and diode two D2 is connected together, and forms the common port P1 of the 2nd IGBT, diode two D2 and electric capacity three C3;
Power frequency lower half specifically comprises electric capacity two C2 being connected to bus input two, and electric capacity two C2 is connected with electric capacity one C1, for ZERO holds between electric capacity one C1 and electric capacity two C2; Bus input two is also connected with the 4th IGBT, diode four D4, diode ten D10 and resistance two R2, concrete, 4th IGBT is connected with bus input two by its emitter E, and diode four D4 is all connected with bus input two by its positive pole with diode ten D10; The common port of electric capacity two C2 and electric capacity one C1 is also connected with diode six D6 and diode nine D9 in turn, concrete, and in the same way, and diode six D6 is connected between electric capacity two C2 and electric capacity one C1 by its negative pole diode six D6 and diode nine D9; The collector electrode C of the 4th IGBT and the negative pole of diode four D4 are all connected between diode six D6 and diode nine D9, form the common port A2 of the 4th IGBT, diode four D4, diode six D6 and diode nine D9, the negative pole of diode ten D10 and the other end of resistance two are all connected to the negative pole of diode nine D9, form the common port B2 of diode nine D9, diode ten D10 and resistance two R2; Common port A2 is also connected with diode three D3 and the 3rd IGBT, concrete, and the 3rd IGBT is connected with the collector electrode C of the 4th IGBT by its emitter E, and diode three D3 is connected to common port A2 by its positive pole; Common port B2 is also connected with electric capacity four C4, and the negative pole of the free end of electric capacity four C4 and the collector electrode C of the 3rd IGBT and diode three D3 is connected together, and forms the common port P2 of the 3rd IGBT, diode three D3 and electric capacity four C4; Common port P1 and common port P2 is connected together and forms output (OUTX).
In sum, compared with prior art, the invention has the beneficial effects as follows:
The present invention adopts symmetrical power frequency upper half and power frequency lower half, and power frequency upper half and power frequency lower half only by IGBT, diode, electric capacity and resistance form above-mentioned in pipe turns off peak voltage absorbing circuit, energy can't harm feedback loop and initial pre-charge circuit, effectively can solve the problem that in NPC three level brachium pontis two, pipe wrench position is all pressed, improve the reliability of NPC tri-level circuit application.When NPC tri-level circuit inner and outer pipes parameter has a larger difference, manage in dynamic clamp two, make it be no more than+10% of the half of busbar voltage, reach the object of pipe shutoff voltage spike in harmless the suppression.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is schematic diagram of the present invention;
Fig. 2 is interior pipe wrench position principle of absorption figure of the present invention;
Fig. 3 is that Absorption Capacitance of the present invention can't harm feedback schematic diagram.
Embodiment
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
As shown in Figure 1: in a kind of NPC three level of the present invention, pipe is harmless all presses clamp circuit, in the present embodiment, comprise and be connected to bus high level end BUS+(bus input one) electric capacity one C1, bus high level end BUS+ is also connected with an IGBT(Q1), diode one D1, diode eight D8 and resistance one R1, concrete, one IGBT(Q1) be connected with bus high level end BUS+ by its collector electrode C, diode one D1 and diode eight D8 are all connected with bus high level end BUS+ by its negative pole; The low level end of electric capacity one C1 is also connected with diode five D5 and diode seven D7 in turn, concrete, and in the same way, and diode five D5's diode five D5 and diode seven D7 is connected with the low level end of electric capacity one C1 by its positive pole; One IGBT(Q1) emitter E and the positive pole of diode one D1 to be all connected between diode five D5 and diode seven D7 (the common port A1 forming an IGBT, diode one D1, diode five D5 and diode seven D7), the positive pole of diode eight D8 and the low level end of resistance one are all connected to the negative pole (forming the common port B1 of diode seven D7, diode eight D8 and resistance one R1) of diode seven D7;
One IGBT(Q1) emitter E (i.e. common port A1) be also connected with diode two D2 two IGBT(Q2 identical with another), concrete, 2nd IGBT(Q2) by its collector electrode C and an IGBT(Q1) emitter E be connected, diode two D2 is connected to common port A1 by its negative pole; Common port B1 is also connected with electric capacity three C3, the low level end of electric capacity three C3 and the 2nd IGBT(Q2) emitter E and the positive pole of diode two D2 be connected together (the common port P1 forming the 2nd IGBT, diode two D2 and electric capacity three C3);
Foregoing circuit forms power frequency upper half of the present invention, and the present invention also comprises a power frequency lower half, and the structure of power frequency lower half and upper half symmetry.
Electric capacity two C2 as shown in Figure 1: the circuit structure of power frequency lower half is as described below: comprise and be connected to bus low level end BUS-(bus input two), the high level end of electric capacity two C2 is connected to the low level end of electric capacity one C1, for ZERO holds between electric capacity one C1 and electric capacity two C2; Bus high level end BUS-is also connected with the 4th IGBT(Q4), diode four D4, diode ten D10 and resistance two R2, concrete, 4th IGBT(Q4) be connected with bus high level end BUS-by its emitter E, diode four D4 and diode ten D10 are all connected with bus high level end BUS-by its positive pole; The high level end of electric capacity two C2 is also connected with diode six D6 and diode nine D9 in turn, concrete, and in the same way, and diode six D6's diode six D6 and diode nine D9 is connected with the high level end of electric capacity two C2 by its negative pole; 4th IGBT(Q4) collector electrode C and the negative pole of diode four D4 to be all connected between diode six D6 and diode nine D9 (the common port A2 forming the 4th IGBT, diode four D4, diode six D6 and diode nine D9), the negative pole of diode ten D10 and the high level end of resistance two are all connected to the negative pole (forming the common port B2 of diode nine D9, diode ten D10 and resistance two R2) of diode nine D9;
4th IGBT(Q4) collector electrode (i.e. common port A2) be also connected with diode three D3 three IGBT(Q3 identical with another), concrete, 3rd IGBT(Q3) by its emitter E and the 4th IGBT(Q4) collector electrode C be connected, diode three D3 is connected to common port A2 by its positive pole; Common port B2 is also connected with electric capacity four C4, the high level end of electric capacity four C4 and the 3rd IGBT(Q3) collector electrode C and the negative pole of diode three D3 be connected together (the common port P2 forming the 3rd IGBT, diode three D3 and electric capacity four C4); Common port P1 and common port P2 is connected together and forms output (OUTX).The circuit that Q1, Q2, Q3 and Q4 grid G is separately connected is driving circuits, and (being prior art, as well known to those skilled in the art) omits.
See the dotted line frame of accompanying drawing 1 below, dotted line frame comprises three parts, Part I is that interior pipe turns off peak voltage absorbing circuit, and interior pipe turns off peak voltage absorbing circuit and comprises diode seven D7, diode nine D9 and Absorption Capacitance (electric capacity three C3, electric capacity four C4); Part II is that energy can't harm feedback loop, and energy can't harm feedback loop and comprises diode eight D8, diode ten D10 and Absorption Capacitance (electric capacity three C3, electric capacity four C4); Part III is initial pre-charge circuit, and initial pre-charge circuit comprises charging resistor (resistance one R1, resistance two R2) and Absorption Capacitance (electric capacity three C3, electric capacity four C4).
Below in conjunction with accompanying drawing 1 ~ 3, a brief description is done to general principle of the present invention.
The structure of power frequency lower half and upper half are symmetrical, to electric capacity three C3, electric capacity four C4 precharge when resistance one R1, resistance two R2 are for starting, make electric capacity three C3, electric capacity four C4 reaches Vin/2 voltage before inversion work.Resistance one R1, resistance two R2 value are comparatively large, and during work, power consumption is less.For the value of the elements such as resistance one R1, resistance two R2, those skilled in the art will know that how to choose suitable value, do not do concrete restriction herein.
Refer to accompanying drawing 2, in foregoing description, interior pipe shutoff peak voltage absorbing circuit can regard diode seven D7, electric capacity three C3 of power frequency upper half as and electric capacity four C4 of power frequency lower half and diode nine D9 is in series; In like manner, diode eight D8, electric capacity three C3, electric capacity four C4 and diode ten D10 energy in series can't harm feedback loop; Resistance one R1, electric capacity three C3, electric capacity four C4 and resistance two R2 initial pre-charge circuit in series.In power frequency upper half Q2 conducting always, when Q1 be in open instantaneously time, Q3 turns off, Q3, Q4 bears whole busbar voltage Vin, if Q3, all dynamic distributed parameter of Q4 are consistent, Q3, Q4 will divide equally busbar voltage, if but Q3, the dynamic distributed parameter of Q4 is inconsistent, Q3 will be caused, Q4 can not divide equally busbar voltage, speed is opened particularly as Q1, and the distributed inductance LF2(wiring distributed inductance that connects up is divided into wiring distributed inductance LF1 and wiring distributed inductance LF2, concrete, wiring distributed inductance LF1 to be in power frequency upper half between electric capacity one C1 and diode five D5, wiring distributed inductance LF2 to be in power frequency lower half between electric capacity two C2 and diode six D6) when can not ignore, higher peak voltage can be produced at Q3 two ends.After applying circuit of the present invention, excess energy, from electric capacity four C4, diode nine D9, the circulation of diode six D6 loop, is stored in electric capacity four C4, thus successfully inhibits the shutoff spike at Q3 two ends by electric current.
Refer to accompanying drawing 3, have no progeny when Q1 closes, Q2 is conducting still, load current flows out from diode five D5, Q2 of power frequency upper half and/or Q3, pole pipe six D6 of power frequency lower half, diode five D5, Q2 conducting and or Q3, pole pipe six D6 conducting, form zero level (i.e. the current potential of OUTX and ZERO hold current potential approximately equal), the unnecessary electric energy that electric capacity four C4 stores is just from diode ten D10, Q2, diode five D5, electric capacity two C2 loop, feed back in bus capacitor two C2, the voltage of electric capacity four C4 is clamped to Vin/2.
Therefore, circuit disclosed by the invention can solve the problem that in NPC three level brachium pontis two, pipe wrench position is all pressed effectively, improves the reliability of NPC tri-level circuit application.And method and apparatus disclosed by the invention has been applied in newly-designed APF100 harmonic compensation equipment and applies, respond well.
Description of the invention and application are illustrative, not want by scope restriction of the present invention in the above-described embodiments.Distortion and the change of embodiment disclosed are here possible, are known for the replacement of embodiment those those of ordinary skill in the art and the various parts of equivalence.Those skilled in the art are noted that when not departing from spirit of the present invention or substantive characteristics, and the present invention with other forms, structure, layout, ratio, and can realize with other elements, material and parts.
Claims (3)
1. in a NPC three level, pipe is harmless all presses clamp circuit, it is characterized in that, comprise the power frequency upper half and the power frequency lower half that are made up of symmetrical configuration IGBT, diode, electric capacity and resistance, IGBT comprises an IGBT, the 2nd IGBT, the 3rd IGBT and the 4th IGBT, wherein, one IGBT and the 2nd IGBT is in power frequency upper half, and the 3rd IGBT and the 4th IGBT is in power frequency lower half, and an IGBT and the 4th IGBT is connected to bus; " the interior pipe shutoff peak voltage absorbing circuit " of shared two electric capacity is also comprised, " energy can't harm feedback loop " and " initial pre-charge circuit " in power frequency upper half and power frequency lower half; When the 2nd IGBT conducting, when an IGBT is in moment opening state, the 3rd IGBT turns off, and the 3rd IGBT and the 4th IGBT bears whole busbar voltage Vin; When the 2nd IGBT conducting, when an IGBT is in off state, power frequency upper half is or/and all have a diode and an IGBT conducting to form zero level in power frequency lower half.
2. in a kind of NPC three level as claimed in claim 1, pipe is harmless all presses clamp circuit, it is characterized in that, interior pipe turn off peak voltage absorbing circuit by diode seven D7, electric capacity three C3 of power frequency upper half and electric capacity four C4 of power frequency lower half and diode nine D9 in series; Diode eight D8, electric capacity three C3, electric capacity four C4 and diode ten D10 energy in series can't harm feedback loop; Resistance one R1, electric capacity three C3, electric capacity four C4 and resistance two R2 initial pre-charge circuit in series.
3. in a kind of NPC three level as claimed in claim 1, pipe is harmless all presses clamp circuit, it is characterized in that, power frequency upper half specifically comprises electric capacity one C1 being connected to bus input one, bus input one is also connected with an IGBT, diode one D1, diode eight D8 and resistance one R1, concrete, one IGBT is connected with bus high level end BUS+ by its collector electrode C, and diode one D1 is all connected with bus input one by its negative pole with diode eight D8; The free end of electric capacity one C1 is also connected with diode five D5 and diode seven D7 in turn, concrete, and in the same way, and diode five D5's diode five D5 and diode seven D7 is connected with the free end of electric capacity one C1 by its positive pole; The emitter E of the one IGBT and the positive pole of diode one D1 are all connected between diode five D5 and diode seven D7, form the common port A1 of an IGBT, diode one D1, diode five D5 and diode seven D7, the positive pole of diode eight D8 and the free end of resistance one are all connected to the negative pole of diode seven D7, form the common port B1 of diode seven D7, diode eight D8 and resistance one R1; Common port A1 is also connected with diode two D2 and the 2nd IGBT, concrete, and the 2nd IGBT is connected with the emitter E of an IGBT by its collector electrode C, and diode two D2 is connected to common port A1 by its negative pole; Common port B1 is also connected with electric capacity three C3, and the positive pole of the free end of electric capacity three C3 and the emitter E of the 2nd IGBT and diode two D2 is connected together, and forms the common port P1 of the 2nd IGBT, diode two D2 and electric capacity three C3;
Power frequency lower half specifically comprises electric capacity two C2 being connected to bus input two, and electric capacity two C2 is connected with electric capacity one C1, for ZERO holds between electric capacity one C1 and electric capacity two C2; Bus input two is also connected with the 4th IGBT, diode four D4, diode ten D10 and resistance two R2, concrete, 4th IGBT is connected with bus input two by its emitter E, and diode four D4 is all connected with bus input two by its positive pole with diode ten D10; The common port of electric capacity two C2 and electric capacity one C1 is also connected with diode six D6 and diode nine D9 in turn, concrete, and in the same way, and diode six D6 is connected between electric capacity two C2 and electric capacity one C1 by its negative pole diode six D6 and diode nine D9; The collector electrode C of the 4th IGBT and the negative pole of diode four D4 are all connected between diode six D6 and diode nine D9, form the common port A2 of the 4th IGBT, diode four D4, diode six D6 and diode nine D9, the negative pole of diode ten D10 and the other end of resistance two are all connected to the negative pole of diode nine D9, form the common port B2 of diode nine D9, diode ten D10 and resistance two R2; Common port A2 is also connected with diode three D3 and the 3rd IGBT, concrete, and the 3rd IGBT is connected with the collector electrode C of the 4th IGBT by its emitter E, and diode three D3 is connected to common port A2 by its positive pole; Common port B2 is also connected with electric capacity four C4, and the negative pole of the free end of electric capacity four C4 and the collector electrode C of the 3rd IGBT and diode three D3 is connected together, and forms the common port P2 of the 3rd IGBT, diode three D3 and electric capacity four C4; Common port P1 and common port P2 is connected together formation output.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510985364.4A CN105406747B (en) | 2015-12-25 | 2015-12-25 | A kind of level inner tubes of NPC tri- are lossless to press clamp circuit |
| PCT/CN2016/077792 WO2017107332A1 (en) | 2015-12-25 | 2016-03-30 | Npc three-level inner tube lossless voltage-sharing clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510985364.4A CN105406747B (en) | 2015-12-25 | 2015-12-25 | A kind of level inner tubes of NPC tri- are lossless to press clamp circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105406747A true CN105406747A (en) | 2016-03-16 |
| CN105406747B CN105406747B (en) | 2018-03-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510985364.4A Active CN105406747B (en) | 2015-12-25 | 2015-12-25 | A kind of level inner tubes of NPC tri- are lossless to press clamp circuit |
Country Status (2)
| Country | Link |
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| CN (1) | CN105406747B (en) |
| WO (1) | WO2017107332A1 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017107332A1 (en) * | 2015-12-25 | 2017-06-29 | 成都麦隆电气有限公司 | Npc three-level inner tube lossless voltage-sharing clamp circuit |
| CN107947612A (en) * | 2017-12-25 | 2018-04-20 | 成都麦隆电气有限公司 | A kind of lossless soft breaking circuit of tri- level of NPC |
| CN109120142A (en) * | 2018-11-05 | 2019-01-01 | 宁波市北仑临宇电子科技有限公司 | The lossless synchronous absorbing circuit of peak voltage, boosting and step-down switching power supply circuit |
| CN109167526A (en) * | 2018-08-24 | 2019-01-08 | 成都麦隆电气有限公司 | A kind of highly reliable high frequency efficient NPC tri-level circuit |
| CN109889028A (en) * | 2019-03-29 | 2019-06-14 | 阳光电源股份有限公司 | A kind of Absorption Capacitance pre-charge circuit and peak voltage absorbing circuit |
| CN110474550A (en) * | 2019-08-21 | 2019-11-19 | 阳光电源股份有限公司 | A kind of striding capacitance type NPC three-level topology |
| CN110649831A (en) * | 2019-05-10 | 2020-01-03 | 阳光电源股份有限公司 | Shutdown wave-sealing control method of multi-level inverter circuit and application device thereof |
| CN113395003A (en) * | 2021-03-24 | 2021-09-14 | 中国人民解放军海军工程大学 | Multi-level active neutral point clamped inverter series IGBT voltage-sharing circuit |
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| CN105406747B (en) * | 2015-12-25 | 2018-03-20 | 成都麦隆电气有限公司 | A kind of level inner tubes of NPC tri- are lossless to press clamp circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017107332A1 (en) * | 2015-12-25 | 2017-06-29 | 成都麦隆电气有限公司 | Npc three-level inner tube lossless voltage-sharing clamp circuit |
| CN107947612A (en) * | 2017-12-25 | 2018-04-20 | 成都麦隆电气有限公司 | A kind of lossless soft breaking circuit of tri- level of NPC |
| CN109167526A (en) * | 2018-08-24 | 2019-01-08 | 成都麦隆电气有限公司 | A kind of highly reliable high frequency efficient NPC tri-level circuit |
| CN109120142A (en) * | 2018-11-05 | 2019-01-01 | 宁波市北仑临宇电子科技有限公司 | The lossless synchronous absorbing circuit of peak voltage, boosting and step-down switching power supply circuit |
| CN109889028A (en) * | 2019-03-29 | 2019-06-14 | 阳光电源股份有限公司 | A kind of Absorption Capacitance pre-charge circuit and peak voltage absorbing circuit |
| CN109889028B (en) * | 2019-03-29 | 2020-11-10 | 阳光电源股份有限公司 | Absorption capacitor pre-charging circuit and peak voltage absorption circuit |
| CN110649831A (en) * | 2019-05-10 | 2020-01-03 | 阳光电源股份有限公司 | Shutdown wave-sealing control method of multi-level inverter circuit and application device thereof |
| US11424694B2 (en) | 2019-05-10 | 2022-08-23 | Sungrow Power Supply Co., Ltd. | Method for controlling shutdown wave blocking of multilevel inverter circuit and application thereof |
| CN110474550A (en) * | 2019-08-21 | 2019-11-19 | 阳光电源股份有限公司 | A kind of striding capacitance type NPC three-level topology |
| CN113395003A (en) * | 2021-03-24 | 2021-09-14 | 中国人民解放军海军工程大学 | Multi-level active neutral point clamped inverter series IGBT voltage-sharing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105406747B (en) | 2018-03-20 |
| WO2017107332A1 (en) | 2017-06-29 |
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