WO2023019742A1

WO2023019742A1 - Fpga having automatic error checking and correcting function for programmable logic module

Info

Publication number: WO2023019742A1
Application number: PCT/CN2021/128310
Authority: WO
Inventors: 单悦尔; 徐彦峰; 范继聪; 井站
Original assignee: 无锡中微亿芯有限公司
Priority date: 2021-08-19
Filing date: 2021-11-03
Publication date: 2023-02-23
Also published as: CN113608918B; CN113608918A

Abstract

The present invention relates to the technical field of FPGAs, and disclosed is an FPGA having an automatic error checking and correcting function for a programmable logic module. The FPGA comprises a error checking and correcting device, a checking code generating circuit in the error checking and correcting device performs ECC encoding according to input data of a corresponding programmable logic register to generate a checking code, and the checking code is refreshed and written into a checking code register according to a clock signal. A checking circuit checks the output of the programmable logic register and the checking code register to generate a checking signal, so as to achieve verification, and a decoding circuit generates, according to the trigger enable pulse of a trigger circuit, a flipping signal corresponding to the checking signal to control a fault register to directly and asynchronously flipping content to achieve error correction. An error checking and correcting device may check and correct errors in real time of the programmable logic register in the normal operation process of the FPGA. Thus, reliability is higher, and compared to a triple module redundancy method, the described method greatly reduces the circuit area and is beneficial to improving circuit integration level.

Description

FPGA with automatic error detection and correction function for programmable logic modules

technical field

The invention relates to the field of FPGA technology, in particular to an FPGA with automatic error detection and correction functions for programmable logic modules.

Background technique

With the development of VLSI technology, FPGA chip (Field Programmable Gate Array, Field Programmable Gate Array) relies on its superior interface performance, rich logic and IP resources, and flexible and convenient field programmability. It has been more and more widely used and has become a key core device.

The reliability requirements of FPGA chips used in aerospace engineering are usually high, but space high-energy particles in the space radiation environment are likely to cause single-event upset (SEU, Single Event Upset) problems and cause circuit functions to malfunction. The method of Triple Module Redundant (TMR) combined with off-chip refresh is used to correct the configuration memory (CRAM, Configuration Random Access Memory) in the FPGA chip to improve reliability: use the TMR method to design the configuration memory All the data shift registers (DSR) and address shift registers (ASR), that is, one register is copied into three copies, and two out of three voting methods are adopted. When any register flips and an error occurs, and the other two registers output normally The register contents are still guaranteed to be correct. When an error occurs, rewrite the configuration bit stream to implement error correction.

However, the existing above-mentioned methods are usually only designed for reliability of the registers in the configuration memory, and the protection effect is relatively limited, and the TMR method needs to occupy a large circuit area, which is not conducive to the integration of the FPGA chip.

Contents of the invention

The inventor proposes a kind of FPGA with automatic error detection and correction function to the programmable logic module for above-mentioned problem and technical demand, technical scheme of the present invention is as follows:

An FPGA with automatic error detection and correction functions for programmable logic modules, the FPGA includes a programmable logic module and a check error corrector, the programmable logic module includes several programmable logic registers, each programmable logic register according to The clock signal refreshes and writes the obtained input data; the verification error corrector includes a verification code generation circuit, M verification code registers, a verification circuit, a decoding circuit and a trigger circuit:

The N input ends of the check code generating circuit are respectively connected to the input ends of the corresponding N programmable logic registers to obtain N input data, and the M output ends of the check code generating circuit are respectively connected to M check code registers, and the verification The code generation circuit performs ECC encoding on the N input data to generate M check codes, and each check code register refreshes and writes the corresponding check code according to the clock signal of the programmable logic register corresponding to the check error corrector;

The output ends of the N programmable logic registers and the M check code registers are connected to the input end of the verification circuit, and the output end of the verification circuit is connected to the input end of the decoding circuit to provide a verification signal, and the verification signal is used to indicate N Faulty registers with data errors in the +M registers;

The trigger circuit is connected to the enabling end of the decoding circuit, and the decoding circuit generates N+M flip signals with a predetermined pulse width corresponding to the verification signal according to the trigger enabling pulse of the trigger circuit, and outputs them to N programmable logic registers and M A check code register controls the fault register to directly flip the content asynchronously to correct errors.

Its further technical solution is that when the programmable logic register corresponding to the check and error corrector refreshes and writes the acquired input data according to the clock signal, the trigger circuit controls the decoding circuit to be in an invalid state for a predetermined duration.

Its further technical solution is that the predetermined duration of the decoding circuit being in the invalid state is longer than the delay between the input end of the verification circuit acquiring data and the output end of the decoding circuit generating a signal.

Its further technical solution is that the invalid duration is longer than the pulse width of the flip signal.

Its further technical solution is that there is at least a predetermined waiting period between the trigger enable pulses output by the trigger circuit, and the predetermined waiting period is longer than the period for which the verification error corrector updates the flip signal according to the error-corrected data.

Its further technical solution is that the verification error corrector further includes a timer, and the interval between the trigger enable pulses output by the trigger circuit is controlled by the timer.

Its further technical solution is that the N programmable logic registers corresponding to one check and error corrector are included in the same programmable logic module, or included in at least two different programmable logic modules.

Its further technical solution is that the N programmable logic registers corresponding to a check error corrector are controlled by the same clock signal;

Or, the N programmable logic registers corresponding to a parity error corrector are controlled by at least two different clock signals, then the parity error corrector works according to all clock signals.

Its further technical solution is that the N programmable logic registers corresponding to a check error corrector are all used to realize the user design, or part of the programmable logic registers are used to realize the user design, and are not used to realize the programmable logic registers of the user design. The input data to the programming logic register is always at an inactive level.

Its further technical solution is that the input data of the programmable logic register used to realize the user design comes from the inside and/or outside of the programmable logic module to which it belongs, and the input data from the inside of the programmable logic module is generated from the look-up table , at least one of a carry chain, a data selector and a flip-flop.

Its further technical solution is that the ECC code adopted by the check code generation circuit is a Hamming code, and the values of M and N conform to the coding rule of the corresponding digit Hamming code.

Its further technical solution is that when the FPGA does not enter the normal working mode because the power-on process of the FPGA is not completed, or the code stream configuration is not completed, or the initialization is not completed, the error correction device is in an invalid state; when the FPGA enters normal operation After the mode is checked, the error corrector performs verification and error correction.

The beneficial technical effect of the present invention is:

This application discloses an FPGA with automatic error detection and correction functions for programmable logic modules. The error correction device is used to detect and correct the programmable logic for the programmable logic registers in the programmable logic module, and the FPGA runs normally. During the process, the programmable logic register is updated in real time according to the clock signal, and the verification and error corrector can verify and correct the error in real time to ensure that the contents of the programmable logic register are correct. Moreover, this method greatly reduces the circuit area compared with the triple-mode redundancy method, and is beneficial to improving the circuit integration degree.

Description of drawings

FIG. 1 is a schematic diagram of the connection between the parity error corrector and the corresponding N programmable logic registers in the present application.

Fig. 2 is a schematic diagram of sources of input data of N programmable logic registers corresponding to an error checking and correcting device in an embodiment.

Detailed ways

The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

The present application discloses an FPGA with automatic error detection and correction function for programmable logic modules.

FPGA contains conventional programmable logic resources. Programmable logic resources inside FPGA mainly include programmable resources and interconnect resources. Programmable resources include programmable logic blocks (CLB), BRAM, IOB, DSP, and PC. Interconnect resources include winding resources. Boxes and interconnecting wires, etc. Each programmable logic module CLB includes a number of programmable logic registers, and in addition, usually includes a look-up table (LUT), a carry chain, a data selector, a flip-flop, and the like.

In addition to these conventional programmable logic resources, the FPGA of the present application has also designed a special check and error corrector corresponding to the programmable logic block (CLB), that is, additionally increased hardware resources, check and corrector The fault device is a hardware resource based on the production and implementation of conventional circuit components, so it can be realized by using a conventional FPGA production process.

As shown in FIG. 1 , the check error corrector includes a check code generating circuit, M check code registers REG2 , a check circuit, a decoding circuit and a trigger circuit. In FIG. 1 , M=4 is taken as an example. The N input terminals of the check code generation circuit are respectively connected to the input terminals of the corresponding N programmable logic registers REG1, as shown in Figure 1, taking N=8 as an example, the M output terminals of the check code generation circuit are respectively connected to M calibration registers. The output ends of the verification code register, the N programmable logic registers and the M verification code registers are all connected to the input end of the verification circuit, and the output end of the verification circuit is connected to the input end of the decoding circuit. The trigger circuit is connected to the enabling terminal of the decoding circuit, and the output terminal of the decoding circuit is connected to N programmable logic registers and M check code registers.

The check error corrector corresponds to the N programmable logic registers, and also corresponds to the programmable logic module to which the N programmable logic registers belong. In one embodiment, the N programmable logic registers corresponding to one check and error corrector are included in the same programmable logic module, and then one check and error corrector corresponds to one programmable logic module. In another embodiment, the N programmable logic registers corresponding to a check error corrector are included in at least two different programmable logic modules, and then a check error corrector corresponds to a plurality of different programmable logic modules , That is to say, multiple programmable logic modules can share a verification error corrector, which reduces the circuit area and also reduces the extra cost of the error correction function. On the other hand, the programmable logic register inside a programmable logic module corresponds to one parity error corrector, or corresponds to multiple parity error correctors.

During the operation of the FPGA, the N programmable logic registers corresponding to the verification error corrector refresh and write data according to the normal working process of the internal programmable logic registers of the programmable logic module, that is, the N programmable logic registers corresponding to the verification error corrector The programming logic register obtains the corresponding input signal from the input terminal, and then refreshes and writes the obtained input data according to the clock signal CLK. The so-called refreshing and writing according to the clock signal CLK generally refers to the rising or falling edge of the clock signal according to the actual configuration. When the input data is written into the programmable logic register, it remains until the next clock cycle is overwritten by new input data.

The input data of the N programmable logic registers corresponding to the check error corrector will be sent to the check error corrector, specifically sent to the input terminal of the check code generation circuit, and the N input terminals of the check code generation circuit will obtain After receiving N input data, perform ECC encoding on the N input data to generate M check codes. The values of M and N conform to the encoding rules of ECC encoding. In one embodiment, the ECC encoding adopted by the check code generation circuit is a Hamming code, and the values of M and N conform to the coding rules of the corresponding digit Hamming code, such as common N=8, M=4 so as to meet (8 , 4) the encoding rule of Hamming code, for example again N=4, M=3 meet the encoding rule of (4,3) Hamming code, for example again N=16, M=5 meet the encoding rule of (16,5) Hamming code . Since multiple CLBs can share a check error corrector, the actual effect can be that one CLB uses a check error corrector encoded with (8,4), and two CLBs share a check error corrector that uses (8+8,5) ) coded check error corrector, four CLBs share (8+8+8+8, 6) coded check error corrector and so on.

Each check code register refreshes and writes the corresponding check code according to the clock signal of the programmable logic register corresponding to the check error corrector, and the meaning of refreshing and writing the check code in the check code register is similar to that of the programmable logic register. That is, it is refreshed and written on the rising or falling edge of the clock signal, so the input data and the check code will be synchronously divided into the programmable logic register and the check code register respectively.

The signals at the output terminals of N programmable logic registers and the signals at the output terminals of M verification code registers form a total of N+M bit codes and are transmitted to the verification circuit. The verification circuit adopts a verification circuit that matches the ECC code. On the basis of plain code, the check circuit generally adopts a parity check circuit. The verification circuit generates a verification signal (Syndrome) according to the acquired N+M bit code. The verification signal is used to indicate a faulty register with data error in the N+M registers. The faulty register may be a programmable logic register or a The check code register, so that the function of check and error detection can be realized. It should be noted that Figure 1 only outputs the connection relationship between the circuits, but does not indicate the arrangement order of the N+M bit codes. The actual order of the bit codes in the N+M bit codes is determined according to the coding rule.

The decoding circuit can decode the verification signal to obtain the decoding result of N+M bits. Each bit of the decoding result corresponds to one of the N+M registers, and the decoding result of one bit corresponding to the fault register is an active level. The decoding results are all invalid levels. Typically, the invalid level is 0 and the active level is 1, and the active level can be used to flip the fault register. Because it is used to flip the fault register, due to circuit considerations, the trigger circuit at the enable end is used to control the waveform of the decoded signal, and the N+M bit decoding result is processed into a pulse form. The trigger circuit can use a common one-shot circuit, which defaults to 0 when it is not enabled. At this time, the decoding circuit outputs an invalid level, that is, all registers are not flipped. When it is enabled, the trigger circuit outputs a predetermined The trigger enable pulse of the pulse width enables the decoding circuit, so that the decoding circuit outputs N+M inversion signals with a predetermined pulse width corresponding to the verification signal, wherein one inversion signal corresponding to the fault register outputs an active level of a predetermined pulse width , and the rest of the flip signals continue to output invalid levels, so as to control the faulty registers in the N+M registers to directly flip the content asynchronously to correct errors, without waiting for the arrival of the clock signal, and realize the error correction of the faulty registers. Therefore, in this application, when error correction is performed on the fault register, the content of the error correction update is different from the data written by the clock signal, and it is not directly rewritten and refreshed. Wherein, there is at least a predetermined waiting period between the trigger enable pulses output by the trigger circuit, and the predetermined waiting period is longer than the time for which the check error corrector updates the flip signal according to the error-corrected data, so that the errors of the fault register can be corrected. The data has time to be transmitted to the verification and error corrector for re-verification and error correction, avoiding the situation where continuous pulses lead to continuous errors. A typical method can be controlled by a timer, and the error checking and correcting device further includes a timer, and the interval between the trigger enable pulses output by the trigger circuit is controlled by the timer.

In the above process, the verification error corrector also needs to avoid conflicts with the input data normally written in the clock cycle, then when the programmable logic register corresponding to the verification error corrector refreshes and writes the acquired input data according to the clock signal , the trigger circuit controls the decoding circuit to be in an invalid state for a predetermined period of time, so as to avoid conflicts between the inversion signal and the data written by the clock. In one embodiment, the predetermined duration of the decoding circuit being in the invalid state is longer than the delay between the input terminal of the verification circuit acquiring data and the output terminal of the decoding circuit generating a signal, that is, it is necessary to wait until the output of the verification error corrector is stable, When the output of the decoding circuit is unstable, the decoding result is messy and cannot be used to control the register, so it is necessary to wait until the output of the verification error corrector, that is, the output of the decoding circuit is stable. In another embodiment, the inactive time of the decoding circuit is longer than the pulse width of the toggle signal, so as to completely avoid conflicts.

As mentioned above, during the working process of the verification error corrector, the verification code register needs to refresh and write data according to the clock signal of the programmable logic register, and the trigger circuit also needs to control the decoding circuit to be invalid according to the clock signal to avoid conflicts, so the verification The error corrector works according to the clock signals of its corresponding N programmable logic registers. In one embodiment, the N programmable logic registers corresponding to one check and error corrector are controlled by the same clock signal, and then the check and error corrector works according to one clock signal. In another embodiment, the N programmable logic registers corresponding to a check and error corrector are controlled by at least two different clock signals, and then the check and error corrector works according to all clock signals, such as N programmable logic registers N1 of the programming logic registers are controlled by CLK1 and N2 are controlled by CLK2, then the check code register and the N1 programmable logic registers are refreshed and written according to CLK1, and the check code register is also connected with the N2 programmable logic registers Refresh and write together according to CLK2. Similarly, the trigger circuit controls the decoding circuit to be in an invalid state when CLK1 writes data to N1 programmable logic registers, and also controls the decoding circuit when CLK2 writes data to N2 programmable logic registers. is in an invalid state.

In the application process of the above method, the N programmable logic registers corresponding to a check error corrector are all used to realize the user design, or part of the programmable logic registers are used to realize the user design, and are not used to realize the user design. The input data of the programmable logic register is always at an invalid level, that is, connected to 0, which does not affect the realization of the above error detection and correction process.

The input data of the programmable logic register used to realize the user design comes from the inside and/or outside of the programmable logic module to which it belongs, and the input data from the inside of the programmable logic module is generated from the look-up table, the carry chain, and the data selector And at least one of the flip-flops, the source of the input data of the N programmable logic registers can be the same or different, that is, the input data of some programmable logic registers can come from the outside of the programmable logic module where they are located, and some can be programmed The input data of the logic register comes from an internal look-up table, some from another internal look-up table, some from the internal carry chain, and so on. In one embodiment, the input data of a programmable logic register comes from the outside of the programmable logic module or the look-up table, then the input end of the programmable logic register is connected to the module input port and the look-up table output of the programmable logic module, And through the configuration bits to select the actual selected input data. As shown in Figure 2, the eight programmable logic registers are all located in the same programmable logic module, and there are eight six-input look-up tables LUT6-0~LUT6-7 in the programmable logic module, and the inputs of each look-up table are respectively There are 8 groups of signals A, B, C, D, E, F, G, and H. The width of each group of signals is 6 bits, and the output of each lookup table is L0~L7. The input data of 8 programmable logic registers There are two sources of r0~r7, one is the input X0~X7 of the input port of the module, and the other is the output L0~L7 of each look-up table. The input of each programmable logic register can be independently selected through the configuration bits.

In actual application, when the power-on process of the FPGA is not completed, or the configuration of the code stream is not completed, or the initialization is not completed, so that the FPGA does not enter the normal working mode, the check error corrector is in an invalid state. When the FPGA enters the normal working mode, the verification error corrector starts to work, and performs verification and error correction according to the method described above.

In one example, the check error corrector corresponds to 8 programmable logic registers. On the basis of using (8.4) Hamming code, the check code generation circuit performs input data r0, r1, r2, r3, r4, r5, r6, r7 generate 4 check codes p1, p2, p4, p8, 8 input data and 4 check codes to form a 12-bit code as {c1, c2, c3, c4, c5, c6,c7,c8,c9,c10,c11,c12}, its composition is {p1,p2,r0,p4,r1,r2,r3,p8,r4,r5,r6,r7}, namely c1=p1 , c2=p2, c3=r0, c4=p4, c5=r1, c6=r2, c7=r3, c8=p8, c9=r4, c10=r5, c11=r6, c12=r7. During encoding, the method of generating 4 check codes is: select p1 so that the result of XOR(c1,c3,c5,c7,c9,c11) is 0 (even number), that is, p1=c1=XOR(c3,c5, c7, c9, c11), select p2 so that the result of XOR (c2, c3, c6, c7, c10, c11) is 0 (even number), that is, p2 = c2 = XOR (c3, c6, c7, c10, c11) , choose p4 so that the result of XOR(c4,c5,c6,c7,c12) is 0 (even number), that is, p4=c4=XOR(c5,c6,c7,c12), choose p8 so that XOR(c8,c9, The result of c10, c11, c12) is 0 (even number), that is, p8=c8=XOR(c9, c10, c11, c12). This 12-bit code is written into the register under the control of the clock signal.

When verifying and correcting, check the written 12-bit code {c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12}, the output of the programmable logic register Q0, Q1 ,Q2,Q3,Q4,Q5,Q6,Q7 and the output P1,P2,P4,P8 of the check register, the composition of which is {P1,P2,Q0,P4,Q1,Q2,Q3,P8,Q4,Q5 , Q6, Q7}, namely c1=P1, c2=P2, c3=Q0, c4=P4, c5=Q1, c6=Q2, c7=Q3, c8=P8, c9=Q4, c10=Q5, c11= Q6, c12=Q7. At this time, P8, P4, P2, and P1 can be regarded as the verification signal (Syndrome). If these 4 bits are all 0, it means that all the contents are correct and error-free, otherwise the 4-bit signal indicates that there is a faulty register with data error, such as P8 , P4, P2, P1 = 0110 means that the register corresponding to c6 is wrong and is the fault register.

Input the verification signals P8, P4, P2, P1 to the 4 to 12-bit decoder, which generates {f0, f1, f2, f3, f4, f5, f6, f7, f8 under the action of the trigger enable pulse , f9, f10, f11}, only one bit of the flip signal corresponding to the fault register is at high level, and the rest are all 0. For example, in the above example, c6 corresponds to the fault register, and the output flip signal has only the corresponding bit of f6 as 1, and the rest are 0, and the output flip signal is {0,0,0,0,0,0,1 ,0,0,0,0,0}.

Claims

An FPGA with automatic error detection and correction functions for programmable logic modules is characterized in that the FPGA includes a programmable logic module and a check error corrector, and the programmable logic module includes several programmable logic registers inside, Each of the programmable logic registers refreshes and writes the acquired input data according to the clock signal; the verification error corrector includes a verification code generating circuit, M verification code registers, a verification circuit, a decoding circuit and a trigger circuit :

The N input ends of the check code generation circuit are respectively connected to the input ends of the corresponding N programmable logic registers to obtain N input data, and the M output ends of the check code generation circuit are respectively connected to the M calibration registers. A check code register, the check code generation circuit performs ECC encoding on N input data to generate M check codes, each of the check code registers is based on the clock of the programmable logic register corresponding to the check error corrector The signal refreshes and writes the corresponding check code;

The output terminals of the N programmable logic registers and the M check code registers are connected to the input terminals of the verification circuit, and the output terminals of the verification circuit are connected to the input terminals of the decoding circuit to provide calibration. A check signal, the check signal is used to indicate that there is a faulty register with data error in the N+M registers;

The trigger circuit is connected to the enabling terminal of the decoding circuit, and the decoding circuit generates N+M inversion signals with a predetermined pulse width corresponding to the verification signal according to the trigger enabling pulse of the trigger circuit, and respectively Output to the N programmable logic registers and the M check code registers to control the fault registers to directly reverse the content asynchronously to correct errors.
FPGA according to claim 1, is characterized in that,

When the programmable logic register corresponding to the verification error corrector refreshes and writes the acquired input data according to the clock signal, the trigger circuit controls the decoding circuit to be in an invalid state for a predetermined duration.
FPGA according to claim 2, is characterized in that,

The predetermined time period during which the decoding circuit is in the invalid state is longer than the delay between when the input end of the verification circuit acquires data and when the output end of the decoding circuit generates a signal.
FPGA according to claim 2, is characterized in that,

The invalid duration is longer than the pulse width of the toggle signal.
FPGA according to claim 1, is characterized in that,

The trigger enable pulses output by the trigger circuit are at least separated by a predetermined waiting period, and the predetermined waiting period is longer than the period for which the verification error corrector updates the flip signal according to the error-corrected data.
FPGA according to claim 5, is characterized in that,

The verification error corrector further includes a timer, and the interval between the trigger enable pulses output by the trigger circuit is controlled by the timer.
FPGA according to claim 1, is characterized in that,

The N programmable logic registers corresponding to a parity and error corrector are contained in the same programmable logic module, or contained in at least two different programmable logic modules.
FPGA according to claim 1, is characterized in that,

The N programmable logic registers corresponding to a parity error corrector are controlled by the same clock signal;

Alternatively, the N programmable logic registers corresponding to a check and error corrector are controlled by at least two different clock signals, and the check and error corrector works according to all clock signals.
According to the arbitrary described FPGA of claim 1-8, it is characterized in that,

The N programmable logic registers corresponding to a check error corrector are all used to realize the user design, or part of the programmable logic registers are used to realize the user design, and the input data of the programmable logic registers that are not used to realize the user design are constant is an invalid level.
According to the described FPGA of claim 1-8, it is characterized in that,

The input data of the programmable logic register used to realize the user design comes from the inside and/or outside of the programmable logic module to which it belongs, and the input data from the inside of the programmable logic module is generated from the look-up table, the carry chain, and the data selector and at least one of triggers.
According to the arbitrary described FPGA of claim 1-8, it is characterized in that,

The ECC code adopted by the verification code generation circuit is a Hamming code, and the values of M and N conform to the coding rule of the corresponding digit Hamming code.
According to the arbitrary described FPGA of claim 1-8, it is characterized in that,

When the power-on process of the FPGA is not completed, or the code stream configuration is not completed, or the initialization is not completed so that the FPGA does not enter the normal operating mode, the verification error corrector is in an invalid state; when the FPGA enters the normal After the working mode, the verification and error corrector performs verification and error correction.