CN110727543A

CN110727543A - Commercial asymmetric cryptographic algorithm hardware module

Info

Publication number: CN110727543A
Application number: CN201910885731.1A
Authority: CN
Inventors: 高金超; 杨晓龙
Original assignee: 707th Research Institute of CSIC
Current assignee: 707th Research Institute of CSIC
Priority date: 2019-09-19
Filing date: 2019-09-19
Publication date: 2020-01-24

Abstract

The invention relates to a commercial asymmetric cryptographic algorithm hardware module, which is technically characterized in that: the system comprises a check code generation module, an error positioning module and a finite state control logic module which are arranged on an FPGA (field programmable gate array), wherein the modules are connected with an NAND Flash main controller and an NAND Flash chip, read-write signals and data are captured through a control line and a data line, and the ECC (error correction code) check function is enabled and disabled by setting or resetting a corresponding register. The invention has reasonable design, adopts an FPGA hardware structure, realizes the ECC function by the mutual matching of the check code generating module, the error positioning module and the finite state control logic module with the NAND Flash main controller and the NAND Flash chip, has good error correction capability, remarkably improves the read-write performance of the storage system, and can be widely applied to a large-capacity solid-state memory.

Description

Commercial asymmetric cryptographic algorithm hardware module

Technical Field

The invention belongs to the technical field of large-capacity solid-state memories, and particularly relates to a commercial asymmetric cryptographic algorithm hardware module.

Background

In recent years, in high-speed data exchange devices, solid-state memories have been increasingly used because they can perform very fast data exchange at high frequencies because they use transistors to store data. The problem of data dislocation exists in the use process of the large-capacity solid-state memory. For the problem of data dislocation in a large-capacity solid-state memory, a software ECC model is usually used for checking and correcting, but the software ECC model is used for checking and correcting, which inevitably affects the read-write performance of the storage system.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a commercial asymmetric cryptographic algorithm hardware module which is reasonable in design, high in processing speed and stable in performance.

The technical problem to be solved by the invention is realized by adopting the following technical scheme:

a commercial asymmetric cryptographic algorithm hardware module comprises a check code generation module, an error positioning module and a finite state control logic module which are arranged on an FPGA (field programmable gate array), wherein the modules are connected with a NAND Flash main controller and a NAND Flash chip, read-write signals and data are captured through a control line and a data line, and the ECC (error correction code) check function is enabled and disabled by setting or resetting a corresponding register.

The ECC check code generation module divides each page of data with the size of 4KB into 8 groups of 512-byte data blocks, each group corresponds to 3-byte parity check codes, 8 registers with the size of 3 bytes in the check code generation module update parity check values in a response mode according to the sent address and data, and finally the ECC check code is generated.

When the NAND Flash chip is read, the first 4KB data read out by the error positioning module is recalculated by the ECC check code generation module, and finally 24 bytes are shifted by the error positioning module and stored in the ECC storage value register, and compared with the ECC calculated value newly generated by the ECC check code generation module, whether a data bit has an error is judged, and the type and the position of the error are stored in the error information register.

The finite state control logic module controls the working time sequence of the check code generation module and the error positioning module, and simultaneously outputs a state signal according to the current state information.

The invention has the advantages and positive effects that:

the invention adopts FPGA hardware structure, realizes ECC function by the mutual cooperation of the check code generation module, the error positioning module and the finite state control logic module with the NAND Flash main controller and the NAND Flash chip, has good error correction capability, remarkably improves the read-write performance of the storage system, and can be widely used in large-capacity solid-state memories.

Drawings

FIG. 1 is a schematic structural view of the present invention;

Detailed Description

The following describes the embodiments of the present invention in detail with reference to the accompanying drawings.

A commercial asymmetric cryptographic algorithm hardware module is shown in figure 1 and comprises a check code generation module, an error positioning module and a finite state control logic module, wherein the modules are realized by an FPGA chip and connected with an NAND Flash main controller and an NAND Flash chip. The module captures read-write signals and data through a control line and a data line, enables and disables an ECC (error correction code) check function through setting or resetting a corresponding register, directly receives signals of the NANDFlash main controller and transmits the signals to the NAND Flash chip when the module does not need to work, intercepts control signals of the NAND Flash main controller when the module needs to work, analyzes and processes the control signals, and then transmits the control signals to the NANN Flash chip. The following explains three modules separately:

1. an ECC check code generation module: since the NAND Flash is performed by taking a page as a unit when data is read and written, the module is combined with an ECC (error correction code) checking algorithm to divide data with the size of 4KB on each page into 8 groups of 512-byte data blocks, and each group corresponds to 3-byte parity check codes. According to the sent address and data, 8 registers with the size of 3 bytes in the check code generation module update the parity check value in response, and finally generate the ECC check code.

2. An error positioning module: when the NAND Flash chip carries out reading operation, the read-out first 4KB data is recalculated with the ECC value by the ECC check code generation module. Finally, the 24 bytes are shifted and stored into an ECC storage value register by the error positioning module, compared with an ECC calculated value newly generated by the ECC check code generation module, whether a data bit has an error is judged, and the type and the position of the error are stored into an error information register.

3. A finite state control logic module: the ECC finite state control logic controls the working time sequence of the whole ECC functional module and outputs a state signal according to the current state information.

Nothing in this specification is said to apply to the prior art.

It should be emphasized that the embodiments described herein are illustrative rather than restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but also includes other embodiments that can be derived from the technical solutions of the present invention by those skilled in the art.

Claims

1. A commercial asymmetric cryptographic algorithm hardware module, comprising: the system comprises a check code generation module, an error positioning module and a finite state control logic module which are arranged on an FPGA (field programmable gate array), wherein the modules are connected with an NAND Flash main controller and an NAND Flash chip, read-write signals and data are captured through a control line and a data line, and the ECC (error correction code) check function is enabled and disabled by setting or resetting a corresponding register.

2. The commercial asymmetric cryptographic algorithm hardware module of claim 1, wherein: the ECC check code generation module divides each page of data with the size of 4KB into 8 groups of 512-byte data blocks, each group corresponds to 3-byte parity check codes, 8 registers with the size of 3 bytes in the check code generation module update parity check values in a response mode according to the sent address and data, and finally the ECC check code is generated.

3. The commercial asymmetric cryptographic algorithm hardware module of claim 1, wherein: when the NAND Flash chip is read, the first 4KB data read out by the error positioning module is recalculated by the ECC check code generation module, and finally 24 bytes are shifted by the error positioning module and stored in the ECC storage value register, and compared with the ECC calculated value newly generated by the ECC check code generation module, whether a data bit has an error is judged, and the type and the position of the error are stored in the error information register.

4. The commercial asymmetric cryptographic algorithm hardware module of claim 1, wherein: the finite state control logic module controls the working time sequence of the check code generation module and the error positioning module, and simultaneously outputs a state signal according to the current state information.