WO2022208616A1 - Common mode filter circuit - Google Patents

Common mode filter circuit Download PDF

Info

Publication number
WO2022208616A1
WO2022208616A1 PCT/JP2021/013316 JP2021013316W WO2022208616A1 WO 2022208616 A1 WO2022208616 A1 WO 2022208616A1 JP 2021013316 W JP2021013316 W JP 2021013316W WO 2022208616 A1 WO2022208616 A1 WO 2022208616A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
voltage
common mode
output
band
Prior art date
Application number
PCT/JP2021/013316
Other languages
French (fr)
Japanese (ja)
Inventor
将幸 大石
友一 坂下
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2023509929A priority Critical patent/JP7433516B2/en
Priority to PCT/JP2021/013316 priority patent/WO2022208616A1/en
Publication of WO2022208616A1 publication Critical patent/WO2022208616A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • This application relates to a common mode filter circuit.
  • a power electronics device equipped with a voltage-source power conversion circuit outputs a square-wave voltage by switching a power device, which is a semiconductor element, at high speed. to generate The path formed by the stray capacitance between the power conversion circuit and ground when the common mode voltage, defined as the average value of the voltage between the AC terminals of the power conversion circuit and ground (GND), which is the reference potential, fluctuates. That is, a common mode current flows through the common mode path. It is known that the common mode current causes an inductive failure and has adverse effects such as malfunctioning of electronic circuits around the power conversion circuit. Therefore, in order to reduce the common mode current, a common mode filter that offsets the common mode voltage by detecting the common mode voltage generated by the power conversion circuit and injecting a compensation voltage (injection voltage) with the opposite phase to the detected value. A circuit is proposed.
  • Patent Literature 1 discloses an active common canceller that cancels common mode voltages generated when power conversion is performed based on the switching operation of power semiconductor devices.
  • the active common canceller of Patent Document 1 detects a common mode voltage between the neutral point of three capacitors Y-connected to each phase of a three-phase AC wiring and the ground, and comprises a transistor and a power conversion circuit. Amplifies the common mode voltage detected by the push-pull circuit whose input side is used as the driving power supply, and outputs it to the primary winding (primary winding) of the common mode transformer via the capacitor.
  • the secondary winding (secondary winding) of the common mode transformer is connected to the three-phase AC wiring.
  • a push-pull circuit is, so to speak, an output voltage generation circuit that generates an output voltage to be output to a common mode transformer.
  • an active element with a large current capacity is used in the output voltage generation circuit because the excitation current increases. Is required. Since an active element with a large current capacity operates in a linear region, when a large current flows, the loss is large and heat is generated. Therefore, when the active common canceller of Patent Document 1 copes with the common mode voltage of the low frequency component, the cooling system of the active element becomes large due to the mounting of the active element having a large current capacity, and the device becomes large. There was a problem of becoming
  • the above-mentioned problem is caused by a large increase in the output current output from the output voltage generation circuit to the common mode transformer when dealing with the common mode voltage of the low frequency component. Therefore, even in the case of a common mode voltage with a low frequency component, by preventing a large increase in the output current output from the output voltage generation circuit to the common mode transformer, an active element with a large current capacity becomes unnecessary, and the current capacity is reduced. There are no problems associated with mounting large active devices.
  • An object of the technology disclosed in the specification of the present application is to provide a common mode filter circuit that prevents a large increase in the output current output from the output voltage generation circuit even in the case of a common mode voltage with a low frequency component. .
  • An example of the common mode filter circuit disclosed in the specification of the present application is a common mode filter circuit that reduces a common mode voltage generated on a power line by a power conversion circuit that converts power by switching operations of semiconductor elements.
  • the common mode filter circuit includes a voltage detection circuit that detects a common mode voltage generated on a power line and outputs a voltage detection signal containing information on the common mode voltage, and a specific frequency component in the voltage detection signal output by the voltage detection circuit.
  • a common mode transformer that has a secondary winding and a primary winding connected to the power line, and superimposes an injection voltage that reduces the common mode voltage on the power line
  • the band limiting circuit outputs an output voltage generating circuit that generates an output voltage that reduces the voltage amplitude of a signal based on a band-limited signal that includes a frequency component of the band-limited signal to an allowable value or less, and that outputs the output voltage to a primary winding of a common mode transformer
  • an impedance adjuster that adjusts the load impedance of a load circuit that is connected in parallel to the primary winding of the and includes a common mode transformer that is connected between output terminals of the output voltage generation circuit.
  • the impedance of the impedance adjuster is set such that the frequency at which the load impedance connected between the output terminals of the output voltage generating circuit including the impedance becomes maximum is within the range of the two cutoff frequencies of the band limiting circuit.
  • An example common-mode filter circuit disclosed herein comprises an impedance adjuster in parallel with the primary winding of a common-mode transformer such that the frequency at which the load impedance is maximum is the two cut-off frequencies of the bandlimiting circuit. Since the impedance of the impedance adjuster is adjusted so that it falls within the range of can.
  • FIG. 1 is a diagram showing a configuration of a common mode filter circuit according to Embodiment 1;
  • FIG. 2 is a diagram showing the configuration of the power conversion circuit of FIG. 1;
  • FIG. 2 is a diagram showing a configuration of a control circuit in FIG. 1;
  • FIG. 2 is a diagram showing a configuration of an amplifier circuit in FIG. 1;
  • FIG. 2 is a diagram showing an equivalent circuit of a load circuit connected between output terminals of the amplifier circuit of FIG. 1;
  • FIG. 6 is a diagram showing gain characteristics of the band limiting circuit of FIG. 1 and impedance characteristics of the load circuit of FIG. 5;
  • FIG. 2 is a diagram showing vectors of output currents of the amplifier circuit of FIG. 1;
  • FIG. 5 is a diagram showing vectors of output currents of an amplifier circuit in a common mode filter circuit of a comparative example
  • 2 is a diagram showing a first example of gain characteristics of the band limiting circuit of FIG. 1 and frequency components of a common mode voltage
  • FIG. 2 is a diagram showing a second example of gain characteristics of the band limiting circuit of FIG. 1 and frequency components of a common mode voltage
  • FIG. 4 is a diagram showing the configuration of a first example of the digital circuit of FIG. 3
  • FIG. 4 is a flowchart for explaining the operation of the first example of the common mode filter circuit according to Embodiment 1
  • FIG. 13 is a flow chart illustrating a phase adjustment process of FIG. 12;
  • FIG. 13 is a flowchart for explaining an amplitude adjustment process of FIG. 12;
  • FIG. FIG. 10 is a diagram for explaining a residual amount of common mode voltage due to phase adjustment in the common mode filter circuit according to the first embodiment;
  • FIG. 10 is a diagram for explaining a residual amount of common mode voltage due to amplitude adjustment in the common mode filter circuit according to the first embodiment;
  • 4 is a diagram showing an example of phase adjustment in the first example of the digital circuit of FIG. 3;
  • FIG. 4 is a diagram showing an example of amplitude adjustment in the first example of the digital circuit of FIG. 3;
  • FIG. 4 is a diagram showing a configuration of a second example of the digital circuit of FIG. 3;
  • FIG. 20 is a diagram showing a configuration of a search circuit in FIG. 19;
  • FIG. 8 is a flowchart for explaining the operation of the second example of the common mode filter circuit according to Embodiment 1;
  • FIG. 4 is a diagram showing a hardware configuration example that realizes the functions of the digital circuit in FIG. 3;
  • FIG. 20 is a diagram showing the configuration of a learning device that generates a model to be incorporated into the search circuit of FIG. 19;
  • FIG. 25 is a diagram showing a configuration of a control circuit of FIG. 24;
  • FIG. 25 is a diagram showing the configuration of a variable capacitor in FIG. 24;
  • FIG. 25 is a diagram showing a first example of gain characteristics of the band limiting circuit group of FIG. 24 and frequency components of a common mode voltage;
  • FIG. 25 is a diagram showing a second example of gain characteristics of the band limiting circuit group of FIG. 24 and frequency components of common mode voltage;
  • FIG. 9 is a flow chart for explaining the operation of the common mode filter circuit according to the second embodiment;
  • FIG. 10 is a diagram showing the configuration of a common mode filter circuit according to Embodiment 3; 32 is a diagram showing the configuration of the LC regulator of FIG. 31;
  • FIG. 32 is a diagram showing a configuration of a control circuit in FIG. 31;
  • FIG. 32 is a diagram showing an equivalent circuit of a load circuit connected between output terminals of the amplifier circuit of FIG. 31;
  • FIG. 10 is a flow chart for explaining the operation of the common mode filter circuit according to the third embodiment;
  • FIG. 36 is a flowchart for explaining a resonance frequency adjustment process of FIG. 35;
  • FIG. 36 is
  • FIG. 1 is a diagram showing the configuration of a common mode filter circuit according to Embodiment 1
  • FIG. 2 is a diagram showing the configuration of the power conversion circuit in FIG. 3 is a diagram showing the configuration of the control circuit in FIG. 1
  • FIG. 4 is a diagram showing the configuration of the amplifier circuit in FIG. 5 is a diagram showing an equivalent circuit of the load circuit connected between the output terminals of the amplifier circuit of FIG. 1, and
  • FIG. 6 shows the gain characteristics of the band limiting circuit of FIG. 1 and the impedance characteristics of the load circuit of FIG. It is a diagram. 7 is a diagram showing an output current vector of the amplifier circuit of FIG. 1, and FIG.
  • FIG. 8 is a diagram showing an output current vector of the amplifier circuit in the common mode filter circuit of the comparative example.
  • 9 is a diagram showing a first example of the gain characteristics of the band limiting circuit of FIG. 1 and the frequency components of the common mode voltage
  • FIG. 10 is a diagram showing the gain characteristics of the band limiting circuit of FIG. It is a figure which shows two examples.
  • FIG. 11 is a diagram showing the configuration of a first example of the digital circuit of FIG. 12 is a flowchart for explaining the operation of the first example of the common mode filter circuit according to the first embodiment;
  • FIG. 13 is a flow chart explaining the phase adjustment process of FIG. 12, and
  • FIG. 14 is a flow chart explaining the amplitude adjustment process of FIG. FIG.
  • FIG. 15 is a diagram for explaining the amount of residual common mode voltage due to phase adjustment in the common mode filter circuit according to the first embodiment.
  • FIG. 16 is a diagram for explaining the amount of residual common mode voltage due to amplitude adjustment in the common mode filter circuit according to the first embodiment.
  • 17 is a diagram showing an example of phase adjustment in the first example of the digital circuit in FIG. 3
  • FIG. 18 is a diagram showing an example of amplitude adjustment in the first example of the digital circuit in FIG. 19 is a diagram showing the configuration of a second example of the digital circuit of FIG. 3, and
  • FIG. 20 is a diagram showing the configuration of the search circuit of FIG. 21 is a flowchart for explaining the operation of the second example of the common mode filter circuit according to the first embodiment;
  • the common mode voltage Vcm generated on the power lines 4 and 5 by the power conversion circuit 2 that converts power by the switching operations of the semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6 is It is a common mode filter circuit that reduces
  • the compensation target 3 and the power conversion circuit 2 are connected via the power line 4 , the secondary winding 7 of the common mode transformer 16 and the power line 5 .
  • the compensation target 3 is, for example, a power system, an electric motor, and the like.
  • the common mode filter circuit 1 includes a voltage detection circuit 11 , a band limiting circuit 12 , an output voltage generation circuit 66 , an impedance adjuster 18 and a common mode transformer 16 .
  • the voltage detection circuit 11 detects a common mode voltage Vcm generated on the power lines 4 and 5 and outputs a voltage detection signal sig1 containing information on the common mode voltage Vcm.
  • the band-limiting circuit 12 passes a specific frequency component in the voltage detection signal sig1 output from the voltage detection circuit 11, and outputs a band-limiting signal sig2.
  • the output voltage generation circuit 66 includes a control circuit 13 and an amplifier circuit 14 that amplifies the compensation signal sig3 output from the control circuit 13 and outputs the amplified output signal sig4 to the common mode transformer 16.
  • the control circuit 13 of the output voltage generation circuit 66 controls the band limit circuit 12 so that the common mode voltage Vcm becomes equal to or less than the allowable value (threshold value Vth1) by the output voltage Vs, which is the voltage of the output signal sig4 output from the amplifier circuit 14.
  • An output voltage Vs that reduces the voltage amplitude V.sub.O of the computation output signal sig3d computed by the control circuit 13 to a permissible value (threshold value Vth2) or less is generated so that the amplitude decreases.
  • the common mode transformer 16 has a secondary winding 7 connected to the power lines 4 and 5 and a primary winding 8 connected between the output terminals of the output voltage generating circuit 66.
  • An injection voltage Vap that reduces Vcm is superimposed. That is, when the output voltage Vs output by the output voltage generation circuit 66 is input to the primary winding 8 , the common mode transformer 16 injects the injection voltage Vap that reduces the common mode voltage Vcm into the power lines 4 and 5 .
  • the impedance adjuster 18 is connected in parallel to the primary winding 8 of the common mode transformer 16, and is connected between the output terminals of the output voltage generating circuit 66, that is, the output terminals 45s and 45g of the amplifier circuit. 16 is adjusted.
  • the power lines 4 include a u-phase power line 4u, a v-phase power line 4v, and a w-phase power line 4w.
  • the power lines 5 include a u-phase power line 5u, a v-phase power line 5v, and a w-phase power line 5w.
  • the secondary winding 7 of the common mode transformer 16 includes a u-phase secondary winding 7u, a v-phase secondary winding 7v, and a w-phase secondary winding 7w.
  • the power conversion circuit 2 when outputting AC power includes a DC voltage source 21 that generates a DC voltage using a diode rectifier circuit or other means, a DC capacitor 22 that smoothes the DC voltage, and semiconductor devices Q1, Q2, Q3. , Q4, Q5 and Q6, and a grounding capacitor 24 is provided between a grounding terminal 26 connected to the grounding line 6 and a low potential side wiring 27b.
  • a three-phase full bridge comprises six semiconductor elements Q1, Q2, Q3, Q4, Q5, Q6.
  • Three-phase power lines 4u, 4v, and 4w, one end of which is connected to one end of secondary windings 7u, 7v, and 7w of common mode transformer 16, have the other ends of AC terminals 25u, 25v, and 25w of power conversion circuit 2, respectively. It is connected to the.
  • Three-phase power lines 5u, 5v, and 5w, one end of which is connected to the compensation target 3, are connected to the other ends of secondary windings 7u, 7v, and 7w of the common mode transformer
  • the power conversion circuit 2 is a circuit that performs a rectification operation for receiving power from the power system or an operation for transmitting power to the power system.
  • the DC voltage source 21 is a rectifier circuit having an AC generator as a power source, a solar cell, a fuel cell, or the like.
  • the DC voltage source 21 is a storage battery that stores power.
  • the power conversion circuit 2 is a circuit that drives an electric motor if the compensation target 3 is an electric motor.
  • the power conversion circuit 2 has the same configuration except for the DC voltage source 21 even if the DC voltage source 21 is a storage battery.
  • FIG. 2 shows an example of an IGBT.
  • Semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6 include IGBTs and diodes D. As shown in FIG. A diode D is connected anti-parallel to the IGBT.
  • the collectors of the semiconductor elements Q1, Q3 and Q5 are connected to the high potential side wiring 27a, and the emitters of the semiconductor elements Q2, Q4 and Q6 are connected to the low potential side wiring 27b.
  • the emitter of the semiconductor element Q1 and the collector of the semiconductor element Q2 are connected, the emitter of the semiconductor element Q3 and the collector of the semiconductor element Q4 are connected, and the emitter of the semiconductor element Q5 and the collector of the semiconductor element Q6 are connected.
  • Drive signals are input from a drive circuit (not shown) to the gates of the semiconductor elements Q1, Q2, Q3, Q4, Q5 and Q6.
  • the power conversion circuit 2 transmits power or drives a motor
  • the three-phase full bridge switches the semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6 based on the drive signal from the drive circuit, Converts DC power to AC power.
  • the power conversion circuit 2 receives power
  • the three-phase full bridge switches the semiconductor elements Q1, Q2, Q3, Q4, Q5, Q6 based on the drive signal from the drive circuit to convert AC power into DC power. Convert.
  • the voltage detection circuit 11 includes a voltage dividing capacitor 10 between a neutral point n0 of three capacitors 9u, 9v, and 9w Y-connected to three-phase power lines 5u, 5v, and 5w, respectively, and a ground line 6. They are connected in series and detect the divided common mode voltage Vcm.
  • the capacitor 9u is connected to the power line 5u and the neutral point n0
  • the capacitor 9v is connected to the power line 5v and the neutral point n0
  • the capacitor 9w is connected to the power line 5w and the neutral point n0.
  • the detection method of the voltage detection circuit 11 is a voltage lower than the normal common mode voltage Vcm, which is the voltage between the neutral point n0 of the three-phase power lines 5u, 5v, and 5w and the ground line 6 when the voltage dividing capacitor 10 is not present. is detected, and the divided common mode voltage Vcm is detected.
  • a voltage detection signal sig1 output from the voltage detection circuit 11 includes information on the divided common mode voltage Vcm.
  • Information on the divided common mode voltage Vcm reflects information on the normal common mode voltage Vcm, so the voltage detection signal sig1 includes information on the normal common mode voltage Vcm.
  • Vcm is used without distinguishing between the sign of the normal common mode voltage and the sign of the divided common mode voltage.
  • the common mode filter circuit 1 of Embodiment 1 includes the amplifier circuit 14 in the output voltage generation circuit 66 .
  • the amplifier circuit 14 increases the voltage amplitude of the voltage detection signal sig1 to the power lines 4 and 5 according to the voltage division ratio of the voltage detection circuit 11 and the winding ratio between the primary winding 8 and the secondary winding 7 in the common mode transformer 16.
  • the voltage amplitude of the generated normal common mode voltage Vcm is amplified to a voltage amplitude that reduces it, and the amplified output signal sig4 is output to the common mode transformer 16 .
  • a voltage detection signal sig1 containing information on the detected common mode voltage Vcm is passed through the band-limiting circuit 12 to extract a band-limiting signal sig2, which is a signal in a specific frequency band.
  • the band-limited signal sig2 is input to the control circuit 13 of the output voltage generation circuit 66.
  • FIG. FIG. 3 shows an example of the control circuit 13 when the band limiting circuit 12 is an analog filter.
  • the control circuit 13 includes an AD (Analog Digital) converter 31 , a digital circuit 32 and a DA (Digital Analog) converter 33 .
  • the AD converter 31 converts the analog band-limited signal sig2 into a digital operation input signal sig2d.
  • a calculation input signal sig2d is input to the digital circuit 32 .
  • the digital circuit 32 is implemented by, for example, a microcomputer, a DSP (Digital Signal Processor), or an FPGA (Field-Programmable Gate Array).
  • the operation input signal sig2d has the amplitude and phase of voltage amplitude V2 and voltage phase ⁇ 2.
  • the digital circuit 32 outputs a computation output signal sig3d.
  • the amplitude and phase of the operation output signal sig3d are the voltage amplitude Vo and the voltage phase ⁇ o.
  • the DA converter 33 converts the digital operation output signal sig3d into an analog compensation signal sig3.
  • the control circuit 13 receives the band-limited signal sig2 of the band-limited circuit 12 from the input terminals 34s and 34g, and generates the compensation signal sig3 so that the voltage amplitude Vo of the operation output signal sig3d, which is the internal signal of the control circuit 13, decreases. and output a compensation signal sig3 from the output terminals 35s and 35g.
  • the input terminal 34g and the output terminal 35g are connected to the ground line 6 and are at the ground potential.
  • the amplifier circuit 14 is an inverting amplifier circuit including an operational amplifier 41, an input resistor 42, and a negative feedback resistor 43, for example.
  • the amplifier circuit 14 amplifies the compensation signal sig3 and outputs the output signal sig4 from the output terminals 45s and 45g to the impedance adjuster 18 and the common mode signal.
  • Output to primary winding 8 of transformer 16 The voltage and current of the output signal sig4 are the output voltage Vs and the output current Is.
  • the input terminal 44g and the output terminal 45g are connected to the ground line 6 and are at the ground potential. A ground potential is input to the positive input terminal of the operational amplifier 41 via the input terminal 44g.
  • the input from the input terminal 44 s is input to the negative side input terminal of the operational amplifier 41 via the input resistor 42 , and the output of the operational amplifier 41 is input via the negative feedback resistor 43 .
  • a positive power source +Vcc and a negative power source ⁇ Vcc are connected to the operational amplifier 41 .
  • the output terminals of the output voltage generation circuit 66 that is, the output terminals 45s and 45g of the amplifier circuit 14 are connected to one end and the other end of the primary winding 8 of the impedance adjuster 18 and the common mode transformer 16 connected in parallel, respectively.
  • the common mode filter circuit 1 applies the output voltage Vs from the output voltage generation circuit 66 to the impedance adjuster 18 and the primary winding 8 of the common mode transformer 16 .
  • the secondary winding 7 of the common mode transformer 16 is connected to the power lines 4 and 5, and the common mode filter circuit 1 injects a common injection voltage Vap into each phase, thereby reducing the common voltage generated by the power conversion circuit 2.
  • An injection voltage Vap of a reverse phase component is injected with respect to a specific frequency component of the mode voltage Vcm.
  • FIG. 1 shows an example in which the impedance adjuster 18 is the capacitor 15 , that is, an example in which the impedance adjuster 18 includes the capacitor 15 .
  • FIG. 5 shows an equivalent circuit of the load circuit 60 between the output terminals of the amplifier circuit 14.
  • An equivalent circuit between the output terminals 45 s and 45 g of the amplifier circuit 14 is an equivalent circuit on the load side of the amplifier circuit 14 .
  • the load circuit 60 is a circuit including the common mode transformer 16 connected between the output terminals 45 s and 45 g of the output voltage generation circuit 66 .
  • the common mode impedance Z is the combined impedance of the power conversion circuit 2 , the power line 4 , the power line 5 , the voltage detection circuit 11 , the compensation target 3 , and the loop path 61 of the ground line 6 .
  • the common mode impedance Z can be expressed by the impedance of the LC series resonance circuit.
  • capacitor 15 as impedance adjuster 18, exciting inductor having exciting inductance value Lm in common mode transformer 16, and common mode impedance Z of loop path 61 connected to common mode transformer 16 are connected in parallel. That is, the load circuit 60 can be represented by an LC parallel resonant circuit.
  • the impedance of the load circuit 60 be the load impedance Zt.
  • the impedance of each component of the load circuit 60 is also represented by alphabets as follows.
  • the impedance of a magnetizing inductor having magnetizing inductance value Lm is magnetizing impedance Zl. Therefore, the impedance when the common mode transformer 16 is excited is the excitation impedance Zl.
  • the impedance of impedance adjuster 18 is adjuster impedance Zst.
  • a load impedance Zt of the load circuit 60 is a composite impedance in which the regulator impedance Zst, the excitation impedance Zl, and the common mode impedance Z are connected in parallel.
  • the common mode impedance Z can be expressed by the impedance of the LC series resonance circuit having the inductance value La and the capacitance value Ca, the common mode impedance Z is the inductance corresponding to the frequency component based on the resonance frequency of the LC series resonance circuit. It can be thought of as the value La or the capacitance value Ca.
  • the common mode impedance Z operates as a capacitor having a capacitance value Ca for components lower than the resonance frequency of the common mode impedance Z, and as an inductance having an inductance value La for components higher than the resonance frequency of the common mode impedance Z.
  • the frequency f and the exciting current Im are inversely proportional. Therefore, when compensating for the low-frequency common mode voltage Vcm, that is, when injecting the injection voltage Vap that reduces the low-frequency common mode voltage Vcm into the power lines 4 and 5, the excitation current Im increases.
  • the impedance adjuster 18, that is, the capacitor 15 is not arranged between the output terminals of the output voltage generation circuit. was supplied only.
  • the exciting current Im increases in order to compensate for the low-frequency component, active elements with large current capacity are required, and the change in current capacity leads to an increase in the cost of the active elements.
  • the active element supplying the excitation current Im operates in the linear region. Therefore, an active element having a large current capacity generates heat due to a large loss when a large current is passed through it, so that the cooling system for the active element becomes large and the cost of the cooling system also increases. Therefore, the cost of a device equipped with the common mode filter circuit of the comparative example increases as the capacity of the active element increases and the cooling system increases in size.
  • the common mode filter circuit 1 of the first embodiment uses the impedance adjuster 18 of the load circuit 60, which is an LC parallel resonance circuit, to adjust the output terminal 45s and the output terminal 45g of the amplifier circuit 14 at a specific frequency. It is possible to suppress the output current Is of the amplifier circuit 14 by increasing the impedance of the load circuit 60 connected between and, that is, the load impedance Zt. Specifically, when compensating for low frequencies, by appropriately setting the adjuster impedance Zst of the impedance adjuster 18, that is, the capacitance value C of the capacitor 15, the load impedance Zt increases and the output of the amplifier circuit 14 increases. It is possible to suppress the current Is.
  • the load impedance Zt of the load circuit 60 is the impedance of an LC parallel resonance circuit in which the regulator impedance Zst, the exciting impedance Zl, and the common mode impedance Z are connected in parallel. Also, the value of the load impedance Zt of the load circuit 60 can be expressed using the capacitance value C of the capacitor 15, the exciting inductance value Lm of the common mode transformer 16, the inductance value La of the common mode impedance Z, and the capacitance value Ca.
  • FIG. 6 shows frequency characteristics of the gain G of the band limiting circuit 12 and the load impedance Zt connected to the amplifier circuit 14 .
  • a gain characteristic 88 of the gain G and an impedance characteristic 89 of the load impedance Zt are simultaneously shown in FIG.
  • the vertical axis of the gain characteristic 88 is the gain G
  • the vertical axis of the impedance characteristic 89 is the load impedance Zt.
  • the horizontal axis is the frequency f.
  • the load impedance Zt connected to the amplifier circuit 14 is the impedance of the LC parallel resonance circuit in which the exciting inductor having the exciting inductance value Lm and the capacitor 15 having the capacitance value C are connected in parallel.
  • the value of the load impedance Zt becomes the maximum value at the resonance frequency fr1 shown in the equation (2).
  • the frequency fs of the output voltage Vs of the amplifier circuit 14 determined by the characteristics of the band limiting circuit 12, and the resonance frequency determined by the exciting inductance value Lm of the exciting impedance Zl and the capacitance value C of the capacitor 15 are shown in equation (2).
  • the load impedance Zt can be kept high.
  • the amplifier circuit 14 performs compensation based on the band-limited signal sig2, which is a signal extracted from the band-limiting circuit 12 as described above, between the two cutoff frequencies fh and fl of the band-limiting circuit 12,
  • the resonance frequency fr1 of the LC parallel resonance circuit represented by the exciting inductance value Lm of the common mode transformer 16 and the capacitance value C of the capacitor 15
  • the main Such frequency components are those for which the load impedance Zt of the amplifier circuit 14 is high. That is, when the influence of the common mode impedance Z can be ignored, the common mode filter circuit 1 is arranged so that the resonance frequency fr1 of the load circuit 60 falls between the two cutoff frequencies fl and fh of the band limiting circuit 12. , it becomes possible to output only the frequency component where the load impedance Zt between the output terminals of the amplifier circuit 14 is high.
  • a load impedance Zt between the output terminals of the amplifier circuit 14 at a low frequency is an LC parallel connection in which an exciting inductor having an exciting inductance value Lm, a capacitor 15 having a capacitance value C, and a common mode impedance Z having a capacitance value Ca are connected in parallel. It becomes the impedance of the resonant circuit.
  • the resonance frequency of the LC parallel resonance circuit at this low frequency can be expressed by the resonance frequency fr2 shown in Equation (3).
  • a load impedance Zt between the output terminals of the amplifier circuit 14 at a high frequency is an LC parallel resonance in which an exciting inductor having an exciting inductance value Lm, a capacitor 15 having a capacitance value C, and a common mode impedance Z having an inductance value La are connected in parallel. becomes the impedance of the circuit.
  • the resonance frequency of the LC parallel resonance circuit at this high frequency can be expressed by the resonance frequency fr3 shown in Equation (4).
  • a combined inductance value obtained by synthesizing an exciting inductor having an exciting inductance value Lm and a common mode impedance Z having an inductance value La is defined as a combined inductance value Lb, and a capacitor 15 having a capacitance value C and a common mode impedance having a capacitance value Ca.
  • the load impedance Zt between the output terminals of the amplifier circuit 14 is such that the resonant frequency of the LC parallel resonant circuit is represented by the equation (5). It reaches its maximum value at frequency fr4.
  • the magnetizing inductance value Lm of the common mode transformer 16 and the inductance value La of the common mode impedance Z are between the two cutoff frequencies fl and fh of the band limiting circuit 12.
  • the resonance frequency of the LC parallel resonance circuit expressed by the combined inductance value Lb of the combined combined inductance and the combined capacitance value Cb of the combined capacitance resulting from combining the capacitance value C of the capacitor 15 and the capacitance value Ca of the common mode impedance Z
  • the common mode filter circuit 1 is configured so that the resonance frequency fr4 of the load circuit 60 is between the two cutoff frequencies fl and fh of the band limiting circuit 12. , it becomes possible to output only the frequency component where the load impedance Zt between the output terminals of the amplifier circuit 14 is high. The effect is maximized by matching the center frequency of the band limiting circuit 12 and the resonance frequency fr4.
  • the adjuster impedance Zst of the impedance adjuster 18 is set so that the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonant frequency fr4 is included in the range of the two cutoff frequencies fl and fh of the band limiting circuit 12. adjusted. Therefore, the fact that the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonance frequency fr4 is included in the range of the two cutoff frequencies fl and fh of the band limiting circuit 12 means that the impedance condition is satisfied. is. That is, the adjuster impedance Zst of the impedance adjuster 18 is adjusted so as to satisfy the impedance condition. In Embodiment 1, since the impedance adjuster 18 is an example of the capacitor 15, the capacitance value C of the impedance adjuster 18 is adjusted so as to satisfy the impedance condition.
  • a vector of the output current Is in the common mode filter circuit 1 of Embodiment 1 and a vector of the output current Ise in the common mode filter circuit 1 of the comparative example will be described using FIGS.
  • a current vector 91e which is the vector of the output current Ise of the comparative example shown in FIG.
  • the common mode current was determined by the combined vector of the current vector 91d, which is the vector of the current Icma induced in the primary winding 8 by the law of equal ampere turns.
  • the excitation current Ilm becomes dominant.
  • the common mode filter circuit 1 of the first embodiment supplies the excitation current Ilm from the capacitor 15, the current vector, which is the vector of the output current Is of the first embodiment shown in FIG.
  • the common mode current flowing through the secondary winding 7 side is determined by the current vector 91c, which is the vector of the current Icma induced in the primary winding 8 according to the law of equal ampere turns.
  • a current vector 91a which is the vector of the excitation current Ilm
  • a current vector 91b which is the vector of the capacitor current Ic from the capacitor 15 have the same magnitude and opposite directions
  • the output current Is and the current Icma has the same size and the same direction.
  • the common mode filter circuit 1 of the first embodiment prevents the increase in the output current Is of the amplifier circuit 14 due to the increase in the excitation current Ilm generated when compensating for the low-frequency common mode voltage Vcm. can be prevented.
  • the capacity of the amplifier circuit 14 of the output voltage generation circuit 66 does not become insufficient, and the low-frequency common mode voltage Vcm can be compensated.
  • FIG. 9 shows an example in which the carrier frequency f1 is set between the two cutoff frequencies fl and fh of the band limiting circuit 12, and FIG. In this example, the frequency is set to include an integral multiple of the carrier frequency f1. Even when set as shown in FIG. 10, the load impedance Zt reaches its maximum value at the resonance frequency fr4. In addition, when the frequency component 92b is larger than the frequency component 92a, setting as shown in FIG. 10 is assumed. .
  • the common mode component in the specific frequency band that is, the voltage having the same amplitude and the opposite phase with respect to the specific frequency component of the common mode voltage Vcm
  • the common mode voltage Vcm is applied to the secondary of the common mode transformer 16 as the injection voltage Vap.
  • the common mode voltage Vcm is reduced below the allowable value.
  • FIG. 11 shows a first example of the digital circuit 32 of the first embodiment.
  • the digital circuit 32 obtains the voltage amplitude V2 and the voltage phase ⁇ 2 with the amplitude calculator 36 and the phase calculator 37 based on the detected value of the common mode voltage Vcm, and reduces the voltage amplitude V2 to reduce the voltage of the calculation output signal sig3d.
  • a phase adjuster 38 determines the phase ⁇ o, and an amplitude adjuster 39 determines the voltage amplitude Vo of the operation output signal sig3d.
  • the digital circuit 32 includes an amplitude calculator 36 for calculating the voltage amplitude V2 of the band-limited signal sig2 from the AD-converted signal of the band-limited signal sig2 output from the band-limiting circuit 12, that is, the calculation input signal sig2d.
  • a phase calculator 37 for calculating the voltage phase ⁇ 2 of the band-limited signal sig2, a phase adjuster 38 for determining the voltage phase ⁇ o from the initial voltage phase ⁇ o or the previous voltage phase ⁇ b of the previously output computation output signal sig3d, and the initial voltage amplitude.
  • An amplitude adjuster 39 that determines the voltage amplitude Vo from Vo or the previous voltage amplitude Vb of the previously output operation output signal sig3d, and a waveform generator that generates the voltage waveform of the operation output signal sig3d based on the voltage phase ⁇ o and the voltage amplitude Vo. 51.
  • the phase adjuster 38 has a searcher 40a and the amplitude adjuster 39 has a searcher 40b.
  • the amplitude adjuster 39 outputs the voltage amplitude Vo adjusted from the previous time, and the phase adjustment flag flg1 indicates the end of the phase adjustment. is not shown, the same voltage amplitude Vo as the previous time is output.
  • FIG. 12 When the power conversion circuit 2 starts operating, a common mode voltage Vcm is generated.
  • the voltage detection circuit 11 detects the common mode voltage Vcm.
  • the digital circuit 32 of the control circuit 13 determines whether the common mode voltage Vcm exceeds the threshold value Vth1. If the common mode voltage Vcm exceeds the threshold Vth1, the process proceeds to step S05, and if the common mode voltage Vcm does not exceed the threshold Vth1, that is, if the common mode voltage Vcm is equal to or less than the threshold Vth1, the process proceeds to step S03.
  • the control circuit 13 includes information on the common mode voltage Vcm detected by the voltage detection circuit 11, and calculates a voltage amplitude V2 calculated from the band-limited band-limited signal sig2 and a threshold corresponding to the threshold Vth1. After comparison, step S02 is executed.
  • step S03 it is determined whether the voltage amplitude V? of the arithmetic output signal sig3d output by the digital circuit 32 exceeds the threshold value Vth2. If the voltage amplitude V0 exceeds the threshold Vth2, the process proceeds to step S05, and if the voltage amplitude V0 does not exceed the threshold Vth2, that is, if the voltage amplitude V0 is equal to or less than the threshold Vth2, the process proceeds to step S04.
  • step S04 the control circuit 13 stops outputting the compensation signal sig3, the amplifier circuit 14 stops outputting the output signal sig4 as the compensation signal sig3 is stopped, and the process ends. As the output of the output signal sig4 is stopped, the common mode filter circuit 1 stops injection of the injection voltage Vap to the power lines 4 and 5.
  • FIG. Step S04 is an injection voltage stopping step.
  • the common mode filter circuit 1 From step S05 to step S09, the common mode filter circuit 1 generates the compensation signal sig3 and the output signal sig4 in which at least one of the voltage phase ⁇ réelle and the voltage amplitude V réelle is adjusted based on the detected common mode voltage Vcm. to inject the injection voltage Vap into the power lines 4 and 5 .
  • the detected value of the common mode voltage Vcm exceeds the threshold Vth1
  • the phase of the output voltage Vs of the output signal sig4 is adjusted, and then the amplitude of the output voltage Vs of the output signal sig4 is adjusted.
  • This adjustment of the output voltage Vs continues while the detected value of the common mode voltage Vcm exceeds the threshold value Vth1.
  • the voltage amplitude Vo which is the output of the control circuit 13 exceeds the threshold value Vth2
  • the injection of the injection voltage Vap by the transformer 16 continues.
  • step S05 the control circuit 13 determines whether or not the phase adjustment has been completed. If the phase adjustment has been completed, the process proceeds to step S06, and if the phase adjustment has not been completed, the process proceeds to step S07. Normally, the phase adjustment is not completed in the first adjustment.
  • step S07 the digital circuit 32 generates the voltage phase ⁇ réelle in the phase adjustment process.
  • step S08 the digital circuit 32 generates the voltage amplitude V Azure without changing the voltage amplitude V2 calculated from the band-limited signal sig2. That is, the digital circuit 32 generates the voltage amplitude V2 as the voltage amplitude V plin.
  • step S ⁇ b>09 the control circuit 13 outputs the compensation signal sig ⁇ b>3 having the voltage phase ⁇ 1958 and the voltage amplitude V réelle to the amplifier circuit 14 .
  • the amplifier circuit 14 outputs an output signal sig4 obtained by amplifying the compensation signal sig3 to the common mode transformer 16 and the impedance adjuster 18 .
  • the amplitude of the output voltage Vs which is the voltage of the output signal sig4, is amplified from the voltage amplitude VO.
  • the voltage amplitude of the output voltage Vs is used as it is.
  • the output voltage Vs has a phase of voltage phase ⁇ réelle and an amplitude of voltage amplitude Vs.
  • the control circuit 13 When generating the first compensation signal sig3, the control circuit 13 generates the compensation signal sig3 having a voltage phase ⁇ réelle and a voltage amplitude V McG that are opposite in phase to and have the same amplitude as the band-limited signal sig2 output from the band-limiting circuit 12.
  • An initial voltage phase ⁇ 2i which is the initial voltage phase ⁇
  • an initial voltage amplitude V2i which is the initial voltage amplitude V
  • V2i which is the initial voltage amplitude V
  • the voltage amplitude V Center When generating the compensation signal sig3 for the first time, the voltage amplitude V Center is generated without changing the voltage amplitude V2 as described above, so the voltage amplitude V Moderator is the same as the band-limited signal sig2.
  • the voltage phase ⁇ 2 and the voltage amplitude V2 obtained by the amplitude calculator 36 and the phase calculator 37 are used as the initial values, the voltage phase ⁇ в and the voltage amplitude V
  • having the same amplitude and the opposite phase as the band-limited signal sig2 are obtained.
  • the amplifier circuit 14 can output a compensating signal sig3 with The amplifier circuit 14 amplifies the compensation signal sig3 to generate an output signal sig4 having an output voltage Vs generated by an injection voltage Vap having the same amplitude and opposite in phase to the common mode voltage Vcm generated on the power lines 4 and 5 as a common mode. Outputting to transformer 16 is ideal for rapidly canceling specific frequency components of common mode voltage Vcm.
  • the load circuit 60 which is an LC parallel resonance circuit, is stepwise reversed in phase with the specific frequency component of the common mode voltage Vcm generated on the power lines 4 and 5.
  • the control circuit 13 incorporates an algorithm for optimizing the voltage phase ⁇ réelle and the voltage amplitude V adopted. For example, by updating the voltage phase ⁇ réelle and voltage amplitude V réelle changed by a small phase width ⁇ and a small amplitude ⁇ V from the initial voltage phase ⁇ 2i and the initial voltage amplitude V2i, and optimizing the values thereof, the common mode voltage Vcm can be set to a specific value. A specific frequency component of the common mode voltage Vcm can be reduced so as not to cause an abrupt transient change. Note that the initial voltage phase ⁇ 2i and the initial voltage amplitude V2i are values different from those in the case of rapid cancellation.
  • the residual amount of the common mode voltage Vcm by setting the phase and amplitude of the injection voltage Vap that is, The reduction effect will be described with reference to FIGS. 15 and 16.
  • FIG. 15 and 16 the horizontal axis is the phase ⁇ , and the vertical axis is the common mode voltage Vcm.
  • the common mode voltage Vcm is shown as a standardized value based on the maximum value of amplitude.
  • Common mode voltage characteristics 93a and 94a are characteristics of common mode voltage Vcm at one specific frequency before injection voltage Vap is injected into power lines 4 and 5, ie, before compensation.
  • FIG. 15 shows common mode voltage characteristics 93b, 93c, and 93d when the phase difference (negative phase difference) between the injection voltage Vap and the common mode voltage Vcm is 60°, 30°, and 0°.
  • the injected injection voltage Vap has the same voltage amplitude as the specific frequency component of the common mode voltage Vcm.
  • the common mode voltage characteristic 93b is a characteristic with a negative phase difference of 60°
  • the common mode voltage characteristic 93c is a characteristic with a negative phase difference of 30°
  • the common mode voltage characteristic 93d is a characteristic with a negative phase difference of 0°.
  • the optimum value for the antiphase phase difference is 0°. If the negative phase difference is small, it can be confirmed that the common mode voltage Vcm of the specific frequency, that is, the residual amount of the specific frequency component of the common mode voltage Vcm is reduced.
  • FIG. 16 shows the common mode voltages when the ratio (amplitude ratio) of the voltage amplitude of the injected voltage Vap to the voltage amplitude opposite to the specific frequency component of the common mode voltage Vcm is 1/3, 2/3, and 3/3.
  • Properties 94b, 94c, 94d are shown.
  • the injected injection voltage Vap has a voltage phase opposite to the specific frequency component of the common mode voltage Vcm.
  • the common mode voltage characteristic 94b has an amplitude ratio of 1/3
  • the common mode voltage characteristic 94c has an amplitude ratio of 2/3
  • the common mode voltage characteristic 94d has an amplitude ratio of 3/3.
  • the optimum value for the amplitude ratio is 3/3. If the amplitude error of the amplitude ratio is small, it can be confirmed that the residual amount of the specific frequency component of the common mode voltage Vcm is reduced.
  • FIG. 17 shows an example of phase adjustment in the first example of the digital circuit 32 of the first embodiment, that is, an example of an optimization method of the voltage phase ⁇ schreib.
  • a phase change characteristic 95 of the voltage phase ⁇ réelle and a voltage change characteristic 96 of the common mode voltage Vcm are shown at the same time.
  • the horizontal axis is time
  • the vertical axis of the phase change characteristic 95 is the voltage phase ⁇ réelle
  • the vertical axis of the voltage change characteristic 96 is the common mode voltage Vcm.
  • the control circuit 13 shown in FIG. 3 is digital.
  • an AD converter 31 is provided and the common mode voltage Vcm is taken in and used as a detection value.
  • the phase amplitude ⁇ 2 and voltage amplitude V2 of the operation input signal sig2d that the AD converter 31 converts from the band-limited signal sig2 to a digital signal correspond to the detected value of the common mode voltage Vcm processed by the digital circuit 32 .
  • the digital circuit 32 generates a phase amplitude ⁇ 1958 and a voltage amplitude V réelle based on the phase amplitude ⁇ 2 and the voltage amplitude V2, and an output voltage Vs is generated based on the phase amplitude ⁇ réelle and the voltage amplitude V whatsoever.
  • the common mode transformer 16 injects the injection voltage Vap into the power lines 4 and 5, and a new common mode voltage Vcm detection value, that is, the phase amplitude ⁇ 2 and the voltage amplitude V2 are obtained.
  • Three polarities indicating the change direction of the phase change characteristic 95 for each control period ⁇ T of the digital circuit 32 are used so that the amplitude of the detected value, that is, the voltage amplitude V2, is reduced, that is, the voltage amplitude of the common mode voltage Vcm is reduced. If the same polarity changes continuously, the search for the optimum point is continued, and the point where the polarity is reversed when the number of consecutive same polarity changes is less than 3 times is taken as the optimum point.
  • the phase determination condition for determining whether the voltage phase ⁇ GmbH has been optimized is that the phase width ⁇ does not change to the same polarity three times in succession. is to be reversed.
  • An optimum value of the optimum point p1, that is, the voltage phase ⁇ MUSTp is obtained by the optimization method of the voltage phase ⁇ réelle.
  • FIG. 17 shows an example in which the optimum point p1 is obtained by ten searches.
  • the voltage phase ⁇ réelle at time t0 is the initial voltage phase ⁇ 2i.
  • the voltage phase ⁇ réelle is generated by adding the phase width ⁇ to the initial voltage phase ⁇ 2i in the first process.
  • the polarity of the first treatment is positive.
  • the polarity is negative when the phase width ⁇ is subtracted.
  • the processes at times t1, t2, t3, t4, t5, and t6 are processes with positive polarities, and the processes at times t7 and t8 are processes with negative polarities.
  • the polarity is positive, which is the opposite of the previous one.
  • the phase width ⁇ continuously changes to the negative polarity twice, and since it was reversed to the positive polarity in the immediately preceding process, it is assumed that the phase determination condition is satisfied. be judged.
  • the digital circuit 32 determines that the phase determination condition is satisfied in the process at time t10, and generates the voltage phase ⁇ réelle without changing the previous voltage phase ⁇ b.
  • the polarity of the phase width ⁇ is changed opposite to the polarity of the common mode voltage Vcm.
  • the common mode voltage Vcm increased by the previous process, that is, the polarity of the change in the common mode voltage Vcm was reversed from negative to positive, so the polarity of the phase width ⁇ is changed from positive to negative. .
  • the output voltage Vs and the injection voltage Vap at a specific frequency can maintain the opposite phase with respect to the common mode voltage Vcm without a phase difference.
  • the voltage phase ⁇ O of the compensation signal sig3 generated by the control circuit 13 does not change even with the output signal sig4 output from the amplifier circuit and the injection voltage Vap injected into the power lines 4 and 5 by the common mode transformer 16 .
  • the voltage phase ⁇ s of the output voltage Vs in the output signal sig4 output from the amplifier circuit is the same as the voltage phase ⁇ réelle, and the voltage phase of the injected voltage Vap is the same as the voltage phase ⁇ plinth.
  • a sine table for self-oscillation (a sine wave table) is prepared in the control circuit 13 and the phase amount is changed, or a digital signal captured by AD conversion is stored in a register.
  • RAM random access memory
  • the optimum value of the voltage amplitude Vo is searched. That is, the amplitude adjustment process is performed after the phase adjustment process is completed.
  • the method of optimizing the voltage amplitude Vo is the same as the method of optimizing the voltage phase ⁇ réelle.
  • the amplitude is changed by a small amplitude ⁇ V with respect to the initial voltage amplitude V2i, and the voltage amplitude V Mother is changed so as to always be smaller than the previous value of the detected common mode voltage Vcm.
  • the voltage amplitude V.sub.O stops changing, the voltage amplitude V.sub.O is taken as the optimum value.
  • FIG. 18 shows an example of amplitude adjustment in the first example of the digital circuit 32 of the first embodiment, that is, an example of an optimization method of the voltage amplitude V.sub.O.
  • An amplitude change characteristic 97 of the voltage amplitude V Brighton and a voltage change characteristic 98 of the common mode voltage Vcm are shown at the same time.
  • the horizontal axis is time
  • the vertical axis of amplitude change characteristic 97 is voltage amplitude V
  • the vertical axis of voltage change characteristic 98 is common mode voltage Vcm.
  • the search for the optimum point is continued, and the point at which the polarity is reversed when the number of consecutive changes in the same polarity is less than three times is taken as the optimum point. do.
  • the amplitude judgment condition for judging whether the voltage amplitude V plin has been optimized is that the small amplitude ⁇ V does not change to the same polarity three times in succession, and the polarity is to be reversed.
  • the optimum value of the optimum point p2, that is, the voltage amplitude V MUSTp is obtained by the method of optimizing the voltage amplitude V réelle.
  • FIG. 18 shows an example in which the optimum point p2 is obtained by ten searches.
  • the time at which the method of optimizing the voltage amplitude V.sub.O is started is the time t10 at which the method of optimizing the voltage phase .PHI..sub.O ends.
  • the voltage amplitude V réelle at time t10 is the initial voltage amplitude V2i.
  • the voltage amplitude V plin is generated by adding the small amplitude ⁇ V to the initial voltage amplitude V2i in the first process.
  • the polarity of the first treatment is positive.
  • the polarity is negative when the small amplitude ⁇ V is subtracted.
  • the processes at times t11, t12, t13, t14, t15, and t16 are positive in polarity, and the processes at times t17 and t18 are negative in polarity.
  • the polarity is positive, which is the opposite of the previous one.
  • the negative polarity change of the small amplitude ⁇ V occurs twice in succession, and the positive polarity is reversed in the immediately preceding processing. be judged.
  • the digital circuit 32 determines that the amplitude determination condition is satisfied in the process at time t20, and generates the voltage amplitude V réelle without changing the previous voltage amplitude Vb.
  • the polarity of the small amplitude ⁇ V is changed opposite to the polarity of the common mode voltage Vcm.
  • the common mode voltage Vcm increased by the previous process, that is, the polarity of the change in the common mode voltage Vcm was reversed from negative to positive, so the polarity of the small amplitude ⁇ V is changed from positive to negative. .
  • the method of optimizing the voltage phase ⁇ Mr is executed in the phase adjustment process of step S07. Details of the phase adjustment process in step S07 are shown in FIG.
  • the method of optimizing the voltage amplitude V réelle is executed in the amplitude adjustment step of step S06. Details of the amplitude adjustment process in step S06 are shown in FIG. First, the phase adjustment process shown in FIG. 13 will be described.
  • step S11 the phase adjuster 38 of the digital circuit 32 determines whether the phase adjustment is the first time. If the phase adjustment is the first time, the process proceeds to step S12, and if the phase adjustment is not the first time, the process proceeds to step S13.
  • step S12 the phase adjuster 38 generates a voltage phase ⁇ 1958 from the voltage phase ⁇ 2 of the operation input signal sig2d.
  • the voltage phase ⁇ 2 in the first process is the initial voltage phase ⁇ 2i.
  • the voltage phase ⁇ 1958 generated in step S12 is a phase obtained by adding the phase width ⁇ to the initial voltage phase ⁇ 2i.
  • step S07 which is executed again after steps S08, S09, and S01, is the second phase adjustment.
  • step S13 the phase adjuster 38 determines whether or not the phase width ⁇ has changed to the same polarity three times in succession (phase condition determination step). If the phase width ⁇ changes to the same polarity three times in succession, it means that the phase determination condition is not satisfied, and the process proceeds to step S14. If the phase width ⁇ does not change to the same polarity three times in a row, that is, if the phase width ⁇ changes the same polarity less than three times in succession and the polarity is reversed, the phase determination condition is satisfied. , the process proceeds to step S15.
  • step S14 the phase adjuster 38 generates a voltage phase ⁇ 1958 that is different from the previous voltage phase ⁇ b by the phase width ⁇ .
  • step S15 since the phase determination condition is satisfied, the phase adjuster 38 generates and outputs the previous voltage phase ⁇ b as the voltage phase ⁇ réelle. Also, in step S15, the phase adjuster 38 outputs a phase adjustment flag flg1 indicating the end of phase adjustment.
  • step S07 which is executed again through steps S08, S09, and S01, is the third phase adjustment. The phase adjustment process of step S07 is repeated with execution of steps S08, S09, and S01 until the phase determination condition is satisfied.
  • step S21 the amplitude adjuster 39 of the digital circuit 32 determines whether the amplitude adjustment is the first time. If the amplitude adjustment is the first time, the process proceeds to step S22, and if the amplitude adjustment is not the first time, the process proceeds to step S23.
  • the amplitude adjuster 39 generates a voltage amplitude V réelle from the voltage amplitude V2 of the operation input signal sig2d.
  • the voltage amplitude V2 in the first process is the initial voltage amplitude V2i.
  • the voltage amplitude V Mother generated in step S22 is the sum of the initial voltage amplitude V2i and the small amplitude ⁇ V.
  • step S06 is executed again through steps S09 and S01, which is the second amplitude adjustment.
  • step S23 the amplitude adjuster 39 determines whether or not the small amplitude ⁇ V changes to the same polarity three times in succession (amplitude condition determination step). If the small amplitude ⁇ V changes to the same polarity three times in succession, it means that the amplitude determination condition is not satisfied, and the process proceeds to step S24. If the small amplitude ⁇ V does not change to the same polarity three times in succession, that is, if the number of consecutive changes in the same polarity of the small amplitude ⁇ V is less than three times and the polarity is reversed, the amplitude determination condition is satisfied. , the process proceeds to step S25.
  • step S24 the amplitude adjuster 39 generates a voltage amplitude V administrat that is changed by a small amplitude ⁇ V from the previous voltage amplitude Vb.
  • step S25 since the amplitude determination condition is satisfied, the amplitude adjuster 39 generates and outputs the previous voltage amplitude Vb as the voltage amplitude V réelle.
  • step S06 which is executed again after steps S09 and S01, is the third amplitude adjustment. The amplitude adjustment process of step S06 is repeated with the execution of steps S09 and S01 until the amplitude determination condition is satisfied.
  • the first example of the common mode filter circuit 1 of Embodiment 1 generates a compensation signal sig3 having a voltage phase ⁇ réelle and a voltage amplitude V Reserved by the phase adjustment step of step S07 and the amplitude adjustment step of step S06, Since the injection voltage Vap is injected into the power lines 4 and 5 from the common mode transformer 16 based on the output signal sig4 obtained by amplifying the compensation signal sig3, the injection voltage Vap at a specific frequency is equal to the common mode voltage Vcm at the specific frequency. Voltages of opposite phase and equal amplitude can be obtained. As a result, the first example of the common mode filter circuit 1 of the first embodiment can significantly suppress the specific frequency component in the common mode voltage Vcm.
  • the first example of the common mode filter circuit 1 can significantly reduce the low frequency common mode voltage Vcm.
  • the output voltage generation circuit 66 in the first example of the common mode filter circuit 1 of the first embodiment changes the voltage phase ⁇ o of the signal based on the band-limited signal sig2 every time the band-limited signal sig2 is output from the band-limited circuit 12.
  • a phase adjuster 38 that adjusts the phase ⁇ s of the output voltage Vs, that is, the voltage phase ⁇ o, by a predetermined phase width ⁇ until a predetermined phase determination condition (condition for proceeding from step S13 to step S15) is satisfied; 38 outputs the phase adjustment flag flg1 indicating the end of phase adjustment, each time the band limiting circuit 12 outputs the band limiting signal sig2, the voltage amplitude Vo of the signal based on the band limiting signal sig2 is predetermined.
  • the amplitude of the output voltage Vs is adjusted by a predetermined small amplitude ⁇ V1 until the determined amplitude determination condition (condition for proceeding from step S23 to step S25) is satisfied. and an amplitude adjuster 39 that adjusts by small amplitudes ⁇ V.
  • the small amplitude ⁇ V1 is a value obtained by multiplying the small amplitude ⁇ V by the amplification factor of the amplifier circuit 14 .
  • the first example of the common mode filter circuit 1 of Embodiment 1 can optimize the voltage phase ⁇ o and the voltage amplitude Vo for controlling the phase (output voltage phase ⁇ s) and amplitude of the output voltage Vs using the hill-climbing method. can.
  • the method is not limited to the hill-climbing method as long as it has a function of generating the compensation signal sig3 by optimizing the voltage phase ⁇ o and voltage amplitude Vo of a specific frequency.
  • the function of generating the compensation signal sig3 by optimizing the voltage phase ⁇ o and the voltage amplitude Vo of a specific frequency so that the detection value of the specific frequency obtained by the band limiting circuit 12 is reduced is an optimization using a neural network. optimization using other machine learning methods.
  • FIG. 19 A second example of a digital circuit 32 having a search circuit 28 that optimizes the voltage phase ⁇ o and voltage amplitude Vo using a neural network is shown in FIG.
  • the second example of the digital circuit 32 shown in FIG. 19 is different from the digital circuit 32 shown in FIG. This is different from the first example.
  • the regulator 50 generates a voltage phase ⁇ o and a voltage amplitude Vo from the voltage amplitude V2 calculated by the amplitude calculator 36 and the voltage phase ⁇ 2 calculated by the phase calculator 37 .
  • the adjuster 50 comprises a search circuit 28 using a neural network.
  • the search circuit 28 incorporates a trained model learned to minimize the input voltage amplitude V2 and the output voltage amplitude Vo by changing the output voltage Vs by, for example, a predetermined number of adjustments. . If the predetermined number of adjustments is 10, which is the same as the number of phase adjustments shown in FIG. 17 and the number of amplitude adjustments shown in FIG. are updated at the same time. Therefore, the second example of the digital circuit 32 can optimize the voltage phase ⁇ o and the voltage amplitude Vo with fewer adjustments than the first example of the digital circuit 32 .
  • step S10 the digital circuit 32 generates the first voltage phase ⁇ o and voltage amplitude Vo.
  • step S ⁇ b>09 the control circuit 13 outputs the compensation signal sig ⁇ b>3 having the voltage phase ⁇ réelle and the voltage amplitude V réelle to the amplifier circuit 14 .
  • the amplifier circuit 14 outputs an output signal sig4 obtained by amplifying the compensation signal sig3 to the common mode transformer 16 and the impedance adjuster 18 .
  • step S01 the adjustment process of updating the voltage phase ⁇ 1958 and the voltage amplitude V réelle in step S10 is repeated until step S04 is executed through steps S02 and S03.
  • the output voltage generation circuit 66 in the second example of the common mode filter circuit 1 of Embodiment 1 determines the phase of the output voltage Vs based on the voltage phase ⁇ 2 and the voltage amplitude V2 of the band-limited signal sig2 output from the band-limiting circuit 12. (output voltage phase ⁇ s) and an adjuster 50 for adjusting the amplitude.
  • the adjuster 50 is learned to generate the value of the voltage phase ⁇ o and the value of the voltage amplitude Vo that control the phase (output voltage phase ⁇ s) and the amplitude of the output voltage Vs from the voltage phase ⁇ 2 and the voltage amplitude V2 of the bandlimited signal sig2.
  • a search circuit 28 is provided for constructing the model.
  • the search circuit 28 inputs the voltage phase ⁇ 2 and the voltage amplitude V2 of the band-limited signal sig2 and detects the voltage of the band-limited signal sig2 until the voltage amplitude Vo of the signal based on the band-limited signal sig2 decreases below the allowable value (threshold value Vth2). It is learned to generate the phase (output voltage phase ⁇ s) of the output voltage Vs at which the amplitude V2 decreases and the value of the voltage phase ⁇ réelle and the value of the voltage amplitude V faculty that control the amplitude, and the band-limited signal sig2 is output.
  • phase (output voltage phase ⁇ s) and amplitude of the output voltage Vs are adjusted based on the value of the voltage phase ⁇ O and the value of the voltage amplitude Vo generated by the search circuit 28 from the band-limited signal sig2.
  • a second example of the common mode filter circuit 1 of Embodiment 1 uses a learned model to optimize the voltage phase ⁇ o and the voltage amplitude Vo that control the phase (output voltage phase ⁇ s) and amplitude of the output voltage Vs. can be done.
  • a model to be incorporated into the search circuit 28 is generated by the learning device 110 .
  • the learning device 110 includes a data acquisition unit 111 and a model generation unit 112 and stores the generated model in the model storage device 113 .
  • the data acquisition unit 111 acquires input data data1 input to the digital circuit 32 and optimized data to be output from the digital circuit 32, ie, expected output data data2, as learning data.
  • Input data data1 includes voltage amplitude V2 and voltage phase ⁇ 2
  • output data data2 includes voltage amplitude Vos and voltage phase ⁇ os, which are expected values corresponding to input voltage amplitude V2 and voltage phase ⁇ 2.
  • the model generation unit 112 learns the voltage amplitude Vo and the voltage phase ⁇ o based on the learning data created based on the combination of the input data data1 and the output data data2 output from the data acquisition unit 111 . That is, a trained model for inferring the optimum voltage amplitude Vo and voltage phase ⁇ o from the input data data1 of the digital circuit 32 and the expected output data data2 is generated.
  • the learning data is data in which the voltage amplitude V2 and the voltage phase ⁇ 2 of the input data data1 and the voltage amplitude Vos and the voltage phase ⁇ os of the output data data2 are associated with each other.
  • the model generation unit 112 learns the voltage amplitude Vo and the voltage phase ⁇ o by so-called supervised learning according to the neural network model.
  • supervised learning refers to a method of inferring a result from an input by giving a set of input and result data to a learning device to learn features in the learning data.
  • a neural network consists of an input layer consisting of multiple neurons, an intermediate layer (hidden layer) consisting of multiple neurons, and an output layer consisting of multiple neurons.
  • the intermediate layer may be one layer, or two or more layers.
  • the search circuit 28 has a three-layer neural network as shown in FIG.
  • voltage amplitude V2 and voltage phase ⁇ 2 are input to input layers N1 and N2, respectively, voltage amplitude V2 and voltage phase ⁇ 2 are multiplied by weighting function wa (w11, w12, w13, w14, w21, w22, w23, w24). are input to the intermediate layers N3, N4, N5 and N6, and the results are multiplied by the weighting function wb (w31, w32, w41, w42, w51, w52, w61, w62) and output from the output layers N7 and N8. .
  • the voltage amplitude Vo and voltage phase ⁇ o output from the output layers N7 and N8 change depending on the weighting functions wa and wb.
  • the weighting function wa is a general term for weighting functions when input from the input layers N1 and N2 to the intermediate layers N3, N4, N5 and N6, and the weighting function wb is the weighting function from the intermediate layers N3, N4, N5 and N6 to the output layer N7, It is a general term for the weighting function when input to N8.
  • the weighting function wa is one of w11, w12, w13, w14, w21, w22, w23 and w24 depending on the combination of the input layers N1 and N2 and the intermediate layers N3, N4, N5 and N6.
  • the weighting function wb is one of w31, w32, w41, w42, w51, w52, w61 and w62 depending on the combination of the intermediate layers N3, N4, N5 and N6 and the output layers N7 and N8.
  • the weighting functions wa from the input layer N1 to the intermediate layers N3, N4, N5 and N6 are w11, w12, w13 and w14, respectively.
  • Weighting functions wa from the input layer N2 to the intermediate layers N3, N4, N5 and N6 are w21, w22, w23 and w24, respectively.
  • Weighting functions wb from the intermediate layer N3 to the output layers N7 and N8 are w31 and w32, respectively.
  • Weighting functions wb from the intermediate layer N4 to the output layers N7 and N8 are w41 and w42, respectively.
  • Weighting functions wb from the intermediate layer N5 to the output layers N7 and N8 are w51 and w52, respectively.
  • Weighting functions wb from the intermediate layer N6 to the output layers N7 and N8 are w61 and w62, respectively.
  • the search circuit 28 learns the voltage amplitude Vo and the voltage phase ⁇ o by so-called supervised learning according to the learning data created based on the combination of the input data data1 and the output data data2 acquired by the data acquisition unit 111. That is, the search circuit 28 inputs the voltage amplitude V2 and the voltage phase ⁇ 2 to the input layers N1 and N2, and outputs the results from the output layers N7 and N8 so that they approach the voltage amplitude Vos and the voltage phase ⁇ os of the output data data2. is learned by adjusting the weights wa and wb.
  • the model generating unit 112 generates a trained model by executing the learning as described above, and outputs the trained model to the model storage device 113 .
  • the optimization of the values of the weighting functions wa and wb is performed by changing the output voltage Vs by, for example, a predetermined number of adjustments, so that the input voltage amplitude V2 and the output voltage amplitude Vo are minimized. Repeated learning is performed using the output data data2. 17 and 18 show an example of reducing the common mode voltage Vcm by generating the output voltage Vs a total of 20 times.
  • the common mode filter circuit 1 provided with the search circuit 28 can reduce the common mode voltage Vcm even if the number of adjustments of the output voltage Vs is less than that of the hill-climbing optimization method, for example, the number of adjustments of the output voltage Vs is 10 or less. can be done.
  • the search circuit 28 incorporates a trained model generated by the model generation unit 112 of the learning device 110 .
  • search circuit 28 is implemented in digital circuit 32 so that the trained model is embedded in digital circuit 32 .
  • the function of the digital circuit 32 is implemented by, for example, a microcomputer, DSP, FPGA, or the like.
  • Embodiment 1 the case where supervised learning is applied to the learning algorithm used by the model generating unit 112 has been described, but the present invention is not limited to this. In addition to supervised learning, it is also possible to apply reinforcement learning, unsupervised learning, semi-supervised learning, and the like as learning algorithms.
  • the number of devices equipped with the common mode filter circuit 1 that collects learning data is not limited to one.
  • the learning data when the compensation target 3 is the first motor and the learning data when the compensation target 3 is the second motor with different specifications may be used simultaneously for learning.
  • the learning device 110 that has learned the voltage amplitude Vo and the voltage phase ⁇ o with respect to the common mode filter circuit 1 of a certain compensation target 3 is applied to the common mode filter circuit 1 of another compensation target 3, The voltage amplitude Vo and voltage phase ⁇ o of the mode filter circuit 1 may be re-learned and updated.
  • neural programming that learns to extract the feature amount itself can also be used, and other known methods such as genetic programming, functional logic programming, Machine learning may be performed according to support vector machines and the like.
  • phase adjuster 38 and the amplitude adjuster 39 in the first example of the digital circuit 32 may be implemented by the processor 120 and memory 121 shown in FIG.
  • the phase adjuster 38 and the amplitude adjuster 39 are realized by executing a program stored in the memory 121 by the processor 120 .
  • the plurality of processors 120 and the plurality of memories 121 may work together to perform the functions of the phase adjuster 38 and the amplitude adjuster 39 .
  • the power conversion circuit 2, the compensation object 3, the power lines 4, and the power lines 5 have been described as an example of a three-phase, three-wire system. It can also be applied to wire systems, single-phase circuits, and the like.
  • the three-phase full-bridge converter has been described as an example of the power conversion circuit 2, it is not limited to this. As long as the power conversion circuit 2 has an AC/DC conversion function, it may be, for example, a three-level converter or other circuit configuration.
  • the voltage detection circuit 11 is not limited to the method of detecting the common mode voltage Vcm using the voltage dividing circuit of the Y-connected capacitors 9u, 9v, 9w and the voltage dividing capacitor 10 .
  • the voltage detection circuit 11 can also be applied to a common mode current detection circuit using a common mode transformer.
  • the windings connected to the power lines 4 and 5 function as the primary windings, and the current obtained from the secondary windings via the excitation inductance of the common mode transformer is voltage-converted by the terminating resistor, and the common mode current is Detected after voltage conversion.
  • the band-limiting circuit 12 may be an analog filter composed of analog parts combining inductors, capacitors, resistors, and amplifier circuits, as long as it can pass a specific frequency component, that is, if it can extract a signal containing a specific frequency component. , may be a digital filter composed of digital components. If band limiting circuit 12 is a digital filter, the function of band limiting circuit 12 may be incorporated into digital circuit 32 . In this case, the voltage detection signal sig1 is input to the control circuit 13, the voltage detection signal sig1 is AD-converted by the AD converter 31 of the control circuit 13, and the band-limited signal sig2, which is a digital signal band-limited in the digital circuit 32, is obtained. generated.
  • the configuration of the control circuit 13 is not limited to the configuration shown in FIG. If the control circuit 13 has a function of generating a compensating signal sig3 so that the band-limited signal sig2 detected from the next time onward is reduced from the band-limited signal sig2 of the specific frequency component obtained by the band-limiting circuit 12. It may be composed of analog parts.
  • the searcher 40b incorporated in the control circuit 13 may include a limiter to prevent saturation of the output voltage of the amplifier circuit 14 when searching for the voltage amplitude V.sub.O, that is, when generating the voltage amplitude V.sub.O.
  • the amplifier circuit 14 is not limited to the configuration shown in FIG.
  • the amplifier circuit 14 may be an inverting amplifier circuit using the operational amplifier 41, a non-inverting amplifier circuit, a push-pull circuit composed of transistors, or the like.
  • the voltage of the compensation signal sig3 input to the input terminals 44s and 44g of the amplifier circuit 14 is amplified to generate the output voltage Vs from the output terminals 45s and 45g so that the specific frequency component included in the compensation signal sig3 is reduced.
  • Any configuration other than that shown in FIG. 4 may be used as long as it has the function.
  • the common mode filter circuit 1 connects the output terminal of the band limiting circuit 12 to the input terminals 44s and 44g of the amplifier circuit 14, and operationally amplifies the input signal so that the common mode voltage Vcm or the common mode current is equal to or lower than the reference value. can be maintained, the control circuit 13 need not be mounted.
  • the capacitor 15 of the impedance adjuster 18 can be configured as a single capacitor if the resonance frequency fr4 of the load impedance Zt of the load circuit 60 can be adjusted to a capacitance value that can be set between the two cutoff frequencies fl and fh of the band limiting circuit 12.
  • a plurality of capacitors may be connected in series or in parallel to obtain the desired capacitance value.
  • the common mode filter circuit 1 of the first embodiment reduces the common mode voltage Vcm generated in the power lines 4 and 5 by the power conversion circuit 2 that converts power by switching operation of semiconductor elements.
  • the common mode filter circuit 1 includes a voltage detection circuit 11 that detects a common mode voltage Vcm generated in the power lines 4 and 5 and outputs a voltage detection signal sig1 containing information on the common mode voltage Vcm, and a voltage detection signal sig1 that is output by the voltage detection circuit 11.
  • the voltage amplitude Vo of the signal (calculation output signal sig3d) based on the band-limited signal sig2 containing the frequency components 92a and 92b output by the common mode transformer 16 that superimposes the injection voltage Vap that reduces Vcm and the band-limiting circuit 12 is allowed.
  • An output voltage generating circuit 66 that generates an output voltage Vs that is reduced to a value (threshold value Vth2) or less and outputs the output voltage Vs to the primary winding 8 of the common mode transformer 16, and the primary winding 8 of the common mode transformer 16: and an impedance adjuster 18 that adjusts the load impedance Zt of the load circuit 60 that includes the common mode transformer 16 that is connected in parallel and connected between the output terminals 45s and 45g of the output voltage generation circuit 66. .
  • the impedance (adjuster impedance Zst) of the impedance adjuster 18 is set at the frequency (resonance The frequency fr4) is set within the range of the two cutoff frequencies fl and fh of the band limiting circuit 12 .
  • the common mode filter circuit 1 of Embodiment 1, with this configuration, includes the impedance adjuster 18 connected in parallel to the primary winding 8 of the common mode transformer 16. is within the range of the two cutoff frequencies fl and fh of the band-limiting circuit 12, the impedance of the impedance adjuster 18 (adjuster impedance Zst) is adjusted so that the common mode voltage Vcm of the low frequency component is Even in this case, a significant increase in the output current Is output from the output voltage generation circuit 66 can be prevented.
  • Embodiment 2. 24 is a diagram showing the configuration of a common mode filter circuit according to the second embodiment
  • FIG. 25 is a diagram showing the configuration of the band limiting circuit group of FIG. 26 is a diagram showing the configuration of the control circuit in FIG. 24, and
  • FIG. 27 is a diagram showing the configuration of the variable capacitor in FIG.
  • FIG. 28 is a diagram showing a first example of the gain characteristics of the band limiting circuit group of FIG. 24 and the frequency components of the common mode voltage.
  • FIG. 29 is a diagram showing a second example of the gain characteristics of the band limiting circuit group of FIG. 24 and the frequency components of the common mode voltage.
  • 30 is a flowchart for explaining the operation of the common mode filter circuit according to the second embodiment;
  • FIG. 25 is a diagram showing the configuration of the band limiting circuit group of FIG. 26 is a diagram showing the configuration of the control circuit in FIG. 24, and
  • FIG. 27 is a diagram showing the configuration of the variable capacitor in FIG.
  • FIG. 28 is a diagram showing
  • the cutoff frequencies fl and fh of the band limiting circuit 12 are set according to the carrier frequency of the power conversion circuit 2 . Therefore, when considering application to a device equipped with the power conversion circuit 2 that switches the carrier frequency, the frequency characteristic of the common mode voltage Vcm changes according to the change of the carrier frequency.
  • the common mode filter circuit 1 preferably has a plurality of band limiting circuits 12 with different center frequencies in the passband.
  • the common mode filter circuit 1 according to the second embodiment is an example corresponding to different carrier frequencies of the power conversion circuit 2 .
  • the common mode filter circuit 1 of the second embodiment differs from the common mode filter circuit 1 of the first embodiment in that the band limiting circuit 12, the control circuit 13, and the capacitor 15 are provided with a plurality of band limiting circuits 12a, 12b, and 12n. The difference is that the band limiting circuit group 20, the control circuit 30a, and the variable capacitor 59 are replaced.
  • the parts different from the common mode filter circuit 1 of the first embodiment will be mainly described.
  • the impedance adjuster 18 is an example of the variable capacitor 59 , that is, the impedance adjuster 18 is an example provided with the variable capacitor 59 .
  • the output voltage generation circuit 66 generates an output voltage Vs and outputs a setting signal sig6 for setting the capacitance value of the impedance adjuster 18.
  • FIG. 28 shows the relationship between the frequency components of the common mode voltage Vcm generated by the power conversion circuit 2 with a plurality of different carrier frequencies and the frequency characteristics of the gain G in the band limiting circuit group 20, that is, a plurality of gain characteristics.
  • FIG. 28 shows frequency components and gain characteristics 88a, 88b, 88n corresponding to three carrier frequencies f1a, f1b, f1n out of n carrier frequencies f1a to f1n.
  • the frequency components of the common mode voltage Vcm related to the carrier frequency f1a showed four frequency components 71a, 72a, 73a, 74a.
  • a frequency component 71a of carrier frequency f1a, a frequency component 72a of third-order component frequency f3a, a frequency component 73a of fifth-order component frequency f5a, and a frequency component 74a of seventh-order component frequency f7a are shown.
  • a gain characteristic 88a is the gain characteristic of the band limiting circuit 12a set so that the carrier frequency f1a is between the two cutoff frequencies fl and fh.
  • the frequency components of the common mode voltage Vcm related to the carrier frequency f1b showed four frequency components 71b, 72b, 73b and 74b.
  • a frequency component 71b of carrier frequency f1b, a frequency component 72b of third-order component frequency f3b, a frequency component 73b of fifth-order component frequency f5b, and a frequency component 74b of seventh-order component frequency f7b are shown.
  • a gain characteristic 88b is a gain characteristic of the band limiting circuit 12b set so that the carrier frequency f1b is between the two cutoff frequencies fl and fh.
  • the frequency components of the common mode voltage Vcm related to the carrier frequency f1n showed four frequency components 71n, 72n, 73n, 74n.
  • a frequency component 71n of carrier frequency f1n, a frequency component 72n of third-order component frequency f3n, a frequency component 73n of fifth-order component frequency f5n, and a frequency component 74n of seventh-order component frequency f7n are shown.
  • a gain characteristic 88n is a gain characteristic of the band limiting circuit 12n set so that the carrier frequency f1n is between the two cutoff frequencies fl and fh.
  • a plurality of band limiting circuits 12a to 12n are provided in the band limiting circuit group 20, and the control circuit 30a selects one of the output values of the band limiting circuits 12a to 12n in accordance with fluctuations in the carrier frequency of the power conversion circuit 2. which one is used for compensation is selected.
  • the control circuit 30a has a selection circuit 52 which compares the output values of the plurality of band limiting circuits 12a to 12n and selects the maximum one.
  • the amplifier circuit 14 When the control circuit 30a generates the compensation signal sig3 based on one band-limited signal sigse selected from the plurality of band-limited signals sig5a to sig5n output from the band-limited circuit group 20, the amplifier circuit 14 outputs The frequency components contained in the output voltage Vs change according to the selected band-limited signal sigse. 12 is used as the code for the band-limiting circuits selected from the plurality of band-limiting circuits 12a to 12n in the band-limiting circuit group 20.
  • FIG. Therefore, the function of adjusting the capacitance value of the variable capacitor 59 so that the resonance frequency fr4 of the load circuit 60 falls between the two cutoff frequencies fl and fh of the band-limiting circuit 12 through which the selected band-limiting signal sigse is passed is provided. It is desirable to have
  • the variable capacitor 59 includes a plurality of series bodies 55a, 55b, 55c, and 55d in which capacitors and switches are connected in series.
  • FIG. 27 shows an example with four serial bodies 55a, 55b, 55c and 55d.
  • the variable capacitor 59 has four series bodies 55a, 55b, 55c, and 55d arranged in parallel between a wiring 64a connected to an input terminal 62s and an output terminal 63s and a wiring 64b connected to an input terminal 62g and an output terminal 63g. It is connected to the.
  • the input terminals 62s and 62g are connected to the output terminals 45s and 45g of the amplifier circuit 14, respectively, and the output terminals 63s and 63g are connected to one end and the other end of the primary winding 8 of the common mode transformer 16, respectively.
  • the series body 55a has the capacitor 15a and the switch 54a connected in series
  • the series body 55b has the capacitor 15b and the switch 54b connected in series
  • the series body 55c has the capacitor 15c and the switch 54c connected in series
  • the series body 55d has the capacitor 15d and the switch 54d connected in series.
  • the switch 54a is controlled to be on and off by a setting signal sig6a input from the input terminal 67a.
  • Switches 54b, 54c, and 54d are similarly controlled to be on and off by setting signals sig6b, sig6c, and sig6d, respectively.
  • the switch 54b is controlled to be on and off by a setting signal sig6b input from the input terminal 67b.
  • the switch 54c is controlled to be turned on and off by a setting signal sig6c input from the input terminal 67c.
  • the switch 54d is controlled to be turned on and off by a setting signal sig6d input from the input terminal 67d.
  • sig6 is used in general, and sig6a, sig6b, sig6c, and sig6d are used when they are distinguished.
  • the switches 54a, 54b, 54c and 54d are turned on, the series bodies 55a, 55b, 55c and 55d operate as capacitors 15a, 15b, 15c and 15d.
  • the switches 54a, 54b, 54c, and 54d are turned off, the series bodies 55a, 55b, 55c, and 55d, that is, the capacitors 15a, 15b, 15c, and 15d are opened (disconnected), and the capacitance of the variable capacitor 59 is changed to can be lowered.
  • the capacitance value of the variable capacitor 59 can be increased by increasing the number of parallel connections of the capacitors 15a, 15b, 15c, and 15d, and the capacitance value of the variable capacitor 59 can be increased by decreasing the number of parallel connections of the capacitors 15a, 15b, 15c, and 15d. can be reduced.
  • the band limiting circuit group 20 includes a plurality of band limiting circuits 12a-12n.
  • FIG. 25 shows three band limiting circuits 12a, 12b, and 12n out of n band limiting circuits.
  • Band-limiting circuit 12a passes a specific frequency component according to gain characteristic 88a in voltage detection signal sig1 output from voltage detection circuit 11, and outputs band-limiting signal sig5a.
  • Band-limited signal sig5a includes a frequency component corresponding to gain characteristic 88a of band-limited circuit 12a.
  • Band-limiting circuit 12b passes a specific frequency component according to gain characteristic 88b in voltage detection signal sig1 output from voltage detection circuit 11, and outputs band-limiting signal sig5b.
  • the band-limiting circuit 12n passes a specific frequency component according to the gain characteristic 88n in the voltage detection signal sig1 output from the voltage detection circuit 11, and outputs a band-limiting signal sig5n.
  • Band-limited signal sig5b contains a frequency component corresponding to gain characteristic 88b of band-limiting circuit 12b
  • band-limited signal sig5n contains a frequency component corresponding to gain characteristic 88n of band-limiting circuit 12n.
  • sig5 is generally used, and sig5a, sig5b, and sig5n are used for distinction.
  • the control circuit 30a is different from the control circuit 13 shown in FIG. 53 is added. A part different from the control circuit 13 will be mainly described.
  • the selection circuit 52 has a plurality of input terminals 34sa to 34sn and an input terminal 34g.
  • the selection circuit 52 takes in the band-limited signal sig5a of the band-limited circuit group 20 from the input terminals 34sa and 34g, and takes in the band-limited signal sig5b of the band-limited circuit group 20 from the input terminals 34sb and 34g.
  • the selection circuit 52 takes in the band-limiting signal sig5n of the band-limiting circuit group 20 from the input terminals 34sn and 34g.
  • the 26 shows three input terminals 34sa, 34sb, and 34sn out of n input terminals 34sa to 34sn, and three band-limited signals sig5a, sig5b, and sig5n input thereto.
  • the selection circuit 52 compares the output values of the plurality of band-limited signals sig5 output from the plurality of band-limited circuits 12a to 12n, selects the maximum one, and outputs it as the band-limited signal sigse. Also, the selection circuit 52 outputs a selection information signal ssig indicating which of the band-limited signals sig5a to sig5n has been selected.
  • the AD converter 31 converts the analog band-limited signal sigse into a digital operation input signal sig2d.
  • the setting signal generation circuit 53 generates setting signals sig6a to sig6a to turn off the switches 54a to 54d of the variable capacitor 59 corresponding to the cutoff frequencies fl and fh of the band limiting circuits 12a to 12n of the band limiting circuit group 20. Set the state of sig6a.
  • the setting signal generating circuit 53 is connected between the cutoff frequencies fl and fh of the band limiting circuit 12 corresponding to the selected band limiting signal sigse, and the load circuit connected between the output terminals 45s and 45g of the output voltage generating circuit 66.
  • a preset set of states, ie, potential levels, of the setting signals sig6a to sig6a is output so that the frequency at which the load impedance Zt of 60 is maximized is included. For example, when the potential levels of the setting signals sig6a to sig6a are high, the switches 54a to 54d are turned on, and when the potential levels of the setting signals sig6a to sig6a are low, the switches 54a to 54d are turned off.
  • the adjuster impedance Zst of the impedance adjuster 18 of the second embodiment is adjusted in the same manner as in the first embodiment.
  • the adjuster impedance Zst of the impedance adjuster 18 of the second embodiment is the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonant frequency fr4 of the band-limiting circuit group 20 that outputs the selected band-limiting signal sigse. It is adjusted to fall within the two cutoff frequencies fl and fh of the band limiting circuit 12 .
  • the adjuster impedance Zst of the impedance adjuster 18 of the second embodiment is within the range of the two cutoff frequencies fl and fh of the band-limiting circuit 12 of the band-limiting circuit group 20 that outputs the selected band-limiting signal sigse. is adjusted to include the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonance frequency fr4.
  • the frequency at which the load impedance Zt of the load circuit 60 maximizes, i.e., the resonant frequency fr4 is included means that the impedance condition is satisfied.
  • the impedance adjuster 18 is an example of the variable capacitor 59
  • the capacitance value C of the variable capacitor 59 which is the impedance adjuster 18, is adjusted so as to satisfy the impedance condition.
  • the control circuit 30 adjusts the capacitance value of the variable capacitor 59 according to the gain characteristic of the band limiting circuit 12 of the band limiting circuit group 20 that outputs the selected band limiting signal sigse. C can be set such that the impedance condition is satisfied.
  • the common mode filter circuit 1 of the second embodiment even if the carrier frequency of the power conversion circuit 2 is changed, the frequency component of the output voltage Vs output from the amplifier circuit 14 of the output voltage generation circuit 66 is kept under the impedance condition is satisfied, the load impedance Zt of the load circuit 60 is increased by the output voltage Vs, and an increase in the output current output from the output voltage generating circuit 66 can be prevented.
  • step S41 the control circuit 30a selects one band-limiting circuit 12 that maximizes the output value of the band-limiting signal sig5 output by each of the plurality of band-limiting circuits 12a to 12n of the band-limiting circuit group 20.
  • the capacitance value of the variable capacitor 59 is set so that the resonance frequency fr4 of the load circuit 60 is set according to the characteristics of the circuit 12, that is, so as to satisfy the impedance condition (adjuster impedance setting step).
  • Step S05 is performed after the adjuster impedance setting process of step S41.
  • the common mode filter circuit 1 of Embodiment 2 can prevent an increase in the output current output from the output voltage generation circuit 66 even if the carrier frequency of the power conversion circuit 2 is changed.
  • the flowchart shown in FIG. 30 is an example corresponding to the flowchart for explaining the operation of the first example of the common mode filter circuit 1 of the first embodiment.
  • This is the first example in which the digital circuit 32 in the control circuit 30a of the second embodiment is shown in FIG.
  • the digital circuit 32 in the control circuit 30a of the second embodiment may be the second example shown in FIG.
  • the flowchart in this case is a flowchart in which step S41 is added before step S10 in the flowchart shown in FIG.
  • the gain characteristics 88a-88n of the n band-limiting circuits 12a-12n of the band-limiting circuit group 20 are set so that the carrier frequencies f1a-f1n are included between the two cut-off frequencies fl and fh.
  • An example is shown.
  • the gain characteristics 88a-88n of the n band-limiting circuits 12a-12n of the band-limiting circuit group 20 are, as shown in FIG. It may be set so that the frequency is included.
  • FIG. 29 shows an example in which frequencies f3a to f3n, which are integral multiples of carrier frequencies f1a to f1n, are included between two cutoff frequencies fl and fh. Even when set as shown in FIG. 29, the load impedance Zt reaches its maximum value at the resonance frequency fr4.
  • the frequency components 72a to 72n are larger than the frequency components 71a to 71n, it is assumed to be set as shown in FIG. This is not the case.
  • each of the series bodies 55a to 55d may have a plurality of capacitors. That is, each of the capacitors 15a to 15d may be a series connection or a series connection of a plurality of capacitors. Also, each of the capacitors 15a to 15d may be a variable capacitor.
  • Each of the switches 54a to 54d may be a mechanical switch, a semiconductor switch, or the like, as long as it has a bidirectional cut-off and conduction function.
  • Embodiment 3 is a diagram showing the configuration of a common mode filter circuit according to Embodiment 3
  • FIG. 32 is a diagram showing the configuration of the LC regulator of FIG. 33 is a diagram showing the configuration of the control circuit of FIG. 31,
  • FIG. 34 is a diagram showing an equivalent circuit of the load circuit connected between the output terminals of the amplifier circuit of FIG. 35 is a flow chart for explaining the operation of the common mode filter circuit according to the third embodiment, and FIG. 36 is a flow chart for explaining the resonance frequency adjustment process of FIG.
  • the common mode filter circuit 1 of the third embodiment has a resonance frequency fr4 at which the load impedance Zt of the load circuit 60 connected between the output terminals 45s and 45g of the output voltage generation circuit 66 becomes maximum, and This is an example provided with a function of adjusting the difference between the output voltage Vs and the frequency fs.
  • the common-mode filter circuit 1 of Embodiments 1 and 2 extracts An output voltage Vs having a frequency corresponding to the frequency component of the common mode voltage Vcm is output from the output voltage generation circuit 66 to the load circuit 60 .
  • the capacitance of the impedance adjuster 18 is adjusted so as to satisfy the impedance condition described above. Value C was adjusted.
  • the impedance condition to be satisfied is that the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonance frequency fr4 is included in the range of the two cutoff frequencies fl and fh of the band limiting circuit 12 .
  • the common mode filter circuit 1 of the first and second embodiments is adjusted so that the load impedance Zt of the load circuit 60 is maximized with respect to the output voltage Vs having the frequency extracted by the band limiting circuit 12.
  • the load connected to the output voltage generation circuit 66 The resonance frequency fr4 at which the load impedance Zt of the circuit 60 is maximized and the frequency fs of the output voltage Vs output from the output voltage generation circuit 66 can be matched with high precision or made sufficiently close.
  • the common mode filter circuit 1 has a function of adjusting the resonance point of the load circuit 60, that is, the resonance frequency fr4 and the frequency fs of the output voltage Vs output from the output voltage generation circuit 66.
  • the common mode filter circuit 1 of the third embodiment shown in FIG. 31 differs from the common mode filter circuit 1 of the first embodiment in that the control circuit 13 and the capacitor 15 are replaced with the control circuit 30b and the LC regulator 65, and the output voltage It differs in that a current detector 17 for detecting the output current Is of the generating circuit 66 and a band limiting circuit 19 are added.
  • the impedance adjuster 18 is an example of the LC adjuster 65 , that is, an example in which the impedance adjuster 18 includes the capacitor 15 , the variable capacitor 57 and the variable inductor 58 .
  • the output voltage generation circuit 66 outputs a setting signal sig6 for setting the capacitance value and the inductance value of the impedance adjuster 18 based on the detected value of the output current Is detected by the current detector 17 .
  • the current detector 17 is a detector using a shunt resistor and an insulation amplifier, a non-contact magnetic detector, or the like.
  • the current detector 17 detects the output current Is of the output voltage generation circuit 66 and outputs a current detection signal sig7 containing information on the detected current Id.
  • Information on the detected current Id includes current amplitude and phase ⁇ d. As appropriate, the current amplitude of the detection current Id is used as it is.
  • the phase ⁇ d of the detection current Id is the same as the current phase of the output current Is.
  • Band-limiting circuit 19 passes a specific frequency component in current detection signal sig7 output from current detector 17, and outputs band-limiting signal sig8.
  • the band-limited signal sig8 contains information on the extracted current Idf in a specific frequency band.
  • Information on the extracted current Idf includes the current amplitude and phase ⁇ d. As appropriate, the current amplitude of the extracted current Idf is used as it is.
  • the current amplitude of the extraction current Idf is the same as the current amplitude of the detection current Id.
  • the extracted current Idf has the same phase as the detected current Id, and ⁇ d is used as the phase sign of the extracted current Idf.
  • Band-limited signal sig8 is input to control circuit 30b.
  • Control circuit 30b outputs setting signal sig6 for setting adjuster impedance Zst of LC adjuster 65, which is impedance adjuster 18, to LC adjuster 65 based on band-limiting signal sig8.
  • the LC adjuster 65 includes a capacitor 15, a variable capacitor 57, a variable An inductor 58 is provided.
  • the variable capacitor 57 includes a plurality of series bodies 55a and 55b in which capacitors and switches are connected in series.
  • the variable inductor 58 includes a plurality of series bodies 85a and 85b in which inductors and switches are connected in series.
  • FIG. 32 shows an example in which the variable capacitor 57 has two series bodies 55a and 55b and the variable inductor 58 has two series bodies 85a and 85b.
  • the variable capacitor 57 has two series bodies 55a and 55b connected in parallel between the wiring 64a and the wiring 64b.
  • the variable inductor 58 has two series bodies 85a and 85b connected in parallel between the wiring 64a and the wiring 64b.
  • the input terminals 62s and 62g are connected to the output terminals 45s and 45g of the amplifier circuit 14, respectively, and the output terminals 63s and 63g are connected to one end and the other end of the primary winding 8 of the common mode transformer 16, respectively.
  • the series body 55a has a capacitor 81a and a switch 54a connected in series
  • the series body 55b has a capacitor 81b and a switch 54b connected in series
  • the series body 85a has the inductor 82a and the switch 86a connected in series
  • the series body 85b has the inductor 82b and the switch 86b connected in series.
  • the switch 54a is controlled to be on and off by a setting signal sig6a input from the input terminal 67a.
  • Switches 54b, 86a, and 86b are similarly controlled to be on and off by setting signals sig6b, sig6c, and sig6d, respectively.
  • the switch 54b is controlled to be on and off by a setting signal sig6b input from the input terminal 67b.
  • the switch 86a is controlled to be on and off by a setting signal sig6c input from the input terminal 67c.
  • the switch 86b is controlled to be on and off by a setting signal sig6d input from the input terminal 67d.
  • sig6 is used in general, and sig6a, sig6b, sig6c, and sig6d are used when they are distinguished.
  • the series bodies 55a and 55b When the switches 54a and 54b are turned on, the series bodies 55a and 55b operate as capacitors 81a and 81b. When the switches 86a, 86b are turned on, the series bodies 85a, 85b operate as inductors 82a, 82b. When the switches 54a and 54b are turned off, the series bodies 55a and 55b, that is, the capacitors 81a and 81b are brought into an open state (disconnected state), and the capacitance value of the variable capacitor 57 can be reduced. The capacitance value of the variable capacitor 57 can be increased by increasing the number of parallel connections of the capacitors 15a and 15b, and the capacitance value of the variable capacitor 57 can be decreased by decreasing the number of parallel connections of the capacitors 15a and 15b.
  • the series bodies 85a and 85b that is, the inductors 82a and 82b are brought into an open state (disconnected state), and the inductance value of the variable inductor 58 can be lowered.
  • the inductance value of the variable inductor 58 can be decreased by increasing the number of parallel connections of the inductors 82a and 82b, and the inductance value of the variable inductor 58 can be increased by decreasing the number of parallel connections of the inductors 82a and 82b.
  • FIG. 34 shows an equivalent circuit of the load circuit 60 between the output terminals of the amplifier circuit 14 in the common mode filter circuit 1 of the third embodiment.
  • the impedance adjuster 18 of the common mode filter circuit 1 of the third embodiment includes the capacitor 15, the variable capacitor 57 and the variable inductor 58.
  • the load circuit 60 of the third embodiment is an LC parallel resonance circuit in which the impedances of the capacitor 15, the variable capacitor 57, the variable inductor 58, the excitation inductor of the common mode transformer 16, and the loop path 61 are connected in parallel.
  • the capacitor 15, the variable capacitor 57, and the variable inductor 58 are components of the impedance adjuster 18, and the adjuster impedance Zst of the impedance adjuster 18 is composed of the capacitor 15 with a capacitance value C, the variable capacitor 57 with a capacitance value Ccp, and the inductance value It is an impedance in which the variable inductor 58 of Lcp is connected in parallel.
  • FIG. 34 also shows capacitor current Ica and inductor current Ila of variable capacitor 57 and variable inductor 58 added to the equivalent circuit of FIG.
  • the impedance adjuster 18 adjusts the capacitance value Ccp of the variable capacitor 57 and the inductance value Lcp of the variable inductor 58 by controlling the on and off of the switches 54a, 54b and the switches 86a, 86b. Since the impedance adjuster 18 also includes a capacitor 15 with a capacitance value of C, the capacitance value of the impedance adjuster 18 is C+Ccp.
  • the control circuit 30b adjusts the capacitance value and the inductance value of the impedance adjuster 18 by the setting signal sig6 so that the load impedance Zt of the load circuit 60 becomes equal to the output voltage Vs having a specific frequency.
  • the control circuit 30b adjusts the resonance frequency fr4 of the load circuit 60 so that the load impedance Zt of the load circuit 60 becomes maximum with respect to the output voltage Vs having a specific frequency.
  • the common mode impedance Z is sufficiently larger than the excitation impedance Zl in a specific frequency band determined by the gain characteristic of the band limiting circuit 12, the common mode impedance Z can be ignored, and the capacitance value Ccp of the variable capacitor 57 and the variable
  • the inductance value Lcp of the inductor 58 is intended for error correction of the exciting inductance value Lm of the exciting impedance Zl and the capacitance value C of the capacitor 15 .
  • the inductance value Lcp is preferably five times or more the exciting inductance value Lm.
  • Ccp be 1/5 or less of the capacitance value C of the capacitor 15 .
  • the fluctuation value of the common mode impedance Z cannot be ignored with respect to the excitation impedance Zl, the fluctuation value of the common mode impedance Z also becomes an error factor.
  • the inductance value Lcp and the capacitance value Ccp may be set so as to correspond to the fluctuation value of the common mode impedance Z.
  • the control circuit 30a is different from the control circuit 13 shown in FIG. and a setting signal generation circuit 56 that outputs a setting signal sig6 for setting the inductance value Lcp of the variable inductor 58 is added. A part different from the control circuit 13 will be mainly described.
  • the AD converter 31a takes in the band limited signal sig8 of the band limiting circuit 19 from the input terminals 34ss and 34g.
  • the AD converter 31a converts the analog band-limited signal sig8 into a digital extracted signal sig8d.
  • the extracted signal sig8d contains information on the extracted current Idf in a specific frequency band.
  • the setting signal generation circuit 56 operates the switches 54a and 54b of the variable capacitor 57 and the switch 86a of the variable inductor 58 based on the current amplitude Idf of the extraction current and the phase ⁇ d of the extraction current Idf, which are information on the extraction current Idf of the extraction signal sig8d. , 86b are turned on or off. Since the step of setting the capacitance value Ccp of the variable capacitor 57 and the inductance value Lcp of the variable inductor 58 is the step of adjusting the resonance frequency of the load circuit 60, the setting signal generation circuit 56 executes the resonance frequency adjustment step. The resonance frequency adjustment process is performed prior to the phase adjustment process and the amplitude adjustment process described in the first embodiment.
  • the setting signal generation circuit 56 compares the phase ⁇ s of the output voltage Vs and the phase ⁇ d of the extracted current Idf in the resonance frequency adjustment step, and if the phase ⁇ d lags behind the phase ⁇ s, sets the capacitive capacitance value Ccp. Applied to the load circuit 60, an inductive inductance value Lcp is applied to the load circuit 60 when the phase ⁇ d leads the phase ⁇ s.
  • the voltage phase ⁇ 2 and the voltage amplitude V2 calculated from the band-limited signal sig2 are generated as the voltage phase ⁇ réelle and the voltage amplitude V réelle, and the voltage phase A compensation signal sig3 having ⁇ 0 and voltage amplitude V 0 is output.
  • An output signal sig4 having an output voltage Vs is output to the load circuit 60 based on the compensation signal sig3. Therefore, the voltage phase ⁇ réelle output by the digital circuit 32 is used as the phase ⁇ s of the output voltage Vs.
  • the setting signal generation circuit 56 turns on at least one of the switches 54a and 54b of the variable capacitor 57 when the phase ⁇ d lags behind the voltage phase ⁇ GmbH so that the phase ⁇ d becomes the voltage phase ⁇ réelle. turns on at least one of the switches 86a, 86b of the variable inductor 58 if it is ahead.
  • the setting signal generation circuit 56 keeps the switches 54a and 54b of the variable capacitor 57 and the switch 86a of the variable inductor 58 until the current amplitude Idf of the extracted current becomes equal to or less than the threshold value Ith or until the current amplitude Idf of the extracted current becomes minimum.
  • the load circuit 60 connected between the output terminals 45s and 45g of the amplifier circuit 14 has a frequency fs of the output voltage Vs output from the amplifier circuit 14 of the output voltage generation circuit 66.
  • the resonance point of the load circuit 60 that is, the resonance frequency fr4 can be changed so that the load impedance Zt of the load circuit 60 becomes high. Therefore, a large increase in the output current Is can be prevented.
  • step S51 the control circuit 30b executes a resonance frequency adjustment process to set the capacitance value Ccp of the variable capacitor 57 and the inductance value Lcp of the variable inductor 58 in this resonance frequency adjustment process.
  • Steps S52 to S55 of FIG. 36 are executed in the resonance frequency adjustment process.
  • Step S05 is performed after the resonance frequency adjustment process of step S51.
  • the resonance frequency adjustment process is executed prior to the phase adjustment process and the amplitude adjustment process, and the capacitance value Ccp and the inductance value Lcp are set only once.
  • the control circuit 30b determines whether the compensation signal sig3 is being output. If the compensation signal sig3 is not being output, the process proceeds to step S53, and if the compensation signal sig3 is being output, the process ends.
  • the control circuit 30b generates the voltage phase ⁇ 2 and the voltage amplitude V2 calculated from the band-limited signal sig2 as the voltage phase ⁇ réelle and the voltage amplitude V technically, and generates the compensation signal sig3 having the voltage phase ⁇ réelle and the voltage amplitude V réelle. Output.
  • the amplifier circuit 14 outputs an output signal sig4 based on the compensation signal sig3 output from the control circuit 30b.
  • step S54 the control circuit 30b detects whether the current amplitude Idf of the extracted current in the information of the extracted current Idf, which is the information of the band-limited output current Is detected by the current detector 17, exceeds the threshold value Ith. judge. If the current amplitude Idf of the extracted current exceeds the threshold Ith, the process proceeds to step S55, and if the current amplitude Idf of the extracted current does not exceed the threshold Ith, that is, if the current amplitude Idf of the extracted current is equal to or less than the threshold Ith, the process ends. .
  • step S55 the control circuit 30b compares the phase ⁇ d in the information of the extracted current Idf with the voltage phase ⁇ réelle generated by the digital circuit 32.
  • FIG. The voltage phase ⁇ Washington and the phase ⁇ d of the extracted current Idf are compared, and if the phase ⁇ d lags behind the voltage phase ⁇ réelle, the capacitance value Ccp is increased, and if the phase ⁇ d leads the voltage phase ⁇ réelle, the inductance value By increasing Lcp, the capacitance value Ccp and the inductance value Lcp are set.
  • Step S54 is executed after step S55.
  • the current amplitude Idf of the extracted current Idf is determined based on the information of the output current Is newly detected by the current detector 17 until the current amplitude Idf does not exceed the threshold value Ith, that is, the current amplitude Idf Steps S54 and S55 are repeated until the threshold value Ith or less is reached.
  • Step S05 is performed after the resonance frequency adjustment process of step S51.
  • step S54 in FIG. 36 an example is shown in which whether or not the current amplitude Idf of the extracted current exceeds the threshold value Ith is used as the determination condition. good.
  • the output voltage generation circuit 66 determines the capacitance value and the inductance value of the impedance adjuster 18 at which the output value of the signal output from the band limiting circuit 19 (second band limiting circuit), that is, the band limiting signal sig8 is equal to or lower than the threshold value Ith. Alternatively, it determines the capacitance value and inductance value of the impedance adjuster 18 that minimizes the output value of the band-limiting signal sig8, and outputs the setting signal sig6 that sets the capacitance value.
  • the flowchart shown in FIG. 35 is an example corresponding to the flowchart for explaining the operation of the first example of the common mode filter circuit 1 of the first embodiment.
  • This is the first example in which the digital circuit 32 in the control circuit 30b of the third embodiment is shown in FIG.
  • the digital circuit 32 in the control circuit 30b of the third embodiment may be the second example shown in FIG.
  • the flowchart in this case is a flowchart in which step S51 is added before step S10 in the flowchart shown in FIG.
  • Each of the switches 54a to 54d only needs to have a bidirectional cut-off and conduction function, and is, for example, a mechanical switch, a semiconductor switch, or the like.
  • frequency component C ... capacitance value Ccp ... capacitance value f1, f1a, f1b, f1n ... carrier frequency f3, f3a, f3b, f3n ... tertiary component frequency f5, f5a, f5b, f5n ... quintic component frequency , f7, f7a, f7b, f7n... seventh component frequency, flg1... phase adjustment flag, fl... cutoff frequency, fh... cutoff frequency, fr4... resonance frequency, Idf... extracted current, Is... output current, Ith... threshold , Lcp... inductance value, Lm... exciting inductance value, sig1...

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Inverter Devices (AREA)

Abstract

This common mode filter circuit (1) comprises: a voltage detection circuit (11) for outputting a signal (sig1) including information of the common mode voltage (Vcm) generated on power lines (4, 5); a band limiting circuit (12) for allowing a specific frequency component to pass; a common mode transformer (16) for superimposing an injection voltage (Vap) onto the power lines (4, 5); an output voltage generation circuit (66) for outputting an output voltage (Vs) to the primary winding (8) of the transformer (16); and an impedance adjuster (18) for adjusting the load impedance (Zt) of a load circuit (60) including the transformer (16) connected between the output terminals of the output voltage generation circuit (66). The impedance (Zst) of the adjuster (18) is set such that a frequency (fr4) at which the load impedance (Zt) including the impedance (Zst) is maximized is within a range of two cut-off frequencies (fl, fh) of the band limiting circuit (12).

Description

コモンモードフィルタ回路Common mode filter circuit
　本願は、コモンモードフィルタ回路に関するものである。 This application relates to a common mode filter circuit.
　電圧形の電力変換回路を備えたパワーエレクトロニクス機器は、半導体素子であるパワーデバイスを高速にスイッチングさせることで矩形波状の電圧を出力し、その平均値を制御することで任意の電流波形あるいは電圧波形を生成する。電力変換回路の交流端子と基準電位になっている接地（GND）との間の電圧の平均値で定義されるコモンモード電圧が変動すると、電力変換回路と接地との浮遊容量により形成される経路すなわちコモンモード経路にコモンモード電流が流れる。コモンモード電流は誘導障害を発生させるため電力変換回路の周辺の電子回路を誤動作させるなどの悪影響を及ぼすことが知られている。そこでコモンモード電流を低減するために、電力変換回路から発生するコモンモード電圧を検出し、検出値に対し逆相の補償電圧（注入電圧）を注入することでコモンモード電圧を相殺するコモンモードフィルタ回路が提案されている。 A power electronics device equipped with a voltage-source power conversion circuit outputs a square-wave voltage by switching a power device, which is a semiconductor element, at high speed. to generate The path formed by the stray capacitance between the power conversion circuit and ground when the common mode voltage, defined as the average value of the voltage between the AC terminals of the power conversion circuit and ground (GND), which is the reference potential, fluctuates. That is, a common mode current flows through the common mode path. It is known that the common mode current causes an inductive failure and has adverse effects such as malfunctioning of electronic circuits around the power conversion circuit. Therefore, in order to reduce the common mode current, a common mode filter that offsets the common mode voltage by detecting the common mode voltage generated by the power conversion circuit and injecting a compensation voltage (injection voltage) with the opposite phase to the detected value. A circuit is proposed.
　例えば特許文献１には、電力用半導体素子のスイッチング動作に基づいて電力変換を行う際に発生するコモンモード電圧を相殺するアクティブコモンキャンセラが開示されている。特許文献１のアクティブコモンキャンセラは、三相交流配線の各相にＹ結線された３つのコンデンサの中性点と接地との間のコモンモード電圧を検出し、トランジスタで構成されると共に電力変換回路の入力側を駆動電源にしたプッシュプル回路により検出されたコモンモード電圧を増幅し、コンデンサを介してコモンモードトランスの一次側巻線（一次巻線）に出力する。コモンモードトランスの二次側巻線（二次巻線）は三相交流配線に接続されており、コモンモードトランスを用いて、三相交流配線の各相にコモンモード電圧と逆相で同一電圧を注入することでコモンモード電圧を相殺する。すなわち、特許文献１のアクティブコモンキャンセラは、電力変換回路から発生するコモンモード電圧に対し、逆相の補償電圧（注入電圧）をコモンモードトランスに出力することでコモンモード電圧を打ち消している。プッシュプル回路は、言わばコモンモードトランスに出力する出力電圧を生成する出力電圧生成回路である。 For example, Patent Literature 1 discloses an active common canceller that cancels common mode voltages generated when power conversion is performed based on the switching operation of power semiconductor devices. The active common canceller of Patent Document 1 detects a common mode voltage between the neutral point of three capacitors Y-connected to each phase of a three-phase AC wiring and the ground, and comprises a transistor and a power conversion circuit. Amplifies the common mode voltage detected by the push-pull circuit whose input side is used as the driving power supply, and outputs it to the primary winding (primary winding) of the common mode transformer via the capacitor. The secondary winding (secondary winding) of the common mode transformer is connected to the three-phase AC wiring. cancels the common-mode voltage by injecting That is, the active common canceller of Patent Document 1 cancels the common mode voltage generated from the power conversion circuit by outputting a compensation voltage (injection voltage) having an opposite phase to the common mode transformer. A push-pull circuit is, so to speak, an output voltage generation circuit that generates an output voltage to be output to a common mode transformer.
特許第２８６３８３３号公報（図１）Japanese Patent No. 2863833 (Fig. 1)
　特許文献１のアクティブコモンキャンセラのようなコモンモードフィルタ回路において、コモンモードトランスの励磁インダクタンス値をＬｍとした場合に特定の周波数ｆの電圧Ｖを印加すると、磁束発生のためにＩｍ＝Ｖ／（２πｆＬｍ）で決まる励磁電流Ｉｍを流す必要がある。低周波の電圧を印加した場合には、励磁電流の振幅すなわち励磁電流を増大させるか、又は励磁インダクタンスを増加させる必要がある。トランスの励磁インダクタンスは、巻数の２乗に比例、鉄心断面積に比例、鉄心磁路長に反比例する。したがって、設計次第では励磁インダクタンスを増加できるが、励磁インダクタンスを大きくするとトランスの体積が増大し、構造上の制約からその対策には限界がある。低周波成分に対しては励磁インダクタンスのインピーダンスは低く制限され、短絡状態に近い状態となってしまうため、何らかの対策が必要になる。 In a common mode filter circuit such as the active common canceller of Patent Document 1, when the excitation inductance value of the common mode transformer is Lm and a voltage V of a specific frequency f is applied, Im=V/( 2πfLm) is required to flow. When a low-frequency voltage is applied, it is necessary to increase the amplitude of the exciting current, that is, the exciting current, or to increase the exciting inductance. The excitation inductance of the transformer is proportional to the square of the number of turns, proportional to the core cross-sectional area, and inversely proportional to the core magnetic path length. Therefore, depending on the design, the exciting inductance can be increased. Since the impedance of the exciting inductance is limited to a low frequency component and the state is close to a short-circuit state, some countermeasures are required.
　特許文献１のアクティブコモンキャンセラでは、励磁インダクタンスを増加させずに数１０ｋＨｚ以下の低周波成分のコモンモード電圧を低減するには、励磁電流が増加するため出力電圧生成回路において電流容量の大きい能動素子が必要となる。電流容量の大きい能動素子は線形領域で動作するため、大電流を流すと損失が大きく発熱する。このため、特許文献１のアクティブコモンキャンセラは、低周波成分のコモンモード電圧に対処する場合に、電流容量の大きい能動素子の搭載に伴って、能動素子の冷却系が大型になり、装置が大型になる問題があった。 In the active common canceller of Patent Document 1, in order to reduce the common mode voltage of low frequency components of several tens of kHz or less without increasing the excitation inductance, an active element with a large current capacity is used in the output voltage generation circuit because the excitation current increases. Is required. Since an active element with a large current capacity operates in a linear region, when a large current flows, the loss is large and heat is generated. Therefore, when the active common canceller of Patent Document 1 copes with the common mode voltage of the low frequency component, the cooling system of the active element becomes large due to the mounting of the active element having a large current capacity, and the device becomes large. There was a problem of becoming
　前述の問題は、低周波成分のコモンモード電圧に対処する場合に、出力電圧生成回路からコモンモードトランスに出力する出力電流が大幅に増加することで生じる。このため、低周波成分のコモンモード電圧の場合でも、出力電圧生成回路からコモンモードトランスに出力する出力電流の大幅な増加を防止することで、電流容量の大きい能動素子が不要となり、電流容量の大きい能動素子の搭載に伴う問題は生じない。 The above-mentioned problem is caused by a large increase in the output current output from the output voltage generation circuit to the common mode transformer when dealing with the common mode voltage of the low frequency component. Therefore, even in the case of a common mode voltage with a low frequency component, by preventing a large increase in the output current output from the output voltage generation circuit to the common mode transformer, an active element with a large current capacity becomes unnecessary, and the current capacity is reduced. There are no problems associated with mounting large active devices.
　本願明細書に開示される技術は、低周波成分のコモンモード電圧の場合でも、出力電圧生成回路から出力される出力電流の大幅な増加を防止するコモンモードフィルタ回路を提供することを目的とする。 An object of the technology disclosed in the specification of the present application is to provide a common mode filter circuit that prevents a large increase in the output current output from the output voltage generation circuit even in the case of a common mode voltage with a low frequency component. .
　本願明細書に開示される一例のコモンモードフィルタ回路は、半導体素子のスイッチング動作により電力変換を行う電力変換回路が電力線に発生させるコモンモード電圧を低減するコモンモードフィルタ回路である。コモンモードフィルタ回路は、電力線に生じたコモンモード電圧を検出してコモンモード電圧の情報を含む電圧検出信号を出力する電圧検出回路と、電圧検出回路により出力された電圧検出信号における特定の周波数成分を通過させる帯域制限回路と、電力線に接続された二次巻線と一次巻線とを有し、電力線にコモンモード電圧を低減する注入電圧を重畳するコモンモードトランスと、帯域制限回路により出力された周波数成分を含む帯域制限信号に基づく信号の電圧振幅を許容値以下に低減する出力電圧を生成すると共に、出力電圧をコモンモードトランスの一次巻線に出力する出力電圧生成回路と、コモンモードトランスの一次巻線に並列に接続されると共に、出力電圧生成回路の出力端子間に接続されているコモンモードトランスを含む負荷回路の負荷インピーダンスを調整するインピーダンス調整器と、を備えている。インピーダンス調整器のインピーダンスは、当該インピーダンスを含む出力電圧生成回路の出力端子間に接続された負荷インピーダンスが最大となる周波数が、帯域制限回路の二つのカットオフ周波数の範囲内に設定されている。 An example of the common mode filter circuit disclosed in the specification of the present application is a common mode filter circuit that reduces a common mode voltage generated on a power line by a power conversion circuit that converts power by switching operations of semiconductor elements. The common mode filter circuit includes a voltage detection circuit that detects a common mode voltage generated on a power line and outputs a voltage detection signal containing information on the common mode voltage, and a specific frequency component in the voltage detection signal output by the voltage detection circuit. , a common mode transformer that has a secondary winding and a primary winding connected to the power line, and superimposes an injection voltage that reduces the common mode voltage on the power line, and the band limiting circuit outputs an output voltage generating circuit that generates an output voltage that reduces the voltage amplitude of a signal based on a band-limited signal that includes a frequency component of the band-limited signal to an allowable value or less, and that outputs the output voltage to a primary winding of a common mode transformer; an impedance adjuster that adjusts the load impedance of a load circuit that is connected in parallel to the primary winding of the and includes a common mode transformer that is connected between output terminals of the output voltage generation circuit. The impedance of the impedance adjuster is set such that the frequency at which the load impedance connected between the output terminals of the output voltage generating circuit including the impedance becomes maximum is within the range of the two cutoff frequencies of the band limiting circuit.
　本願明細書に開示される一例のコモンモードフィルタ回路は、コモンモードトランスの一次巻線に並列にされたインピーダンス調整器を備え、負荷インピーダンスが最大となる周波数が帯域制限回路の二つのカットオフ周波数の範囲内に含まれるようにインピーダンス調整器のインピーダンスが調整されているので、低周波成分のコモンモード電圧の場合でも、出力電圧生成回路から出力される出力電流の大幅な増加を防止することができる。 An example common-mode filter circuit disclosed herein comprises an impedance adjuster in parallel with the primary winding of a common-mode transformer such that the frequency at which the load impedance is maximum is the two cut-off frequencies of the bandlimiting circuit. Since the impedance of the impedance adjuster is adjusted so that it falls within the range of can.
実施の形態１に係るコモンモードフィルタ回路の構成を示す図である。1 is a diagram showing a configuration of a common mode filter circuit according to Embodiment 1; FIG. 図１の電力変換回路の構成を示す図である。2 is a diagram showing the configuration of the power conversion circuit of FIG. 1; FIG. 図１の制御回路の構成を示す図である。2 is a diagram showing a configuration of a control circuit in FIG. 1; FIG. 図１の増幅回路の構成を示す図である。2 is a diagram showing a configuration of an amplifier circuit in FIG. 1; FIG. 図１の増幅回路の出力端子間に接続された負荷回路の等価回路を示す図である。2 is a diagram showing an equivalent circuit of a load circuit connected between output terminals of the amplifier circuit of FIG. 1; FIG. 図１の帯域制限回路のゲイン特性及び図５の負荷回路のインピーダンス特性を示す図である。6 is a diagram showing gain characteristics of the band limiting circuit of FIG. 1 and impedance characteristics of the load circuit of FIG. 5; FIG. 図１の増幅回路の出力電流のベクトルを示す図である。2 is a diagram showing vectors of output currents of the amplifier circuit of FIG. 1; FIG. 比較例のコモンモードフィルタ回路における増幅回路の出力電流のベクトルを示す図である。FIG. 5 is a diagram showing vectors of output currents of an amplifier circuit in a common mode filter circuit of a comparative example; 図１の帯域制限回路のゲイン特性及びコモンモード電圧の周波数成分の第一例を示す図である。2 is a diagram showing a first example of gain characteristics of the band limiting circuit of FIG. 1 and frequency components of a common mode voltage; FIG. 図１の帯域制限回路のゲイン特性及びコモンモード電圧の周波数成分の第二例を示す図である。2 is a diagram showing a second example of gain characteristics of the band limiting circuit of FIG. 1 and frequency components of a common mode voltage; FIG. 図３のデジタル回路の第一例の構成を示す図である。4 is a diagram showing the configuration of a first example of the digital circuit of FIG. 3; FIG. 実施の形態１に係るコモンモードフィルタ回路の第一例の動作を説明するフローチャートである。4 is a flowchart for explaining the operation of the first example of the common mode filter circuit according to Embodiment 1; 図１２の位相調整工程を説明するフローチャートである。FIG. 13 is a flow chart illustrating a phase adjustment process of FIG. 12; FIG. 図１２の振幅調整工程を説明するフローチャートである。FIG. 13 is a flowchart for explaining an amplitude adjustment process of FIG. 12; FIG. 実施の形態１に係るコモンモードフィルタ回路における位相調整によるコモンモード電圧の残留量を説明する図である。FIG. 10 is a diagram for explaining a residual amount of common mode voltage due to phase adjustment in the common mode filter circuit according to the first embodiment; 実施の形態１に係るコモンモードフィルタ回路における振幅調整によるコモンモード電圧の残留量を説明する図である。FIG. 10 is a diagram for explaining a residual amount of common mode voltage due to amplitude adjustment in the common mode filter circuit according to the first embodiment; 図３のデジタル回路の第一例における位相調整例を示す図である。4 is a diagram showing an example of phase adjustment in the first example of the digital circuit of FIG. 3; FIG. 図３のデジタル回路の第一例における振幅調整例を示す図である。4 is a diagram showing an example of amplitude adjustment in the first example of the digital circuit of FIG. 3; FIG. 図３のデジタル回路の第二例の構成を示す図である。4 is a diagram showing a configuration of a second example of the digital circuit of FIG. 3; FIG. 図１９の探索回路の構成を示す図である。20 is a diagram showing a configuration of a search circuit in FIG. 19; FIG. 実施の形態１に係るコモンモードフィルタ回路の第二例の動作を説明するフローチャートである。8 is a flowchart for explaining the operation of the second example of the common mode filter circuit according to Embodiment 1; 図３のデジタル回路の機能を実現するハードウェア構成例を示す図である。FIG. 4 is a diagram showing a hardware configuration example that realizes the functions of the digital circuit in FIG. 3; 図１９の探索回路に組込むモデルを生成する学習装置の構成を示す図である。FIG. 20 is a diagram showing the configuration of a learning device that generates a model to be incorporated into the search circuit of FIG. 19; 実施の形態２に係るコモンモードフィルタ回路の構成を示す図である。FIG. 10 is a diagram showing a configuration of a common mode filter circuit according to Embodiment 2; 図２４の帯域制限回路群の構成を示す図である。25 is a diagram showing a configuration of a band limiting circuit group of FIG. 24; FIG. 図２４の制御回路の構成を示す図である。25 is a diagram showing a configuration of a control circuit of FIG. 24; FIG. 図２４の可変コンデンサの構成を示す図である。25 is a diagram showing the configuration of a variable capacitor in FIG. 24; FIG. 図２４の帯域制限回路群のゲイン特性及びコモンモード電圧の周波数成分の第一例を示す図である。25 is a diagram showing a first example of gain characteristics of the band limiting circuit group of FIG. 24 and frequency components of a common mode voltage; FIG. 図２４の帯域制限回路群のゲイン特性及びコモンモード電圧の周波数成分の第二例を示す図である。25 is a diagram showing a second example of gain characteristics of the band limiting circuit group of FIG. 24 and frequency components of common mode voltage; FIG. 実施の形態２に係るコモンモードフィルタ回路の動作を説明するフローチャートである。9 is a flow chart for explaining the operation of the common mode filter circuit according to the second embodiment; 実施の形態３に係るコモンモードフィルタ回路の構成を示す図である。FIG. 10 is a diagram showing the configuration of a common mode filter circuit according to Embodiment 3; 図３１のＬＣ調整器の構成を示す図である。32 is a diagram showing the configuration of the LC regulator of FIG. 31; FIG. 図３１の制御回路の構成を示す図である。32 is a diagram showing a configuration of a control circuit in FIG. 31; FIG. 図３１の増幅回路の出力端子間に接続された負荷回路の等価回路を示す図である。32 is a diagram showing an equivalent circuit of a load circuit connected between output terminals of the amplifier circuit of FIG. 31; FIG. 実施の形態３に係るコモンモードフィルタ回路の動作を説明するフローチャートである。10 is a flow chart for explaining the operation of the common mode filter circuit according to the third embodiment; 図３５の共振周波数調整工程を説明するフローチャートである。FIG. 36 is a flowchart for explaining a resonance frequency adjustment process of FIG. 35; FIG.
　コモンモードフィルタ回路について、図面を参照しながら説明する。以下の図面において、同一又はこれに相当するものに同一符号を付けて説明する。 The common mode filter circuit will be explained with reference to the drawings. In the following drawings, the same reference numerals are assigned to the same or corresponding parts.
実施の形態１．
　図１は実施の形態１に係るコモンモードフィルタ回路の構成を示す図であり、図２は図１の電力変換回路の構成を示す図である。図３は図１の制御回路の構成を示す図であり、図４は図１の増幅回路の構成を示す図である。図５は図１の増幅回路の出力端子間に接続された負荷回路の等価回路を示す図であり、図６は図１の帯域制限回路のゲイン特性及び図５の負荷回路のインピーダンス特性を示す図である。図７は図１の増幅回路の出力電流のベクトルを示す図であり、図８は比較例のコモンモードフィルタ回路における増幅回路の出力電流のベクトルを示す図である。図９は図１の帯域制限回路のゲイン特性及びコモンモード電圧の周波数成分の第一例を示す図であり、図１０は図１の帯域制限回路のゲイン特性及びコモンモード電圧の周波数成分の第二例を示す図である。図１１は図３のデジタル回路の第一例の構成を示す図である。図１２は、実施の形態１に係るコモンモードフィルタ回路の第一例の動作を説明するフローチャートである。図１３は図１２の位相調整工程を説明するフローチャートであり、図１４は図１２の振幅調整工程を説明するフローチャートである。図１５は、実施の形態１に係るコモンモードフィルタ回路における位相調整によるコモンモード電圧の残留量を説明する図である。図１６は、実施の形態１に係るコモンモードフィルタ回路における振幅調整によるコモンモード電圧の残留量を説明する図である。図１７は図３のデジタル回路の第一例における位相調整例を示す図であり、図１８は図３のデジタル回路の第一例における振幅調整例を示す図である。図１９は図３のデジタル回路の第二例の構成を示す図であり、図２０は図１９の探索回路の構成を示す図である。図２１は、実施の形態１に係るコモンモードフィルタ回路の第二例の動作を説明するフローチャートである。図２２は、図３のデジタル回路の機能を実現するハードウェア構成例を示す図である。図２３は、図１９の探索回路に組込むモデルを生成する学習装置の構成を示す図である。 Embodiment 1.
FIG. 1 is a diagram showing the configuration of a common mode filter circuit according to Embodiment 1, and FIG. 2 is a diagram showing the configuration of the power conversion circuit in FIG. 3 is a diagram showing the configuration of the control circuit in FIG. 1, and FIG. 4 is a diagram showing the configuration of the amplifier circuit in FIG. 5 is a diagram showing an equivalent circuit of the load circuit connected between the output terminals of the amplifier circuit of FIG. 1, and FIG. 6 shows the gain characteristics of the band limiting circuit of FIG. 1 and the impedance characteristics of the load circuit of FIG. It is a diagram. 7 is a diagram showing an output current vector of the amplifier circuit of FIG. 1, and FIG. 8 is a diagram showing an output current vector of the amplifier circuit in the common mode filter circuit of the comparative example. 9 is a diagram showing a first example of the gain characteristics of the band limiting circuit of FIG. 1 and the frequency components of the common mode voltage, and FIG. 10 is a diagram showing the gain characteristics of the band limiting circuit of FIG. It is a figure which shows two examples. FIG. 11 is a diagram showing the configuration of a first example of the digital circuit of FIG. 12 is a flowchart for explaining the operation of the first example of the common mode filter circuit according to the first embodiment; FIG. 13 is a flow chart explaining the phase adjustment process of FIG. 12, and FIG. 14 is a flow chart explaining the amplitude adjustment process of FIG. FIG. 15 is a diagram for explaining the amount of residual common mode voltage due to phase adjustment in the common mode filter circuit according to the first embodiment. FIG. 16 is a diagram for explaining the amount of residual common mode voltage due to amplitude adjustment in the common mode filter circuit according to the first embodiment. 17 is a diagram showing an example of phase adjustment in the first example of the digital circuit in FIG. 3, and FIG. 18 is a diagram showing an example of amplitude adjustment in the first example of the digital circuit in FIG. 19 is a diagram showing the configuration of a second example of the digital circuit of FIG. 3, and FIG. 20 is a diagram showing the configuration of the search circuit of FIG. 21 is a flowchart for explaining the operation of the second example of the common mode filter circuit according to the first embodiment; FIG. FIG. 22 is a diagram showing a hardware configuration example that implements the functions of the digital circuit in FIG. 23 is a diagram showing the configuration of a learning device that generates a model to be incorporated into the search circuit of FIG. 19. FIG.
　実施の形態１のコモンモードフィルタ回路１は、半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６のスイッチング動作により電力変換を行う電力変換回路２が電力線４、５に発生させるコモンモード電圧Ｖｃｍを低減するコモンモードフィルタ回路である。補償対象３と電力変換回路２とは、電力線４、コモンモードトランス１６の二次巻線７、電力線５を介して接続されている。補償対象３は、例えば電力系統、電動機等である。コモンモードフィルタ回路１は、電圧検出回路１１、帯域制限回路１２、出力電圧生成回路６６、インピーダンス調整器１８、コモンモードトランス１６を備えている。電圧検出回路１１は、電力線４、５に生じたコモンモード電圧Ｖｃｍを検出してコモンモード電圧Ｖｃｍの情報を含む電圧検出信号ｓｉｇ１を出力する。帯域制限回路１２は、電圧検出回路１１により出力された電圧検出信号ｓｉｇ１における特定の周波数成分を通過させ、帯域制限信号ｓｉｇ２を出力する。 In the common mode filter circuit 1 of the first embodiment, the common mode voltage Vcm generated on the power lines 4 and 5 by the power conversion circuit 2 that converts power by the switching operations of the semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6 is It is a common mode filter circuit that reduces The compensation target 3 and the power conversion circuit 2 are connected via the power line 4 , the secondary winding 7 of the common mode transformer 16 and the power line 5 . The compensation target 3 is, for example, a power system, an electric motor, and the like. The common mode filter circuit 1 includes a voltage detection circuit 11 , a band limiting circuit 12 , an output voltage generation circuit 66 , an impedance adjuster 18 and a common mode transformer 16 . The voltage detection circuit 11 detects a common mode voltage Vcm generated on the power lines 4 and 5 and outputs a voltage detection signal sig1 containing information on the common mode voltage Vcm. The band-limiting circuit 12 passes a specific frequency component in the voltage detection signal sig1 output from the voltage detection circuit 11, and outputs a band-limiting signal sig2.
　出力電圧生成回路６６は、制御回路１３と、制御回路１３により出力された補償信号ｓｉｇ３を増幅し、増幅された出力信号ｓｉｇ４をコモンモードトランス１６に出力する増幅回路１４と、を備えている。出力電圧生成回路６６の制御回路１３は、増幅回路１４から出力される出力信号ｓｉｇ４の電圧である出力電圧Ｖｓによりコモンモード電圧Ｖｃｍが許容値（閾値Ｖｔｈ１）以下になるように、帯域制限回路１２により出力された周波数成分を含む帯域制限信号ｓｉｇ２に基づく信号すなわち当該制御回路１３が演算した演算出力信号ｓｉｇ３ｄの電圧振幅Ｖоを許容値（閾値Ｖｔｈ２）以下に低減する補償信号ｓｉｇ３を生成する。したがって、出力電圧生成回路６６は、制御回路１３、増幅回路１４により、コモンモード電圧Ｖｃｍが許容値（閾値Ｖｔｈ１）以下になるように、すなわち電圧検出回路１１により出力された電圧検出信号ｓｉｇ１の電圧振幅が減少するように、当該制御回路１３が演算した演算出力信号ｓｉｇ３ｄの電圧振幅Ｖоを許容値（閾値Ｖｔｈ２）以下に低減する出力電圧Ｖｓを生成する。 The output voltage generation circuit 66 includes a control circuit 13 and an amplifier circuit 14 that amplifies the compensation signal sig3 output from the control circuit 13 and outputs the amplified output signal sig4 to the common mode transformer 16. The control circuit 13 of the output voltage generation circuit 66 controls the band limit circuit 12 so that the common mode voltage Vcm becomes equal to or less than the allowable value (threshold value Vth1) by the output voltage Vs, which is the voltage of the output signal sig4 output from the amplifier circuit 14. A signal based on the band-limited signal sig2 including the frequency component output from the control circuit 13, that is, a compensation signal sig3 that reduces the voltage amplitude V.sub.O of the operation output signal sig3d calculated by the control circuit 13 to an allowable value (threshold value Vth2) or less. Therefore, the output voltage generating circuit 66 controls the control circuit 13 and the amplifying circuit 14 so that the common mode voltage Vcm becomes equal to or less than the allowable value (threshold value Vth1), that is, the voltage of the voltage detection signal sig1 output by the voltage detection circuit 11. An output voltage Vs that reduces the voltage amplitude V.sub.O of the computation output signal sig3d computed by the control circuit 13 to a permissible value (threshold value Vth2) or less is generated so that the amplitude decreases.
　コモンモードトランス１６は、電力線４、５に接続された二次巻線７と出力電圧生成回路６６の出力端子間に接続された一次巻線８とを有し、電力線４、５にコモンモード電圧Ｖｃｍを低減する注入電圧Ｖａｐを重畳する。すなわちコモンモードトランス１６は、出力電圧生成回路６６により出力された出力電圧Ｖｓが一次巻線８に入力されると、コモンモード電圧Ｖｃｍを低減する注入電圧Ｖａｐを電力線４、５に注入する。インピーダンス調整器１８は、コモンモードトランス１６の一次巻線８に並列に接続されると共に、出力電圧生成回路６６の出力端子すなわち増幅回路の出力端子４５ｓ、４５ｇの間に接続されているコモンモードトランス１６を含む負荷回路６０の負荷インピーダンスＺｔを調整する。電力線４は、ｕ相の電力線４ｕ、ｖ相の電力線４ｖ、ｗ相の電力線４ｗを備えている。電力線５は、ｕ相の電力線５ｕ、ｖ相の電力線５ｖ、ｗ相の電力線５ｗを備えている。コモンモードトランス１６の二次巻線７は、ｕ相の二次巻線７ｕ、ｖ相の二次巻線７ｖ、ｗ相の二次巻線７ｗを備えている。 The common mode transformer 16 has a secondary winding 7 connected to the power lines 4 and 5 and a primary winding 8 connected between the output terminals of the output voltage generating circuit 66. An injection voltage Vap that reduces Vcm is superimposed. That is, when the output voltage Vs output by the output voltage generation circuit 66 is input to the primary winding 8 , the common mode transformer 16 injects the injection voltage Vap that reduces the common mode voltage Vcm into the power lines 4 and 5 . The impedance adjuster 18 is connected in parallel to the primary winding 8 of the common mode transformer 16, and is connected between the output terminals of the output voltage generating circuit 66, that is, the output terminals 45s and 45g of the amplifier circuit. 16 is adjusted. The power lines 4 include a u-phase power line 4u, a v-phase power line 4v, and a w-phase power line 4w. The power lines 5 include a u-phase power line 5u, a v-phase power line 5v, and a w-phase power line 5w. The secondary winding 7 of the common mode transformer 16 includes a u-phase secondary winding 7u, a v-phase secondary winding 7v, and a w-phase secondary winding 7w.
　交流電力を出力する場合の電力変換回路２は、ダイオード整流回路又はその他の手段を用いて直流電圧を発生する直流電圧源２１、直流電圧を平滑化する直流コンデンサ２２、半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６で構成された三相フルブリッジ、接地線６に接続される接地端子２６と低電位側配線２７ｂとの間に接地用のコンデンサ２４を備えている。三相フルブリッジは、６個の半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６を備えている。一端がコモンモードトランス１６の二次巻線７ｕ、７ｖ、７ｗの一端に接続されている三相の電力線４ｕ、４ｖ、４ｗは、それぞれ他端が電力変換回路２の交流端子２５ｕ、２５ｖ、２５ｗに接続されている。一端が補償対象３に接続されている三相の電力線５ｕ、５ｖ、５ｗは、それぞれ他端がコモンモードトランス１６の二次巻線７ｕ、７ｖ、７ｗの他端に接続されている。 The power conversion circuit 2 when outputting AC power includes a DC voltage source 21 that generates a DC voltage using a diode rectifier circuit or other means, a DC capacitor 22 that smoothes the DC voltage, and semiconductor devices Q1, Q2, Q3. , Q4, Q5 and Q6, and a grounding capacitor 24 is provided between a grounding terminal 26 connected to the grounding line 6 and a low potential side wiring 27b. A three-phase full bridge comprises six semiconductor elements Q1, Q2, Q3, Q4, Q5, Q6. Three- phase power lines 4u, 4v, and 4w, one end of which is connected to one end of secondary windings 7u, 7v, and 7w of common mode transformer 16, have the other ends of AC terminals 25u, 25v, and 25w of power conversion circuit 2, respectively. It is connected to the. Three- phase power lines 5u, 5v, and 5w, one end of which is connected to the compensation target 3, are connected to the other ends of secondary windings 7u, 7v, and 7w of the common mode transformer 16, respectively.
　電力変換回路２は、補償対象３が電力系統であれば、電力系統から電力を受電する整流動作もしくは電力系統に電力を送電する動作を行う回路である。送電する場合、直流電圧源２１は、電力源に交流発電機を持つ整流回路、太陽電池、燃料電池等である。受電する場合、直流電圧源２１は電力を蓄電する蓄電池である。また、電力変換回路２は、補償対象３が電動機であれば、電動機を駆動する回路である。電力変換回路２は、直流電圧源２１が蓄電池であっても、直流電圧源２１以外の構成は同じである。 If the compensation target 3 is a power system, the power conversion circuit 2 is a circuit that performs a rectification operation for receiving power from the power system or an operation for transmitting power to the power system. When transmitting power, the DC voltage source 21 is a rectifier circuit having an AC generator as a power source, a solar cell, a fuel cell, or the like. When receiving power, the DC voltage source 21 is a storage battery that stores power. Further, the power conversion circuit 2 is a circuit that drives an electric motor if the compensation target 3 is an electric motor. The power conversion circuit 2 has the same configuration except for the DC voltage source 21 even if the DC voltage source 21 is a storage battery.
　半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６は、例えばＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor　Field-Effect　Transistor）等の電力用半導体素子が用いられる。図２では、ＩＧＢＴの例を示した。半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６は、ＩＧＢＴ、ダイオードＤを備えている。ダイオードＤは、ＩＧＢＴに逆並列に接続されている。半導体素子Ｑ１、Ｑ３、Ｑ５のコレクタは高電位側配線２７ａに接続されており、半導体素子Ｑ２、Ｑ４、Ｑ６のエミッタは低電位側配線２７ｂに接続されている。半導体素子Ｑ１のエミッタと半導体素子Ｑ２のコレクタは接続されており、半導体素子Ｑ３のエミッタと半導体素子Ｑ４のコレクタは接続されており、半導体素子Ｑ５のエミッタと半導体素子Ｑ６のコレクタは接続されている。半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６のゲートに、図示しない駆動回路から駆動信号が入力される。電力変換回路２が電力を送電する場合又は電動機駆動を行う場合、三相フルブリッジは、駆動回路からの駆動信号に基づいて半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６をスイッチングして、直流電力を交流電力に変換する。電力変換回路２が電力を受電する場合、三相フルブリッジは、駆動回路からの駆動信号に基づいて半導体素子Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６をスイッチングして、交流電力を直流電力に変換する。 For the semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6, power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used. FIG. 2 shows an example of an IGBT. Semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6 include IGBTs and diodes D. As shown in FIG. A diode D is connected anti-parallel to the IGBT. The collectors of the semiconductor elements Q1, Q3 and Q5 are connected to the high potential side wiring 27a, and the emitters of the semiconductor elements Q2, Q4 and Q6 are connected to the low potential side wiring 27b. The emitter of the semiconductor element Q1 and the collector of the semiconductor element Q2 are connected, the emitter of the semiconductor element Q3 and the collector of the semiconductor element Q4 are connected, and the emitter of the semiconductor element Q5 and the collector of the semiconductor element Q6 are connected. . Drive signals are input from a drive circuit (not shown) to the gates of the semiconductor elements Q1, Q2, Q3, Q4, Q5 and Q6. When the power conversion circuit 2 transmits power or drives a motor, the three-phase full bridge switches the semiconductor elements Q1, Q2, Q3, Q4, Q5, and Q6 based on the drive signal from the drive circuit, Converts DC power to AC power. When the power conversion circuit 2 receives power, the three-phase full bridge switches the semiconductor elements Q1, Q2, Q3, Q4, Q5, Q6 based on the drive signal from the drive circuit to convert AC power into DC power. Convert.
　電圧検出回路１１は、三相の電力線５ｕ、５ｖ、５ｗのそれぞれにＹ結線接続された３個のコンデンサ９ｕ、９ｖ、９ｗの中性点ｎ０と接地線６との間に分圧コンデンサ１０が直列接続されており、分圧されたコモンモード電圧Ｖｃｍを検出する。コンデンサ９ｕは電力線５ｕと中性点ｎ０とに接続されており、コンデンサ９ｖは電力線５ｖと中性点ｎ０とに接続されており、コンデンサ９ｗは電力線５ｗと中性点ｎ０とに接続されている。電圧検出回路１１の検出方式は、分圧コンデンサ１０がない場合における三相の電力線５ｕ、５ｖ、５ｗの中性点ｎ０と接地線６との電圧である通常のコモンモード電圧Ｖｃｍよりも低い電圧を検出しており、分圧されたコモンモード電圧Ｖｃｍを検出する方式である。電圧検出回路１１が出力する電圧検出信号ｓｉｇ１は、分圧されたコモンモード電圧Ｖｃｍの情報を含んでいる。分圧されたコモンモード電圧Ｖｃｍの情報は通常のコモンモード電圧Ｖｃｍの情報が反映されているので、電圧検出信号ｓｉｇ１は、通常のコモンモード電圧Ｖｃｍの情報を含んでいる。ここでは、通常のコモンモード電圧の符号、分圧されたコモンモード電圧の符号は、区別せずにＶｃｍを用いる。実施の形態１のコモンモードフィルタ回路１は、出力電圧生成回路６６において増幅回路１４を備えている。増幅回路１４は、電圧検出回路１１の分圧比、コモンモードトランス１６における一次巻線８と二次巻線７との巻線比に応じて、電圧検出信号ｓｉｇ１の電圧振幅が電力線４、５に生じている通常のコモンモード電圧Ｖｃｍの電圧振幅を低減する電圧振幅に増幅し、増幅された出力信号ｓｉｇ４をコモンモードトランス１６に出力する。 The voltage detection circuit 11 includes a voltage dividing capacitor 10 between a neutral point n0 of three capacitors 9u, 9v, and 9w Y-connected to three- phase power lines 5u, 5v, and 5w, respectively, and a ground line 6. They are connected in series and detect the divided common mode voltage Vcm. The capacitor 9u is connected to the power line 5u and the neutral point n0, the capacitor 9v is connected to the power line 5v and the neutral point n0, and the capacitor 9w is connected to the power line 5w and the neutral point n0. . The detection method of the voltage detection circuit 11 is a voltage lower than the normal common mode voltage Vcm, which is the voltage between the neutral point n0 of the three- phase power lines 5u, 5v, and 5w and the ground line 6 when the voltage dividing capacitor 10 is not present. is detected, and the divided common mode voltage Vcm is detected. A voltage detection signal sig1 output from the voltage detection circuit 11 includes information on the divided common mode voltage Vcm. Information on the divided common mode voltage Vcm reflects information on the normal common mode voltage Vcm, so the voltage detection signal sig1 includes information on the normal common mode voltage Vcm. Here, Vcm is used without distinguishing between the sign of the normal common mode voltage and the sign of the divided common mode voltage. The common mode filter circuit 1 of Embodiment 1 includes the amplifier circuit 14 in the output voltage generation circuit 66 . The amplifier circuit 14 increases the voltage amplitude of the voltage detection signal sig1 to the power lines 4 and 5 according to the voltage division ratio of the voltage detection circuit 11 and the winding ratio between the primary winding 8 and the secondary winding 7 in the common mode transformer 16. The voltage amplitude of the generated normal common mode voltage Vcm is amplified to a voltage amplitude that reduces it, and the amplified output signal sig4 is output to the common mode transformer 16 .
　検出されたコモンモード電圧Ｖｃｍの情報を含む電圧検出信号ｓｉｇ１を帯域制限回路１２に通過させ、特定の周波数帯域の信号である帯域制限信号ｓｉｇ２を抽出する。帯域制限信号ｓｉｇ２は、出力電圧生成回路６６の制御回路１３に入力される。帯域制限回路１２がアナログフィルタである場合の制御回路１３の例を図３に示した。制御回路１３は、ＡＤ（Analog　Digital）変換器３１、デジタル回路３２、ＤＡ（Digital　Analog）変換器３３を備えている。ＡＤ変換器３１は、アナログの帯域制限信号ｓｉｇ２をデジタルの演算入力信号ｓｉｇ２ｄに変換する。演算入力信号ｓｉｇ２ｄはデジタル回路３２に入力される。デジタル回路３２は、例えばマイクロコンピュータ、ＤＳＰ（Digital　Signal　Processor）、又はＦＰＧＡ（Field-Programmable　Gate　Array）等により実現されている。演算入力信号ｓｉｇ２ｄは、振幅及び位相が電圧振幅Ｖ２及び電圧位相Φ２である。デジタル回路３２は、演算出力信号ｓｉｇ３ｄを出力する。演算出力信号ｓｉｇ３ｄは、振幅及び位相が電圧振幅Ｖｏ及び電圧位相Φｏである。ＤＡ変換器３３はデジタルの演算出力信号ｓｉｇ３ｄをアナログの補償信号ｓｉｇ３に変換する。制御回路１３は、入力端子３４ｓ、３４ｇから帯域制限回路１２の帯域制限信号ｓｉｇ２を取り込み、当該制御回路１３の内部信号である演算出力信号ｓｉｇ３ｄの電圧振幅Ｖｏが減少するように補償信号ｓｉｇ３を生成し、出力端子３５ｓ、３５ｇから補償信号ｓｉｇ３を出力する。入力端子３４ｇ、出力端子３５ｇは、接地線６に接続されており、接地電位になっている。 A voltage detection signal sig1 containing information on the detected common mode voltage Vcm is passed through the band-limiting circuit 12 to extract a band-limiting signal sig2, which is a signal in a specific frequency band. The band-limited signal sig2 is input to the control circuit 13 of the output voltage generation circuit 66. FIG. FIG. 3 shows an example of the control circuit 13 when the band limiting circuit 12 is an analog filter. The control circuit 13 includes an AD (Analog Digital) converter 31 , a digital circuit 32 and a DA (Digital Analog) converter 33 . The AD converter 31 converts the analog band-limited signal sig2 into a digital operation input signal sig2d. A calculation input signal sig2d is input to the digital circuit 32 . The digital circuit 32 is implemented by, for example, a microcomputer, a DSP (Digital Signal Processor), or an FPGA (Field-Programmable Gate Array). The operation input signal sig2d has the amplitude and phase of voltage amplitude V2 and voltage phase Φ2. The digital circuit 32 outputs a computation output signal sig3d. The amplitude and phase of the operation output signal sig3d are the voltage amplitude Vo and the voltage phase Φo. The DA converter 33 converts the digital operation output signal sig3d into an analog compensation signal sig3. The control circuit 13 receives the band-limited signal sig2 of the band-limited circuit 12 from the input terminals 34s and 34g, and generates the compensation signal sig3 so that the voltage amplitude Vo of the operation output signal sig3d, which is the internal signal of the control circuit 13, decreases. and output a compensation signal sig3 from the output terminals 35s and 35g. The input terminal 34g and the output terminal 35g are connected to the ground line 6 and are at the ground potential.
　増幅回路１４は、例えばオペレーショナルアンプ４１、入力抵抗４２、負帰還抵抗４３を備えた反転増幅回路である。制御回路１３により出力された補償信号ｓｉｇ３が入力端子４４ｓ、４４ｇから入力されると、増幅回路１４は補償信号ｓｉｇ３を増幅し、出力端子４５ｓ、４５ｇから出力信号ｓｉｇ４をインピーダンス調整器１８及びコモンモードトランス１６の一次巻線８に出力する。出力信号ｓｉｇ４は、電圧及び電流が出力電圧Ｖｓ及び出力電流Ｉｓである。入力端子４４ｇ、出力端子４５ｇは、接地線６に接続されており、接地電位になっている。オペレーショナルアンプ４１の正側入力端子に、入力端子４４ｇを介して接地電位が入力されている。オペレーショナルアンプ４１の負側入力端子に、入力端子４４ｓからの入力が入力抵抗４２を介して入力され、かつオペレーショナルアンプ４１の出力が負帰還抵抗４３を介して入力されている。オペレーショナルアンプ４１には、正側電源＋Ｖｃｃ、負側電源－Ｖｃｃが接続されている。 The amplifier circuit 14 is an inverting amplifier circuit including an operational amplifier 41, an input resistor 42, and a negative feedback resistor 43, for example. When the compensation signal sig3 output by the control circuit 13 is input from the input terminals 44s and 44g, the amplifier circuit 14 amplifies the compensation signal sig3 and outputs the output signal sig4 from the output terminals 45s and 45g to the impedance adjuster 18 and the common mode signal. Output to primary winding 8 of transformer 16 . The voltage and current of the output signal sig4 are the output voltage Vs and the output current Is. The input terminal 44g and the output terminal 45g are connected to the ground line 6 and are at the ground potential. A ground potential is input to the positive input terminal of the operational amplifier 41 via the input terminal 44g. The input from the input terminal 44 s is input to the negative side input terminal of the operational amplifier 41 via the input resistor 42 , and the output of the operational amplifier 41 is input via the negative feedback resistor 43 . A positive power source +Vcc and a negative power source −Vcc are connected to the operational amplifier 41 .
　出力電圧生成回路６６の出力端子すなわち増幅回路１４の出力端子４５ｓ、４５ｇは、それぞれ並列接続されたインピーダンス調整器１８及びコモンモードトランス１６の一次巻線８の一端及び他端に接続されている。コモンモードフィルタ回路１は、出力電圧生成回路６６から出力電圧Ｖｓをインピーダンス調整器１８及びコモンモードトランス１６の一次巻線８に印加する。コモンモードトランス１６の二次巻線７は電力線４及び電力線５に接続されており、コモンモードフィルタ回路１は、各相に共通の注入電圧Ｖａｐを注入することで電力変換回路２が発生するコモンモード電圧Ｖｃｍの特定周波数成分に対し、逆相成分の注入電圧Ｖａｐを注入する。図１ではインピーダンス調整器１８がコンデンサ１５である例であり、すなわちインピーダンス調整器１８がコンデンサ１５を備えている例を示した。 The output terminals of the output voltage generation circuit 66, that is, the output terminals 45s and 45g of the amplifier circuit 14 are connected to one end and the other end of the primary winding 8 of the impedance adjuster 18 and the common mode transformer 16 connected in parallel, respectively. The common mode filter circuit 1 applies the output voltage Vs from the output voltage generation circuit 66 to the impedance adjuster 18 and the primary winding 8 of the common mode transformer 16 . The secondary winding 7 of the common mode transformer 16 is connected to the power lines 4 and 5, and the common mode filter circuit 1 injects a common injection voltage Vap into each phase, thereby reducing the common voltage generated by the power conversion circuit 2. An injection voltage Vap of a reverse phase component is injected with respect to a specific frequency component of the mode voltage Vcm. FIG. 1 shows an example in which the impedance adjuster 18 is the capacitor 15 , that is, an example in which the impedance adjuster 18 includes the capacitor 15 .
　次に、電圧検出信号ｓｉｇ１が低周波成分を含んだ場合においても、増幅回路１４の出力電流Ｉｓを抑制する方法を説明する。図５に増幅回路１４の出力端子間の負荷回路６０の等価回路を示した。増幅回路１４の出力端子４５ｓ、出力端子４５ｇ間の等価回路は、増幅回路１４の負荷側の等価回路である。負荷回路６０は、出力電圧生成回路６６の出力端子４５ｓ、４５ｇ間に接続されているコモンモードトランス１６を含む回路である。コモンモードインピーダンスＺは、電力変換回路２、電力線４、電力線５、電圧検出回路１１、補償対象３、と接地線６との一巡経路６１の合成インピーダンスである。コモンモードインピーダンスＺはＬＣ直列共振回路のインピーダンスで表現できる。負荷回路６０は、インピーダンス調整器１８であるコンデンサ１５、コモンモードトランス１６における励磁インダクタンス値Ｌｍを有する励磁インダクタ、コモンモードトランス１６に接続される一巡経路６１のコモンモードインピーダンスＺが並列接続される。すなわち負荷回路６０は、ＬＣ並列共振回路で表現できる。 Next, a method of suppressing the output current Is of the amplifier circuit 14 even when the voltage detection signal sig1 contains low-frequency components will be described. FIG. 5 shows an equivalent circuit of the load circuit 60 between the output terminals of the amplifier circuit 14. As shown in FIG. An equivalent circuit between the output terminals 45 s and 45 g of the amplifier circuit 14 is an equivalent circuit on the load side of the amplifier circuit 14 . The load circuit 60 is a circuit including the common mode transformer 16 connected between the output terminals 45 s and 45 g of the output voltage generation circuit 66 . The common mode impedance Z is the combined impedance of the power conversion circuit 2 , the power line 4 , the power line 5 , the voltage detection circuit 11 , the compensation target 3 , and the loop path 61 of the ground line 6 . The common mode impedance Z can be expressed by the impedance of the LC series resonance circuit. In load circuit 60, capacitor 15 as impedance adjuster 18, exciting inductor having exciting inductance value Lm in common mode transformer 16, and common mode impedance Z of loop path 61 connected to common mode transformer 16 are connected in parallel. That is, the load circuit 60 can be represented by an LC parallel resonant circuit.
　負荷回路６０のインピーダンスを負荷インピーダンスＺｔとする。負荷回路６０の各構成物のインピーダンスについても次のようにアルファベットで表現する。励磁インダクタンス値Ｌｍを有する励磁インダクタのインピーダンスは励磁インピーダンスＺｌである。したがって、コモンモードトランス１６が励磁する際のインピーダンスは励磁インピーダンスＺｌである。インピーダンス調整器１８のインピーダンスは調整器インピーダンスＺｓｔである。負荷回路６０の負荷インピーダンスＺｔは、調整器インピーダンスＺｓｔ、励磁インピーダンスＺｌ、コモンモードインピーダンスＺが並列接続された合成インピーダンスである。コモンモードインピーダンスＺは、インダクタンス値Ｌａ、容量値Ｃａを有するＬＣ直列共振回路のインピーダンスで表現できるので、コモンモードインピーダンスＺは、ＬＣ直列共振回路の共振周波数を基準にした周波数成分に応じた、インダクタンス値Ｌａ又は容量値Ｃａとして考えることができる。まず、コモンモードインピーダンスＺを単純化できる場合について説明する。コモンモードインピーダンスＺは、コモンモードインピーダンスＺの共振周波数より低い成分に関しては容量値Ｃａを持つコンデンサとして動作し、コモンモードインピーダンスＺの共振周波数より高い成分に関してはインダクタンス値Ｌａを持つインダクタンスとして動作する。 Let the impedance of the load circuit 60 be the load impedance Zt. The impedance of each component of the load circuit 60 is also represented by alphabets as follows. The impedance of a magnetizing inductor having magnetizing inductance value Lm is magnetizing impedance Zl. Therefore, the impedance when the common mode transformer 16 is excited is the excitation impedance Zl. The impedance of impedance adjuster 18 is adjuster impedance Zst. A load impedance Zt of the load circuit 60 is a composite impedance in which the regulator impedance Zst, the excitation impedance Zl, and the common mode impedance Z are connected in parallel. Since the common mode impedance Z can be expressed by the impedance of the LC series resonance circuit having the inductance value La and the capacitance value Ca, the common mode impedance Z is the inductance corresponding to the frequency component based on the resonance frequency of the LC series resonance circuit. It can be thought of as the value La or the capacitance value Ca. First, the case where the common mode impedance Z can be simplified will be described. The common mode impedance Z operates as a capacitor having a capacitance value Ca for components lower than the resonance frequency of the common mode impedance Z, and as an inductance having an inductance value La for components higher than the resonance frequency of the common mode impedance Z.
　増幅回路１４から電圧がＶ、周波数がｆの出力電圧Ｖｓを印加する場合は、励磁インダクタンス値Ｌｍを持つコモンモードトランス１６の一次巻線８の側に式（１）で決定される励磁電流Ｉｍを流す必要がある。
Figure JPOXMLDOC01-appb-M000001
 When an output voltage Vs having a voltage of V and a frequency of f is applied from the amplifier circuit 14, the exciting current Im determined by the equation (1) is applied to the primary winding 8 side of the common mode transformer 16 having an exciting inductance value Lm. must flow.
Figure JPOXMLDOC01-appb-M000001
　周波数の異なる同一振幅の電圧を印加することを想定した場合には、周波数ｆと励磁電流Ｉｍは反比例する。したがって、低周波のコモンモード電圧Ｖｃｍを補償する際すなわち低周波のコモンモード電圧Ｖｃｍを低減する注入電圧Ｖａｐを電力線４、５に注入する際には、励磁電流Ｉｍが増大する。前述した特許文献１の方式を適用した比較例のコモンモードフィルタ回路は、出力電圧生成回路の出力端子間にインピーダンス調整器１８すなわちコンデンサ１５が配置されていないため、励磁電流Ｉｍは増幅回路１４からのみ供給されていた。したがって、比較例のコモンモードフィルタ回路は、低周波成分を補償するには励磁電流Ｉｍが増加するため電流容量の大きい能動素子が必要となり、電流容量の変更に伴い能動素子のコストの増大を招いていた。また、励磁電流Ｉｍを供給する能動素子は線形領域で動作する。このため、電流容量の大きい能動素子は、大電流を流すと損失が大きく発熱するため、能動素子の冷却系が大型になり、冷却系のコストも増大する。したがって、比較例のコモンモードフィルタ回路を搭載する装置は、能動素子の大容量化、冷却系の大型化に伴って、装置のコストも増大する。 When it is assumed that voltages with different frequencies and the same amplitude are applied, the frequency f and the exciting current Im are inversely proportional. Therefore, when compensating for the low-frequency common mode voltage Vcm, that is, when injecting the injection voltage Vap that reduces the low-frequency common mode voltage Vcm into the power lines 4 and 5, the excitation current Im increases. In the common mode filter circuit of the comparative example to which the method of Patent Document 1 is applied, the impedance adjuster 18, that is, the capacitor 15 is not arranged between the output terminals of the output voltage generation circuit. was supplied only. Therefore, in the common mode filter circuit of the comparative example, since the exciting current Im increases in order to compensate for the low-frequency component, active elements with large current capacity are required, and the change in current capacity leads to an increase in the cost of the active elements. was Also, the active element supplying the excitation current Im operates in the linear region. Therefore, an active element having a large current capacity generates heat due to a large loss when a large current is passed through it, so that the cooling system for the active element becomes large and the cost of the cooling system also increases. Therefore, the cost of a device equipped with the common mode filter circuit of the comparative example increases as the capacity of the active element increases and the cooling system increases in size.
　これに対して、実施の形態１のコモンモードフィルタ回路１は、ＬＣ並列共振回路である負荷回路６０のインピーダンス調整器１８を用いて、特定の周波数において増幅回路１４の出力端子４５ｓと出力端子４５ｇとの間に接続される負荷回路６０のインピーダンスすなわち負荷インピーダンスＺｔを増加することで、増幅回路１４の出力電流Ｉｓを抑制することが可能である。具体的には、低周波の補償を行う場合に、インピーダンス調整器１８の調整器インピーダンスＺｓｔすなわちコンデンサ１５の容量値Ｃを適切に設定することで、負荷インピーダンスＺｔが増加し、増幅回路１４の出力電流Ｉｓを抑制することが可能である。負荷回路６０の負荷インピーダンスＺｔは、調整器インピーダンスＺｓｔ、励磁インピーダンスＺｌ、コモンモードインピーダンスＺが並列接続されたＬＣ並列共振回路のインピーダンスになる。また、負荷回路６０の負荷インピーダンスＺｔの値は、コンデンサ１５の容量値Ｃ、コモンモードトランス１６の励磁インダクタンス値Ｌｍ、コモンモードインピーダンスＺのインダクタンス値Ｌａ及び容量値Ｃａを用いて表現できる。 In contrast, the common mode filter circuit 1 of the first embodiment uses the impedance adjuster 18 of the load circuit 60, which is an LC parallel resonance circuit, to adjust the output terminal 45s and the output terminal 45g of the amplifier circuit 14 at a specific frequency. It is possible to suppress the output current Is of the amplifier circuit 14 by increasing the impedance of the load circuit 60 connected between and, that is, the load impedance Zt. Specifically, when compensating for low frequencies, by appropriately setting the adjuster impedance Zst of the impedance adjuster 18, that is, the capacitance value C of the capacitor 15, the load impedance Zt increases and the output of the amplifier circuit 14 increases. It is possible to suppress the current Is. The load impedance Zt of the load circuit 60 is the impedance of an LC parallel resonance circuit in which the regulator impedance Zst, the exciting impedance Zl, and the common mode impedance Z are connected in parallel. Also, the value of the load impedance Zt of the load circuit 60 can be expressed using the capacitance value C of the capacitor 15, the exciting inductance value Lm of the common mode transformer 16, the inductance value La of the common mode impedance Z, and the capacitance value Ca.
　図６に、帯域制限回路１２のゲインＧと増幅回路１４に接続される負荷インピーダンスＺｔの周波数特性を示した。ゲインＧのゲイン特性８８と、負荷インピーダンスＺｔのインピーダンス特性８９とが図６に同時に示されている。ゲイン特性８８における縦軸はゲインＧであり、インピーダンス特性８９における縦軸は負荷インピーダンスＺｔである。横軸は周波数ｆである。最初に、コモンモードインピーダンスＺは、励磁インダクタンス値Ｌｍを有する励磁インダクタによる励磁インピーダンスＺｌに対して十分に大きく、無視できる場合を考える。この場合、増幅回路１４に接続される負荷インピーダンスＺｔは、励磁インダクタンス値Ｌｍを有する励磁インダクタと容量値Ｃを有するコンデンサ１５とが並列接続されたＬＣ並列共振回路のインピーダンスになる。このＬＣ並列共振回路すなわち負荷回路６０の周波数特性は、式（２）に示す共振周波数ｆｒ１の時に、負荷インピーダンスＺｔの値が最大値になる。 FIG. 6 shows frequency characteristics of the gain G of the band limiting circuit 12 and the load impedance Zt connected to the amplifier circuit 14 . A gain characteristic 88 of the gain G and an impedance characteristic 89 of the load impedance Zt are simultaneously shown in FIG. The vertical axis of the gain characteristic 88 is the gain G, and the vertical axis of the impedance characteristic 89 is the load impedance Zt. The horizontal axis is the frequency f. First, consider the case where the common mode impedance Z is sufficiently large relative to the excitation impedance Zl due to the excitation inductor having the excitation inductance value Lm and can be ignored. In this case, the load impedance Zt connected to the amplifier circuit 14 is the impedance of the LC parallel resonance circuit in which the exciting inductor having the exciting inductance value Lm and the capacitor 15 having the capacitance value C are connected in parallel. As for the frequency characteristics of this LC parallel resonance circuit, that is, the load circuit 60, the value of the load impedance Zt becomes the maximum value at the resonance frequency fr1 shown in the equation (2).
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　したがって、帯域制限回路１２の特性で決定される増幅回路１４の出力電圧Ｖｓの周波数ｆｓと、励磁インピーダンスＺｌの励磁インダクタンス値Ｌｍとコンデンサ１５の容量値Ｃで決まる共振周波数を式（２）に示すｆｒ１とを一致させること又は十分に近づけることで、負荷インピーダンスＺｔを高く保てる。増幅回路１４は前述した通り帯域制限回路１２から抽出された信号である帯域制限信号ｓｉｇ２に基づいて補償を行うため、帯域制限回路１２の二つのカットオフ周波数ｆｈとカットオフ周波数ｆｌの間に、コモンモードトランス１６の励磁インダクタンス値Ｌｍとコンデンサ１５の容量値Ｃとで表現されたＬＣ並列共振回路の共振周波数ｆｒ１が入るように調整することで、増幅回路１４により出力される出力電圧Ｖｓにおける主な周波数成分は増幅回路１４の負荷インピーダンスＺｔが高い周波数成分となる。すなわち、コモンモードフィルタ回路１は、コモンモードインピーダンスＺの影響が無視できる場合、帯域制限回路１２の二つのカットオフ周波数ｆｌとカットオフ周波数ｆｈの間に、負荷回路６０の共振周波数ｆｒ１が入るように調整することで、増幅回路１４の出力端子間の負荷インピーダンスＺｔが高い周波数成分のみを出力することが可能となる。 Therefore, the frequency fs of the output voltage Vs of the amplifier circuit 14 determined by the characteristics of the band limiting circuit 12, and the resonance frequency determined by the exciting inductance value Lm of the exciting impedance Zl and the capacitance value C of the capacitor 15 are shown in equation (2). By matching or sufficiently close to fr1, the load impedance Zt can be kept high. Since the amplifier circuit 14 performs compensation based on the band-limited signal sig2, which is a signal extracted from the band-limiting circuit 12 as described above, between the two cutoff frequencies fh and fl of the band-limiting circuit 12, By adjusting the resonance frequency fr1 of the LC parallel resonance circuit represented by the exciting inductance value Lm of the common mode transformer 16 and the capacitance value C of the capacitor 15, the main Such frequency components are those for which the load impedance Zt of the amplifier circuit 14 is high. That is, when the influence of the common mode impedance Z can be ignored, the common mode filter circuit 1 is arranged so that the resonance frequency fr1 of the load circuit 60 falls between the two cutoff frequencies fl and fh of the band limiting circuit 12. , it becomes possible to output only the frequency component where the load impedance Zt between the output terminals of the amplifier circuit 14 is high.
　次に、励磁インダクタンス値Ｌｍに対してコモンモードインピーダンスＺが十分に大きくなく、コモンモードインピーダンスＺの影響が無視できない場合を考える。低周波では、コモンモードインピーダンスＺの値は容量値Ｃａとして扱える。また、高周波では、コモンモードインピーダンスＺの値はインダクタンス値Ｌａとして扱える。低周波における増幅回路１４の出力端子間の負荷インピーダンスＺｔは、励磁インダクタンス値Ｌｍを有する励磁インダクタと容量値Ｃを有するコンデンサ１５と容量値Ｃａを有するコモンモードインピーダンスＺとが並列接続されたＬＣ並列共振回路のインピーダンスになる。この低周波におけるＬＣ並列共振回路の共振周波数は、式（３）に示す共振周波数ｆｒ２で表すことができる。高周波における増幅回路１４の出力端子間の負荷インピーダンスＺｔは、励磁インダクタンス値Ｌｍを有する励磁インダクタと容量値Ｃを有するコンデンサ１５とインダクタンス値Ｌａを有するコモンモードインピーダンスＺとが並列接続されたＬＣ並列共振回路のインピーダンスになる。この高周波におけるＬＣ並列共振回路の共振周波数は、式（４）に示す共振周波数ｆｒ３で表すことができる。 Next, consider a case where the common mode impedance Z is not sufficiently large with respect to the exciting inductance value Lm and the influence of the common mode impedance Z cannot be ignored. At low frequencies, the value of common mode impedance Z can be treated as capacitance value Ca. Also, at high frequencies, the value of the common mode impedance Z can be treated as the inductance value La. A load impedance Zt between the output terminals of the amplifier circuit 14 at a low frequency is an LC parallel connection in which an exciting inductor having an exciting inductance value Lm, a capacitor 15 having a capacitance value C, and a common mode impedance Z having a capacitance value Ca are connected in parallel. It becomes the impedance of the resonant circuit. The resonance frequency of the LC parallel resonance circuit at this low frequency can be expressed by the resonance frequency fr2 shown in Equation (3). A load impedance Zt between the output terminals of the amplifier circuit 14 at a high frequency is an LC parallel resonance in which an exciting inductor having an exciting inductance value Lm, a capacitor 15 having a capacitance value C, and a common mode impedance Z having an inductance value La are connected in parallel. becomes the impedance of the circuit. The resonance frequency of the LC parallel resonance circuit at this high frequency can be expressed by the resonance frequency fr3 shown in Equation (4).
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
　励磁インダクタンス値Ｌｍを有する励磁インダクタとインダクタンス値Ｌａを有するコモンモードインピーダンスＺとが合成された合成インダクタンスの値を合成インダクタンス値Ｌｂとし、容量値Ｃを有するコンデンサ１５と容量値Ｃａを有するコモンモードインピーダンスＺとが合成された合成キャパシタンスの容量値を合成容量値Ｃｂとした場合には、増幅回路１４の出力端子間の負荷インピーダンスＺｔは、ＬＣ並列共振回路の共振周波数が式（５）に示す共振周波数ｆｒ４で最大値になる。 A combined inductance value obtained by synthesizing an exciting inductor having an exciting inductance value Lm and a common mode impedance Z having an inductance value La is defined as a combined inductance value Lb, and a capacitor 15 having a capacitance value C and a common mode impedance having a capacitance value Ca. When the combined capacitance value Cb is the combined capacitance value of Z, the load impedance Zt between the output terminals of the amplifier circuit 14 is such that the resonant frequency of the LC parallel resonant circuit is represented by the equation (5). It reaches its maximum value at frequency fr4.
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000005
　コモンモードインピーダンスＺの影響が無視できない場合、帯域制限回路１２の二つのカットオフ周波数ｆｌとカットオフ周波数ｆｈの間に、コモンモードトランス１６の励磁インダクタンス値Ｌｍ及びコモンモードインピーダンスＺのインダクタンス値Ｌａが合成された合成インダクタンスの合成インダクタンス値Ｌｂと、コンデンサ１５の容量値Ｃ及びコモンモードインピーダンスＺの容量値Ｃａが合成された合成キャパシタンスの合成容量値Ｃｂとで表現されたＬＣ並列共振回路の共振周波数ｆｒ４が入るように調整することで、増幅回路１４により出力される出力電圧Ｖｓにおける主な周波数成分は増幅回路１４の負荷インピーダンスＺｔが高い周波数成分となる。すなわち、コモンモードフィルタ回路１は、コモンモードインピーダンスＺの影響が無視できない場合、帯域制限回路１２の二つのカットオフ周波数ｆｌとカットオフ周波数ｆｈの間に、負荷回路６０の共振周波数ｆｒ４が入るように調整することで、増幅回路１４の出力端子間の負荷インピーダンスＺｔが高い周波数成分のみを出力することが可能となる。なお、その効果は帯域制限回路１２の中心周波数と共振周波数ｆｒ４を一致させることで最大となる。 If the influence of the common mode impedance Z cannot be ignored, the magnetizing inductance value Lm of the common mode transformer 16 and the inductance value La of the common mode impedance Z are between the two cutoff frequencies fl and fh of the band limiting circuit 12. The resonance frequency of the LC parallel resonance circuit expressed by the combined inductance value Lb of the combined combined inductance and the combined capacitance value Cb of the combined capacitance resulting from combining the capacitance value C of the capacitor 15 and the capacitance value Ca of the common mode impedance Z By adjusting so that fr4 is included, the main frequency component in the output voltage Vs output from the amplifier circuit 14 becomes the frequency component with a high load impedance Zt of the amplifier circuit 14 . That is, when the influence of the common mode impedance Z cannot be ignored, the common mode filter circuit 1 is configured so that the resonance frequency fr4 of the load circuit 60 is between the two cutoff frequencies fl and fh of the band limiting circuit 12. , it becomes possible to output only the frequency component where the load impedance Zt between the output terminals of the amplifier circuit 14 is high. The effect is maximized by matching the center frequency of the band limiting circuit 12 and the resonance frequency fr4.
　インピーダンス調整器１８の調整器インピーダンスＺｓｔは、負荷回路６０の負荷インピーダンスＺｔが最大となる周波数すなわち共振周波数ｆｒ４が、帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に含まれるように調整されている。したがって、負荷回路６０の負荷インピーダンスＺｔが最大となる周波数すなわち共振周波数ｆｒ４が、帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に含まれることは、インピーダンス条件が満たされていることである。つまり、インピーダンス調整器１８の調整器インピーダンスＺｓｔは、インピーダンス条件を満足するように調整されている。実施の形態１では、インピーダンス調整器１８がコンデンサ１５の例なので、インピーダンス調整器１８の容量値Ｃは、インピーダンス条件を満たすように調整されている。 The adjuster impedance Zst of the impedance adjuster 18 is set so that the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonant frequency fr4 is included in the range of the two cutoff frequencies fl and fh of the band limiting circuit 12. adjusted. Therefore, the fact that the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonance frequency fr4 is included in the range of the two cutoff frequencies fl and fh of the band limiting circuit 12 means that the impedance condition is satisfied. is. That is, the adjuster impedance Zst of the impedance adjuster 18 is adjusted so as to satisfy the impedance condition. In Embodiment 1, since the impedance adjuster 18 is an example of the capacitor 15, the capacitance value C of the impedance adjuster 18 is adjusted so as to satisfy the impedance condition.
　図７、図８を用いて、実施の形態１のコモンモードフィルタ回路１における出力電流Ｉｓのベクトルと比較例のコモンモードフィルタ回路１における出力電流Ｉｓｅのベクトルとを説明する。図８に示した比較例の出力電流Ｉｓｅのベクトルである電流ベクトル９１ｅは、コモンモードトランス１６の励磁電流Ｉｌｍのベクトルである電流ベクトル９１ａと、コモンモードトランス１６の二次巻線７側に流れるコモンモード電流が等アンペアターンの法則で一次巻線８に誘起される電流Ｉｃｍａのベクトルである電流ベクトル９１ｄとの、合成ベクトルで決まっていた。ここで、低周波の出力電圧Ｖｓを発生させた場合には励磁電流Ｉｌｍが支配的となる。 A vector of the output current Is in the common mode filter circuit 1 of Embodiment 1 and a vector of the output current Ise in the common mode filter circuit 1 of the comparative example will be described using FIGS. A current vector 91e, which is the vector of the output current Ise of the comparative example shown in FIG. The common mode current was determined by the combined vector of the current vector 91d, which is the vector of the current Icma induced in the primary winding 8 by the law of equal ampere turns. Here, when the low-frequency output voltage Vs is generated, the excitation current Ilm becomes dominant.
　一方、実施の形態１のコモンモードフィルタ回路１は励磁電流Ｉｌｍをコンデンサ１５から供給するので、図７に示した実施の形態１の出力電流Ｉｓのベクトルである電流ベクトルは、コモンモードトランス１６の二次巻線７側に流れるコモンモード電流が等アンペアターンの法則で一次巻線８に誘起される電流Ｉｃｍａのベクトルである電流ベクトル９１ｃで決まる。図７では、励磁電流Ｉｌｍのベクトルである電流ベクトル９１ａと、コンデンサ１５からのコンデンサ電流Ｉｃのベクトルである電流ベクトル９１ｂとが同一の大きさで方向が逆向になっており、出力電流Ｉｓと電流Ｉｃｍａとが同一の大きさで方向が同じになっている状態を示した。その結果として、実施の形態１のコモンモードフィルタ回路１は、低周波のコモンモード電圧Ｖｃｍを補償する際に発生していた励磁電流Ｉｌｍの増加による増幅回路１４の出力電流Ｉｓが増大することを防止することができる。その結果、実施の形態１のコモンモードフィルタ回路１は、出力電圧生成回路６６の増幅回路１４の容量不足は生じることがなく、低周波のコモンモード電圧Ｖｃｍを補償することが可能となる。 On the other hand, since the common mode filter circuit 1 of the first embodiment supplies the excitation current Ilm from the capacitor 15, the current vector, which is the vector of the output current Is of the first embodiment shown in FIG. The common mode current flowing through the secondary winding 7 side is determined by the current vector 91c, which is the vector of the current Icma induced in the primary winding 8 according to the law of equal ampere turns. In FIG. 7, a current vector 91a, which is the vector of the excitation current Ilm, and a current vector 91b, which is the vector of the capacitor current Ic from the capacitor 15, have the same magnitude and opposite directions, and the output current Is and the current Icma has the same size and the same direction. As a result, the common mode filter circuit 1 of the first embodiment prevents the increase in the output current Is of the amplifier circuit 14 due to the increase in the excitation current Ilm generated when compensating for the low-frequency common mode voltage Vcm. can be prevented. As a result, in the common mode filter circuit 1 of the first embodiment, the capacity of the amplifier circuit 14 of the output voltage generation circuit 66 does not become insufficient, and the low-frequency common mode voltage Vcm can be compensated.
　次に、帯域制限回路１２の二つのカットオフ周波数ｆｌとカットオフ周波数ｆｈを決定する方法を説明する。図９、図１０に、実施の形態１の電力変換回路２が発生させるコモンモード電圧Ｖｃｍの周波数成分９２ａ、９２ｂ、９２ｃ、９２ｄと、帯域制限回路１２のゲインＧの周波数特性であるゲイン特性８８との関係を示した。ここでは、電力変換回路２は一定のキャリア周波数ｆ１で動作することを想定する。一定のキャリア周波数ｆ１で動作する電力変換回路２は、キャリア周波数ｆ１のコモンモード電圧Ｖｃｍ及びキャリア周波数ｆ１の奇数倍のコモンモード電圧Ｖｃｍを発生する。図９、図１０にはキャリア周波数ｆ１の周波数成分９２ａ、３次成分周波数ｆ３の周波数成分９２ｂ、５次成分周波数ｆ５の周波数成分９２ｃ、７次成分周波数ｆ７の周波数成分９２ｄを図示している。コモンモードフィルタ回路１が搭載される装置の回路条件によっては、キャリア周波数ｆ１の偶数倍の周波数成分も発生する。したがって、コモンモード電圧Ｖｃｍあるいはコモンモード電流の周波数解析結果から、キャリア周波数ｆ１の整数倍の周波数成分を含むコモンモード電圧Ｖｃｍが発生する。したがって、帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈ間すなわちカットオフ周波数ｆｌとカットオフ周波数ｆｈとの間に、キャリア周波数ｆ１あるいはキャリア周波数ｆ１の整数倍の周波数が含まれるように設定することで、コモンモード電圧Ｖｃｍ又はコモンモード電流の支配的な成分を抽出できる。図９は帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１が含まれるように設定されている例であり、図１０は帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１の整数倍の周波数が含まれるように設定されている例である。図１０のように設定した場合でも、負荷インピーダンスＺｔは、共振周波数ｆｒ４で最大値になる。なお、周波数成分９２ｂの方が周波数成分９２ａよりも大きい場合には、図１０のように設定することを想定しているが、特定の周波数成分を優先的に除去したい場合にはこの限りではない。 Next, a method for determining the two cutoff frequencies fl and fh of the band limiting circuit 12 will be described. 9 and 10 show frequency components 92a, 92b, 92c, and 92d of the common mode voltage Vcm generated by the power conversion circuit 2 of the first embodiment, and a gain characteristic 88, which is the frequency characteristic of the gain G of the band limiting circuit 12. showed the relationship with Here, it is assumed that the power conversion circuit 2 operates at a constant carrier frequency f1. The power conversion circuit 2 operating at a constant carrier frequency f1 generates a common mode voltage Vcm of the carrier frequency f1 and a common mode voltage Vcm of odd multiples of the carrier frequency f1. 9 and 10 show a frequency component 92a of carrier frequency f1, a frequency component 92b of third-order component frequency f3, a frequency component 92c of fifth-order component frequency f5, and a frequency component 92d of seventh-order component frequency f7. Depending on the circuit conditions of the device in which the common mode filter circuit 1 is mounted, frequency components of even multiples of the carrier frequency f1 are also generated. Therefore, the common mode voltage Vcm including frequency components of integral multiples of the carrier frequency f1 is generated from the frequency analysis result of the common mode voltage Vcm or the common mode current. Therefore, between the two cutoff frequencies fl and fh of the band limiting circuit 12, that is, between the cutoff frequency fl and the cutoff frequency fh, the carrier frequency f1 or an integer multiple of the carrier frequency f1 is set to be included. Dominant components of the common mode voltage Vcm or common mode current can thus be extracted. FIG. 9 shows an example in which the carrier frequency f1 is set between the two cutoff frequencies fl and fh of the band limiting circuit 12, and FIG. In this example, the frequency is set to include an integral multiple of the carrier frequency f1. Even when set as shown in FIG. 10, the load impedance Zt reaches its maximum value at the resonance frequency fr4. In addition, when the frequency component 92b is larger than the frequency component 92a, setting as shown in FIG. 10 is assumed. .
　次に、制御回路１３に組み込むコモンモード成分の低減機能を実現する方法について説明する。実施の形態１のコモンモードフィルタ回路１は、特定周波数帯域のコモンモード成分すなわちコモンモード電圧Ｖｃｍの特定周波数成分に対して逆相かつ同一振幅の電圧を注入電圧Ｖａｐとしてコモンモードトランス１６の二次巻線７から電力線４、５に注入することで、コモンモード電圧Ｖｃｍを許容値以下に低減する。図１１に、実施の形態１のデジタル回路３２の第一例を示した。デジタル回路３２は、コモンモード電圧Ｖｃｍの検出値に基づいて振幅演算器３６及び位相演算器３７で電圧振幅Ｖ２及び電圧位相Φ２を求め、その電圧振幅Ｖ２を低減するように演算出力信号ｓｉｇ３ｄの電圧位相Φｏを位相調整器３８で決定し、さらに演算出力信号ｓｉｇ３ｄの電圧振幅Ｖｏを振幅調整器３９で決定する。デジタル回路３２について詳しく説明する。 Next, a method for realizing a common mode component reduction function incorporated in the control circuit 13 will be described. In the common mode filter circuit 1 of the first embodiment, the common mode component in the specific frequency band, that is, the voltage having the same amplitude and the opposite phase with respect to the specific frequency component of the common mode voltage Vcm, is applied to the secondary of the common mode transformer 16 as the injection voltage Vap. By injecting from the winding 7 to the power lines 4, 5, the common mode voltage Vcm is reduced below the allowable value. FIG. 11 shows a first example of the digital circuit 32 of the first embodiment. The digital circuit 32 obtains the voltage amplitude V2 and the voltage phase Φ2 with the amplitude calculator 36 and the phase calculator 37 based on the detected value of the common mode voltage Vcm, and reduces the voltage amplitude V2 to reduce the voltage of the calculation output signal sig3d. A phase adjuster 38 determines the phase Φo, and an amplitude adjuster 39 determines the voltage amplitude Vo of the operation output signal sig3d. The digital circuit 32 will be described in detail.
　デジタル回路３２は、帯域制限回路１２から出力された帯域制限信号ｓｉｇ２のＡＤ変換後の信号すなわち演算入力信号ｓｉｇ２ｄから帯域制限信号ｓｉｇ２の電圧振幅Ｖ２を演算する振幅演算器３６、演算入力信号ｓｉｇ２ｄから帯域制限信号ｓｉｇ２の電圧位相Φ２を演算する位相演算器３７、初期の電圧位相Φｏ又は前回出力した演算出力信号ｓｉｇ３ｄの前回電圧位相Φｂから電圧位相Φｏを決定する位相調整器３８、初期の電圧振幅Ｖｏ又は前回出力した演算出力信号ｓｉｇ３ｄの前回の電圧振幅Ｖｂから電圧振幅Ｖｏを決定する振幅調整器３９、電圧位相Φｏ及び電圧振幅Ｖｏに基づいて演算出力信号ｓｉｇ３ｄの電圧波形を生成する波形生成器５１を備えている。位相調整器３８は探索器４０ａを備えており、振幅調整器３９は探索器４０ｂを備えている。振幅調整器３９は、位相調整器３８が位相調整の終了を示す位相調整フラグｆｌｇ１を出力している場合に、前回から調整された電圧振幅Ｖｏを出力し、位相調整フラグｆｌｇ１が位相調整の終了を示さない場合に、前回と同じ電圧振幅Ｖｏを出力する。 The digital circuit 32 includes an amplitude calculator 36 for calculating the voltage amplitude V2 of the band-limited signal sig2 from the AD-converted signal of the band-limited signal sig2 output from the band-limiting circuit 12, that is, the calculation input signal sig2d. A phase calculator 37 for calculating the voltage phase Φ2 of the band-limited signal sig2, a phase adjuster 38 for determining the voltage phase Φo from the initial voltage phase Φo or the previous voltage phase Φb of the previously output computation output signal sig3d, and the initial voltage amplitude. An amplitude adjuster 39 that determines the voltage amplitude Vo from Vo or the previous voltage amplitude Vb of the previously output operation output signal sig3d, and a waveform generator that generates the voltage waveform of the operation output signal sig3d based on the voltage phase Φo and the voltage amplitude Vo. 51. The phase adjuster 38 has a searcher 40a and the amplitude adjuster 39 has a searcher 40b. When the phase adjuster 38 outputs the phase adjustment flag flg1 indicating the end of the phase adjustment, the amplitude adjuster 39 outputs the voltage amplitude Vo adjusted from the previous time, and the phase adjustment flag flg1 indicates the end of the phase adjustment. is not shown, the same voltage amplitude Vo as the previous time is output.
　図１２～図１４を用いて、実施の形態１のコモンモードフィルタ回路１の第一例の動作を説明する。電力変換回路２の運転が始まるとコモンモード電圧Ｖｃｍが発生する。ステップＳ０１にて、電圧検出回路１１でコモンモード電圧Ｖｃｍを検出する。ステップＳ０２にて、制御回路１３のデジタル回路３２はコモンモード電圧Ｖｃｍが閾値Ｖｔｈ１を超えているかを判定する。コモンモード電圧Ｖｃｍが閾値Ｖｔｈ１を超えている場合はステップＳ０５に進み、コモンモード電圧Ｖｃｍが閾値Ｖｔｈ１を超えていない場合すなわちコモンモード電圧Ｖｃｍが閾値Ｖｔｈ１以下の場合はステップＳ０３に進む。制御回路１３は、電圧検出回路１１で検出されたコモンモード電圧Ｖｃｍの情報を含んでおり、かつ帯域制限された帯域制限信号ｓｉｇ２から演算された電圧振幅Ｖ２と、閾値Ｖｔｈ１に対応する閾値とを比較してステップＳ０２を実行する。 The operation of the first example of the common mode filter circuit 1 of the first embodiment will be described using FIGS. 12 to 14. FIG. When the power conversion circuit 2 starts operating, a common mode voltage Vcm is generated. In step S01, the voltage detection circuit 11 detects the common mode voltage Vcm. In step S02, the digital circuit 32 of the control circuit 13 determines whether the common mode voltage Vcm exceeds the threshold value Vth1. If the common mode voltage Vcm exceeds the threshold Vth1, the process proceeds to step S05, and if the common mode voltage Vcm does not exceed the threshold Vth1, that is, if the common mode voltage Vcm is equal to or less than the threshold Vth1, the process proceeds to step S03. The control circuit 13 includes information on the common mode voltage Vcm detected by the voltage detection circuit 11, and calculates a voltage amplitude V2 calculated from the band-limited band-limited signal sig2 and a threshold corresponding to the threshold Vth1. After comparison, step S02 is executed.
　ステップＳ０３にて、デジタル回路３２が出力する演算出力信号ｓｉｇ３ｄの電圧振幅Ｖоが閾値Ｖｔｈ２を超えているかを判定する。電圧振幅Ｖоが閾値Ｖｔｈ２を超えている場合はステップＳ０５に進み、電圧振幅Ｖоが閾値Ｖｔｈ２を超えていない場合すなわち電圧振幅Ｖоが閾値Ｖｔｈ２以下の場合はステップＳ０４に進む。ステップＳ０４にて、制御回路１３は補償信号ｓｉｇ３の出力を停止し、増幅回路１４は補償信号ｓｉｇ３の出力停止に伴い出力信号ｓｉｇ４の出力を停止し、終了する。出力信号ｓｉｇ４の出力停止に伴い、コモンモードフィルタ回路１は電力線４、５への注入電圧Ｖａｐの注入を停止する。ステップＳ０４は注入電圧停止工程である。 In step S03, it is determined whether the voltage amplitude V? of the arithmetic output signal sig3d output by the digital circuit 32 exceeds the threshold value Vth2. If the voltage amplitude V0 exceeds the threshold Vth2, the process proceeds to step S05, and if the voltage amplitude V0 does not exceed the threshold Vth2, that is, if the voltage amplitude V0 is equal to or less than the threshold Vth2, the process proceeds to step S04. In step S04, the control circuit 13 stops outputting the compensation signal sig3, the amplifier circuit 14 stops outputting the output signal sig4 as the compensation signal sig3 is stopped, and the process ends. As the output of the output signal sig4 is stopped, the common mode filter circuit 1 stops injection of the injection voltage Vap to the power lines 4 and 5. FIG. Step S04 is an injection voltage stopping step.
　ステップＳ０５～ステップＳ０９までは、コモンモードフィルタ回路１は、検出されたコモンモード電圧Ｖｃｍに基づいて、電圧位相Φо、電圧振幅Ｖоの少なくとも一方が調整された補償信号ｓｉｇ３、出力信号ｓｉｇ４を生成して、電力線４、５へ注入電圧Ｖａｐの注入を実行する。コモンモード電圧Ｖｃｍの検出値が閾値Ｖｔｈ１を超えると、出力信号ｓｉｇ４の出力電圧Ｖｓの位相調整を行い、その後に出力信号ｓｉｇ４の出力電圧Ｖｓの振幅調整を行う。この出力電圧Ｖｓの調整はコモンモード電圧Ｖｃｍの検出値が閾値Ｖｔｈ１を超えている間は継続されるが、その一方で調整の結果である２回目以降のコモンモード電圧Ｖｃｍの検出値が低下しても、制御回路１３の出力である電圧振幅Ｖｏが閾値Ｖｔｈ２を超えていれば電力変換回路２が運転されていることが判断できるため、出力電圧生成回路６６による出力電圧Ｖｓの出力、コモンモードトランス１６による注入電圧Ｖａｐの注入は継続される。 From step S05 to step S09, the common mode filter circuit 1 generates the compensation signal sig3 and the output signal sig4 in which at least one of the voltage phase Φо and the voltage amplitude Vо is adjusted based on the detected common mode voltage Vcm. to inject the injection voltage Vap into the power lines 4 and 5 . When the detected value of the common mode voltage Vcm exceeds the threshold Vth1, the phase of the output voltage Vs of the output signal sig4 is adjusted, and then the amplitude of the output voltage Vs of the output signal sig4 is adjusted. This adjustment of the output voltage Vs continues while the detected value of the common mode voltage Vcm exceeds the threshold value Vth1. However, if the voltage amplitude Vo, which is the output of the control circuit 13, exceeds the threshold value Vth2, it can be determined that the power conversion circuit 2 is in operation. The injection of the injection voltage Vap by the transformer 16 continues.
　ステップＳ０５にて、制御回路１３は位相調整が完了したかを判定し、位相調整が完了している場合はステップＳ０６に進み、位相調整が完了していない場合はステップＳ０７に進む。通常、初回の調整では位相調整が完了していない。ステップＳ０７にて、デジタル回路３２は位相調整工程にて電圧位相Φоを生成する。ステップＳ０８にて、デジタル回路３２は帯域制限信号ｓｉｇ２から演算された電圧振幅Ｖ２から変更せずに電圧振幅Ｖоを生成する。つまり、デジタル回路３２は電圧振幅Ｖ２を電圧振幅Ｖоとして生成する。ステップＳ０９にて、制御回路１３は、電圧位相Φо、電圧振幅Ｖоを有する補償信号ｓｉｇ３を増幅回路１４に出力する。増幅回路１４は補償信号ｓｉｇ３が増幅された出力信号ｓｉｇ４をコモンモードトランス１６及びインピーダンス調整器１８に出力する。出力信号ｓｉｇ４の電圧である出力電圧Ｖｓの振幅は、電圧振幅Ｖоから増幅されている。適宜、出力電圧Ｖｓの電圧振幅はＶｓのまま用いる。出力電圧Ｖｓは、位相が電圧位相Φоであり、振幅が電圧振幅はＶｓである。ステップＳ０９の後にステップＳ０１に戻る。ステップＳ０６にて、デジタル回路３２は帯域制限信号ｓｉｇ２から演算された電圧振幅Ｖоを生成する。その後、ステップＳ０９に進む。 At step S05, the control circuit 13 determines whether or not the phase adjustment has been completed. If the phase adjustment has been completed, the process proceeds to step S06, and if the phase adjustment has not been completed, the process proceeds to step S07. Normally, the phase adjustment is not completed in the first adjustment. At step S07, the digital circuit 32 generates the voltage phase Φо in the phase adjustment process. At step S08, the digital circuit 32 generates the voltage amplitude Vо without changing the voltage amplitude V2 calculated from the band-limited signal sig2. That is, the digital circuit 32 generates the voltage amplitude V2 as the voltage amplitude Vо. In step S<b>09 , the control circuit 13 outputs the compensation signal sig<b>3 having the voltage phase Φо and the voltage amplitude Vо to the amplifier circuit 14 . The amplifier circuit 14 outputs an output signal sig4 obtained by amplifying the compensation signal sig3 to the common mode transformer 16 and the impedance adjuster 18 . The amplitude of the output voltage Vs, which is the voltage of the output signal sig4, is amplified from the voltage amplitude VO. As appropriate, the voltage amplitude of the output voltage Vs is used as it is. The output voltage Vs has a phase of voltage phase Φо and an amplitude of voltage amplitude Vs. After step S09, the process returns to step S01. At step S06, the digital circuit 32 generates the voltage amplitude V.sub.O calculated from the band-limited signal sig2. After that, the process proceeds to step S09.
　まず、コモンモード電圧Ｖｃｍの特定周波数成分を急速に相殺する場合を考える。第１回目の補償信号ｓｉｇ３を生成する際に、制御回路１３は、帯域制限回路１２から出力された帯域制限信号ｓｉｇ２と逆相かつ同一振幅の電圧位相Φо及び電圧振幅Ｖоを有する補償信号ｓｉｇ３を出力するように、初期の電圧位相Φоである初期電圧位相Φ２ｉ、初期の電圧振幅Ｖоである初期電圧振幅Ｖ２ｉを決定する。１回目の補償信号ｓｉｇ３を生成する際に、前述したように電圧振幅Ｖ２から変更せずに電圧振幅Ｖоを生成するので、電圧振幅Ｖоは帯域制限信号ｓｉｇ２と同一である。理想的には、振幅演算器３６及び位相演算器３７で得られる電圧位相Φ２及び電圧振幅Ｖ２をそのまま初期値とすると、帯域制限信号ｓｉｇ２と逆相かつ同一振幅の電圧位相Φо及び電圧振幅Ｖоを有する補償信号ｓｉｇ３を出力できる。増幅回路１４が、補償信号ｓｉｇ３を増幅して、電力線４、５に発生しているコモンモード電圧Ｖｃｍと逆相かつ同一振幅の注入電圧Ｖａｐが発生する出力電圧Ｖｓを有する出力信号ｓｉｇ４をコモンモードトランス１６に出力することは、コモンモード電圧Ｖｃｍの特定周波数成分を急速に相殺するには理想的である。 First, consider the case of rapidly canceling out a specific frequency component of the common mode voltage Vcm. When generating the first compensation signal sig3, the control circuit 13 generates the compensation signal sig3 having a voltage phase Φо and a voltage amplitude Vо that are opposite in phase to and have the same amplitude as the band-limited signal sig2 output from the band-limiting circuit 12. An initial voltage phase Φ2i, which is the initial voltage phase Φо, and an initial voltage amplitude V2i, which is the initial voltage amplitude Vо, are determined so as to output. When generating the compensation signal sig3 for the first time, the voltage amplitude Vо is generated without changing the voltage amplitude V2 as described above, so the voltage amplitude Vо is the same as the band-limited signal sig2. Ideally, if the voltage phase Φ2 and the voltage amplitude V2 obtained by the amplitude calculator 36 and the phase calculator 37 are used as the initial values, the voltage phase Φо and the voltage amplitude Vо having the same amplitude and the opposite phase as the band-limited signal sig2 are obtained. can output a compensating signal sig3 with The amplifier circuit 14 amplifies the compensation signal sig3 to generate an output signal sig4 having an output voltage Vs generated by an injection voltage Vap having the same amplitude and opposite in phase to the common mode voltage Vcm generated on the power lines 4 and 5 as a common mode. Outputting to transformer 16 is ideal for rapidly canceling specific frequency components of common mode voltage Vcm.
　しかし、コモンモードトランス１６が注入電圧Ｖａｐを発生させる前に、ＬＣ並列共振回路である負荷回路６０にステップ的に電力線４、５に発生しているコモンモード電圧Ｖｃｍの特定周波数成分と逆相かつ同一振幅の注入電圧Ｖａｐが発生する電圧振幅の出力電圧Ｖｓを印加する場合又は位相を急変する場合には、ＬＣ並列共振回路である負荷回路６０には過渡的に高周波の電圧が印加される。このために、負荷回路６０に過電流と過電圧とが発生する場合がある。この過渡現象の影響を抑えるために、出力電圧Ｖｓの電圧振幅及び電圧位相の調整の際に、単位時間当たりの変化量に制限をかけることが望ましい。出力電圧Ｖｓの電圧振幅及び電圧位相を制御する補償信号ｓｉｇ３の電圧位相Φо及び電圧振幅Ｖоは、単位時間当たりの変化量に制限をかけることが望ましい。 However, before the common mode transformer 16 generates the injection voltage Vap, the load circuit 60, which is an LC parallel resonance circuit, is stepwise reversed in phase with the specific frequency component of the common mode voltage Vcm generated on the power lines 4 and 5. When the output voltage Vs having the voltage amplitude generated by the injection voltage Vap of the same amplitude is applied, or when the phase is suddenly changed, a high-frequency voltage is transiently applied to the load circuit 60, which is an LC parallel resonance circuit. As a result, overcurrent and overvoltage may occur in the load circuit 60 . In order to suppress the influence of this transient phenomenon, it is desirable to limit the amount of change per unit time when adjusting the voltage amplitude and voltage phase of the output voltage Vs. It is desirable to limit the amount of change per unit time of the voltage phase Φо and voltage amplitude Vо of the compensation signal sig3 that controls the voltage amplitude and voltage phase of the output voltage Vs.
　なお、増幅回路１４の出力電圧Ｖｓの振幅は、最適値に対し、コモンモードフィルタ回路１の各部品のばらつき、環境変化により誤差が生じる。そこで、制御回路１３に電圧位相Φоと電圧振幅Ｖоを最適化するアルゴリズムが組み込まれている。例えば、初期電圧位相Φ２ｉ及び初期電圧振幅Ｖ２ｉから小さな位相幅ΔΦ及び小振幅ΔＶだけ変化した電圧位相Φо及び電圧振幅Ｖоを更新して、その値を最適化することでコモンモード電圧Ｖｃｍの特定の周波数成分を、急激な過渡変化が生じないようにコモンモード電圧Ｖｃｍの特定周波数成分を低減することができる。なお、初期電圧位相Φ２ｉ及び初期電圧振幅Ｖ２ｉは、急速に相殺する場合と異なる値になっている。 It should be noted that the amplitude of the output voltage Vs of the amplifier circuit 14 has an error with respect to the optimum value due to variations in each component of the common mode filter circuit 1 and environmental changes. Therefore, the control circuit 13 incorporates an algorithm for optimizing the voltage phase Φо and the voltage amplitude Vо. For example, by updating the voltage phase Φо and voltage amplitude Vо changed by a small phase width ΔΦ and a small amplitude ΔV from the initial voltage phase Φ2i and the initial voltage amplitude V2i, and optimizing the values thereof, the common mode voltage Vcm can be set to a specific value. A specific frequency component of the common mode voltage Vcm can be reduced so as not to cause an abrupt transient change. Note that the initial voltage phase Φ2i and the initial voltage amplitude V2i are values different from those in the case of rapid cancellation.
　電圧位相Φо及び電圧振幅Ｖоを最適化方法、すなわちステップＳ０７の位相調整工程及びステップＳ０６の振幅調整工程を説明する前に、注入電圧Ｖａｐの位相及び振幅の設定によるコモンモード電圧Ｖｃｍの残留量すなわち低減効果を図１５、図１６を用いて説明する。図１５、図１６の横軸は位相Φであり、縦軸はコモンモード電圧Ｖｃｍである。コモンモード電圧Ｖｃｍは振幅の最大値を基準にした規格化された値で示している。コモンモード電圧特性９３ａ、９４ａは注入電圧Ｖａｐが電力線４、５に注入される前すなわち補償前における一つの特定周波数のコモンモード電圧Ｖｃｍの特性である。図１５には、注入電圧Ｖａｐとコモンモード電圧Ｖｃｍの逆相との位相差（逆相位相差）が６０°、３０°、０°の場合のコモンモード電圧特性９３ｂ、９３ｃ、９３ｄが示されている。コモンモード電圧特性９３ｂ、９３ｃ、９３ｄにおいて、注入される注入電圧Ｖａｐはコモンモード電圧Ｖｃｍの特定周波数成分と同一の電圧振幅を有している。コモンモード電圧特性９３ｂは逆相位相差が６０°の特性であり、コモンモード電圧特性９３ｃは逆相位相差が３０°の特性であり、コモンモード電圧特性９３ｄは逆相位相差が０°の特性である。逆相位相差の最適値は０°である。逆相位相差が小さければ、特定周波数のコモンモード電圧Ｖｃｍすなわちコモンモード電圧Ｖｃｍの特定周波数成分の残留量が低減されていることが確認できる。 Before explaining the method of optimizing the voltage phase Φо and the voltage amplitude Vо, that is, the phase adjustment process of step S07 and the amplitude adjustment process of step S06, the residual amount of the common mode voltage Vcm by setting the phase and amplitude of the injection voltage Vap, that is, The reduction effect will be described with reference to FIGS. 15 and 16. FIG. 15 and 16, the horizontal axis is the phase Φ, and the vertical axis is the common mode voltage Vcm. The common mode voltage Vcm is shown as a standardized value based on the maximum value of amplitude. Common mode voltage characteristics 93a and 94a are characteristics of common mode voltage Vcm at one specific frequency before injection voltage Vap is injected into power lines 4 and 5, ie, before compensation. FIG. 15 shows common mode voltage characteristics 93b, 93c, and 93d when the phase difference (negative phase difference) between the injection voltage Vap and the common mode voltage Vcm is 60°, 30°, and 0°. there is In the common mode voltage characteristics 93b, 93c, 93d, the injected injection voltage Vap has the same voltage amplitude as the specific frequency component of the common mode voltage Vcm. The common mode voltage characteristic 93b is a characteristic with a negative phase difference of 60°, the common mode voltage characteristic 93c is a characteristic with a negative phase difference of 30°, and the common mode voltage characteristic 93d is a characteristic with a negative phase difference of 0°. . The optimum value for the antiphase phase difference is 0°. If the negative phase difference is small, it can be confirmed that the common mode voltage Vcm of the specific frequency, that is, the residual amount of the specific frequency component of the common mode voltage Vcm is reduced.
　図１６には、コモンモード電圧Ｖｃｍの特定周波数成分と逆相の電圧振幅に対する注入電圧Ｖａｐの電圧振幅の割合（振幅割合）が１／３、２／３、３／３の場合のコモンモード電圧特性９４ｂ、９４ｃ、９４ｄが示されている。コモンモード電圧特性９４ｂ、９４ｃ、９４ｄにおいて、注入される注入電圧Ｖａｐはコモンモード電圧Ｖｃｍの特定周波数成分と逆相の電圧位相を有している。コモンモード電圧特性９４ｂは振幅割合が１／３の特性であり、コモンモード電圧特性９４ｃは振幅割合が２／３の特性であり、コモンモード電圧特性９４ｄは振幅割合が３／３の特性である。振幅割合の最適値は３／３である。振幅割合の振幅誤差が小さければ、コモンモード電圧Ｖｃｍの特定周波数成分の残留量は低減されていることが確認できる。 FIG. 16 shows the common mode voltages when the ratio (amplitude ratio) of the voltage amplitude of the injected voltage Vap to the voltage amplitude opposite to the specific frequency component of the common mode voltage Vcm is 1/3, 2/3, and 3/3. Properties 94b, 94c, 94d are shown. In the common mode voltage characteristics 94b, 94c, and 94d, the injected injection voltage Vap has a voltage phase opposite to the specific frequency component of the common mode voltage Vcm. The common mode voltage characteristic 94b has an amplitude ratio of 1/3, the common mode voltage characteristic 94c has an amplitude ratio of 2/3, and the common mode voltage characteristic 94d has an amplitude ratio of 3/3. . The optimum value for the amplitude ratio is 3/3. If the amplitude error of the amplitude ratio is small, it can be confirmed that the residual amount of the specific frequency component of the common mode voltage Vcm is reduced.
　位相調整器３８及び振幅調整器３９に搭載される最適化方法の一例として、山登り法を用いてコモンモード電圧Ｖｃｍの特定周波数成分を最小化する方法を説明する。まず、初期電圧位相Φ２ｉに対し位相を位相幅ΔΦだけ変化させ、常に検出されたコモンモード電圧Ｖｃｍの前回値よりも小さくなるように電圧位相Φоを変化させる。電圧位相Φоが変化しなくなった場合、その電圧位相Φоを最適値とする。図１７に、実施の形態１のデジタル回路３２の第一例における位相調整例すなわち電圧位相Φоの最適化方法例を示した。電圧位相Φоの位相変化特性９５とコモンモード電圧Ｖｃｍの電圧変化特性９６とが同時に示されている。横軸は時間であり、位相変化特性９５の縦軸は電圧位相Φоであり、電圧変化特性９６の縦軸はコモンモード電圧Ｖｃｍである。図３に示した制御回路１３はデジタル方式である。デジタル方式では、ＡＤ変換器３１を設けコモンモード電圧Ｖｃｍを取り込み、検出値とする。ＡＤ変換器３１が帯域制限信号ｓｉｇ２からデジタル信号に変換する演算入力信号ｓｉｇ２ｄの位相振幅Φ２及び電圧振幅Ｖ２が、デジタル回路３２が処理するコモンモード電圧Ｖｃｍの検出値に相当する。 As an example of the optimization method installed in the phase adjuster 38 and the amplitude adjuster 39, a method of minimizing a specific frequency component of the common mode voltage Vcm using the hill-climbing method will be described. First, the phase is changed by the phase width ΔΦ with respect to the initial voltage phase Φ2i, and the voltage phase Φо is changed so as to always be smaller than the previous value of the detected common mode voltage Vcm. When the voltage phase Φо stops changing, the voltage phase Φо is set to the optimum value. FIG. 17 shows an example of phase adjustment in the first example of the digital circuit 32 of the first embodiment, that is, an example of an optimization method of the voltage phase Φо. A phase change characteristic 95 of the voltage phase Φо and a voltage change characteristic 96 of the common mode voltage Vcm are shown at the same time. The horizontal axis is time, the vertical axis of the phase change characteristic 95 is the voltage phase Φо, and the vertical axis of the voltage change characteristic 96 is the common mode voltage Vcm. The control circuit 13 shown in FIG. 3 is digital. In the digital method, an AD converter 31 is provided and the common mode voltage Vcm is taken in and used as a detection value. The phase amplitude Φ2 and voltage amplitude V2 of the operation input signal sig2d that the AD converter 31 converts from the band-limited signal sig2 to a digital signal correspond to the detected value of the common mode voltage Vcm processed by the digital circuit 32 .
　デジタル回路３２は位相振幅Φ２及び電圧振幅Ｖ２に基づいて位相振幅Φо及び電圧振幅Ｖоを生成し、この位相振幅Φо及び電圧振幅Ｖоに基づいて生成された出力電圧Ｖｓが生成される。出力電圧Ｖｓに基づいてコモンモードトランス１６が電力線４、５に注入電圧Ｖａｐが注入され、新たなコモンモード電圧Ｖｃｍ検出値すなわち位相振幅Φ２及び電圧振幅Ｖ２が得られる。この検出値の振幅すなわち電圧振幅Ｖ２が低下するように、すなわちコモンモード電圧Ｖｃｍの電圧振幅が低下するように、デジタル回路３２の制御周期ΔＴ毎の位相変化特性９５の変化方向を示す極性が３回連続して同極性に変化する場合には最適点の探索を継続し、同極性変化の連続回数が３回未満で極性が反転する点を最適点とする。電圧位相Φоが最適化されたかを判定する位相判定条件は、位相幅ΔΦが３回連続して同極性に変化しないことであり、位相幅ΔΦの同極性変化の連続回数が３回未満で極性が反転することである。 The digital circuit 32 generates a phase amplitude Φо and a voltage amplitude Vо based on the phase amplitude Φ2 and the voltage amplitude V2, and an output voltage Vs is generated based on the phase amplitude Φо and the voltage amplitude Vо. Based on the output voltage Vs, the common mode transformer 16 injects the injection voltage Vap into the power lines 4 and 5, and a new common mode voltage Vcm detection value, that is, the phase amplitude Φ2 and the voltage amplitude V2 are obtained. Three polarities indicating the change direction of the phase change characteristic 95 for each control period ΔT of the digital circuit 32 are used so that the amplitude of the detected value, that is, the voltage amplitude V2, is reduced, that is, the voltage amplitude of the common mode voltage Vcm is reduced. If the same polarity changes continuously, the search for the optimum point is continued, and the point where the polarity is reversed when the number of consecutive same polarity changes is less than 3 times is taken as the optimum point. The phase determination condition for determining whether the voltage phase Φо has been optimized is that the phase width ΔΦ does not change to the same polarity three times in succession. is to be reversed.
　電圧位相Φоの最適化方法により、最適点ｐ１の最適値すなわち電圧位相Φоｐが得られる。図１７には１０回の探索により最適点ｐ１が得られた例を示した。時刻ｔ０の電圧位相Φоは初期電圧位相Φ２ｉである。時刻ｔ１で１回目の処理で初期電圧位相Φ２ｉに位相幅ΔΦが加算された電圧位相Φоが生成される。１回目の処理の極性は正である。位相幅ΔΦが減算される場合の極性は負である。時刻ｔ１、ｔ２、ｔ３、ｔ４、ｔ５、ｔ６における処理は極性が正の処理であり、時刻ｔ７、ｔ８の処理は極性が負の処理である。時刻ｔ９の処理すなわち９回目の処理で極性が前回と反転した正になっている。時刻ｔ１０の処理すなわち１０回目の処理の際に、位相幅ΔΦの負極性変化が２回連続しており、直前の処理で正極性に反転しているので、位相判定条件が満たれていると判定される。デジタル回路３２は、時刻ｔ１０の処理において位相判定条件が満たれていると判定し、前回の電圧位相Φｂから変更せずに電圧位相Φоとして生成する。位相幅ΔΦの極性はコモンモード電圧Ｖｃｍの変化極性と反対に変化させる。時刻ｔ７の処理において、前回の処理によりコモンモード電圧Ｖｃｍが増加したので、すなわちコモンモード電圧Ｖｃｍの変化極性が負から正に反転したので、位相幅ΔΦの極性は正から負に変更されている。 An optimum value of the optimum point p1, that is, the voltage phase Φоp is obtained by the optimization method of the voltage phase Φо. FIG. 17 shows an example in which the optimum point p1 is obtained by ten searches. The voltage phase Φо at time t0 is the initial voltage phase Φ2i. At time t1, the voltage phase Φо is generated by adding the phase width ΔΦ to the initial voltage phase Φ2i in the first process. The polarity of the first treatment is positive. The polarity is negative when the phase width ΔΦ is subtracted. The processes at times t1, t2, t3, t4, t5, and t6 are processes with positive polarities, and the processes at times t7 and t8 are processes with negative polarities. In the process at time t9, that is, in the ninth process, the polarity is positive, which is the opposite of the previous one. During the process at time t10, that is, the tenth process, the phase width ΔΦ continuously changes to the negative polarity twice, and since it was reversed to the positive polarity in the immediately preceding process, it is assumed that the phase determination condition is satisfied. be judged. The digital circuit 32 determines that the phase determination condition is satisfied in the process at time t10, and generates the voltage phase Φо without changing the previous voltage phase Φb. The polarity of the phase width ΔΦ is changed opposite to the polarity of the common mode voltage Vcm. In the process at time t7, the common mode voltage Vcm increased by the previous process, that is, the polarity of the change in the common mode voltage Vcm was reversed from negative to positive, so the polarity of the phase width ΔΦ is changed from positive to negative. .
　電圧位相Φоの最適化方法により得られた最適値すなわち電圧位相Φоｐを用いることで、ある特定周波数の出力電圧Ｖｓ、注入電圧Ｖａｐはコモンモード電圧Ｖｃｍに対して位相差なく逆相を維持できる。制御回路１３が生成する補償信号ｓｉｇ３の電圧位相Φоは、増幅回路が出力する出力信号ｓｉｇ４、コモンモードトランス１６が電力線４、５に注入する注入電圧Ｖａｐでも変わらない。増幅回路が出力する出力信号ｓｉｇ４における出力電圧Ｖｓの電圧位相Φｓは電圧位相Φоと同じであり、注入電圧Ｖａｐの電圧位相は電圧位相Φоと同じである。 By using the optimum value obtained by the voltage phase Φо optimization method, that is, the voltage phase Φоp, the output voltage Vs and the injection voltage Vap at a specific frequency can maintain the opposite phase with respect to the common mode voltage Vcm without a phase difference. The voltage phase ΦO of the compensation signal sig3 generated by the control circuit 13 does not change even with the output signal sig4 output from the amplifier circuit and the injection voltage Vap injected into the power lines 4 and 5 by the common mode transformer 16 . The voltage phase Φs of the output voltage Vs in the output signal sig4 output from the amplifier circuit is the same as the voltage phase Φо, and the voltage phase of the injected voltage Vap is the same as the voltage phase Φо.
　なお、電圧位相Φоを調整する方法としては、制御回路１３に自発振用のサインテーブル（サイン波形用テーブル）を用意しておきその位相量を変化させる、又はＡＤ変換で取り込んだデジタル信号をレジスタ、ＲＡＭ（Random　Access　Memory）等に格納し、制御回路１３で使用するまでの遅延を任意に制御するなどが考えらえる。 As a method of adjusting the voltage phase Φо, a sine table for self-oscillation (a sine wave table) is prepared in the control circuit 13 and the phase amount is changed, or a digital signal captured by AD conversion is stored in a register. , RAM (random access memory) or the like, and the control circuit 13 can arbitrarily control the delay until it is used.
　最適な位相探索が完了したら、電圧振幅Ｖｏの最適値の探索を行う。すなわち、位相調整工程が終了した後に、振幅調整工程が実行される。電圧振幅Ｖｏの最適化方法は、電圧位相Φоの最適化方法と同様である。まず、初期電圧振幅Ｖ２ｉに対し振幅を小振幅ΔＶだけ変化させ、常に検出されたコモンモード電圧Ｖｃｍの前回値よりも小さくなるように電圧振幅Ｖоを変化させる。電圧振幅Ｖоが変化しなくなった場合、その電圧振幅Ｖоを最適値とする。図１８に、実施の形態１のデジタル回路３２の第一例における振幅調整例すなわち電圧振幅Ｖоの最適化方法例を示した。電圧振幅Ｖоの振幅変化特性９７とコモンモード電圧Ｖｃｍの電圧変化特性９８とが同時に示されている。横軸は時間であり、振幅変化特性９７の縦軸は電圧振幅Ｖоであり、電圧変化特性９８の縦軸はコモンモード電圧Ｖｃｍである。 After the optimum phase search is completed, the optimum value of the voltage amplitude Vo is searched. That is, the amplitude adjustment process is performed after the phase adjustment process is completed. The method of optimizing the voltage amplitude Vo is the same as the method of optimizing the voltage phase Φо. First, the amplitude is changed by a small amplitude ΔV with respect to the initial voltage amplitude V2i, and the voltage amplitude Vо is changed so as to always be smaller than the previous value of the detected common mode voltage Vcm. When the voltage amplitude V.sub.O stops changing, the voltage amplitude V.sub.O is taken as the optimum value. FIG. 18 shows an example of amplitude adjustment in the first example of the digital circuit 32 of the first embodiment, that is, an example of an optimization method of the voltage amplitude V.sub.O. An amplitude change characteristic 97 of the voltage amplitude Vо and a voltage change characteristic 98 of the common mode voltage Vcm are shown at the same time. The horizontal axis is time, the vertical axis of amplitude change characteristic 97 is voltage amplitude Vо, and the vertical axis of voltage change characteristic 98 is common mode voltage Vcm.
　デジタル回路３２が処理するコモンモード電圧Ｖｃｍの検出値における振幅すなわち電圧振幅Ｖ２が低下するように、すなわちコモンモード電圧Ｖｃｍの電圧振幅が低下するように、デジタル回路３２の制御周期ΔＴ毎の振幅変化特性９７の変化方向を示す極性が３回連続して同極性に変化する場合には最適点の探索を継続し、同極性変化の連続回数が３回未満で極性が反転する点を最適点とする。電圧振幅Ｖоが最適化されたかを判定する振幅判定条件は、小振幅ΔＶが３回連続して同極性に変化しないことであり、小振幅ΔＶの同極性変化の連続回数が３回未満で極性が反転することである。 Amplitude change of the digital circuit 32 at each control period ΔT so that the amplitude of the detected value of the common mode voltage Vcm processed by the digital circuit 32, that is, the voltage amplitude V2 is reduced, that is, the voltage amplitude of the common mode voltage Vcm is reduced When the polarity indicating the change direction of the characteristic 97 changes to the same polarity three times in succession, the search for the optimum point is continued, and the point at which the polarity is reversed when the number of consecutive changes in the same polarity is less than three times is taken as the optimum point. do. The amplitude judgment condition for judging whether the voltage amplitude Vо has been optimized is that the small amplitude ΔV does not change to the same polarity three times in succession, and the polarity is to be reversed.
　電圧振幅Ｖоの最適化方法により、最適点ｐ２の最適値すなわち電圧振幅Ｖоｐが得られる。図１８には１０回の探索により最適点ｐ２が得られた例を示した。図１８において電圧振幅Ｖоの最適化方法が開始される時刻は、電圧位相Φоの最適化方法が終了した時刻ｔ１０にしている。時刻ｔ１０の電圧振幅Ｖоは初期電圧振幅Ｖ２ｉである。時刻ｔ１１で１回目の処理で初期電圧振幅Ｖ２ｉに小振幅ΔＶが加算された電圧振幅Ｖоが生成される。１回目の処理の極性は正である。小振幅ΔＶが減算される場合の極性は負である。時刻ｔ１１、ｔ１２、ｔ１３、ｔ１４、ｔ１５、ｔ１６における処理は極性が正の処理であり、時刻ｔ１７、ｔ１８の処理は極性が負の処理である。時刻ｔ１９の処理すなわち９回目の処理で極性が前回と反転した正になっている。時刻ｔ２０の処理すなわち１０回目の処理の際に、小振幅ΔＶの負極性変化が２回連続しており、直前の処理で正極性に反転しているので、振幅判定条件が満たれていると判定される。デジタル回路３２は、時刻ｔ２０の処理において振幅判定条件が満たれていると判定し、前回の電圧振幅Ｖｂから変更せずに電圧振幅Ｖоとして生成する。小振幅ΔＶの極性はコモンモード電圧Ｖｃｍの変化極性と反対に変化させる。時刻ｔ１７の処理において、前回の処理によりコモンモード電圧Ｖｃｍが増加したので、すなわちコモンモード電圧Ｖｃｍの変化極性が負から正に反転したので、小振幅ΔＶの極性は正から負に変更されている。 The optimum value of the optimum point p2, that is, the voltage amplitude Vоp is obtained by the method of optimizing the voltage amplitude Vо. FIG. 18 shows an example in which the optimum point p2 is obtained by ten searches. In FIG. 18, the time at which the method of optimizing the voltage amplitude V.sub.O is started is the time t10 at which the method of optimizing the voltage phase .PHI..sub.O ends. The voltage amplitude Vо at time t10 is the initial voltage amplitude V2i. At time t11, the voltage amplitude Vо is generated by adding the small amplitude ΔV to the initial voltage amplitude V2i in the first process. The polarity of the first treatment is positive. The polarity is negative when the small amplitude ΔV is subtracted. The processes at times t11, t12, t13, t14, t15, and t16 are positive in polarity, and the processes at times t17 and t18 are negative in polarity. In the process at time t19, that is, in the ninth process, the polarity is positive, which is the opposite of the previous one. During the processing at time t20, that is, the tenth processing, the negative polarity change of the small amplitude ΔV occurs twice in succession, and the positive polarity is reversed in the immediately preceding processing. be judged. The digital circuit 32 determines that the amplitude determination condition is satisfied in the process at time t20, and generates the voltage amplitude Vо without changing the previous voltage amplitude Vb. The polarity of the small amplitude ΔV is changed opposite to the polarity of the common mode voltage Vcm. In the process at time t17, the common mode voltage Vcm increased by the previous process, that is, the polarity of the change in the common mode voltage Vcm was reversed from negative to positive, so the polarity of the small amplitude ΔV is changed from positive to negative. .
　電圧位相Φоの最適化方法は、ステップＳ０７の位相調整工程にて実行される。ステップＳ０７の位相調整工程の詳細は図１３に示した。電圧振幅Ｖоの最適化方法は、ステップＳ０６の振幅調整工程にて実行される。ステップＳ０６の振幅調整工程の詳細は図１４に示した。まず、図１３に示した位相調整工程を説明する。 The method of optimizing the voltage phase Φо is executed in the phase adjustment process of step S07. Details of the phase adjustment process in step S07 are shown in FIG. The method of optimizing the voltage amplitude Vо is executed in the amplitude adjustment step of step S06. Details of the amplitude adjustment process in step S06 are shown in FIG. First, the phase adjustment process shown in FIG. 13 will be described.
　ステップＳ１１にて、デジタル回路３２の位相調整器３８は位相調整が１回目か判定する。位相調整が１回目である場合はステップＳ１２に進み、位相調整が１回目でない場合はステップＳ１３に進む。ステップＳ１２にて、位相調整器３８は演算入力信号ｓｉｇ２ｄの電圧位相Φ２から電圧位相Φоを生成する。１回目の処理の際の電圧位相Φ２が初期電圧位相Φ２ｉである。ステップＳ１２において生成される電圧位相Φоは、初期電圧位相Φ２ｉに位相幅ΔΦが加算された位相になる。１回の位相調整が終了し、ステップＳ０８、ステップＳ０９、ステップＳ０１を経て再度実行されるステップＳ０７が２回目の位相調整になる。 At step S11, the phase adjuster 38 of the digital circuit 32 determines whether the phase adjustment is the first time. If the phase adjustment is the first time, the process proceeds to step S12, and if the phase adjustment is not the first time, the process proceeds to step S13. At step S12, the phase adjuster 38 generates a voltage phase Φо from the voltage phase Φ2 of the operation input signal sig2d. The voltage phase Φ2 in the first process is the initial voltage phase Φ2i. The voltage phase Φо generated in step S12 is a phase obtained by adding the phase width ΔΦ to the initial voltage phase Φ2i. After one phase adjustment is completed, step S07, which is executed again after steps S08, S09, and S01, is the second phase adjustment.
　２回目の位相調整の場合、ステップＳ１１からステップＳ１３に進む。ステップＳ１３にて、位相調整器３８は位相幅ΔΦが３回連続して同極性に変化しているかを判定する（位相条件判定工程）。位相幅ΔΦが３回連続して同極性に変化している場合は、位相判定条件が満たされていない場合であり、ステップＳ１４に進む。位相幅ΔΦが３回連続して同極性に変化していない場合すなわち位相幅ΔΦの同極性変化の連続回数が３回未満で極性が反転する場合は、位相判定条件が満たされた場合であり、ステップＳ１５に進む。ステップＳ１４にて、位相調整器３８は前回電圧位相Φｂから位相幅ΔΦだけ変化した電圧位相Φоを生成する。ステップＳ１５にて、位相判定条件が満たされているので、位相調整器３８は前回電圧位相Φｂを電圧位相Φоとして生成し出力する。また、ステップＳ１５にて、位相調整器３８は位相調整の終了を示す位相調整フラグｆｌｇ１を出力する。２回目の位相調整が終了し、ステップＳ０８、ステップＳ０９、ステップＳ０１を経て再度実行されるステップＳ０７が３回目の位相調整になる。位相判定条件が満たされるまで、ステップＳ０７の位相調整工程が、ステップＳ０８、ステップＳ０９、ステップＳ０１の実行を伴って繰り返される。 In the case of the second phase adjustment, the process proceeds from step S11 to step S13. In step S13, the phase adjuster 38 determines whether or not the phase width ΔΦ has changed to the same polarity three times in succession (phase condition determination step). If the phase width ΔΦ changes to the same polarity three times in succession, it means that the phase determination condition is not satisfied, and the process proceeds to step S14. If the phase width ΔΦ does not change to the same polarity three times in a row, that is, if the phase width ΔΦ changes the same polarity less than three times in succession and the polarity is reversed, the phase determination condition is satisfied. , the process proceeds to step S15. At step S14, the phase adjuster 38 generates a voltage phase Φо that is different from the previous voltage phase Φb by the phase width ΔΦ. In step S15, since the phase determination condition is satisfied, the phase adjuster 38 generates and outputs the previous voltage phase Φb as the voltage phase Φо. Also, in step S15, the phase adjuster 38 outputs a phase adjustment flag flg1 indicating the end of phase adjustment. After the second phase adjustment is completed, step S07, which is executed again through steps S08, S09, and S01, is the third phase adjustment. The phase adjustment process of step S07 is repeated with execution of steps S08, S09, and S01 until the phase determination condition is satisfied.
　次に、図１４に示した振幅調整工程を説明する。ステップＳ２１にて、デジタル回路３２の振幅調整器３９は振幅調整が１回目か判定する。振幅調整が１回目である場合はステップＳ２２に進み、振幅調整が１回目でない場合はステップＳ２３に進む。ステップＳ２２にて、振幅調整器３９は演算入力信号ｓｉｇ２ｄの電圧振幅Ｖ２から電圧振幅Ｖоを生成する。１回目の処理の際の電圧振幅Ｖ２が初期電圧振幅Ｖ２ｉである。ステップＳ２２において生成される電圧振幅Ｖоは、初期電圧振幅Ｖ２ｉに小振幅ΔＶが加算された振幅になる。１回の振幅調整が終了し、ステップＳ０９、ステップＳ０１を経て再度実行されるステップＳ０６の実行が２回目の振幅調整になる。 Next, the amplitude adjustment process shown in FIG. 14 will be described. In step S21, the amplitude adjuster 39 of the digital circuit 32 determines whether the amplitude adjustment is the first time. If the amplitude adjustment is the first time, the process proceeds to step S22, and if the amplitude adjustment is not the first time, the process proceeds to step S23. At step S22, the amplitude adjuster 39 generates a voltage amplitude Vо from the voltage amplitude V2 of the operation input signal sig2d. The voltage amplitude V2 in the first process is the initial voltage amplitude V2i. The voltage amplitude Vо generated in step S22 is the sum of the initial voltage amplitude V2i and the small amplitude ΔV. After one amplitude adjustment is completed, step S06 is executed again through steps S09 and S01, which is the second amplitude adjustment.
　２回目の振幅調整の場合、ステップＳ２１からステップＳ２３に進む。ステップＳ２３にて、振幅調整器３９は小振幅ΔＶが３回連続して同極性に変化しているかを判定する（振幅条件判定工程）。小振幅ΔＶが３回連続して同極性に変化している場合は、振幅判定条件が満たされていない場合であり、ステップＳ２４に進む。小振幅ΔＶが３回連続して同極性に変化していない場合すなわち小振幅ΔＶの同極性変化の連続回数が３回未満で極性が反転する場合は、振幅判定条件が満たされた場合であり、ステップＳ２５に進む。ステップＳ２４にて、振幅調整器３９は前回の電圧振幅Ｖｂから小振幅ΔＶだけ変化した電圧振幅Ｖоを生成する。ステップＳ２５にて、振幅判定条件が満たされているので、振幅調整器３９は前回の電圧振幅Ｖｂを電圧振幅Ｖоとして生成し出力する。２回目の振幅調整が終了し、ステップＳ０９、ステップＳ０１を経て再度実行されるステップＳ０６が３回目の振幅調整になる。振幅判定条件が満たされるまで、ステップＳ０６の振幅調整工程が、ステップＳ０９、ステップＳ０１の実行を伴って繰り返される。 In the case of the second amplitude adjustment, the process proceeds from step S21 to step S23. At step S23, the amplitude adjuster 39 determines whether or not the small amplitude ΔV changes to the same polarity three times in succession (amplitude condition determination step). If the small amplitude ΔV changes to the same polarity three times in succession, it means that the amplitude determination condition is not satisfied, and the process proceeds to step S24. If the small amplitude ΔV does not change to the same polarity three times in succession, that is, if the number of consecutive changes in the same polarity of the small amplitude ΔV is less than three times and the polarity is reversed, the amplitude determination condition is satisfied. , the process proceeds to step S25. At step S24, the amplitude adjuster 39 generates a voltage amplitude Vо that is changed by a small amplitude ΔV from the previous voltage amplitude Vb. In step S25, since the amplitude determination condition is satisfied, the amplitude adjuster 39 generates and outputs the previous voltage amplitude Vb as the voltage amplitude Vо. After the second amplitude adjustment is completed, step S06, which is executed again after steps S09 and S01, is the third amplitude adjustment. The amplitude adjustment process of step S06 is repeated with the execution of steps S09 and S01 until the amplitude determination condition is satisfied.
　実施の形態１のコモンモードフィルタ回路１の第一例は、ステップＳ０７の位相調整工程及びステップＳ０６の振幅調整工程により最適化された電圧位相Φо及び電圧振幅Ｖоを有する補償信号ｓｉｇ３を生成し、補償信号ｓｉｇ３が増幅された出力信号ｓｉｇ４に基づいてコモンモードトランス１６から電力線４，５に注入電圧Ｖａｐを注入するので、ある特定周波数の注入電圧Ｖａｐはその特定周波数のコモンモード電圧Ｖｃｍに対して逆相かつ振幅の等しい電圧にできる。その結果、実施の形態１のコモンモードフィルタ回路１の第一例は、コモンモード電圧Ｖｃｍにおける特定周波数の成分を大幅に抑制することが可能となる。ここで１０ｋＨｚ以下の低周波帯域に含まれるキャリア周波数等の特定周波数が帯域制限回路１２の通過帯域すなわち２つのカットオフ周波数ｆｌ、ｆｈの間に入るように設定することで、実施の形態１のコモンモードフィルタ回路１の第一例は、低周波のコモンモード電圧Ｖｃｍを大幅に低減できる。 The first example of the common mode filter circuit 1 of Embodiment 1 generates a compensation signal sig3 having a voltage phase Φо and a voltage amplitude Vо optimized by the phase adjustment step of step S07 and the amplitude adjustment step of step S06, Since the injection voltage Vap is injected into the power lines 4 and 5 from the common mode transformer 16 based on the output signal sig4 obtained by amplifying the compensation signal sig3, the injection voltage Vap at a specific frequency is equal to the common mode voltage Vcm at the specific frequency. Voltages of opposite phase and equal amplitude can be obtained. As a result, the first example of the common mode filter circuit 1 of the first embodiment can significantly suppress the specific frequency component in the common mode voltage Vcm. Here, by setting a specific frequency such as a carrier frequency included in a low frequency band of 10 kHz or less so as to fall within the passband of the band limiting circuit 12, that is, between the two cutoff frequencies fl and fh, The first example of the common mode filter circuit 1 can significantly reduce the low frequency common mode voltage Vcm.
　実施の形態１のコモンモードフィルタ回路１の第一例における出力電圧生成回路６６は、帯域制限回路１２により帯域制限信号ｓｉｇ２が出力される度に、帯域制限信号ｓｉｇ２に基づく信号の電圧位相Φｏが予め定められた位相判定条件（ステップＳ１３からステップＳ１５に進む条件）を満たすまで出力電圧Ｖｓの位相Φｓすなわち電圧位相Φｏを予め定められた位相幅ΔΦずつ調整する位相調整器３８と、位相調整器３８が位相調整の終了を示す位相調整フラグｆｌｇ１を出力している場合に、帯域制限回路１２により帯域制限信号ｓｉｇ２が出力される度に、帯域制限信号ｓｉｇ２に基づく信号の電圧振幅Ｖｏが予め定められた振幅判定条件（ステップＳ２３からステップＳ２５に進む条件）を満たすまで出力電圧Ｖｓの振幅を予め定められた小振幅ΔＶ１ずつ調整する、すなわち出力電圧Ｖｓの振幅を制御する電圧振幅Ｖｏを予め定められた小振幅ΔＶずつ調整する振幅調整器３９と、を備えている。小振幅ΔＶ１は、小振幅ΔＶに増幅回路１４の増幅率が乗算された値である。実施の形態１のコモンモードフィルタ回路１の第一例は、山登り法を用いて出力電圧Ｖｓの位相（出力電圧位相Φｓ）及び振幅を制御する電圧位相Φｏ及び電圧振幅Ｖｏを最適化することができる。 The output voltage generation circuit 66 in the first example of the common mode filter circuit 1 of the first embodiment changes the voltage phase Φo of the signal based on the band-limited signal sig2 every time the band-limited signal sig2 is output from the band-limited circuit 12. A phase adjuster 38 that adjusts the phase Φs of the output voltage Vs, that is, the voltage phase Φo, by a predetermined phase width ΔΦ until a predetermined phase determination condition (condition for proceeding from step S13 to step S15) is satisfied; 38 outputs the phase adjustment flag flg1 indicating the end of phase adjustment, each time the band limiting circuit 12 outputs the band limiting signal sig2, the voltage amplitude Vo of the signal based on the band limiting signal sig2 is predetermined. The amplitude of the output voltage Vs is adjusted by a predetermined small amplitude ΔV1 until the determined amplitude determination condition (condition for proceeding from step S23 to step S25) is satisfied. and an amplitude adjuster 39 that adjusts by small amplitudes ΔV. The small amplitude ΔV1 is a value obtained by multiplying the small amplitude ΔV by the amplification factor of the amplifier circuit 14 . The first example of the common mode filter circuit 1 of Embodiment 1 can optimize the voltage phase Φo and the voltage amplitude Vo for controlling the phase (output voltage phase Φs) and amplitude of the output voltage Vs using the hill-climbing method. can.
　図１１に示したデジタル回路３２の第一例における位相調整器３８及び振幅調整器３９に組み込む探索器４０ａ、４０ｂのアルゴリズムは、帯域制限回路１２で得られる特定の周波数の検出値が減少するように特定の周波数の電圧位相Φｏ及び電圧振幅Ｖｏを最適化することで補償信号ｓｉｇ３を生成する機能を有していれば、山登り法だけに限定されない。帯域制限回路１２で得られる特定の周波数の検出値が減少するように特定の周波数の電圧位相Φｏ及び電圧振幅Ｖｏを最適化することで補償信号ｓｉｇ３を生成する機能は、ニューラルネットワークを用いた最適化、その他の機械学習方法を用いた最適化等によって実現されてもよい。 The algorithm of the searchers 40a, 40b incorporated in the phase adjuster 38 and the amplitude adjuster 39 in the first example of the digital circuit 32 shown in FIG. The method is not limited to the hill-climbing method as long as it has a function of generating the compensation signal sig3 by optimizing the voltage phase Φo and voltage amplitude Vo of a specific frequency. The function of generating the compensation signal sig3 by optimizing the voltage phase Φo and the voltage amplitude Vo of a specific frequency so that the detection value of the specific frequency obtained by the band limiting circuit 12 is reduced is an optimization using a neural network. optimization using other machine learning methods.
　ニューラルネットワークを用いて電圧位相Φｏ及び電圧振幅Ｖｏを最適化する探索回路２８を備えたデジタル回路３２の第二例を図１９に示した。図１９に示したデジタル回路３２の第二例は、デジタル回路３２の第一例における位相調整器３８及び振幅調整器３９が調整器５０に代わっている点で図１１に示したデジタル回路３２の第一例とは異なる。図１１に示したデジタル回路３２の第一例とは異なる部分を主に説明する。調整器５０は、振幅演算器３６で演算された電圧振幅Ｖ２、位相演算器３７で演算された電圧位相Φ２から電圧位相Φｏ及び電圧振幅Ｖｏを生成する。調整器５０は、ニューラルネットワークを用いた探索回路２８を備えている。探索回路２８は、例えば予め定められた調整回数による出力電圧Ｖｓの変更により、入力である電圧振幅Ｖ２及び出力である電圧振幅Ｖｏが最小化するように学習された学習済みモデルが組込まれている。予め定められた調整回数が１０回であれば、図１７に示した位相調整の回数、図１８に示した振幅調整の回数と同じであるが、探索回路２８は、電圧位相Φｏ及び電圧振幅Ｖｏを同時に更新する。このため、デジタル回路３２の第二例は、デジタル回路３２の第一例に比べて少ない調整回数で電圧位相Φｏ及び電圧振幅Ｖｏの最適化を達成できる。 A second example of a digital circuit 32 having a search circuit 28 that optimizes the voltage phase Φo and voltage amplitude Vo using a neural network is shown in FIG. The second example of the digital circuit 32 shown in FIG. 19 is different from the digital circuit 32 shown in FIG. This is different from the first example. A part different from the first example of the digital circuit 32 shown in FIG. 11 will be mainly described. The regulator 50 generates a voltage phase Φo and a voltage amplitude Vo from the voltage amplitude V2 calculated by the amplitude calculator 36 and the voltage phase Φ2 calculated by the phase calculator 37 . The adjuster 50 comprises a search circuit 28 using a neural network. The search circuit 28 incorporates a trained model learned to minimize the input voltage amplitude V2 and the output voltage amplitude Vo by changing the output voltage Vs by, for example, a predetermined number of adjustments. . If the predetermined number of adjustments is 10, which is the same as the number of phase adjustments shown in FIG. 17 and the number of amplitude adjustments shown in FIG. are updated at the same time. Therefore, the second example of the digital circuit 32 can optimize the voltage phase Φo and the voltage amplitude Vo with fewer adjustments than the first example of the digital circuit 32 .
　デジタル回路３２の第二例を備えたコモンモードフィルタ回路１の第二例の動作を説明する。図２１に示したフローチャートは、図１２に示したフローチャートとはステップＳ０５～ステップＳ０８がステップＳ１０に代わった点で異なる。異なる部分を主に説明する。ステップＳ１０にて、デジタル回路３２は、１回目の電圧位相Φｏ及び電圧振幅Ｖｏを生成する。ステップＳ０９にて、制御回路１３は、電圧位相Φо、電圧振幅Ｖоを有する補償信号ｓｉｇ３を増幅回路１４に出力する。増幅回路１４は補償信号ｓｉｇ３が増幅された出力信号ｓｉｇ４をコモンモードトランス１６及びインピーダンス調整器１８に出力する。１回目の出力信号ｓｉｇ４の出力電圧Ｖｓに基づいてコモンモードトランス１６から電力線４、５に１回目の注入電圧Ｖａｐが注入される。ステップＳ０１に戻り、ステップＳ０２、ステップＳ０３を経てステップＳ０４が実行されるまで、ステップＳ１０の電圧位相Φо、電圧振幅Ｖоを更新する調整工程が繰り返される。 The operation of the second example of the common mode filter circuit 1 including the second example of the digital circuit 32 will be explained. The flowchart shown in FIG. 21 differs from the flowchart shown in FIG. 12 in that steps S05 to S08 are replaced with step S10. Mainly different parts will be explained. In step S10, the digital circuit 32 generates the first voltage phase Φo and voltage amplitude Vo. In step S<b>09 , the control circuit 13 outputs the compensation signal sig<b>3 having the voltage phase Φо and the voltage amplitude Vо to the amplifier circuit 14 . The amplifier circuit 14 outputs an output signal sig4 obtained by amplifying the compensation signal sig3 to the common mode transformer 16 and the impedance adjuster 18 . The first injection voltage Vap is injected into the power lines 4 and 5 from the common mode transformer 16 based on the output voltage Vs of the first output signal sig4. Returning to step S01, the adjustment process of updating the voltage phase Φо and the voltage amplitude Vо in step S10 is repeated until step S04 is executed through steps S02 and S03.
　実施の形態１のコモンモードフィルタ回路１の第二例における出力電圧生成回路６６は、帯域制限回路１２により出力された帯域制限信号ｓｉｇ２の電圧位相Φ２及び電圧振幅Ｖ２に基づいて出力電圧Ｖｓの位相（出力電圧位相Φｓ）及び振幅を調整する調整器５０を備えている。調整器５０は、帯域制限信号ｓｉｇ２の電圧位相Φ２及び電圧振幅Ｖ２から出力電圧Ｖｓの位相（出力電圧位相Φｓ）及び振幅を制御する電圧位相Φｏの値及び電圧振幅Ｖｏの値を生成する学習済みモデルを構成する探索回路２８を備えている。探索回路２８は、帯域制限信号ｓｉｇ２に基づく信号の電圧振幅Ｖｏが許容値（閾値Ｖｔｈ２）以下に低減するまで、帯域制限信号ｓｉｇ２の電圧位相Φ２及び電圧振幅Ｖ２を入力として帯域制限信号ｓｉｇ２の電圧振幅Ｖ２が減少する出力電圧Ｖｓの位相（出力電圧位相Φｓ）及び振幅を制御する電圧位相Φоの値及び電圧振幅Ｖоの値を生成するように学習されており、帯域制限信号ｓｉｇ２が出力される度に、帯域制限信号ｓｉｇ２から探索回路２８により生成された電圧位相Φоの値及び電圧振幅Ｖｏの値に基づいて、出力電圧Ｖｓの位相（出力電圧位相Φｓ）及び振幅を調整する。実施の形態１のコモンモードフィルタ回路１の第二例は、学習済みモデルを用いて出力電圧Ｖｓの位相（出力電圧位相Φｓ）及び振幅を制御する電圧位相Φｏ及び電圧振幅Ｖｏを最適化することができる。 The output voltage generation circuit 66 in the second example of the common mode filter circuit 1 of Embodiment 1 determines the phase of the output voltage Vs based on the voltage phase Φ2 and the voltage amplitude V2 of the band-limited signal sig2 output from the band-limiting circuit 12. (output voltage phase Φs) and an adjuster 50 for adjusting the amplitude. The adjuster 50 is learned to generate the value of the voltage phase Φo and the value of the voltage amplitude Vo that control the phase (output voltage phase Φs) and the amplitude of the output voltage Vs from the voltage phase Φ2 and the voltage amplitude V2 of the bandlimited signal sig2. A search circuit 28 is provided for constructing the model. The search circuit 28 inputs the voltage phase Φ2 and the voltage amplitude V2 of the band-limited signal sig2 and detects the voltage of the band-limited signal sig2 until the voltage amplitude Vo of the signal based on the band-limited signal sig2 decreases below the allowable value (threshold value Vth2). It is learned to generate the phase (output voltage phase Φs) of the output voltage Vs at which the amplitude V2 decreases and the value of the voltage phase Φо and the value of the voltage amplitude Vо that control the amplitude, and the band-limited signal sig2 is output. Each time, the phase (output voltage phase Φs) and amplitude of the output voltage Vs are adjusted based on the value of the voltage phase ΦO and the value of the voltage amplitude Vo generated by the search circuit 28 from the band-limited signal sig2. A second example of the common mode filter circuit 1 of Embodiment 1 uses a learned model to optimize the voltage phase Φo and the voltage amplitude Vo that control the phase (output voltage phase Φs) and amplitude of the output voltage Vs. can be done.
　探索回路２８に組込むモデルは、学習装置１１０により生成される。学習装置１１０は、データ取得部１１１、モデル生成部１１２を備え、生成したモデルをモデル記憶装置１１３に記憶する。データ取得部１１１は、デジタル回路３２に入力される入力データｄａｔａ１、デジタル回路３２から出力されるべき最適化されたデータ、すなわち期待される出力データｄａｔａ２を学習用データとして取得する。入力データｄａｔａ１は電圧振幅Ｖ２、電圧位相Φ２を含んでおり、出力データｄａｔａ２は入力された電圧振幅Ｖ２、電圧位相Φ２に対応した期待値である電圧振幅Ｖｏｓ、電圧位相Φｏｓを含んでいる。 A model to be incorporated into the search circuit 28 is generated by the learning device 110 . The learning device 110 includes a data acquisition unit 111 and a model generation unit 112 and stores the generated model in the model storage device 113 . The data acquisition unit 111 acquires input data data1 input to the digital circuit 32 and optimized data to be output from the digital circuit 32, ie, expected output data data2, as learning data. Input data data1 includes voltage amplitude V2 and voltage phase Φ2, and output data data2 includes voltage amplitude Vos and voltage phase Φos, which are expected values corresponding to input voltage amplitude V2 and voltage phase Φ2.
　モデル生成部１１２は、データ取得部１１１から出力される入力データｄａｔａ１、出力データｄａｔａ２の組合せに基づいて作成される学習用データに基づいて、電圧振幅Ｖｏ、電圧位相Φｏを学習する。すなわち、デジタル回路３２の入力データｄａｔａ１、期待される出力データｄａｔａ２から最適な電圧振幅Ｖｏ、電圧位相Φｏを推論する学習済モデルを生成する。ここで、学習用データは、入力データｄａｔａ１の電圧振幅Ｖ２、電圧位相Φ２、出力データｄａｔａ２の電圧振幅Ｖｏｓ、電圧位相Φｏｓを互いに関連付けたデータである。 The model generation unit 112 learns the voltage amplitude Vo and the voltage phase Φo based on the learning data created based on the combination of the input data data1 and the output data data2 output from the data acquisition unit 111 . That is, a trained model for inferring the optimum voltage amplitude Vo and voltage phase Φo from the input data data1 of the digital circuit 32 and the expected output data data2 is generated. Here, the learning data is data in which the voltage amplitude V2 and the voltage phase Φ2 of the input data data1 and the voltage amplitude Vos and the voltage phase Φos of the output data data2 are associated with each other.
　モデル生成部１１２は、ニューラルネットワークモデルに従って、いわゆる教師あり学習により、電圧振幅Ｖｏ、電圧位相Φｏを学習する。ここで、教師あり学習とは、入力と結果のデータの組を学習装置に与えることで、それらの学習用データにある特徴を学習し、入力から結果を推論する方法をいう。 The model generation unit 112 learns the voltage amplitude Vo and the voltage phase Φo by so-called supervised learning according to the neural network model. Here, supervised learning refers to a method of inferring a result from an input by giving a set of input and result data to a learning device to learn features in the learning data.
　ニューラルネットワークは、複数のニューロンからなる入力層、複数のニューロンからなる中間層（隠れ層）、及び複数のニューロンからなる出力層で構成される。中間層は、１層、又は２層以上でもよい。 A neural network consists of an input layer consisting of multiple neurons, an intermediate layer (hidden layer) consisting of multiple neurons, and an output layer consisting of multiple neurons. The intermediate layer may be one layer, or two or more layers.
　例えば、探索回路２８は、図２０に示すような３層のニューラルネットワークを備えている。電圧振幅Ｖ２、電圧位相Φ２がそれぞれ入力層Ｎ１、Ｎ２に入力されると、電圧振幅Ｖ２、電圧位相Φ２に重み関数ｗａ（ｗ１１、ｗ１２、ｗ１３、ｗ１４、ｗ２１、ｗ２２、ｗ２３、ｗ２４）を掛けて中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６に入力され、その結果にさらに重み関数ｗｂ（ｗ３１、ｗ３２、ｗ４１、ｗ４２、ｗ５１、ｗ５２、ｗ６１、ｗ６２）を掛けて出力層Ｎ７、Ｎ８から出力される。出力層Ｎ７、Ｎ８から出力される電圧振幅Ｖｏ、電圧位相Φｏは重み関数ｗａ、ｗｂの値によって変わる。重み関数ｗａは入力層Ｎ１、Ｎ２から中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６に入力される際の重み関数の総称であり、重み関数ｗｂは中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６から出力層Ｎ７、Ｎ８に入力される際の重み関数の総称である。重み関数ｗａは、入力層Ｎ１、Ｎ２と中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６との組合せに応じて、ｗ１１、ｗ１２、ｗ１３、ｗ１４、ｗ２１、ｗ２２、ｗ２３、ｗ２４のいずれかになる。重み関数ｗｂは、中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６と出力層Ｎ７、Ｎ８との組合せに応じて、ｗ３１、ｗ３２、ｗ４１、ｗ４２、ｗ５１、ｗ５２、ｗ６１、ｗ６２のいずれかになる。 For example, the search circuit 28 has a three-layer neural network as shown in FIG. When voltage amplitude V2 and voltage phase Φ2 are input to input layers N1 and N2, respectively, voltage amplitude V2 and voltage phase Φ2 are multiplied by weighting function wa (w11, w12, w13, w14, w21, w22, w23, w24). are input to the intermediate layers N3, N4, N5 and N6, and the results are multiplied by the weighting function wb (w31, w32, w41, w42, w51, w52, w61, w62) and output from the output layers N7 and N8. . The voltage amplitude Vo and voltage phase Φo output from the output layers N7 and N8 change depending on the weighting functions wa and wb. The weighting function wa is a general term for weighting functions when input from the input layers N1 and N2 to the intermediate layers N3, N4, N5 and N6, and the weighting function wb is the weighting function from the intermediate layers N3, N4, N5 and N6 to the output layer N7, It is a general term for the weighting function when input to N8. The weighting function wa is one of w11, w12, w13, w14, w21, w22, w23 and w24 depending on the combination of the input layers N1 and N2 and the intermediate layers N3, N4, N5 and N6. The weighting function wb is one of w31, w32, w41, w42, w51, w52, w61 and w62 depending on the combination of the intermediate layers N3, N4, N5 and N6 and the output layers N7 and N8.
　入力層Ｎ１から中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６への重み関数ｗａは、それぞれｗ１１、ｗ１２、ｗ１３、ｗ１４である。入力層Ｎ２から中間層Ｎ３、Ｎ４、Ｎ５、Ｎ６への重み関数ｗａは、それぞれｗ２１、ｗ２２、ｗ２３、ｗ２４である。中間層Ｎ３から出力層Ｎ７、Ｎ８への重み関数ｗｂは、それぞれｗ３１、ｗ３２である。中間層Ｎ４から出力層Ｎ７、Ｎ８への重み関数ｗｂは、それぞれｗ４１、ｗ４２である。中間層Ｎ５から出力層Ｎ７、Ｎ８への重み関数ｗｂは、それぞれｗ５１、ｗ５２である。中間層Ｎ６から出力層Ｎ７、Ｎ８への重み関数ｗｂは、それぞれｗ６１、ｗ６２である。 The weighting functions wa from the input layer N1 to the intermediate layers N3, N4, N5 and N6 are w11, w12, w13 and w14, respectively. Weighting functions wa from the input layer N2 to the intermediate layers N3, N4, N5 and N6 are w21, w22, w23 and w24, respectively. Weighting functions wb from the intermediate layer N3 to the output layers N7 and N8 are w31 and w32, respectively. Weighting functions wb from the intermediate layer N4 to the output layers N7 and N8 are w41 and w42, respectively. Weighting functions wb from the intermediate layer N5 to the output layers N7 and N8 are w51 and w52, respectively. Weighting functions wb from the intermediate layer N6 to the output layers N7 and N8 are w61 and w62, respectively.
　探索回路２８は、データ取得部１１１によって取得される入力データｄａｔａ１、出力データｄａｔａ２の組合せに基づいて作成される学習用データに従って、いわゆる教師あり学習により、電圧振幅Ｖｏ、電圧位相Φｏを学習する。すなわち、探索回路２８は、入力層Ｎ１、Ｎ２に電圧振幅Ｖ２、電圧位相Φ２を入力して出力層Ｎ７、Ｎ８から出力された結果が、出力データｄａｔａ２の電圧振幅Ｖｏｓ、電圧位相Φｏｓに近づくように重みｗａとｗｂを調整することで学習する。モデル生成部１１２は、以上のような学習を実行することで学習済モデルを生成し、モデル記憶装置１１３に出力する。 The search circuit 28 learns the voltage amplitude Vo and the voltage phase Φo by so-called supervised learning according to the learning data created based on the combination of the input data data1 and the output data data2 acquired by the data acquisition unit 111. That is, the search circuit 28 inputs the voltage amplitude V2 and the voltage phase Φ2 to the input layers N1 and N2, and outputs the results from the output layers N7 and N8 so that they approach the voltage amplitude Vos and the voltage phase Φos of the output data data2. is learned by adjusting the weights wa and wb. The model generating unit 112 generates a trained model by executing the learning as described above, and outputs the trained model to the model storage device 113 .
　重み関数ｗａ、ｗｂの値の最適化は、例えば予め定められた調整回数による出力電圧Ｖｓの変更により、入力である電圧振幅Ｖ２及び出力である電圧振幅Ｖｏが最小化するような入力データｄａｔａ１、出力データｄａｔａ２を用いて繰り返し学習を行う。図１７、図１８では合計２０回の出力電圧Ｖｓの生成でコモンモード電圧Ｖｃｍを低減する例を示した。探索回路２８を備えたコモンモードフィルタ回路１は、山登り法による最適化方法よりも少ない出力電圧Ｖｓの調整回数、例えば１０回以下の出力電圧Ｖｓの調整回数でも、コモンモード電圧Ｖｃｍを低減することができる。 The optimization of the values of the weighting functions wa and wb is performed by changing the output voltage Vs by, for example, a predetermined number of adjustments, so that the input voltage amplitude V2 and the output voltage amplitude Vo are minimized. Repeated learning is performed using the output data data2. 17 and 18 show an example of reducing the common mode voltage Vcm by generating the output voltage Vs a total of 20 times. The common mode filter circuit 1 provided with the search circuit 28 can reduce the common mode voltage Vcm even if the number of adjustments of the output voltage Vs is less than that of the hill-climbing optimization method, for example, the number of adjustments of the output voltage Vs is 10 or less. can be done.
　探索回路２８は、学習装置１１０のモデル生成部１１２が生成した学習済モデルが組込まれている。例えば、探索回路２８は、デジタル回路３２に実装されるので、学習済モデルはデジタル回路３２に組込まれている。デジタル回路３２は、例えばマイクロコンピュータ、ＤＳＰ、ＦＰＧＡ等により機能が実現されている。 The search circuit 28 incorporates a trained model generated by the model generation unit 112 of the learning device 110 . For example, search circuit 28 is implemented in digital circuit 32 so that the trained model is embedded in digital circuit 32 . The function of the digital circuit 32 is implemented by, for example, a microcomputer, DSP, FPGA, or the like.
　探索回路２８を備えたコモンモードフィルタ回路１すなわちデジタル回路３２の第二例を備えたコモンモードフィルタ回路１は、デジタル回路３２の第一例を備えたコモンモードフィルタ回路１と同様に出力電圧Ｖｓの変化量に制限をかけた出力電圧Ｖｓを生成することができる。 The common mode filter circuit 1 with the search circuit 28, i.e. the common mode filter circuit 1 with the second example of the digital circuit 32, like the common mode filter circuit 1 with the first example of the digital circuit 32, has an output voltage Vs It is possible to generate an output voltage Vs in which the amount of change in is limited.
　なお、実施の形態１では、モデル生成部１１２が用いる学習アルゴリズムに教師あり学習を適用した場合について説明したが、これに限られるものではない。学習アルゴリズムについては、教師あり学習以外にも、強化学習、教師なし学習、又は半教師あり学習等を適用することも可能である。 In addition, in Embodiment 1, the case where supervised learning is applied to the learning algorithm used by the model generating unit 112 has been described, but the present invention is not limited to this. In addition to supervised learning, it is also possible to apply reinforcement learning, unsupervised learning, semi-supervised learning, and the like as learning algorithms.
　また、学習用データを収集するコモンモードフィルタ回路１が搭載される装置は、１つに限定されない。補償対象３が第一の電動機である場合の学習用データと補償対象３が仕様の異なる第二の電動機である場合の学習用データとを同時使用して学習してもよい。さらに、ある補償対象３のコモンモードフィルタ回路１に関して電圧振幅Ｖｏ、電圧位相Φｏを学習した学習装置１１０を、これとは別の補償対象３のコモンモードフィルタ回路１に適用し、当該別のコモンモードフィルタ回路１に関して電圧振幅Ｖｏ、電圧位相Φｏを再学習して更新するようにしてもよい。 Also, the number of devices equipped with the common mode filter circuit 1 that collects learning data is not limited to one. The learning data when the compensation target 3 is the first motor and the learning data when the compensation target 3 is the second motor with different specifications may be used simultaneously for learning. Furthermore, the learning device 110 that has learned the voltage amplitude Vo and the voltage phase Φo with respect to the common mode filter circuit 1 of a certain compensation target 3 is applied to the common mode filter circuit 1 of another compensation target 3, The voltage amplitude Vo and voltage phase Φo of the mode filter circuit 1 may be re-learned and updated.
　また、モデル生成部１１２に用いられる学習アルゴリズムとしては、特徴量そのものの抽出を学習する、深層学習（Deep　Learning）を用いることもでき、他の公知の方法、例えば遺伝的プログラミング、機能論理プログラミング、サポートベクターマシンなどに従って機械学習を実行してもよい。 In addition, as the learning algorithm used in the model generation unit 112, deep learning that learns to extract the feature amount itself can also be used, and other known methods such as genetic programming, functional logic programming, Machine learning may be performed according to support vector machines and the like.
　なお、デジタル回路３２の第一例における位相調整器３８、振幅調整器３９の機能は、図２２に示すプロセッサ１２０、メモリ１２１により機能が実現されてもよい。この場合、位相調整器３８、振幅調整器３９は、プロセッサ１２０がメモリ１２１に記憶されたプログラムを実行することにより、実現される。また、複数のプロセッサ１２０および複数のメモリ１２１が連携して位相調整器３８、振幅調整器３９の各機能を実行してもよい。 The functions of the phase adjuster 38 and the amplitude adjuster 39 in the first example of the digital circuit 32 may be implemented by the processor 120 and memory 121 shown in FIG. In this case, the phase adjuster 38 and the amplitude adjuster 39 are realized by executing a program stored in the memory 121 by the processor 120 . Also, the plurality of processors 120 and the plurality of memories 121 may work together to perform the functions of the phase adjuster 38 and the amplitude adjuster 39 .
　今まで、電力変換回路２、補償対象３、電力線４、電力線５は、三相三線式の例で説明しているが、実施の形態１のコモンモードフィルタ回路１は、それに限らず三相四線式、単相回路等にも適用できる。 So far, the power conversion circuit 2, the compensation object 3, the power lines 4, and the power lines 5 have been described as an example of a three-phase, three-wire system. It can also be applied to wire systems, single-phase circuits, and the like.
　電力変換回路２の例として三相フルブリッジ変換器で説明したが、これに限定されない。電力変換回路２は交直変換機能を有していれば、例えば３レベル変換器、その他の回路構成等をとっても良い。 Although the three-phase full-bridge converter has been described as an example of the power conversion circuit 2, it is not limited to this. As long as the power conversion circuit 2 has an AC/DC conversion function, it may be, for example, a three-level converter or other circuit configuration.
　電圧検出回路１１は、Ｙ接続するコンデンサ９ｕ、９ｖ、９ｗと分圧コンデンサ１０との分圧回路を用いてコモンモード電圧Ｖｃｍを検出する方式だけに限定されない。電圧検出回路１１は、コモンモードトランスを利用したコモンモード電流検出回路にも適用可能である。この場合、電力線４、５に接続された巻線が一次巻線として機能し、コモンモードトランスの励磁インダクタンスを介して二次巻線から得られる電流を終端抵抗で電圧変換し、コモンモード電流が電圧変換されて検出される。 The voltage detection circuit 11 is not limited to the method of detecting the common mode voltage Vcm using the voltage dividing circuit of the Y-connected capacitors 9u, 9v, 9w and the voltage dividing capacitor 10 . The voltage detection circuit 11 can also be applied to a common mode current detection circuit using a common mode transformer. In this case, the windings connected to the power lines 4 and 5 function as the primary windings, and the current obtained from the secondary windings via the excitation inductance of the common mode transformer is voltage-converted by the terminating resistor, and the common mode current is Detected after voltage conversion.
　帯域制限回路１２は、特定の周波数成分を通過させることができれば、すなわち特定の周波数成分を含む信号を抽出できれば、インダクタ、コンデンサ、抵抗、増幅回路を組み合わせたアナログ部品で構成されたアナログフィルタでもよく、デジタル部品で構成されたデジタルフィルタでもよい。帯域制限回路１２がデジタルフィルタの場合は、帯域制限回路１２の機能が、デジタル回路３２に組込まれてもよい。この場合、電圧検出信号ｓｉｇ１が制御回路１３に入力され、電圧検出信号ｓｉｇ１が制御回路１３のＡＤ変換器３１でＡＤ変換され、デジタル回路３２において帯域制限されたデジタル信号である帯域制限信号ｓｉｇ２が生成される。 The band-limiting circuit 12 may be an analog filter composed of analog parts combining inductors, capacitors, resistors, and amplifier circuits, as long as it can pass a specific frequency component, that is, if it can extract a signal containing a specific frequency component. , may be a digital filter composed of digital components. If band limiting circuit 12 is a digital filter, the function of band limiting circuit 12 may be incorporated into digital circuit 32 . In this case, the voltage detection signal sig1 is input to the control circuit 13, the voltage detection signal sig1 is AD-converted by the AD converter 31 of the control circuit 13, and the band-limited signal sig2, which is a digital signal band-limited in the digital circuit 32, is obtained. generated.
　制御回路１３の構成は、図３に示した構成に限定されない。制御回路１３は、帯域制限回路１２で得られる特定の周波数成分の帯域制限信号ｓｉｇ２から次回以降に検出される帯域制限信号ｓｉｇ２が減少するように補償信号ｓｉｇ３を生成する機能を有していればアナログ部品で構成してもよい。 The configuration of the control circuit 13 is not limited to the configuration shown in FIG. If the control circuit 13 has a function of generating a compensating signal sig3 so that the band-limited signal sig2 detected from the next time onward is reduced from the band-limited signal sig2 of the specific frequency component obtained by the band-limiting circuit 12. It may be composed of analog parts.
　制御回路１３に組み込む探索器４０ｂは、電圧振幅Ｖоを探索する際すなわち電圧振幅Ｖоを生成する際に、増幅回路１４の出力電圧の飽和を防止するためにリミッタを備えてもよい。 The searcher 40b incorporated in the control circuit 13 may include a limiter to prevent saturation of the output voltage of the amplifier circuit 14 when searching for the voltage amplitude V.sub.O, that is, when generating the voltage amplitude V.sub.O.
　増幅回路１４は、図４に示した構成に限定されない。増幅回路１４は、オペレーショナルアンプ４１を用いた反転増幅回路の他に、非反転増幅回路、トランジスタで構成されるプッシュプル回路等でもよい。増幅回路１４の入力端子４４ｓ、４４ｇに入力される補償信号ｓｉｇ３の電圧を増幅して、補償信号ｓｉｇ３に含まれる特定の周波数成分が減少するように出力端子４５ｓ、４５ｇから出力電圧Ｖｓを生成する機能を有していれば、図４に示した構成以外でもよい。 The amplifier circuit 14 is not limited to the configuration shown in FIG. The amplifier circuit 14 may be an inverting amplifier circuit using the operational amplifier 41, a non-inverting amplifier circuit, a push-pull circuit composed of transistors, or the like. The voltage of the compensation signal sig3 input to the input terminals 44s and 44g of the amplifier circuit 14 is amplified to generate the output voltage Vs from the output terminals 45s and 45g so that the specific frequency component included in the compensation signal sig3 is reduced. Any configuration other than that shown in FIG. 4 may be used as long as it has the function.
　コモンモードフィルタ回路１は、帯域制限回路１２の出力端子を増幅回路１４の入力端子４４ｓ、４４ｇに接続し、入力された信号を演算増幅することでコモンモード電圧Ｖｃｍ又はコモンモード電流が基準値以下を維持できれば、制御回路１３を搭載しなくてもよい。 The common mode filter circuit 1 connects the output terminal of the band limiting circuit 12 to the input terminals 44s and 44g of the amplifier circuit 14, and operationally amplifies the input signal so that the common mode voltage Vcm or the common mode current is equal to or lower than the reference value. can be maintained, the control circuit 13 need not be mounted.
　インピーダンス調整器１８のコンデンサ１５は、負荷回路６０の負荷インピーダンスＺｔの共振周波数ｆｒ４が帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈ間に設定できる容量値に調整できれば、単一で構成しても、複数のコンデンサを直列もしくは並列接続して所望の容量値を得てもよい。 The capacitor 15 of the impedance adjuster 18 can be configured as a single capacitor if the resonance frequency fr4 of the load impedance Zt of the load circuit 60 can be adjusted to a capacitance value that can be set between the two cutoff frequencies fl and fh of the band limiting circuit 12. Alternatively, a plurality of capacitors may be connected in series or in parallel to obtain the desired capacitance value.
　以上のように、実施の形態１のコモンモードフィルタ回路１は、半導体素子のスイッチング動作により電力変換を行う電力変換回路２が電力線４、５に発生させるコモンモード電圧Ｖｃｍを低減するコモンモードフィルタ回路である。コモンモードフィルタ回路１は、電力線４、５に生じたコモンモード電圧Ｖｃｍを検出してコモンモード電圧Ｖｃｍの情報を含む電圧検出信号ｓｉｇ１を出力する電圧検出回路１１と、電圧検出回路１１により出力された電圧検出信号ｓｉｇ１における特定の周波数成分を通過させる帯域制限回路１２と、電力線４、５に接続された二次巻線７と一次巻線８とを有し、電力線４、５にコモンモード電圧Ｖｃｍを低減する注入電圧Ｖａｐを重畳するコモンモードトランス１６と、帯域制限回路１２により出力された周波数成分９２ａ、９２ｂを含む帯域制限信号ｓｉｇ２に基づく信号（演算出力信号ｓｉｇ３ｄ）の電圧振幅Ｖｏを許容値（閾値Ｖｔｈ２）以下に低減する出力電圧Ｖｓを生成すると共に、出力電圧Ｖｓをコモンモードトランス１６の一次巻線８に出力する出力電圧生成回路６６と、コモンモードトランス１６の一次巻線８に並列に接続されると共に、出力電圧生成回路６６の出力端子４５ｓ、４５ｇ間に接続されているコモンモードトランス１６を含む負荷回路６０の負荷インピーダンスＺｔを調整するインピーダンス調整器１８と、を備えている。インピーダンス調整器１８のインピーダンス（調整器インピーダンスＺｓｔ）は、当該インピーダンス（調整器インピーダンスＺｓｔ）を含む出力電圧生成回路６６の出力端子４５ｓ、４５ｇ間に接続された負荷インピーダンスＺｔが最大となる周波数（共振周波数ｆｒ４）が、帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に設定されている。実施の形態１のコモンモードフィルタ回路１は、この構成により、コモンモードトランス１６の一次巻線８に並列にされたインピーダンス調整器１８を備え、負荷インピーダンスＺｔが最大となる周波数（共振周波数ｆｒ４）が帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に含まれるようにインピーダンス調整器１８のインピーダンス（調整器インピーダンスＺｓｔ）が調整されているので、低周波成分のコモンモード電圧Ｖｃｍの場合でも、出力電圧生成回路６６から出力される出力電流Ｉｓの大幅な増加を防止することができる。 As described above, the common mode filter circuit 1 of the first embodiment reduces the common mode voltage Vcm generated in the power lines 4 and 5 by the power conversion circuit 2 that converts power by switching operation of semiconductor elements. is. The common mode filter circuit 1 includes a voltage detection circuit 11 that detects a common mode voltage Vcm generated in the power lines 4 and 5 and outputs a voltage detection signal sig1 containing information on the common mode voltage Vcm, and a voltage detection signal sig1 that is output by the voltage detection circuit 11. a band-limiting circuit 12 for passing a specific frequency component in the voltage detection signal sig1, and a secondary winding 7 and a primary winding 8 connected to the power lines 4 and 5, respectively. The voltage amplitude Vo of the signal (calculation output signal sig3d) based on the band-limited signal sig2 containing the frequency components 92a and 92b output by the common mode transformer 16 that superimposes the injection voltage Vap that reduces Vcm and the band-limiting circuit 12 is allowed. An output voltage generating circuit 66 that generates an output voltage Vs that is reduced to a value (threshold value Vth2) or less and outputs the output voltage Vs to the primary winding 8 of the common mode transformer 16, and the primary winding 8 of the common mode transformer 16: and an impedance adjuster 18 that adjusts the load impedance Zt of the load circuit 60 that includes the common mode transformer 16 that is connected in parallel and connected between the output terminals 45s and 45g of the output voltage generation circuit 66. . The impedance (adjuster impedance Zst) of the impedance adjuster 18 is set at the frequency (resonance The frequency fr4) is set within the range of the two cutoff frequencies fl and fh of the band limiting circuit 12 . The common mode filter circuit 1 of Embodiment 1, with this configuration, includes the impedance adjuster 18 connected in parallel to the primary winding 8 of the common mode transformer 16. is within the range of the two cutoff frequencies fl and fh of the band-limiting circuit 12, the impedance of the impedance adjuster 18 (adjuster impedance Zst) is adjusted so that the common mode voltage Vcm of the low frequency component is Even in this case, a significant increase in the output current Is output from the output voltage generation circuit 66 can be prevented.
実施の形態２．
　図２４は実施の形態２に係るコモンモードフィルタ回路の構成を示す図であり、図２５は図２４の帯域制限回路群の構成を示す図である。図２６は図２４の制御回路の構成を示す図であり、図２７は図２４の可変コンデンサの構成を示す図である。図２８は、図２４の帯域制限回路群のゲイン特性及びコモンモード電圧の周波数成分の第一例を示す図である。図２９は、図２４の帯域制限回路群のゲイン特性及びコモンモード電圧の周波数成分の第二例を示す図である。図３０は、実施の形態２に係るコモンモードフィルタ回路の動作を説明するフローチャートである。 Embodiment 2.
24 is a diagram showing the configuration of a common mode filter circuit according to the second embodiment, and FIG. 25 is a diagram showing the configuration of the band limiting circuit group of FIG. 26 is a diagram showing the configuration of the control circuit in FIG. 24, and FIG. 27 is a diagram showing the configuration of the variable capacitor in FIG. FIG. 28 is a diagram showing a first example of the gain characteristics of the band limiting circuit group of FIG. 24 and the frequency components of the common mode voltage. FIG. 29 is a diagram showing a second example of the gain characteristics of the band limiting circuit group of FIG. 24 and the frequency components of the common mode voltage. 30 is a flowchart for explaining the operation of the common mode filter circuit according to the second embodiment; FIG.
　実施の形態１のコモンモードフィルタ回路１は、電力変換回路２のキャリア周波数に応じた帯域制限回路１２のカットオフ周波数ｆｌ、ｆｈが設定されている。このため、キャリア周波数を切り換える電力変換回路２を搭載した装置への適用を考慮した場合には、キャリア周波数の変化に応じてコモンモード電圧Ｖｃｍの周波数特性が変化する。異なるキャリア周波数によって発生するコモンモード電圧Ｖｃｍを低減するためには、コモンモードフィルタ回路１は、通過帯域における中心周波数の異なる帯域制限回路１２を複数備えることが望ましい。実施の形態２のコモンモードフィルタ回路１は、電力変換回路２の異なるキャリア周波数に対応した例である。 In the common mode filter circuit 1 of Embodiment 1, the cutoff frequencies fl and fh of the band limiting circuit 12 are set according to the carrier frequency of the power conversion circuit 2 . Therefore, when considering application to a device equipped with the power conversion circuit 2 that switches the carrier frequency, the frequency characteristic of the common mode voltage Vcm changes according to the change of the carrier frequency. In order to reduce the common mode voltage Vcm generated by different carrier frequencies, the common mode filter circuit 1 preferably has a plurality of band limiting circuits 12 with different center frequencies in the passband. The common mode filter circuit 1 according to the second embodiment is an example corresponding to different carrier frequencies of the power conversion circuit 2 .
　実施の形態２のコモンモードフィルタ回路１は、実施の形態１のコモンモードフィルタ回路１とは、帯域制限回路１２、制御回路１３、コンデンサ１５が、複数の帯域制限回路１２ａ、１２ｂ、１２ｎを備えた帯域制限回路群２０、制御回路３０ａ、可変コンデンサ５９に代わっている点で異なる。実施の形態１のコモンモードフィルタ回路１と異なる部分を主に説明する。実施の形態２のコモンモードフィルタ回路１は、インピーダンス調整器１８が可変コンデンサ５９の例であり、すなわちインピーダンス調整器１８が可変コンデンサ５９を備えている例である。出力電圧生成回路６６は、出力電圧Ｖｓを生成すると共に、インピーダンス調整器１８の容量値を設定する設定信号ｓｉｇ６を出力する。 The common mode filter circuit 1 of the second embodiment differs from the common mode filter circuit 1 of the first embodiment in that the band limiting circuit 12, the control circuit 13, and the capacitor 15 are provided with a plurality of band limiting circuits 12a, 12b, and 12n. The difference is that the band limiting circuit group 20, the control circuit 30a, and the variable capacitor 59 are replaced. The parts different from the common mode filter circuit 1 of the first embodiment will be mainly described. In the common mode filter circuit 1 of the second embodiment, the impedance adjuster 18 is an example of the variable capacitor 59 , that is, the impedance adjuster 18 is an example provided with the variable capacitor 59 . The output voltage generation circuit 66 generates an output voltage Vs and outputs a setting signal sig6 for setting the capacitance value of the impedance adjuster 18. FIG.
　図２８に複数の異なるキャリア周波数によって電力変換回路２が発生させるコモンモード電圧Ｖｃｍの周波数成分と、帯域制限回路群２０におけるゲインＧの周波数特性すなわち複数のゲイン特性との関係を示した。図２８には、ｎ個のキャリア周波数ｆ１ａ～ｆ１ｎの内、３つのキャリア周波数ｆ１ａ、ｆ１ｂ、ｆ１ｎに対応した周波数成分及びゲイン特性８８ａ、８８ｂ、８８ｎを示した。キャリア周波数ｆ１ａに関係するコモンモード電圧Ｖｃｍの周波数成分は、４つの周波数成分７１ａ、７２ａ、７３ａ、７４ａを示した。キャリア周波数ｆ１ａの周波数成分７１ａ、３次成分周波数ｆ３ａの周波数成分７２ａ、５次成分周波数ｆ５ａの周波数成分７３ａ、７次成分周波数ｆ７ａの周波数成分７４ａを図示している。ゲイン特性８８ａは、２つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１ａが入るように設定された帯域制限回路１２ａのゲイン特性である。 FIG. 28 shows the relationship between the frequency components of the common mode voltage Vcm generated by the power conversion circuit 2 with a plurality of different carrier frequencies and the frequency characteristics of the gain G in the band limiting circuit group 20, that is, a plurality of gain characteristics. FIG. 28 shows frequency components and gain characteristics 88a, 88b, 88n corresponding to three carrier frequencies f1a, f1b, f1n out of n carrier frequencies f1a to f1n. The frequency components of the common mode voltage Vcm related to the carrier frequency f1a showed four frequency components 71a, 72a, 73a, 74a. A frequency component 71a of carrier frequency f1a, a frequency component 72a of third-order component frequency f3a, a frequency component 73a of fifth-order component frequency f5a, and a frequency component 74a of seventh-order component frequency f7a are shown. A gain characteristic 88a is the gain characteristic of the band limiting circuit 12a set so that the carrier frequency f1a is between the two cutoff frequencies fl and fh.
　キャリア周波数ｆ１ｂに関係するコモンモード電圧Ｖｃｍの周波数成分は、４つの周波数成分７１ｂ、７２ｂ、７３ｂ、７４ｂを示した。キャリア周波数ｆ１ｂの周波数成分７１ｂ、３次成分周波数ｆ３ｂの周波数成分７２ｂ、５次成分周波数ｆ５ｂの周波数成分７３ｂ、７次成分周波数ｆ７ｂの周波数成分７４ｂを図示している。ゲイン特性８８ｂは、２つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１ｂが入るように設定された帯域制限回路１２ｂのゲイン特性である。キャリア周波数ｆ１ｎに関係するコモンモード電圧Ｖｃｍの周波数成分は、４つの周波数成分７１ｎ、７２ｎ、７３ｎ、７４ｎを示した。キャリア周波数ｆ１ｎの周波数成分７１ｎ、３次成分周波数ｆ３ｎの周波数成分７２ｎ、５次成分周波数ｆ５ｎの周波数成分７３ｎ、７次成分周波数ｆ７ｎの周波数成分７４ｎを図示している。ゲイン特性８８ｎは、２つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１ｎが入るように設定された帯域制限回路１２ｎのゲイン特性である。 The frequency components of the common mode voltage Vcm related to the carrier frequency f1b showed four frequency components 71b, 72b, 73b and 74b. A frequency component 71b of carrier frequency f1b, a frequency component 72b of third-order component frequency f3b, a frequency component 73b of fifth-order component frequency f5b, and a frequency component 74b of seventh-order component frequency f7b are shown. A gain characteristic 88b is a gain characteristic of the band limiting circuit 12b set so that the carrier frequency f1b is between the two cutoff frequencies fl and fh. The frequency components of the common mode voltage Vcm related to the carrier frequency f1n showed four frequency components 71n, 72n, 73n, 74n. A frequency component 71n of carrier frequency f1n, a frequency component 72n of third-order component frequency f3n, a frequency component 73n of fifth-order component frequency f5n, and a frequency component 74n of seventh-order component frequency f7n are shown. A gain characteristic 88n is a gain characteristic of the band limiting circuit 12n set so that the carrier frequency f1n is between the two cutoff frequencies fl and fh.
　帯域制限回路群２０に複数の帯域制限回路１２ａ～１２ｎが用意されており、電力変換回路２のキャリア周波数の変動に応じて、制御回路３０ａにおいて帯域制限回路１２ａ～１２ｎの出力値におけるいずれか１つを補償に用いるかが選択される。制御回路３０ａは、選択回路５２を備えており、複数の帯域制限回路１２ａ～１２ｎの出力値を比較し、最大となるものを選択する。帯域制限回路群２０から出力される複数の帯域制限信号ｓｉｇ５ａ～ｓｉｇ５ｎから選択された１つの帯域制限信号ｓｉｇｓｅに基づいて制御回路３０ａが補償信号ｓｉｇ３を生成する場合には、増幅回路１４が出力する出力電圧Ｖｓに含まれる周波数成分は選択された帯域制限信号ｓｉｇｓｅに応じて変化する。帯域制限回路群２０に複数の帯域制限回路１２ａ～１２ｎから選択された帯域制限回路の符号は、１２を用いる。したがって、選択された帯域制限信号ｓｉｇｓｅを通過させた帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈ間に負荷回路６０の共振周波数ｆｒ４が入るように可変コンデンサ５９の容量値を調整する機能を持たせることが望ましい。 A plurality of band limiting circuits 12a to 12n are provided in the band limiting circuit group 20, and the control circuit 30a selects one of the output values of the band limiting circuits 12a to 12n in accordance with fluctuations in the carrier frequency of the power conversion circuit 2. which one is used for compensation is selected. The control circuit 30a has a selection circuit 52 which compares the output values of the plurality of band limiting circuits 12a to 12n and selects the maximum one. When the control circuit 30a generates the compensation signal sig3 based on one band-limited signal sigse selected from the plurality of band-limited signals sig5a to sig5n output from the band-limited circuit group 20, the amplifier circuit 14 outputs The frequency components contained in the output voltage Vs change according to the selected band-limited signal sigse. 12 is used as the code for the band-limiting circuits selected from the plurality of band-limiting circuits 12a to 12n in the band-limiting circuit group 20. FIG. Therefore, the function of adjusting the capacitance value of the variable capacitor 59 so that the resonance frequency fr4 of the load circuit 60 falls between the two cutoff frequencies fl and fh of the band-limiting circuit 12 through which the selected band-limiting signal sigse is passed is provided. It is desirable to have
　可変コンデンサ５９は、コンデンサとスイッチとが直列に接続された直列体５５ａ、５５ｂ、５５ｃ、５５ｄを複数備えている。図２７では、４つの直列体５５ａ、５５ｂ、５５ｃ、５５ｄを備えた例を示した。可変コンデンサ５９は、入力端子６２ｓ及び出力端子６３ｓに接続された配線６４ａと、入力端子６２ｇ及び出力端子６３ｇに接続された配線６４ｂとの間に４つの直列体５５ａ、５５ｂ、５５ｃ、５５ｄが並列に接続されている。入力端子６２ｓ、６２ｇはそれぞれ増幅回路１４の出力端子４５ｓ、４５ｇに接続されており、出力端子６３ｓ、６３ｇは、それぞれコモンモードトランス１６の一次巻線８の一端及び他端に接続されている。直列体５５ａはコンデンサ１５ａとスイッチ５４ａとが直列に接続されており、直列体５５ｂはコンデンサ１５ｂとスイッチ５４ｂとが直列に接続されている。直列体５５ｃはコンデンサ１５ｃとスイッチ５４ｃとが直列に接続されており、直列体５５ｄはコンデンサ１５ｄとスイッチ５４ｄとが直列に接続されている。 The variable capacitor 59 includes a plurality of series bodies 55a, 55b, 55c, and 55d in which capacitors and switches are connected in series. FIG. 27 shows an example with four serial bodies 55a, 55b, 55c and 55d. The variable capacitor 59 has four series bodies 55a, 55b, 55c, and 55d arranged in parallel between a wiring 64a connected to an input terminal 62s and an output terminal 63s and a wiring 64b connected to an input terminal 62g and an output terminal 63g. It is connected to the. The input terminals 62s and 62g are connected to the output terminals 45s and 45g of the amplifier circuit 14, respectively, and the output terminals 63s and 63g are connected to one end and the other end of the primary winding 8 of the common mode transformer 16, respectively. The series body 55a has the capacitor 15a and the switch 54a connected in series, and the series body 55b has the capacitor 15b and the switch 54b connected in series. The series body 55c has the capacitor 15c and the switch 54c connected in series, and the series body 55d has the capacitor 15d and the switch 54d connected in series.
　スイッチ５４ａは、入力端子６７ａから入力される設定信号ｓｉｇ６ａによりオン及びオフが制御される。スイッチ５４ｂ、５４ｃ、５４ｄも同様に、それぞれ設定信号ｓｉｇ６ｂ、ｓｉｇ６ｃ、ｓｉｇ６ｄによりオン及びオフが制御される。スイッチ５４ｂは、入力端子６７ｂから入力される設定信号ｓｉｇ６ｂによりオン及びオフが制御される。スイッチ５４ｃは、入力端子６７ｃから入力される設定信号ｓｉｇ６ｃによりオン及びオフが制御される。スイッチ５４ｄは、入力端子６７ｄから入力される設定信号ｓｉｇ６ｄによりオン及びオフが制御される。設定信号の符号は、総括的にｓｉｇ６を用い、区別する場合にｓｉｇ６ａ、ｓｉｇ６ｂ、ｓｉｇ６ｃ、ｓｉｇ６ｄを用いる。スイッチ５４ａ、５４ｂ、５４ｃ、５４ｄをオンすれば、各直列体５５ａ、５５ｂ、５５ｃ、５５ｄはコンデンサ１５ａ、１５ｂ、１５ｃ、１５ｄとして動作する。スイッチ５４ａ、５４ｂ、５４ｃ、５４ｄをオフすれば、各直列体５５ａ、５５ｂ、５５ｃ、５５ｄすなわちコンデンサ１５ａ、１５ｂ、１５ｃ、１５ｄは開放状態（非接続状態）になり、可変コンデンサ５９の容量値を低下させることができる。コンデンサ１５ａ、１５ｂ、１５ｃ、１５ｄの並列接続数を増加させれば可変コンデンサ５９の容量値を増大でき、コンデンサ１５ａ、１５ｂ、１５ｃ、１５ｄの並列接続数を減少させれば可変コンデンサ５９の容量値を低下させることができる。 The switch 54a is controlled to be on and off by a setting signal sig6a input from the input terminal 67a. Switches 54b, 54c, and 54d are similarly controlled to be on and off by setting signals sig6b, sig6c, and sig6d, respectively. The switch 54b is controlled to be on and off by a setting signal sig6b input from the input terminal 67b. The switch 54c is controlled to be turned on and off by a setting signal sig6c input from the input terminal 67c. The switch 54d is controlled to be turned on and off by a setting signal sig6d input from the input terminal 67d. As the code of the setting signal, sig6 is used in general, and sig6a, sig6b, sig6c, and sig6d are used when they are distinguished. When the switches 54a, 54b, 54c and 54d are turned on, the series bodies 55a, 55b, 55c and 55d operate as capacitors 15a, 15b, 15c and 15d. When the switches 54a, 54b, 54c, and 54d are turned off, the series bodies 55a, 55b, 55c, and 55d, that is, the capacitors 15a, 15b, 15c, and 15d are opened (disconnected), and the capacitance of the variable capacitor 59 is changed to can be lowered. The capacitance value of the variable capacitor 59 can be increased by increasing the number of parallel connections of the capacitors 15a, 15b, 15c, and 15d, and the capacitance value of the variable capacitor 59 can be increased by decreasing the number of parallel connections of the capacitors 15a, 15b, 15c, and 15d. can be reduced.
　帯域制限回路群２０は複数の帯域制限回路１２ａ～１２ｎを備えている。図２５では、ｎ個の帯域制限回路の内、３つの帯域制限回路１２ａ、１２ｂ、１２ｎを示した。帯域制限回路１２ａは、電圧検出回路１１により出力された電圧検出信号ｓｉｇ１におけるゲイン特性８８ａに応じた特定の周波数成分を通過させ、帯域制限信号ｓｉｇ５ａを出力する。帯域制限信号ｓｉｇ５ａは、帯域制限回路１２ａのゲイン特性８８ａに応じた周波数成分を含んでいる。帯域制限回路１２ｂは、電圧検出回路１１により出力された電圧検出信号ｓｉｇ１におけるゲイン特性８８ｂに応じた特定の周波数成分を通過させ、帯域制限信号ｓｉｇ５ｂを出力する。帯域制限回路１２ｎは、電圧検出回路１１により出力された電圧検出信号ｓｉｇ１におけるゲイン特性８８ｎに応じた特定の周波数成分を通過させ、帯域制限信号ｓｉｇ５ｎを出力する。帯域制限信号ｓｉｇ５ｂは帯域制限回路１２ｂのゲイン特性８８ｂに応じた周波数成分を含んでおり、帯域制限信号ｓｉｇ５ｎは帯域制限回路１２ｎのゲイン特性８８ｎに応じた周波数成分を含んでいる。帯域制限回路群２０が出力する帯域制限信号の符号は、総括的にｓｉｇ５を用い、区別する場合にｓｉｇ５ａ、ｓｉｇ５ｂ、ｓｉｇ５ｎを用いる。 The band limiting circuit group 20 includes a plurality of band limiting circuits 12a-12n. FIG. 25 shows three band limiting circuits 12a, 12b, and 12n out of n band limiting circuits. Band-limiting circuit 12a passes a specific frequency component according to gain characteristic 88a in voltage detection signal sig1 output from voltage detection circuit 11, and outputs band-limiting signal sig5a. Band-limited signal sig5a includes a frequency component corresponding to gain characteristic 88a of band-limited circuit 12a. Band-limiting circuit 12b passes a specific frequency component according to gain characteristic 88b in voltage detection signal sig1 output from voltage detection circuit 11, and outputs band-limiting signal sig5b. The band-limiting circuit 12n passes a specific frequency component according to the gain characteristic 88n in the voltage detection signal sig1 output from the voltage detection circuit 11, and outputs a band-limiting signal sig5n. Band-limited signal sig5b contains a frequency component corresponding to gain characteristic 88b of band-limiting circuit 12b, and band-limited signal sig5n contains a frequency component corresponding to gain characteristic 88n of band-limiting circuit 12n. As the sign of the band-limited signal output by the band-limited circuit group 20, sig5 is generally used, and sig5a, sig5b, and sig5n are used for distinction.
　制御回路３０ａは、図３に示した制御回路１３とは、ＡＤ変換器３１の入力側に選択回路５２が追加され、可変コンデンサ５９の容量値を設定する設定信号ｓｉｇ６を出力する設定信号生成回路５３が追加されている点で異なる。制御回路１３と異なる部分を主に説明する。選択回路５２は複数の入力端子３４ｓａ～３４ｓｎと入力端子３４ｇを備えている。選択回路５２は、入力端子３４ｓａ、３４ｇから帯域制限回路群２０の帯域制限信号ｓｉｇ５ａを取り込み、入力端子３４ｓｂ、３４ｇから帯域制限回路群２０の帯域制限信号ｓｉｇ５ｂを取り込む。選択回路５２は、入力端子３４ｓｎ、３４ｇから帯域制限回路群２０の帯域制限信号ｓｉｇ５ｎを取り込む。図２６では、ｎ個の入力端子３４ｓａ～３４ｓｎの内、３つの入力端子３４ｓａ、３４ｓｂ、３４ｓｎを示し、それぞれに入力される３つの帯域制限信号ｓｉｇ５ａ、ｓｉｇ５ｂ、ｓｉｇ５ｎを示した。選択回路５２は、複数の帯域制限回路１２ａ～１２ｎから出力された複数の帯域制限信号ｓｉｇ５の出力値を比較し、最大となるものを選択して帯域制限信号ｓｉｇｓｅとして出力する。また、選択回路５２は、どの帯域制限信号ｓｉｇ５ａ～ｓｉｇ５ｎを選択したかを示す選択情報信号ｓｓｉｇを出力する。ＡＤ変換器３１は、アナログの帯域制限信号ｓｉｇｓｅをデジタルの演算入力信号ｓｉｇ２ｄに変換する。 The control circuit 30a is different from the control circuit 13 shown in FIG. 53 is added. A part different from the control circuit 13 will be mainly described. The selection circuit 52 has a plurality of input terminals 34sa to 34sn and an input terminal 34g. The selection circuit 52 takes in the band-limited signal sig5a of the band-limited circuit group 20 from the input terminals 34sa and 34g, and takes in the band-limited signal sig5b of the band-limited circuit group 20 from the input terminals 34sb and 34g. The selection circuit 52 takes in the band-limiting signal sig5n of the band-limiting circuit group 20 from the input terminals 34sn and 34g. FIG. 26 shows three input terminals 34sa, 34sb, and 34sn out of n input terminals 34sa to 34sn, and three band-limited signals sig5a, sig5b, and sig5n input thereto. The selection circuit 52 compares the output values of the plurality of band-limited signals sig5 output from the plurality of band-limited circuits 12a to 12n, selects the maximum one, and outputs it as the band-limited signal sigse. Also, the selection circuit 52 outputs a selection information signal ssig indicating which of the band-limited signals sig5a to sig5n has been selected. The AD converter 31 converts the analog band-limited signal sigse into a digital operation input signal sig2d.
　設定信号生成回路５３は、帯域制限回路群２０の各帯域制限回路１２ａ～１２ｎのカットオフ周波数ｆｌ、ｆｈに対応して、可変コンデンサ５９のスイッチ５４ａ～５４ｄのオン又はオフにする設定信号ｓｉｇ６ａ～ｓｉｇ６ａの状態を設定する。設定信号生成回路５３は、選択された帯域制限信号ｓｉｇｓｅに対応した帯域制限回路１２のカットオフ周波数ｆｌ、ｆｈの間に、出力電圧生成回路６６の出力端子４５ｓ、４５ｇ間に接続された負荷回路６０の負荷インピーダンスＺｔが最大となる周波数が含まれるように、予め設定されている設定信号ｓｉｇ６ａ～ｓｉｇ６ａの状態すなわち電位レベルの組を出力する。例えば、設定信号ｓｉｇ６ａ～ｓｉｇ６ａの電位レベルが高電位の場合にスイッチ５４ａ～５４ｄがオンし、設定信号ｓｉｇ６ａ～ｓｉｇ６ａの電位レベルが低電位の場合にスイッチ５４ａ～５４ｄがオフする。 The setting signal generation circuit 53 generates setting signals sig6a to sig6a to turn off the switches 54a to 54d of the variable capacitor 59 corresponding to the cutoff frequencies fl and fh of the band limiting circuits 12a to 12n of the band limiting circuit group 20. Set the state of sig6a. The setting signal generating circuit 53 is connected between the cutoff frequencies fl and fh of the band limiting circuit 12 corresponding to the selected band limiting signal sigse, and the load circuit connected between the output terminals 45s and 45g of the output voltage generating circuit 66. A preset set of states, ie, potential levels, of the setting signals sig6a to sig6a is output so that the frequency at which the load impedance Zt of 60 is maximized is included. For example, when the potential levels of the setting signals sig6a to sig6a are high, the switches 54a to 54d are turned on, and when the potential levels of the setting signals sig6a to sig6a are low, the switches 54a to 54d are turned off.
　実施の形態２のインピーダンス調整器１８の調整器インピーダンスＺｓｔは、実施の形態１と同様に調整される。実施の形態２のインピーダンス調整器１８の調整器インピーダンスＺｓｔは、負荷回路６０の負荷インピーダンスＺｔが最大となる周波数すなわち共振周波数ｆｒ４が、選択された帯域制限信号ｓｉｇｓｅを出力した帯域制限回路群２０の帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に含まれるように調整されている。また、実施の形態２のインピーダンス調整器１８の調整器インピーダンスＺｓｔは、選択された帯域制限信号ｓｉｇｓｅを出力した帯域制限回路群２０の帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に、負荷回路６０の負荷インピーダンスＺｔが最大となる周波数すなわち共振周波数ｆｒ４が含まれるように調整されている、と表現してもよい。選択された帯域制限信号ｓｉｇｓｅを出力した帯域制限回路群２０の帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に、負荷回路６０の負荷インピーダンスＺｔが最大となる周波数すなわち共振周波数ｆｒ４が含まれることは、インピーダンス条件が満たされていることである。実施の形態２では、インピーダンス調整器１８が可変コンデンサ５９の例なので、インピーダンス調整器１８である可変コンデンサ５９の容量値Ｃは、インピーダンス条件を満たすように調整されている。 The adjuster impedance Zst of the impedance adjuster 18 of the second embodiment is adjusted in the same manner as in the first embodiment. The adjuster impedance Zst of the impedance adjuster 18 of the second embodiment is the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonant frequency fr4 of the band-limiting circuit group 20 that outputs the selected band-limiting signal sigse. It is adjusted to fall within the two cutoff frequencies fl and fh of the band limiting circuit 12 . Further, the adjuster impedance Zst of the impedance adjuster 18 of the second embodiment is within the range of the two cutoff frequencies fl and fh of the band-limiting circuit 12 of the band-limiting circuit group 20 that outputs the selected band-limiting signal sigse. is adjusted to include the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonance frequency fr4. The frequency at which the load impedance Zt of the load circuit 60 maximizes, i.e., the resonant frequency fr4 is included means that the impedance condition is satisfied. In Embodiment 2, since the impedance adjuster 18 is an example of the variable capacitor 59, the capacitance value C of the variable capacitor 59, which is the impedance adjuster 18, is adjusted so as to satisfy the impedance condition.
　実施の形態２のコモンモードフィルタ回路１は、選択された帯域制限信号ｓｉｇｓｅを出力した帯域制限回路群２０の帯域制限回路１２のゲイン特性に対応して、制御回路３０が可変コンデンサ５９の容量値Ｃをインピーダンス条件が満足するように設定することができる。その結果として、実施の形態２のコモンモードフィルタ回路１は、電力変換回路２のキャリア周波数が変更されても出力電圧生成回路６６の増幅回路１４から出力される出力電圧Ｖｓの周波数成分はインピーダンス条件を満たしているので、この出力電圧Ｖｓによって負荷回路６０の負荷インピーダンスＺｔが高くなり、出力電圧生成回路６６から出力される出力電流の増加を防ぐことができる。 In the common mode filter circuit 1 of the second embodiment, the control circuit 30 adjusts the capacitance value of the variable capacitor 59 according to the gain characteristic of the band limiting circuit 12 of the band limiting circuit group 20 that outputs the selected band limiting signal sigse. C can be set such that the impedance condition is satisfied. As a result, in the common mode filter circuit 1 of the second embodiment, even if the carrier frequency of the power conversion circuit 2 is changed, the frequency component of the output voltage Vs output from the amplifier circuit 14 of the output voltage generation circuit 66 is kept under the impedance condition is satisfied, the load impedance Zt of the load circuit 60 is increased by the output voltage Vs, and an increase in the output current output from the output voltage generating circuit 66 can be prevented.
　図３０を用いて、実施の形態２のコモンモードフィルタ回路１の動作を説明する。図３０に示したフローチャートは、図１２に示したフローチャートにけるステップＳ０５に前にステップＳ４１が追加されている点で異なる。図１２に示したフローチャートと異なる部分を主に説明する。ステップＳ４１において、制御回路３０ａは帯域制限回路群２０の複数の帯域制限回路１２ａ～１２ｎがそれぞれ出力する帯域制限信号ｓｉｇ５の出力値が最大となる一つの帯域制限回路１２を選択し、この帯域制限回路１２の特性に合わせて負荷回路６０の共振周波数ｆｒ４が設定されるように、すなわちインピーダンス条件を満たすように可変コンデンサ５９の容量値を設定する（調整器インピーダンス設定工程）。ステップＳ４１の調整器インピーダンス設定工程の後に、ステップＳ０５を実行する。実施の形態２のコモンモードフィルタ回路１は、電力変換回路２のキャリア周波数が変更されても、出力電圧生成回路６６から出力される出力電流の増加を防ぐことができる。 The operation of the common mode filter circuit 1 of the second embodiment will be described using FIG. The flowchart shown in FIG. 30 differs from the flowchart shown in FIG. 12 in that step S41 is added before step S05. Differences from the flowchart shown in FIG. 12 will be mainly described. In step S41, the control circuit 30a selects one band-limiting circuit 12 that maximizes the output value of the band-limiting signal sig5 output by each of the plurality of band-limiting circuits 12a to 12n of the band-limiting circuit group 20. The capacitance value of the variable capacitor 59 is set so that the resonance frequency fr4 of the load circuit 60 is set according to the characteristics of the circuit 12, that is, so as to satisfy the impedance condition (adjuster impedance setting step). Step S05 is performed after the adjuster impedance setting process of step S41. The common mode filter circuit 1 of Embodiment 2 can prevent an increase in the output current output from the output voltage generation circuit 66 even if the carrier frequency of the power conversion circuit 2 is changed.
　図３０に示したフローチャートは、実施の形態１のコモンモードフィルタ回路１の第一例の動作を説明するフローチャートに対応した例である。これは、実施の形態２の制御回路３０ａにおけるデジタル回路３２が図１１に示した第一例の場合である。実施の形態２の制御回路３０ａにおけるデジタル回路３２は、図１９に示した第二例の場合でもよい。この場合のフローチャートは、図２１に示したフローチャートにけるステップＳ１０に前にステップＳ４１が追加されたフローチャートになる。 The flowchart shown in FIG. 30 is an example corresponding to the flowchart for explaining the operation of the first example of the common mode filter circuit 1 of the first embodiment. This is the first example in which the digital circuit 32 in the control circuit 30a of the second embodiment is shown in FIG. The digital circuit 32 in the control circuit 30a of the second embodiment may be the second example shown in FIG. The flowchart in this case is a flowchart in which step S41 is added before step S10 in the flowchart shown in FIG.
　図２８では、帯域制限回路群２０のｎ個の帯域制限回路１２ａ～１２ｎのゲイン特性８８ａ～８８ｎは、それぞれ二つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１ａ～ｆ１ｎが含まれるように設定されている例を示した。帯域制限回路群２０のｎ個の帯域制限回路１２ａ～１２ｎのゲイン特性８８ａ～８８ｎは、図２９に示すように、それぞれ二つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１ａ～ｆ１ｎの整数倍の周波数が含まれるように設定されていてもよい。図２９では、二つのカットオフ周波数ｆｌ、ｆｈ間にキャリア周波数ｆ１ａ～ｆ１ｎの整数倍の周波数ｆ３ａ～ｆ３ｎが含まれるように設定されている例を示した。図２９のように設定した場合でも、負荷インピーダンスＺｔは、共振周波数ｆｒ４で最大値になる。なお、周波数成分７２ａ～７２ｎの方が周波数成分７１ａ～７１ｎよりも大きい場合には、図２９のように設定することを想定しているが、特定の周波数成分を優先的に除去したい場合にはこの限りではない。 In FIG. 28, the gain characteristics 88a-88n of the n band-limiting circuits 12a-12n of the band-limiting circuit group 20 are set so that the carrier frequencies f1a-f1n are included between the two cut-off frequencies fl and fh. An example is shown. As shown in FIG. 29, the gain characteristics 88a-88n of the n band-limiting circuits 12a-12n of the band-limiting circuit group 20 are, as shown in FIG. It may be set so that the frequency is included. FIG. 29 shows an example in which frequencies f3a to f3n, which are integral multiples of carrier frequencies f1a to f1n, are included between two cutoff frequencies fl and fh. Even when set as shown in FIG. 29, the load impedance Zt reaches its maximum value at the resonance frequency fr4. In addition, when the frequency components 72a to 72n are larger than the frequency components 71a to 71n, it is assumed to be set as shown in FIG. This is not the case.
　可変コンデンサ５９は、容量値が所望の値に設定できれば、コンデンサ１５ａ～１５ｄは容量値が同一でも異なってもよい。また各直列体５５ａ～５５ｄにおいて複数のコンデンサを備えていてもよい。すなわち、各コンデンサ１５ａ～１５ｄは、複数のコンデンサが直列接続又は及び直列接続されていてもよい。また、各コンデンサ１５ａ～１５ｄが可変容量コンデンサ（バリアブルコンデンサ）であってもよい。各スイッチ５４ａ～５４ｄは、双方向の遮断及び導通する機能を持っていればよく、例えば機械スイッチ、半導体スイッチ等である。 As long as the variable capacitor 59 can be set to a desired value, the capacitors 15a to 15d may have the same or different capacitance values. Also, each of the series bodies 55a to 55d may have a plurality of capacitors. That is, each of the capacitors 15a to 15d may be a series connection or a series connection of a plurality of capacitors. Also, each of the capacitors 15a to 15d may be a variable capacitor. Each of the switches 54a to 54d may be a mechanical switch, a semiconductor switch, or the like, as long as it has a bidirectional cut-off and conduction function.
実施の形態３．
　図３１は実施の形態３に係るコモンモードフィルタ回路の構成を示す図であり、図３２は図３１のＬＣ調整器の構成を示す図である。図３３は図３１の制御回路の構成を示す図であり、図３４は図３１の増幅回路の出力端子間に接続された負荷回路の等価回路を示す図である。図３５は実施の形態３に係るコモンモードフィルタ回路の動作を説明するフローチャートであり、図３６は図３５の共振周波数調整工程を説明するフローチャートである。 Embodiment 3.
31 is a diagram showing the configuration of a common mode filter circuit according to Embodiment 3, and FIG. 32 is a diagram showing the configuration of the LC regulator of FIG. 33 is a diagram showing the configuration of the control circuit of FIG. 31, and FIG. 34 is a diagram showing an equivalent circuit of the load circuit connected between the output terminals of the amplifier circuit of FIG. 35 is a flow chart for explaining the operation of the common mode filter circuit according to the third embodiment, and FIG. 36 is a flow chart for explaining the resonance frequency adjustment process of FIG.
　実施の形態３のコモンモードフィルタ回路１は、出力電圧生成回路６６の出力端子４５ｓ、４５ｇ間に接続される負荷回路６０の負荷インピーダンスＺｔが最大になる共振周波数ｆｒ４と、出力電圧生成回路６６から出力される出力電圧Ｖｓの周波数ｆｓとのずれを調整する機能を備えた例である。複数の周波数成分を有するコモンモード電圧Ｖｃｍから特定の一つの周波数成分のみを通過させるすなわち抽出する帯域制限回路１２を用いれば、実施の形態１及び実施の形態２のコモンモードフィルタ回路１は、抽出されたコモンモード電圧Ｖｃｍの周波数成分における周波数を有する出力電圧Ｖｓを出力電圧生成回路６６から負荷回路６０に出力している。実施の形態１及び実施の形態２のコモンモードフィルタ回路１は、負荷回路６０の励磁インピーダンスＺｌ及びコモンモードインピーダンスＺが予め想定できる場合に、前述したインピーダンス条件を満たすようにインピーダンス調整器１８の容量値Ｃが調整されていた。満たすべきインピーダンス条件は、負荷回路６０の負荷インピーダンスＺｔが最大となる周波数すなわち共振周波数ｆｒ４が、帯域制限回路１２の二つのカットオフ周波数ｆｌ、ｆｈの範囲内に含まれることである。実施の形態１及び実施の形態２のコモンモードフィルタ回路１は、帯域制限回路１２により抽出された周波数を有する出力電圧Ｖｓに対して負荷回路６０の負荷インピーダンスＺｔが最大となるように調整されていた。つまり、実施の形態１及び実施の形態２のコモンモードフィルタ回路１は、負荷回路６０の励磁インピーダンスＺｌ及びコモンモードインピーダンスＺが予め想定されている場合に、出力電圧生成回路６６に接続された負荷回路６０の負荷インピーダンスＺｔが最大になる共振周波数ｆｒ４と、出力電圧生成回路６６から出力される出力電圧Ｖｓの周波数ｆｓとを、高精度で一致させること又は十分に近づけることができる。 The common mode filter circuit 1 of the third embodiment has a resonance frequency fr4 at which the load impedance Zt of the load circuit 60 connected between the output terminals 45s and 45g of the output voltage generation circuit 66 becomes maximum, and This is an example provided with a function of adjusting the difference between the output voltage Vs and the frequency fs. Using the band-limiting circuit 12 that allows only one specific frequency component to pass through from the common-mode voltage Vcm having a plurality of frequency components, that is, extracts it, the common-mode filter circuit 1 of Embodiments 1 and 2 extracts An output voltage Vs having a frequency corresponding to the frequency component of the common mode voltage Vcm is output from the output voltage generation circuit 66 to the load circuit 60 . In the common mode filter circuit 1 of the first and second embodiments, when the excitation impedance Zl and the common mode impedance Z of the load circuit 60 can be assumed in advance, the capacitance of the impedance adjuster 18 is adjusted so as to satisfy the impedance condition described above. Value C was adjusted. The impedance condition to be satisfied is that the frequency at which the load impedance Zt of the load circuit 60 is maximized, that is, the resonance frequency fr4 is included in the range of the two cutoff frequencies fl and fh of the band limiting circuit 12 . The common mode filter circuit 1 of the first and second embodiments is adjusted so that the load impedance Zt of the load circuit 60 is maximized with respect to the output voltage Vs having the frequency extracted by the band limiting circuit 12. rice field. That is, in the common mode filter circuit 1 of the first and second embodiments, when the excitation impedance Zl and the common mode impedance Z of the load circuit 60 are assumed in advance, the load connected to the output voltage generation circuit 66 The resonance frequency fr4 at which the load impedance Zt of the circuit 60 is maximized and the frequency fs of the output voltage Vs output from the output voltage generation circuit 66 can be matched with high precision or made sufficiently close.
　しかし、コモンモードトランス１６、インピーダンス調整器１８のコンデンサ１５等の製造ばらつきにより、励磁インピーダンスＺｌの励磁インダクタンス値Ｌｍ、インピーダンス調整器１８の容量値Ｃのばらつきが大きい場合には、負荷回路６０の共振点すなわち共振周波数ｆｒ４が所望の値から変化してしまうことが考えられる。このため、コモンモードフィルタ回路１は、負荷回路６０の共振点すなわち共振周波数ｆｒ４と出力電圧生成回路６６から出力される出力電圧Ｖｓの周波数ｆｓとのずれを調整する機能を備えることが望ましい。 However, if there are large variations in the exciting inductance value Lm of the exciting impedance Zl and the capacitance value C of the impedance adjuster 18 due to manufacturing variations in the common mode transformer 16, the capacitor 15 of the impedance adjuster 18, etc., resonance of the load circuit 60 will occur. It is conceivable that the point, that is, the resonance frequency fr4 may deviate from the desired value. Therefore, it is desirable that the common mode filter circuit 1 has a function of adjusting the resonance point of the load circuit 60, that is, the resonance frequency fr4 and the frequency fs of the output voltage Vs output from the output voltage generation circuit 66. FIG.
　図３１に示した実施の形態３のコモンモードフィルタ回路１は、実施の形態１のコモンモードフィルタ回路１とは、制御回路１３及びコンデンサ１５が制御回路３０ｂ及びＬＣ調整器６５に代わり、出力電圧生成回路６６の出力電流Ｉｓを検出する電流検出器１７及び帯域制限回路１９が追加されている点で異なる。実施の形態１のコモンモードフィルタ回路１と異なる部分を主に説明する。実施の形態３のコモンモードフィルタ回路１は、インピーダンス調整器１８がＬＣ調整器６５の例であり、すなわちインピーダンス調整器１８がコンデンサ１５、可変コンデンサ５７、可変インダクタ５８を備えている例である。出力電圧生成回路６６は、電流検出器１７により検出された出力電流Ｉｓの検出値に基づいて、インピーダンス調整器１８の容量値及びインダクタンス値を設定する設定信号ｓｉｇ６を出力する。 The common mode filter circuit 1 of the third embodiment shown in FIG. 31 differs from the common mode filter circuit 1 of the first embodiment in that the control circuit 13 and the capacitor 15 are replaced with the control circuit 30b and the LC regulator 65, and the output voltage It differs in that a current detector 17 for detecting the output current Is of the generating circuit 66 and a band limiting circuit 19 are added. The parts different from the common mode filter circuit 1 of the first embodiment will be mainly described. In the common mode filter circuit 1 of Embodiment 3, the impedance adjuster 18 is an example of the LC adjuster 65 , that is, an example in which the impedance adjuster 18 includes the capacitor 15 , the variable capacitor 57 and the variable inductor 58 . The output voltage generation circuit 66 outputs a setting signal sig6 for setting the capacitance value and the inductance value of the impedance adjuster 18 based on the detected value of the output current Is detected by the current detector 17 .
　電流検出器１７は、シャント抵抗と絶縁アンプを用いた方式の検出器、非接触の磁気方式の検出器等である。電流検出器１７は、出力電圧生成回路６６の出力電流Ｉｓを検出し、検出電流Ｉｄの情報を含む電流検出信号ｓｉｇ７を出力する。検出電流Ｉｄの情報は、電流振幅、位相Φｄを含んでいる。適宜、検出電流Ｉｄの電流振幅はＩｄのまま用いる。検出電流Ｉｄの位相Φｄは、出力電流Ｉｓの電流位相と同じである。帯域制限回路１９は、電流検出器１７により出力された電流検出信号ｓｉｇ７における特定の周波数成分を通過させ、帯域制限信号ｓｉｇ８を出力する。帯域制限信号ｓｉｇ８は、特定の周波数帯域の抽出電流Ｉｄｆの情報を含んでいる。抽出電流Ｉｄｆの情報は、電流振幅、位相Φｄを含んでいる。適宜、抽出電流Ｉｄｆの電流振幅はＩｄｆのまま用いる。抽出電流Ｉｄｆの電流振幅は、検出電流Ｉｄの電流振幅と同じである。抽出電流Ｉｄｆの位相は、検出電流Ｉｄと同じであり、抽出電流Ｉｄｆの位相の符号はΦｄを用いる。帯域制限信号ｓｉｇ８は制御回路３０ｂに入力される。制御回路３０ｂは、帯域制限信号ｓｉｇ８に基づいて、インピーダンス調整器１８であるＬＣ調整器６５の調整器インピーダンスＺｓｔを設定する設定信号ｓｉｇ６をＬＣ調整器６５に出力する。 The current detector 17 is a detector using a shunt resistor and an insulation amplifier, a non-contact magnetic detector, or the like. The current detector 17 detects the output current Is of the output voltage generation circuit 66 and outputs a current detection signal sig7 containing information on the detected current Id. Information on the detected current Id includes current amplitude and phase Φd. As appropriate, the current amplitude of the detection current Id is used as it is. The phase Φd of the detection current Id is the same as the current phase of the output current Is. Band-limiting circuit 19 passes a specific frequency component in current detection signal sig7 output from current detector 17, and outputs band-limiting signal sig8. The band-limited signal sig8 contains information on the extracted current Idf in a specific frequency band. Information on the extracted current Idf includes the current amplitude and phase Φd. As appropriate, the current amplitude of the extracted current Idf is used as it is. The current amplitude of the extraction current Idf is the same as the current amplitude of the detection current Id. The extracted current Idf has the same phase as the detected current Id, and Φd is used as the phase sign of the extracted current Idf. Band-limited signal sig8 is input to control circuit 30b. Control circuit 30b outputs setting signal sig6 for setting adjuster impedance Zst of LC adjuster 65, which is impedance adjuster 18, to LC adjuster 65 based on band-limiting signal sig8.
　ＬＣ調整器６５は、入力端子６２ｓ及び出力端子６３ｓに接続された配線６４ａと入力端子６２ｇ及び出力端子６３ｇに接続された配線６４ｂとの間に、並列接続されたコンデンサ１５、可変コンデンサ５７、可変インダクタ５８を備えている。可変コンデンサ５７は、コンデンサとスイッチとが直列に接続された直列体５５ａ、５５ｂを複数備えている。可変インダクタ５８は、インダクタとスイッチとが直列に接続された直列体８５ａ、８５ｂを複数備えている。図３２では、可変コンデンサ５７が２つの直列体５５ａ、５５ｂを備え、可変インダクタ５８が２つの直列体８５ａ、８５ｂを備えた例を示した。可変コンデンサ５７は、配線６４ａと配線６４ｂとの間に２つの直列体５５ａ、５５ｂ、が並列に接続されている。可変インダクタ５８は、配線６４ａと配線６４ｂとの間に２つの直列体８５ａ、８５ｂ、が並列に接続されている。入力端子６２ｓ、６２ｇはそれぞれ増幅回路１４の出力端子４５ｓ、４５ｇに接続されており、出力端子６３ｓ、６３ｇは、それぞれコモンモードトランス１６の一次巻線８の一端及び他端に接続されている。 The LC adjuster 65 includes a capacitor 15, a variable capacitor 57, a variable An inductor 58 is provided. The variable capacitor 57 includes a plurality of series bodies 55a and 55b in which capacitors and switches are connected in series. The variable inductor 58 includes a plurality of series bodies 85a and 85b in which inductors and switches are connected in series. FIG. 32 shows an example in which the variable capacitor 57 has two series bodies 55a and 55b and the variable inductor 58 has two series bodies 85a and 85b. The variable capacitor 57 has two series bodies 55a and 55b connected in parallel between the wiring 64a and the wiring 64b. The variable inductor 58 has two series bodies 85a and 85b connected in parallel between the wiring 64a and the wiring 64b. The input terminals 62s and 62g are connected to the output terminals 45s and 45g of the amplifier circuit 14, respectively, and the output terminals 63s and 63g are connected to one end and the other end of the primary winding 8 of the common mode transformer 16, respectively.
　直列体５５ａはコンデンサ８１ａとスイッチ５４ａとが直列に接続されており、直列体５５ｂはコンデンサ８１ｂとスイッチ５４ｂとが直列に接続されている。直列体８５ａはインダクタ８２ａとスイッチ８６ａとが直列に接続されており、直列体８５ｂはインダクタ８２ｂとスイッチ８６ｂとが直列に接続されている。 The series body 55a has a capacitor 81a and a switch 54a connected in series, and the series body 55b has a capacitor 81b and a switch 54b connected in series. The series body 85a has the inductor 82a and the switch 86a connected in series, and the series body 85b has the inductor 82b and the switch 86b connected in series.
　スイッチ５４ａは、入力端子６７ａから入力される設定信号ｓｉｇ６ａによりオン及びオフが制御される。スイッチ５４ｂ、８６ａ、８６ｂも同様に、それぞれ設定信号ｓｉｇ６ｂ、ｓｉｇ６ｃ、ｓｉｇ６ｄによりオン及びオフが制御される。スイッチ５４ｂは、入力端子６７ｂから入力される設定信号ｓｉｇ６ｂによりオン及びオフが制御される。スイッチ８６ａは、入力端子６７ｃから入力される設定信号ｓｉｇ６ｃによりオン及びオフが制御される。スイッチ８６ｂは、入力端子６７ｄから入力される設定信号ｓｉｇ６ｄによりオン及びオフが制御される。設定信号の符号は、総括的にｓｉｇ６を用い、区別する場合にｓｉｇ６ａ、ｓｉｇ６ｂ、ｓｉｇ６ｃ、ｓｉｇ６ｄを用いる。 The switch 54a is controlled to be on and off by a setting signal sig6a input from the input terminal 67a. Switches 54b, 86a, and 86b are similarly controlled to be on and off by setting signals sig6b, sig6c, and sig6d, respectively. The switch 54b is controlled to be on and off by a setting signal sig6b input from the input terminal 67b. The switch 86a is controlled to be on and off by a setting signal sig6c input from the input terminal 67c. The switch 86b is controlled to be on and off by a setting signal sig6d input from the input terminal 67d. As the code of the setting signal, sig6 is used in general, and sig6a, sig6b, sig6c, and sig6d are used when they are distinguished.
　スイッチ５４ａ、５４ｂをオンすれば、各直列体５５ａ、５５ｂはコンデンサ８１ａ、８１ｂとして動作する。スイッチ８６ａ、８６ｂをオンすれば、各直列体８５ａ、８５ｂはインダクタ８２ａ、８２ｂとして動作する。スイッチ５４ａ、５４ｂをオフすれば、各直列体５５ａ、５５ｂすなわちコンデンサ８１ａ、８１ｂは開放状態（非接続状態）になり、可変コンデンサ５７の容量値を低下させることができる。コンデンサ１５ａ、１５ｂの並列接続数を増加させれば可変コンデンサ５７の容量値を増大でき、コンデンサ１５ａ、１５ｂの並列接続数を減少させれば可変コンデンサ５７の容量値を低下させることができる。スイッチ８６ａ、８６ｂをオフすれば、各直列体８５ａ、８５ｂすなわちインダクタ８２ａ、８２ｂは開放状態（非接続状態）になり、可変インダクタ５８のインダクタンス値を低下させることができる。インダクタ８２ａ、８２ｂの並列接続数を増加させれば可変インダクタ５８のインダクタンス値を低下でき、インダクタ８２ａ、８２ｂの並列接続数を減少させれば可変インダクタ５８のインダクタンス値を増大させることができる。 When the switches 54a and 54b are turned on, the series bodies 55a and 55b operate as capacitors 81a and 81b. When the switches 86a, 86b are turned on, the series bodies 85a, 85b operate as inductors 82a, 82b. When the switches 54a and 54b are turned off, the series bodies 55a and 55b, that is, the capacitors 81a and 81b are brought into an open state (disconnected state), and the capacitance value of the variable capacitor 57 can be reduced. The capacitance value of the variable capacitor 57 can be increased by increasing the number of parallel connections of the capacitors 15a and 15b, and the capacitance value of the variable capacitor 57 can be decreased by decreasing the number of parallel connections of the capacitors 15a and 15b. When the switches 86a and 86b are turned off, the series bodies 85a and 85b, that is, the inductors 82a and 82b are brought into an open state (disconnected state), and the inductance value of the variable inductor 58 can be lowered. The inductance value of the variable inductor 58 can be decreased by increasing the number of parallel connections of the inductors 82a and 82b, and the inductance value of the variable inductor 58 can be increased by decreasing the number of parallel connections of the inductors 82a and 82b.
　図３４に、実施の形態３のコモンモードフィルタ回路１における、増幅回路１４の出力端子間の負荷回路６０の等価回路を示した。図５に示した実施の形態３のコモンモードフィルタ回路１における、増幅回路１４の出力端子間の負荷回路６０の等価回路では、インピーダンス調整器１８の調整器インピーダンスＺｓｔはコンデンサ１５のインピーダンスのみであった。しかし、実施の形態３のコモンモードフィルタ回路１のインピーダンス調整器１８は、コンデンサ１５、可変コンデンサ５７、可変インダクタ５８を備えている。このため、実施の形態３の負荷回路６０は、コンデンサ１５、可変コンデンサ５７、可変インダクタ５８、コモンモードトランス１６の励磁インダクタ、一巡経路６１の各インピーダンスが並列接続されたＬＣ並列共振回路になっている。コンデンサ１５、可変コンデンサ５７、可変インダクタ５８は、インピーダンス調整器１８の構成物であり、インピーダンス調整器１８の調整器インピーダンスＺｓｔは、容量値Ｃのコンデンサ１５、容量値Ｃｃｐの可変コンデンサ５７、インダクタンス値Ｌｃｐの可変インダクタ５８が並列接続されたインピーダンスである。図３４では、図５の等価回路に追加された可変コンデンサ５７及び可変インダクタ５８のコンデンサ電流Ｉｃａ及びインダクタ電流Ｉｌａも示した。 FIG. 34 shows an equivalent circuit of the load circuit 60 between the output terminals of the amplifier circuit 14 in the common mode filter circuit 1 of the third embodiment. In the equivalent circuit of the load circuit 60 between the output terminals of the amplifier circuit 14 in the common mode filter circuit 1 of the third embodiment shown in FIG. rice field. However, the impedance adjuster 18 of the common mode filter circuit 1 of the third embodiment includes the capacitor 15, the variable capacitor 57 and the variable inductor 58. FIG. Therefore, the load circuit 60 of the third embodiment is an LC parallel resonance circuit in which the impedances of the capacitor 15, the variable capacitor 57, the variable inductor 58, the excitation inductor of the common mode transformer 16, and the loop path 61 are connected in parallel. there is The capacitor 15, the variable capacitor 57, and the variable inductor 58 are components of the impedance adjuster 18, and the adjuster impedance Zst of the impedance adjuster 18 is composed of the capacitor 15 with a capacitance value C, the variable capacitor 57 with a capacitance value Ccp, and the inductance value It is an impedance in which the variable inductor 58 of Lcp is connected in parallel. FIG. 34 also shows capacitor current Ica and inductor current Ila of variable capacitor 57 and variable inductor 58 added to the equivalent circuit of FIG.
　インピーダンス調整器１８は、スイッチ５４ａ、５４ｂ及びスイッチ８６ａ、８６ｂのオン及びオフが制御されることで、可変コンデンサ５７の容量値Ｃｃｐ、可変インダクタ５８のインダクタンス値Ｌｃｐが調整される。インピーダンス調整器１８は、容量値Ｃのコンデンサ１５も備えているので、インピーダンス調整器１８の容量値はＣ＋Ｃｃｐになる。制御回路３０ｂは、設定信号ｓｉｇ６によりインピーダンス調整器１８の容量値及びインダクタンス値を調整して、負荷回路６０の負荷インピーダンスＺｔが特定の周波数を有する出力電圧Ｖｓに対して負荷回路６０の負荷インピーダンスＺｔが最大となるように調整する。インピーダンス調整器１８の容量値及びインダクタンス値が調整されるこことで、負荷回路６０の共振周波数ｆｒ４が調整される。したがって、制御回路３０ｂは、特定の周波数を有する出力電圧Ｖｓに対して負荷回路６０の負荷インピーダンスＺｔが最大となるように負荷回路６０の共振周波数ｆｒ４を調整する。 The impedance adjuster 18 adjusts the capacitance value Ccp of the variable capacitor 57 and the inductance value Lcp of the variable inductor 58 by controlling the on and off of the switches 54a, 54b and the switches 86a, 86b. Since the impedance adjuster 18 also includes a capacitor 15 with a capacitance value of C, the capacitance value of the impedance adjuster 18 is C+Ccp. The control circuit 30b adjusts the capacitance value and the inductance value of the impedance adjuster 18 by the setting signal sig6 so that the load impedance Zt of the load circuit 60 becomes equal to the output voltage Vs having a specific frequency. Adjust to maximize When the capacitance value and the inductance value of the impedance adjuster 18 are adjusted, the resonance frequency fr4 of the load circuit 60 is adjusted. Therefore, the control circuit 30b adjusts the resonance frequency fr4 of the load circuit 60 so that the load impedance Zt of the load circuit 60 becomes maximum with respect to the output voltage Vs having a specific frequency.
　帯域制限回路１２のゲイン特性で決定される特定の周波数帯域においてコモンモードインピーダンスＺが励磁インピーダンスＺｌに対し十分に大きい場合には、コモンモードインピーダンスＺが無視でき、可変コンデンサ５７の容量値Ｃｃｐ及び可変インダクタ５８のインダクタンス値Ｌｃｐは、励磁インピーダンスＺｌの励磁インダクタンス値Ｌｍ及びコンデンサ１５の容量値Ｃの誤差補正を目的としている。この場合、コモンモードトランス１６の励磁インダクタンス値Ｌｍ及びコンデンサ１５の容量値Ｃのばらつき２０％を調整する場合には、インダクタンス値Ｌｃｐは励磁インダクタンス値Ｌｍの５倍以上とすることが望ましく、容量値Ｃｃｐはコンデンサ１５の容量値Ｃの１／５以下とすることが望ましい。ただし、コモンモードインピーダンスＺの変動値が励磁インピーダンスＺｌに対して無視できない場合には、コモンモードインピーダンスＺの変動値も誤差要因となるため、励磁インダクタンス値Ｌｍ及びコンデンサ１５の容量値Ｃの誤差補正に限らず、コモンモードインピーダンスＺの変動値に対応するように、インダクタンス値Ｌｃｐ及び容量値Ｃｃｐを設定してもよい。 If the common mode impedance Z is sufficiently larger than the excitation impedance Zl in a specific frequency band determined by the gain characteristic of the band limiting circuit 12, the common mode impedance Z can be ignored, and the capacitance value Ccp of the variable capacitor 57 and the variable The inductance value Lcp of the inductor 58 is intended for error correction of the exciting inductance value Lm of the exciting impedance Zl and the capacitance value C of the capacitor 15 . In this case, when adjusting the variation of 20% in the exciting inductance value Lm of the common mode transformer 16 and the capacitance value C of the capacitor 15, the inductance value Lcp is preferably five times or more the exciting inductance value Lm. It is desirable that Ccp be 1/5 or less of the capacitance value C of the capacitor 15 . However, if the fluctuation value of the common mode impedance Z cannot be ignored with respect to the excitation impedance Zl, the fluctuation value of the common mode impedance Z also becomes an error factor. Alternatively, the inductance value Lcp and the capacitance value Ccp may be set so as to correspond to the fluctuation value of the common mode impedance Z.
　制御回路３０ａは、図３に示した制御回路１３とは、アナログの帯域制限信号ｓｉｇ８をデジタル信号の抽出信号ｓｉｇ８ｄに変換するＡＤ変換器３１ａと、ＬＣ調整器６５における可変コンデンサ５７の容量値Ｃｃｐ及び可変インダクタ５８のインダクタンス値Ｌｃｐを設定する設定信号ｓｉｇ６を出力する設定信号生成回路５６が追加されている点で異なる。制御回路１３と異なる部分を主に説明する。ＡＤ変換器３１ａは、入力端子３４ｓｓ、３４ｇから帯域制限回路１９の帯域制限信号ｓｉｇ８を取り込む。ＡＤ変換器３１ａはアナログの帯域制限信号ｓｉｇ８をデジタル信号の抽出信号ｓｉｇ８ｄに変換する。抽出信号ｓｉｇ８ｄは、特定の周波数帯域の抽出電流Ｉｄｆの情報、を含んでいる。 The control circuit 30a is different from the control circuit 13 shown in FIG. and a setting signal generation circuit 56 that outputs a setting signal sig6 for setting the inductance value Lcp of the variable inductor 58 is added. A part different from the control circuit 13 will be mainly described. The AD converter 31a takes in the band limited signal sig8 of the band limiting circuit 19 from the input terminals 34ss and 34g. The AD converter 31a converts the analog band-limited signal sig8 into a digital extracted signal sig8d. The extracted signal sig8d contains information on the extracted current Idf in a specific frequency band.
　設定信号生成回路５６は、抽出信号ｓｉｇ８ｄの抽出電流Ｉｄｆの情報である抽出電流の電流振幅Ｉｄｆ及び抽出電流Ｉｄｆの位相Φｄに基づいて、可変コンデンサ５７のスイッチ５４ａ、５４ｂ及び可変インダクタ５８のスイッチ８６ａ、８６ｂのオン又はオフにする設定信号ｓｉｇ６ａ～ｓｉｇ６ａの状態を設定する。可変コンデンサ５７の容量値Ｃｃｐ及び可変インダクタ５８のインダクタンス値Ｌｃｐを設定する工程は、負荷回路６０の共振周波数を調整する工程なので、設定信号生成回路５６は、共振周波数調整工程を実行する。共振周波数調整工程は、実施の形態１で説明した位相調整工程及び振幅調整工程より先に実行される。 The setting signal generation circuit 56 operates the switches 54a and 54b of the variable capacitor 57 and the switch 86a of the variable inductor 58 based on the current amplitude Idf of the extraction current and the phase Φd of the extraction current Idf, which are information on the extraction current Idf of the extraction signal sig8d. , 86b are turned on or off. Since the step of setting the capacitance value Ccp of the variable capacitor 57 and the inductance value Lcp of the variable inductor 58 is the step of adjusting the resonance frequency of the load circuit 60, the setting signal generation circuit 56 executes the resonance frequency adjustment step. The resonance frequency adjustment process is performed prior to the phase adjustment process and the amplitude adjustment process described in the first embodiment.
　設定信号生成回路５６は、共振周波数調整工程において、出力電圧Ｖｓの位相Φｓと抽出電流Ｉｄｆの位相Φｄとを比較し、位相Φｄが位相Φｓよりも遅れている場合に容量性の容量値Ｃｃｐを負荷回路６０に付加し、位相Φｄが位相Φｓよりも進んでいる場合に誘導性のインダクタンス値Ｌｃｐを負荷回路６０に付加する。共振周波数調整工程は、位相調整工程及び振幅調整工程より先に実行されるので、帯域制限信号ｓｉｇ２から演算された電圧位相Φ２及び電圧振幅Ｖ２を電圧位相Φо及び電圧振幅Ｖоとして生成し、電圧位相Φо及び電圧振幅Ｖоを有する補償信号ｓｉｇ３が出力される。負荷回路６０には補償信号ｓｉｇ３に基づいて、出力電圧Ｖｓを有する出力信号ｓｉｇ４が出力される。このため、出力電圧Ｖｓの位相Φｓは、デジタル回路３２が出力する電圧位相Φоを用いる。 The setting signal generation circuit 56 compares the phase Φs of the output voltage Vs and the phase Φd of the extracted current Idf in the resonance frequency adjustment step, and if the phase Φd lags behind the phase Φs, sets the capacitive capacitance value Ccp. Applied to the load circuit 60, an inductive inductance value Lcp is applied to the load circuit 60 when the phase Φd leads the phase Φs. Since the resonance frequency adjustment process is executed prior to the phase adjustment process and the amplitude adjustment process, the voltage phase Φ2 and the voltage amplitude V2 calculated from the band-limited signal sig2 are generated as the voltage phase Φо and the voltage amplitude Vо, and the voltage phase A compensation signal sig3 having Φ 0 and voltage amplitude V 0 is output. An output signal sig4 having an output voltage Vs is output to the load circuit 60 based on the compensation signal sig3. Therefore, the voltage phase Φо output by the digital circuit 32 is used as the phase Φs of the output voltage Vs.
　図３３に示したように、設定信号生成回路５６は、位相Φｄが電圧位相Φоよりも遅れている場合に可変コンデンサ５７のスイッチ５４ａ、５４ｂの少なくとも１つをオンにし、位相Φｄが電圧位相Φоよりも進んでいる場合に可変インダクタ５８のスイッチ８６ａ、８６ｂの少なくとも１つをオンにする。設定信号生成回路５６は、抽出電流の電流振幅Ｉｄｆが閾値Ｉｔｈ以下になるまで、もしくは抽出電流の電流振幅Ｉｄｆが最小になるまで、可変コンデンサ５７のスイッチ５４ａ、５４ｂ及び可変インダクタ５８のスイッチ８６ａ、８６ｂのオン又はオフにする設定信号ｓｉｇ６ａ～ｓｉｇ６ａの状態すなわち電位レベルの組を出力する。例えば、設定信号ｓｉｇ６ａ～ｓｉｇ６ａの電位レベルが高電位の場合にスイッチ５４ａ、５４ｂ、８６ａ、８６ｂがオンし、設定信号ｓｉｇ６ａ～ｓｉｇ６ａの電位レベルが低電位の場合にスイッチ５４ａ、５４ｂ、８６ａ、８６ｂがオフする。 As shown in FIG. 33, the setting signal generation circuit 56 turns on at least one of the switches 54a and 54b of the variable capacitor 57 when the phase Φd lags behind the voltage phase Φо so that the phase Φd becomes the voltage phase Φо. turns on at least one of the switches 86a, 86b of the variable inductor 58 if it is ahead. The setting signal generation circuit 56 keeps the switches 54a and 54b of the variable capacitor 57 and the switch 86a of the variable inductor 58 until the current amplitude Idf of the extracted current becomes equal to or less than the threshold value Ith or until the current amplitude Idf of the extracted current becomes minimum. It outputs a set of states of the setting signals sig6a to sig6a to turn on or off the 86b, that is, a set of potential levels. For example, when the potential levels of the setting signals sig6a to sig6a are high, the switches 54a, 54b, 86a, and 86b are turned on. turns off.
　実施の形態３のコモンモードフィルタ回路１は、出力電圧生成回路６６の増幅回路１４が出力する出力電圧Ｖｓの周波数ｆｓに対し、増幅回路１４の出力端子４５ｓ、４５ｇ間に接続された負荷回路６０の負荷インピーダンスＺｔが高くなるように負荷回路６０の共振点すなわち共振周波数ｆｒ４を変更できるので、前述したコモンモードトランス１６、コンデンサ１５等の製造ばらつきがあっても、出力電圧生成回路６６から出力される出力電流Ｉｓの大幅な増加を防止することがでる。 In the common mode filter circuit 1 of the third embodiment, the load circuit 60 connected between the output terminals 45s and 45g of the amplifier circuit 14 has a frequency fs of the output voltage Vs output from the amplifier circuit 14 of the output voltage generation circuit 66. The resonance point of the load circuit 60, that is, the resonance frequency fr4 can be changed so that the load impedance Zt of the load circuit 60 becomes high. Therefore, a large increase in the output current Is can be prevented.
　図３５を用いて、実施の形態３のコモンモードフィルタ回路１の動作を説明する。図３５に示したフローチャートは、図１２に示したフローチャートにけるステップＳ０５に前にステップＳ５１が追加されている点で異なる。図１２に示したフローチャートと異なる部分を主に説明する。ステップＳ５１において、制御回路３０ｂは共振周波数調整工程を実行して、この共振周波数調整工程にて可変コンデンサ５７の容量値Ｃｃｐ及び可変インダクタ５８のインダクタンス値Ｌｃｐを設定する。共振周波数調整工程は、図３６のステップＳ５２～ステップＳ５５の各ステップが実行される。ステップＳ５１の共振周波数調整工程の後に、ステップＳ０５を実行する。 The operation of the common mode filter circuit 1 of Embodiment 3 will be described using FIG. The flowchart shown in FIG. 35 differs from the flowchart shown in FIG. 12 in that step S51 is added before step S05. Differences from the flowchart shown in FIG. 12 will be mainly described. In step S51, the control circuit 30b executes a resonance frequency adjustment process to set the capacitance value Ccp of the variable capacitor 57 and the inductance value Lcp of the variable inductor 58 in this resonance frequency adjustment process. Steps S52 to S55 of FIG. 36 are executed in the resonance frequency adjustment process. Step S05 is performed after the resonance frequency adjustment process of step S51.
　前述したように、共振周波数調整工程は、位相調整工程及び振幅調整工程より先に実行され、容量値Ｃｃｐ及びインダクタンス値Ｌｃｐの設定は一度だけである。ステップＳ５２にて、制御回路３０ｂは補償信号ｓｉｇ３が出力中かを判定する。補償信号ｓｉｇ３が出力中でない場合はステップＳ５３に進み、補償信号ｓｉｇ３が出力中の場合は終了する。ステップＳ５３にて、制御回路３０ｂは、帯域制限信号ｓｉｇ２から演算された電圧位相Φ２及び電圧振幅Ｖ２を電圧位相Φо及び電圧振幅Ｖоとして生成し、電圧位相Φо及び電圧振幅Ｖоを有する補償信号ｓｉｇ３を出力する。増幅回路１４は、制御回路３０ｂにより出力された補償信号ｓｉｇ３に基づいて出力信号ｓｉｇ４を出力する。 As described above, the resonance frequency adjustment process is executed prior to the phase adjustment process and the amplitude adjustment process, and the capacitance value Ccp and the inductance value Lcp are set only once. At step S52, the control circuit 30b determines whether the compensation signal sig3 is being output. If the compensation signal sig3 is not being output, the process proceeds to step S53, and if the compensation signal sig3 is being output, the process ends. In step S53, the control circuit 30b generates the voltage phase Φ2 and the voltage amplitude V2 calculated from the band-limited signal sig2 as the voltage phase Φо and the voltage amplitude Vо, and generates the compensation signal sig3 having the voltage phase Φо and the voltage amplitude Vо. Output. The amplifier circuit 14 outputs an output signal sig4 based on the compensation signal sig3 output from the control circuit 30b.
　ステップＳ５３が実行されることで、負荷回路６０に出力電圧Ｖｓ、出力電流Ｉｓが印加される。ステップＳ５４にて、制御回路３０ｂは、電流検出器１７にて検出され、帯域制限された出力電流Ｉｓの情報である抽出電流Ｉｄｆの情報における抽出電流の電流振幅Ｉｄｆが閾値Ｉｔｈを超えているかを判定する。抽出電流の電流振幅Ｉｄｆが閾値Ｉｔｈを超えている場合はステップＳ５５に進み、抽出電流の電流振幅Ｉｄｆが閾値Ｉｔｈを超えていない場合すなわち抽出電流の電流振幅Ｉｄｆが閾値Ｉｔｈ以下の場合は終了する。ステップＳ５５にて、制御回路３０ｂは、抽出電流Ｉｄｆの情報における位相Φｄとデジタル回路３２が生成した電圧位相Φоとを比較する。電圧位相Φоと抽出電流Ｉｄｆの位相Φｄとを比較し、位相Φｄが電圧位相Φоよりも遅れている場合に容量値Ｃｃｐを増加させ、位相Φｄが電圧位相Φоよりも進んでいる場合にインダクタンス値Ｌｃｐを増加させて、容量値Ｃｃｐ及びインダクタンス値Ｌｃｐが設定される。 The output voltage Vs and the output current Is are applied to the load circuit 60 by executing step S53. In step S54, the control circuit 30b detects whether the current amplitude Idf of the extracted current in the information of the extracted current Idf, which is the information of the band-limited output current Is detected by the current detector 17, exceeds the threshold value Ith. judge. If the current amplitude Idf of the extracted current exceeds the threshold Ith, the process proceeds to step S55, and if the current amplitude Idf of the extracted current does not exceed the threshold Ith, that is, if the current amplitude Idf of the extracted current is equal to or less than the threshold Ith, the process ends. . In step S55, the control circuit 30b compares the phase Φd in the information of the extracted current Idf with the voltage phase Φо generated by the digital circuit 32. FIG. The voltage phase Φо and the phase Φd of the extracted current Idf are compared, and if the phase Φd lags behind the voltage phase Φо, the capacitance value Ccp is increased, and if the phase Φd leads the voltage phase Φо, the inductance value By increasing Lcp, the capacitance value Ccp and the inductance value Lcp are set.
　ステップＳ５５の後にステップＳ５４を実行する。ステップＳ５４にて、新たに電流検出器１７にて検出された出力電流Ｉｓの情報に基づく抽出電流Ｉｄｆの電流振幅Ｉｄｆを判定し、電流振幅Ｉｄｆが閾値Ｉｔｈを超えなくなるまで、すなわち電流振幅Ｉｄｆが閾値Ｉｔｈ以下になるまで、ステップＳ５４、ステップＳ５５を繰り返す。ステップＳ５１の共振周波数調整工程の後に、ステップＳ０５を実行する。なお、図３６におけるステップＳ５４では、抽出電流の電流振幅Ｉｄｆが閾値Ｉｔｈを超えているかを判定条件とした例を示したが、抽出電流の電流振幅Ｉｄｆが最小であるいかを判定条件にしてもよい。出力電圧生成回路６６は、帯域制限回路１９（第二帯域制限回路）により出力された信号すなわち帯域制限信号ｓｉｇ８の出力値が閾値Ｉｔｈ以下になるインピーダンス調整器１８の容量値及びインダクタンス値を決定し、又は帯域制限信号ｓｉｇ８の出力値が最小になるインピーダンス調整器１８の容量値及びインダクタンス値を決定し、当該容量値を設定する設定信号ｓｉｇ６を出力する。 Step S54 is executed after step S55. In step S54, the current amplitude Idf of the extracted current Idf is determined based on the information of the output current Is newly detected by the current detector 17 until the current amplitude Idf does not exceed the threshold value Ith, that is, the current amplitude Idf Steps S54 and S55 are repeated until the threshold value Ith or less is reached. Step S05 is performed after the resonance frequency adjustment process of step S51. In step S54 in FIG. 36, an example is shown in which whether or not the current amplitude Idf of the extracted current exceeds the threshold value Ith is used as the determination condition. good. The output voltage generation circuit 66 determines the capacitance value and the inductance value of the impedance adjuster 18 at which the output value of the signal output from the band limiting circuit 19 (second band limiting circuit), that is, the band limiting signal sig8 is equal to or lower than the threshold value Ith. Alternatively, it determines the capacitance value and inductance value of the impedance adjuster 18 that minimizes the output value of the band-limiting signal sig8, and outputs the setting signal sig6 that sets the capacitance value.
　図３５に示したフローチャートは、実施の形態１のコモンモードフィルタ回路１の第一例の動作を説明するフローチャートに対応した例である。これは、実施の形態３の制御回路３０ｂにおけるデジタル回路３２が図１１に示した第一例の場合である。実施の形態３の制御回路３０ｂにおけるデジタル回路３２は、図１９に示した第二例の場合でもよい。この場合のフローチャートは、図２１に示したフローチャートにけるステップＳ１０に前にステップＳ５１が追加されたフローチャートになる。 The flowchart shown in FIG. 35 is an example corresponding to the flowchart for explaining the operation of the first example of the common mode filter circuit 1 of the first embodiment. This is the first example in which the digital circuit 32 in the control circuit 30b of the third embodiment is shown in FIG. The digital circuit 32 in the control circuit 30b of the third embodiment may be the second example shown in FIG. The flowchart in this case is a flowchart in which step S51 is added before step S10 in the flowchart shown in FIG.
　各スイッチ５４ａ～５４ｄは、双方向の遮断及び導通する機能を持っていればよく、例えば機械スイッチ、半導体スイッチ等である。 Each of the switches 54a to 54d only needs to have a bidirectional cut-off and conduction function, and is, for example, a mechanical switch, a semiconductor switch, or the like.
　なお、本願は、様々な例示的な実施の形態及び実施例が記載されているが、１つ、又は複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、又は様々な組み合わせで実施の形態に適用可能である。従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合又は省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。 It should be noted that while this application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more of the embodiments may lie in particular embodiments. It is not limited to the application of , but can be applied to the embodiments singly or in various combinations. Accordingly, numerous variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, modification, addition or omission of at least one component, extraction of at least one component, and combination with components of other embodiments shall be included.
　１…コモンモードフィルタ回路、２…電力変換回路、４、４ｕ、４ｖ、４ｗ…電力線、５、５ｕ、５ｖ、５ｗ…電力線、７、７ｕ、７ｖ、７ｗ…二次巻線、８…一次巻線、１１…電圧検出回路、１２、１２ａ、１２ｂ、１２ｎ…帯域制限回路、１５、１５ａ、１５ｂ、１５ｃ、１５ｄ…コンデンサ、１６…コモンモードトランス、１７…電流検出器、１８…インピーダンス調整器、１９…帯域制限回路、３８…位相調整器、３９…振幅調整器、４５ｓ、４５ｇ…出力端子、５０…調整器、５７…可変コンデンサ、５８…可変インダクタ、５９…可変コンデンサ、６０…負荷回路、６６…出力電圧生成回路、７１ａ、７１ｂ、７１ｎ…周波数成分、７２ａ、７２ｂ、７２ｎ…周波数成分、７３ａ、７３ｂ、７３ｎ…周波数成分、７４ａ、７４ｂ、７４ｎ…周波数成分、９２ａ、９２ｂ、９２ｃ、９２ｄ…周波数成分、Ｃ…容量値、Ｃｃｐ…容量値、ｆ１、ｆ１ａ、ｆ１ｂ、ｆ１ｎ…キャリア周波数、ｆ３、ｆ３ａ、ｆ３ｂ、ｆ３ｎ…３次成分周波数、ｆ５、ｆ５ａ、ｆ５ｂ、ｆ５ｎ…５次成分周波数、ｆ７、ｆ７ａ、ｆ７ｂ、ｆ７ｎ…７次成分周波数、ｆｌｇ１…位相調整フラグ、ｆｌ…カットオフ周波数、ｆｈ…カットオフ周波数、ｆｒ４…共振周波数、Ｉｄｆ…抽出電流、Ｉｓ…出力電流、Ｉｔｈ…閾値、Ｌｃｐ…インダクタンス値、Ｌｍ…励磁インダクタンス値、ｓｉｇ１…電圧検出信号、ｓｉｇ２…帯域制限信号、ｓｉｇ３ｄ…演算出力信号、ｓｉｇ５、ｓｉｇ５ａ、ｓｉｇ５ｂ、ｓｉｇ５ｎ…帯域制限信号、ｓｉｇ６、ｓｉｇ６ａ、ｓｉｇ６ｂ、ｓｉｇ６ｃ、ｓｉｇ６ｄ…設定信号、ｓｉｇ８…帯域制限信号、Ｖ２…電圧振幅、Ｖｏ…電圧振幅、ΔＶ…小振幅、Φ２…電圧位相、Φｏ…電圧位相、Φｓ…出力電圧位相、ΔΦ…位相幅、Ｖａｐ…注入電圧、Ｖｃｍ…コモンモード電圧、Ｖｓ…出力電圧、Ｖｔｈ２…閾値（許容値）、Ｚ…コモンモードインピーダンス、Ｚｌ…励磁インピーダンス、Ｚｓｔ…調整器インピーダンス、Ｚｔ…負荷インピーダンス DESCRIPTION OF SYMBOLS 1... Common mode filter circuit 2... Power conversion circuit 4, 4u, 4v, 4w... Power line 5, 5u, 5v, 5w... Power line 7, 7u, 7v, 7w... Secondary winding 8... Primary winding Line 11 Voltage detection circuit 12, 12a, 12b, 12n Band limit circuit 15, 15a, 15b, 15c, 15d Capacitor 16 Common mode transformer 17 Current detector 18 Impedance adjuster 19 Band limiting circuit 38 Phase adjuster 39 Amplitude adjuster 45s, 45g Output terminal 50 Adjuster 57 Variable capacitor 58 Variable inductor 59 Variable capacitor 60 Load circuit 66 Output voltage generating circuit 71a, 71b, 71n Frequency components 72a, 72b, 72n Frequency components 73a, 73b, 73n Frequency components 74a, 74b, 74n Frequency components 92a, 92b, 92c, 92d ... frequency component C ... capacitance value Ccp ... capacitance value f1, f1a, f1b, f1n ... carrier frequency f3, f3a, f3b, f3n ... tertiary component frequency f5, f5a, f5b, f5n ... quintic component frequency , f7, f7a, f7b, f7n... seventh component frequency, flg1... phase adjustment flag, fl... cutoff frequency, fh... cutoff frequency, fr4... resonance frequency, Idf... extracted current, Is... output current, Ith... threshold , Lcp... inductance value, Lm... exciting inductance value, sig1... voltage detection signal, sig2... band limit signal, sig3d... calculation output signal, sig5, sig5a, sig5b, sig5n... band limit signal, sig6, sig6a, sig6b, sig6c, sig6d ... setting signal, sig8 ... band-limiting signal, V2 ... voltage amplitude, Vo ... voltage amplitude, ΔV ... small amplitude, Φ2 ... voltage phase, Φo ... voltage phase, Φs ... output voltage phase, ΔΦ ... phase width, Vap ... injection Voltage, Vcm... Common mode voltage, Vs... Output voltage, Vth2... Threshold value (permissible value), Z... Common mode impedance, Zl... Exciting impedance, Zst... Regulator impedance, Zt... Load impedance

Claims (12)

  1. 　半導体素子のスイッチング動作により電力変換を行う電力変換回路が電力線に発生させるコモンモード電圧を低減するコモンモードフィルタ回路であって、
    前記電力線に生じた前記コモンモード電圧を検出して前記コモンモード電圧の情報を含む電圧検出信号を出力する電圧検出回路と、
    前記電圧検出回路により出力された前記電圧検出信号における特定の周波数成分を通過させる帯域制限回路と、
    前記電力線に接続された二次巻線と一次巻線とを有し、前記電力線に前記コモンモード電圧を低減する注入電圧を重畳するコモンモードトランスと、
    前記帯域制限回路により出力された前記周波数成分を含む帯域制限信号に基づく信号の電圧振幅を許容値以下に低減する出力電圧を生成すると共に、前記出力電圧を前記コモンモードトランスの前記一次巻線に出力する出力電圧生成回路と、
    前記コモンモードトランスの前記一次巻線に並列に接続されると共に、前記出力電圧生成回路の出力端子間に接続されている前記コモンモードトランスを含む負荷回路の負荷インピーダンスを調整するインピーダンス調整器と、を備え、
    前記インピーダンス調整器のインピーダンスは、当該インピーダンスを含む前記出力電圧生成回路の出力端子間に接続された前記負荷インピーダンスが最大となる周波数が、前記帯域制限回路の二つのカットオフ周波数の範囲内に設定されている、
    コモンモードフィルタ回路。     A common mode filter circuit for reducing a common mode voltage generated in a power line by a power conversion circuit that converts power by switching operation of a semiconductor element,
    a voltage detection circuit that detects the common mode voltage generated on the power line and outputs a voltage detection signal containing information on the common mode voltage;
    a band-limiting circuit that passes a specific frequency component in the voltage detection signal output by the voltage detection circuit;
    a common mode transformer having a secondary winding and a primary winding connected to the power line and superimposing an injection voltage that reduces the common mode voltage on the power line;
    generating an output voltage that reduces a voltage amplitude of a signal based on the band-limited signal containing the frequency component output from the band-limiting circuit to a permissible value or less, and applying the output voltage to the primary winding of the common mode transformer; an output voltage generation circuit for output;
    an impedance adjuster that is connected in parallel to the primary winding of the common mode transformer and that adjusts the load impedance of a load circuit including the common mode transformer connected between output terminals of the output voltage generating circuit; with
    The impedance of the impedance adjuster is set such that the frequency at which the load impedance connected between the output terminals of the output voltage generating circuit including the impedance is maximized is within the range of two cutoff frequencies of the band limiting circuit. has been
    Common mode filter circuit.
  2. 　前記負荷インピーダンスは、前記インピーダンス調整器のインピーダンス、前記コモンモードトランスにおける前記一次巻線及び前記二次巻線の励磁インダクタンスによる励磁インピーダンス、前記コモンモードトランスにおける前記コモンモード電圧による前記二次巻線側のコモンモードインピーダンスが並列接続された合成インピーダンスであり、
    前記インピーダンス調整器のインピーダンスは、前記負荷インピーダンスの共振周波数が前記帯域制限回路の二つのカットオフ周波数の範囲内に設定されている、
    請求項１記載のコモンモードフィルタ回路。     The load impedance includes the impedance of the impedance adjuster, the excitation impedance due to the excitation inductances of the primary winding and the secondary winding in the common mode transformer, and the secondary winding side due to the common mode voltage in the common mode transformer. is the composite impedance in which the common mode impedances of are connected in parallel, and
    The impedance of the impedance adjuster is such that the resonance frequency of the load impedance is set within the range of two cutoff frequencies of the band-limiting circuit.
    2. The common mode filter circuit of claim 1.
  3. 　前記インピーダンス調整器はコンデンサを備えている、
    請求項１または２に記載のコモンモードフィルタ回路。     the impedance adjuster comprises a capacitor,
    3. The common mode filter circuit according to claim 1 or 2.
  4. 　前記出力電圧生成回路の出力電流を検出する電流検出器を備え、
    前記インピーダンス調整器は、前記出力電圧生成回路から出力される設定信号に基づいて、容量値が変更される可変コンデンサを備えており、
    前記出力電圧生成回路は、前記電流検出器により検出された前記出力電流に基づいて、前記インピーダンス調整器の容量値を設定する前記設定信号を出力する、
    請求項１または２に記載のコモンモードフィルタ回路。     A current detector that detects the output current of the output voltage generation circuit,
    The impedance adjuster includes a variable capacitor whose capacitance value is changed based on a setting signal output from the output voltage generation circuit,
    The output voltage generation circuit outputs the setting signal for setting the capacitance value of the impedance adjuster based on the output current detected by the current detector.
    3. The common mode filter circuit according to claim 1 or 2.
  5. 　前記出力電圧生成回路の出力電流を検出する電流検出器を備え、
    前記インピーダンス調整器は、前記出力電圧生成回路から出力される設定信号に基づいて、容量値が変更される可変コンデンサ及びインダクタンス値が変更される可変インダクタを備えており、
    前記出力電圧生成回路は、前記電流検出器により検出された前記出力電流に基づいて、前記インピーダンス調整器の容量値及びインダクタンス値を設定する前記設定信号を出力する、
    請求項１または２に記載のコモンモードフィルタ回路。     A current detector that detects the output current of the output voltage generation circuit,
    The impedance adjuster includes a variable capacitor whose capacitance value is changed and a variable inductor whose inductance value is changed based on a setting signal output from the output voltage generation circuit,
    The output voltage generation circuit outputs the setting signal for setting the capacitance value and the inductance value of the impedance adjuster based on the output current detected by the current detector.
    3. The common mode filter circuit according to claim 1 or 2.
  6. 　前記帯域制限回路を第一帯域制限回路とし、
    前記第一帯域制限回路と同一特性を有しており、前記出力電圧生成回路の前記出力電流における特定の周波数成分を通過させる第二帯域制限回路を備え、
    前記出力電圧生成回路は、前記第二帯域制限回路により出力された信号の出力値が閾値以下になる前記インピーダンス調整器の容量値を決定し、当該容量値を設定する前記設定信号を出力する、
    請求項４記載のコモンモードフィルタ回路。     The band limiting circuit is a first band limiting circuit,
    a second band-limiting circuit having the same characteristics as the first band-limiting circuit and passing a specific frequency component in the output current of the output voltage generating circuit;
    The output voltage generation circuit determines a capacitance value of the impedance adjuster at which the output value of the signal output by the second band limiting circuit is equal to or less than a threshold, and outputs the setting signal for setting the capacitance value.
    5. The common mode filter circuit according to claim 4.
  7. 　前記帯域制限回路を第一帯域制限回路とし、
    前記第一帯域制限回路と同一特性を有しており、前記出力電圧生成回路の前記出力電流における特定の周波数成分を通過させる第二帯域制限回路を備え、
    前記出力電圧生成回路は、前記第二帯域制限回路により出力された信号の出力値が閾値以下になる前記インピーダンス調整器の容量値及びインダクタンス値を決定し、当該容量値及び当該インダクタンス値を設定する前記設定信号を出力する、
    請求項５記載のコモンモードフィルタ回路。     The band limiting circuit is a first band limiting circuit,
    a second band-limiting circuit having the same characteristics as the first band-limiting circuit and passing a specific frequency component in the output current of the output voltage generating circuit;
    The output voltage generating circuit determines a capacitance value and an inductance value of the impedance adjuster at which the output value of the signal output by the second band limiting circuit is equal to or less than a threshold, and sets the capacitance value and the inductance value. outputting the setting signal;
    6. A common mode filter circuit according to claim 5.
  8. 　前記帯域制限回路と異なる通過周波数帯域を有し、互いに通過周波数帯域が異なる複数の他の帯域制限回路を備え、
    前記インピーダンス調整器は、前記出力電圧生成回路から出力される設定信号に基づいて容量値が変更される可変コンデンサを備えており、
    前記出力電圧生成回路は、
    前記帯域制限回路、複数の前記他の帯域制限回路から出力される複数の帯域制限信号から出力値が最大となる前記帯域制限信号に基づいて、
    前記出力電圧を生成すると共に、前記インピーダンス調整器の容量値を設定する前記設定信号を出力する、
    請求項１または２に記載のコモンモードフィルタ回路。     A plurality of other band limiting circuits having pass frequency bands different from the band limiting circuit and having pass frequency bands different from each other,
    The impedance adjuster includes a variable capacitor whose capacitance value is changed based on a setting signal output from the output voltage generation circuit,
    The output voltage generation circuit is
    Based on the band-limited signal having the maximum output value among a plurality of band-limited signals output from the band-limited circuit and the plurality of other band-limited circuits,
    generating the output voltage and outputting the setting signal for setting the capacitance value of the impedance adjuster;
    3. The common mode filter circuit according to claim 1 or 2.
  9. 　前記帯域制限回路は、前記電力変換回路のキャリア周波数または前記キャリア周波数の整数倍の周波数成分を含むように二つのカットオフ周波数の範囲が設定されている、
    請求項１から７のいずれか１項に記載のコモンモードフィルタ回路。     In the band limiting circuit, two cutoff frequency ranges are set so as to include frequency components of the carrier frequency of the power conversion circuit or integral multiples of the carrier frequency.
    A common mode filter circuit according to any one of claims 1 to 7.
  10. 　前記帯域制限回路、複数の前記他の帯域制限回路の少なくとも一つは、前記電力変換回路のキャリア周波数の周波数成分または前記キャリア周波数の整数倍の周波数成分を含むように二つのカットオフ周波数の範囲が設定されている、
    請求項８記載のコモンモードフィルタ回路。     At least one of the band-limiting circuit and the plurality of other band-limiting circuits has a range of two cutoff frequencies so as to include a frequency component of the carrier frequency of the power conversion circuit or a frequency component of an integral multiple of the carrier frequency. is set,
    9. A common mode filter circuit according to claim 8.
  11. 　前記出力電圧生成回路は、
    前記帯域制限回路により前記帯域制限信号が出力される度に、前記帯域制限信号に基づく信号の電圧位相が予め定められた位相判定条件を満たすまで前記出力電圧の位相を予め定められた位相幅ずつ調整する位相調整器と、
    前記位相調整器が位相調整の終了を示す位相調整フラグを出力している場合に、前記帯域制限回路により前記帯域制限信号が出力される度に、前記帯域制限信号に基づく信号の電圧振幅が予め定められた振幅判定条件を満たすまで前記出力電圧の振幅を予め定められた小振幅ずつ調整する振幅調整器と、を備えている、
    請求項１から１０のいずれか１項に記載のコモンモードフィルタ回路。     The output voltage generation circuit is
    Each time the band limiting circuit outputs the band limiting signal, the phase of the output voltage is changed by a predetermined phase width until the voltage phase of the signal based on the band limiting signal satisfies a predetermined phase determination condition. a phase adjuster to adjust;
    When the phase adjuster outputs a phase adjustment flag indicating the end of phase adjustment, each time the band limiting circuit outputs the band limiting signal, the voltage amplitude of the signal based on the band limiting signal is adjusted in advance. an amplitude adjuster that adjusts the amplitude of the output voltage by a predetermined small amplitude until a predetermined amplitude determination condition is satisfied;
    A common mode filter circuit according to any one of claims 1 to 10.
  12. 　前記出力電圧生成回路は、
    前記帯域制限回路により出力された前記帯域制限信号の電圧位相及び電圧振幅に基づいて前記出力電圧の位相及び振幅を調整する調整器を備えており、
    前記調整器は、
    前記帯域制限信号の電圧位相及び電圧振幅から前記出力電圧の位相及び振幅を制御する電圧位相の値及び電圧振幅の値を生成する学習済みモデルを構成する探索回路を備えており、
    前記探索回路は、
    前記帯域制限信号に基づく信号の電圧振幅が許容値以下に低減するまで、前記帯域制限信号の電圧位相及び電圧振幅を入力として前記帯域制限信号の電圧振幅が減少する前記出力電圧の位相及び振幅を制御する電圧位相の値及び電圧振幅の値を生成するように学習されており、
    前記帯域制限信号が出力される度に、前記帯域制限信号から前記探索回路により生成された電圧位相の値及び電圧振幅の値に基づいて、前記出力電圧の位相及び振幅を調整する、
    請求項１から１０のいずれか１項に記載のコモンモードフィルタ回路。     The output voltage generation circuit is
    an adjuster that adjusts the phase and amplitude of the output voltage based on the voltage phase and voltage amplitude of the band-limited signal output by the band-limiting circuit,
    The regulator is
    a search circuit forming a trained model that generates a voltage phase value and a voltage amplitude value for controlling the phase and amplitude of the output voltage from the voltage phase and voltage amplitude of the band-limited signal;
    The search circuit is
    The phase and amplitude of the output voltage at which the voltage amplitude of the band-limited signal decreases, using the voltage phase and voltage amplitude of the band-limited signal as input, until the voltage amplitude of the signal based on the band-limited signal is reduced to an allowable value or less. It is trained to generate a voltage phase value and a voltage amplitude value to control,
    each time the band-limited signal is output, adjusting the phase and amplitude of the output voltage based on the voltage phase value and the voltage amplitude value generated by the search circuit from the band-limited signal;
    A common mode filter circuit according to any one of claims 1 to 10.
PCT/JP2021/013316 2021-03-29 2021-03-29 Common mode filter circuit WO2022208616A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2023509929A JP7433516B2 (en) 2021-03-29 2021-03-29 common mode filter circuit
PCT/JP2021/013316 WO2022208616A1 (en) 2021-03-29 2021-03-29 Common mode filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/013316 WO2022208616A1 (en) 2021-03-29 2021-03-29 Common mode filter circuit

Publications (1)

Publication Number Publication Date
WO2022208616A1 true WO2022208616A1 (en) 2022-10-06

Family

ID=83455770

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/013316 WO2022208616A1 (en) 2021-03-29 2021-03-29 Common mode filter circuit

Country Status (2)

Country Link
JP (1) JP7433516B2 (en)
WO (1) WO2022208616A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2863833B2 (en) * 1996-09-18 1999-03-03 岡山大学長 Active common mode canceller
JP2004222250A (en) * 2002-12-13 2004-08-05 Stmicroelectronics Sa Frequency selective balun (balanced-unbalanced) transformer
JP2010057268A (en) * 2008-08-28 2010-03-11 Fuji Electric Systems Co Ltd Conductive noise filter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2863833B2 (en) * 1996-09-18 1999-03-03 岡山大学長 Active common mode canceller
JP2004222250A (en) * 2002-12-13 2004-08-05 Stmicroelectronics Sa Frequency selective balun (balanced-unbalanced) transformer
JP2010057268A (en) * 2008-08-28 2010-03-11 Fuji Electric Systems Co Ltd Conductive noise filter

Also Published As

Publication number Publication date
JPWO2022208616A1 (en) 2022-10-06
JP7433516B2 (en) 2024-02-19

Similar Documents

Publication Publication Date Title
US8222885B2 (en) Isolating a control signal source in a high frequency power supply
US20210083585A1 (en) Flying capacitor charging method and apparatus
JP6496329B2 (en) Power supply circuit incorporating a transformer to combine power amplifier output and load voltage clamp circuit isolation
JP6206502B2 (en) Power conversion device and power conversion method
EP3711153A1 (en) Voltage converting system and method of using the same
US9685877B2 (en) Power conversion apparatus
US10050532B2 (en) DC-DC converter with pseudo ripple voltage generation
US10205314B2 (en) Rectifier including MOSFET and hold circuit that boosts gate voltage of MOSFET, and alternator using the same
JP4236634B2 (en) Active common mode EMI filter
US10050546B1 (en) Apparatus for controlling LLC converter
WO2021038823A1 (en) Power conversion device
US7038924B2 (en) Surge current suppression in power-factor-corrected AC-to-DC converter with capacitive load
JP2018074692A (en) Electric power conversion system
US11502685B2 (en) Gate drive circuit and control circuit for switching circuit, and switching power supply
WO2022208616A1 (en) Common mode filter circuit
JP5791811B2 (en) Switching control circuit and switching power supply device
US20150138859A1 (en) System and method for power conversion
JP2015065738A (en) Power supply control circuit and power supply unit
US7023716B1 (en) Precharging load capacitor for power-factor-corrected AC-to-DC power supply
CN110692186A (en) Power conversion device
US20160118883A1 (en) Simo (single inductor multiple output) bidirectional dual-boost architecture
JPWO2020202422A1 (en) Wireless power supply system and power receiving device
Zhu et al. Small-signal modeling and decoupling control method of modular WPT systems
JP6191542B2 (en) Power converter
US9882464B1 (en) System for filtering high frequency noise components and an associated method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21934789

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023509929

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21934789

Country of ref document: EP

Kind code of ref document: A1