JP6191542B2 - Power converter - Google Patents

Description

  The present invention has a main input terminal, a main output terminal, and a switching element, and converts the voltage signal input from the main input terminal into a predetermined value by the on / off operation of the switching element and outputs the power signal from the main output terminal Relates to the device.

  As this type of apparatus, as shown in Patent Document 1 below, an apparatus including an inverter that modulates the output of a DC power source with a pulse width, a first capacitor pair, a second capacitor pair, and a common mode choke coil is known. Yes. Specifically, the first capacitor pair is provided on the output side of the inverter, and the second capacitor pair is provided on the input side of the inverter. The common mode choke coil is provided between the output side of the inverter and the first capacitor pair. The neutral point of the first capacitor pair and the neutral point of the second capacitor pair are connected by a bypass path.

  According to such a configuration, the common mode current (common mode noise) output from the output side of the inverter can flow to the second capacitor pair side via the first capacitor pair and the bypass path. Thereby, suppression of the common mode electric current which flows out out of a power converter device is aimed at.

JP 2010-119188 A

  Here, in the technique described in Patent Document 1, the common mode current flows to the second capacitor pair side via the bypass path. The common mode current that has flowed to the second capacitor pair side then flows to the input side of the power converter. For this reason, when an external device is connected to the input side of the power conversion device, there is a concern that the external device may be adversely affected by the common mode current flowing to the input side.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power converter that can suitably suppress a common mode current flowing out to the outside.

  In order to achieve the above object, the present invention provides a main input terminal (Tpin, Tnin; Ta, Tb, Tc; Tin), a main output terminal (Tpout, Tnout; TU to TW), and a switching element (24p, 24n; 52a). To 52c; 96; SUp to SWn), and a conversion circuit (16, 18;) that converts a voltage signal input from the main input terminal to a predetermined value by an on / off operation of the switching element and outputs the voltage signal from the main output terminal. 16a, 18a; 60, 62, 66, 68; 90; IV), which is connected to at least one electric path constituting the power conversion apparatus and flows in the electric path. A bypass path (36; 36a; 36b; 106; 116) for shunting current, and an electrical path constituting the power converter Among the bypass paths, the high-impedance path (14; 14a; 14b; 14c; which is set to have a relatively high impedance to the common-mode current). 14d).

  A common mode current is generated in the conversion circuit due to the on / off operation of the switching element. The generated common mode current flows through an electrical path that constitutes the power converter. Here, in the said invention, the bypass path which shunts the common mode electric current which flows into the at least 1 electric path which comprises a power converter device is provided. On the premise of such a configuration, the present invention further includes a high impedance path. According to the high impedance path, the common mode current guided through the bypass path can be suitably suppressed from flowing out of the power converter.

  Here, in the above invention, the first capacitor pair (34; 72) provided in the first electric path connecting the output side of the conversion circuit and the main output terminal and connected in series so as to form a neutral point. 102; 112U to 112W), and a second capacitor pair (38; provided in the second electric path on the main input terminal side rather than the output side of the conversion circuit) and connected in series so as to form a neutral point. 38a-38c; 74; 104; 114), wherein the bypass path connects a neutral point of the first capacitor pair and a neutral point of the second capacitor pair, and the high impedance path is The second electric path is provided on the main input terminal side of the second capacitor pair or on the main output terminal side of the first electric path than the first capacitor pair. Against de current can be embodied as including a first electrical path and a high impedance member impedance than the second electrical path.

  Due to the on / off operation of the switching element, a common mode current is output from the output side of the conversion circuit. Here, in the above invention, the output common mode current is caused to flow to the second capacitor pair side through the first capacitor pair and the bypass path. Based on such a configuration, the above invention further includes an impedance member. By providing the impedance member closer to the main input terminal than the second capacitor pair in the second electric path, it is possible to suppress a common mode current flowing out from the main input terminal. On the other hand, the common mode current flowing out from the main output terminal to the outside can be suppressed by providing the impedance member closer to the main output terminal than the first capacitor pair in the first electric path. Thus, according to the said invention, the common mode electric current which flows out outside can be suppressed suitably.

The block diagram of the switching power supply concerning 1st Embodiment. The figure for demonstrating the operation | movement aspect of a switching power supply. The block diagram of the switching power supply concerning a comparison technique. An equivalent circuit of a common mode current flow path according to comparative technology. The equivalent circuit of the common mode electric current flow path concerning 1st Embodiment. The figure which shows the reduction effect of the common mode electric current concerning the embodiment. The block diagram of the switching power supply concerning 2nd Embodiment. The block diagram of the switching power supply concerning 3rd Embodiment. The block diagram of the switching power supply concerning 4th Embodiment. The block diagram of the logic circuit concerning 5th Embodiment. The block diagram of the logic circuit concerning a comparison technique. The figure for demonstrating the operation | movement aspect of the logic circuit concerning 5th Embodiment. The figure for demonstrating the operation | movement aspect of the logic circuit concerning the embodiment. The block diagram of the switching power supply concerning 6th Embodiment. The block diagram of the inverter concerning 7th Embodiment. The block diagram of the switching power supply concerning 8th Embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a power conversion device according to the present invention is embodied as an ACDC converter will be described with reference to the drawings.

  As shown in FIG. 1, the switching power supply 10 serving as an ACDC converter includes a common mode choke coil 14, a chopper type booster circuit 16, a full-wave rectifier circuit 18, and a control device 20. An external power supply 12 (commercial power supply) that outputs an AC voltage is connected to the p-side input terminal Tpin and the n-side input terminal Tnin which are a pair of main input terminals of the switching power supply 10.

  The input side of the booster circuit 16 is connected to the p-side input terminal Tpin and the n-side input terminal Tnin via the common mode choke coil 14. The booster circuit 16 has a function of boosting an AC voltage input via the input terminals Tpin and Tnin and improving the power factor. The booster circuit 16 includes p and n side reactors 22p and 22n, and p and n side switching elements 24p and 24n. In the present embodiment, N-channel MOSFETs are used as the switching elements 24p and 24n. In the figure, the diodes connected in reverse parallel to the switching elements 24p and 24n may be, for example, body diodes of N-channel MOSFETs or diodes of external elements. Incidentally, in the present embodiment, the p and n side reactors 22p and 22n correspond to “first and second reactors”. In the present embodiment, the common mode choke coil 14 corresponds to an “impedance member”.

  A p-side input terminal Tpin is connected to the first end of the p-side reactor 22p through the common mode choke coil 14. An n-side input terminal Tnin is connected to the first end of the n-side reactor 22n via the common mode choke coil 14. The second ends of the reactors 22p and 22n are connected to each other via a series connection body of a p-side switching element 24p and an n-side switching element 24n. Specifically, the second end of the p-side reactor 22p is connected to the drain of the p-side switching element 24p, and the second end of the n-side reactor 22n is connected to the drain of the n-side switching element 24n. The sources of the switching elements 24p and 24n are short-circuited. According to such a connection method, when both of the switching elements 24p and 24n are turned off, the flow of current from one to the other of the ends of the series connection body of the switching elements 24p and 24n is prevented.

  The input side of the full-wave rectifier circuit 18 is connected to the output side of the booster circuit 16 (the drain side of each switching element 24p, 24n). The full-wave rectifier circuit 18 is a full bridge type, and includes a parallel connection body of a series connection body of a first diode D1 and a third diode D3 and a series connection body of a second diode D2 and a fourth diode D4. . Specifically, the drain of the p-side switching element 24p is connected to the connection point between the anode of the first diode D1 and the cathode of the third diode D3. The drain of the n-side switching element 24n is connected to the connection point between the anode of the second diode D2 and the cathode of the fourth diode D4. In the present embodiment, the booster circuit 16 and the full-wave rectifier circuit 18 correspond to a “conversion circuit”.

  A pair of main outputs are connected to the output side of the full-wave rectifier circuit 18 (the cathode side of the first and second diodes D1 and D2 and the anode side of the third and fourth diodes D3 and D4) via a smoothing capacitor 26. A p-side output terminal Tpout and an n-side output terminal Tnout which are terminals are connected. A load 28 is connected to the p and n side output terminals Tpout and Tnout. In the present embodiment, the electrical path connecting the output side of the full-wave rectifier circuit 18 and the p and n side output terminals Tpout and Tnout corresponds to the “first electrical path”. An electrical path connecting the p and n side input terminals Tpin and Tnin and the first ends of the p and n side reactors 22p and 22n corresponds to a “second electrical path”.

  The control device 20 is composed mainly of a microcomputer, and turns on / off each switching element 24p, 24n by controlling the gate voltage of each switching element 24p, 24n. Power is supplied to the load 28 by turning on / off the switching elements 24p and 24n. Hereinafter, the operation method of each of the switching elements 24p and 24n will be described in detail with reference to FIG.

  2A and 2B show a current flow path in the switching power supply 10 during a period in which the polarity of the output voltage of the external power supply 12 is positive. FIGS. 2C and 2D show current flow paths during a period in which the polarity of the output voltage of the external power supply 12 is negative. In FIG. 2, the common mode choke coil 14 and the like are not shown.

  First, during the period in which the polarity of the output voltage of the external power supply 12 is positive, as shown in FIGS. 2A and 2B, the p-side switching is performed under the situation where the n-side switching element 24n is turned off. The element 24p is turned on / off. For this reason, when the p-side switching element 24p is turned on, as shown in FIG. 2A, the external power source 12, the p-side reactor 22p, the p-side switching element 24p, the diode of the n-side switching element 24n, and n A current flows through a closed circuit including the side reactor 22n. Thereby, the electric energy input from each input terminal Tpin and Tnin is stored as magnetic energy in the p side reactor 22p and the n side reactor 22n. In the period shown in FIG. 2A, current is supplied from the smoothing capacitor 26 to the load 28.

  After that, as shown in FIG. 2B, when the p-side switching element 24p is switched to the off operation, the external power source 12, the p-side reactor 22p, the first diode D1, the load 28, the fourth diode D4, and the n-side A current flows through a closed circuit including the reactor 22n. As a result, the output voltage of the external power supply 12 is boosted and applied to the load 28, and power is supplied to the load 28. 2A and 2B, the voltage applied to the load 28 by the switching power supply 10 is the ON operation of the p-side switching element 24p with respect to a specified time (one cycle of the ON-OFF operation of the p-side switching element 24p). It can be adjusted by adjusting the flow rate, which is the ratio of time.

  Subsequently, during a period in which the polarity of the output voltage of the external power supply 12 is negative, as shown in FIGS. 2 (c) and 2 (d), the p-side switching element 24p is turned off. The switching element 24n is turned on / off. When the n-side switching element 24n is turned on, as shown in FIG. 2C, the external power supply 12, the n-side reactor 22n, the n-side switching element 24n, the diode of the p-side switching element 24p, and the p-side reactor 22p A current flows in a closed circuit including. Thereby, magnetic energy is stored in each reactor 22p, 22n like FIG. In the period shown in FIG. 2C, a current is supplied from the smoothing capacitor 26 to the load 28.

  Thereafter, as shown in FIG. 2 (d), when the n-side switching element 24n is switched to the off operation, the external power supply 12, the n-side reactor 22n, the second diode D2, the load 28, the third diode D3, and the p-side A current flows through a closed circuit including the reactor 22p. As a result, the output voltage of the external power source 12 is boosted and applied to the load 28 as in FIG. 2B, and power is supplied to the load 28. Note that the voltage applied to the load 28 by the switching power supply 10 during the period shown in FIGS. 2C and 2D is the ON operation time of the n-side switching element 24n with respect to the specified time (one cycle of ON / OFF operation of the n-side switching element 24n). The ratio can be adjusted by adjusting the flow rate.

  Incidentally, a parasitic capacitor is formed in the switching power supply 10. In the present embodiment, as shown in FIG. 1 above, a power supply side parasitic capacitor 30 is formed between the external power supply 12 and the grounded portion GND (for example, the casing of the switching power supply 10), and the positive side of the load 28 and A p-side parasitic capacitor 80p is formed between the ground portion GND and an n-side parasitic capacitor 80n is formed between the negative electrode side of the load 28 and the ground portion GND. Note that the ground portion GND functions as a ground line of the switching power supply 10, for example.

  Here, when the p-side switching element 24p is switched to the ON operation from the state shown in FIG. 2B, a reverse voltage is applied to the first and fourth diodes D1 and D4. In this case, a recovery current flows through the first and fourth diodes D1 and D4. Here, the recovery characteristics of the first and fourth diodes D1 and D4 may vary depending on, for example, individual differences between the diodes. If the recovery characteristic varies, the completion of recovery of one of the first and fourth diodes D1 and D4 (recovery current becomes 0) may be delayed with respect to the other. For example, it is assumed that the completion of the recovery of the fourth diode D4 is delayed with respect to the completion of the recovery of the first diode D1. In this case, until the recovery current output from the fourth diode D4 becomes zero, the fourth diode D4 can be equivalently regarded as a current source (hereinafter, a common mode current source). The common mode current source outputs a common mode current in a direction from the cathode to the anode. This current flows to the ground part GND via the smoothing capacitor 26 and the p-side parasitic capacitor 80p, or flows to the ground part GND via the n-side parasitic capacitor 80n. The common mode current that flows to the ground portion GND flows into the external power supply 12 via the power supply side parasitic capacitor 30. In this case, other electronic devices connected to the external power supply 12 may be damaged.

  Even when the n-side switching element 24n is switched to the on operation from the state shown in FIG. 2D, a reverse current is applied to the second and third diodes D2 and D3, and a recovery current flows. Of the second and third diodes D2 and D3, the diode whose recovery completion is delayed can be regarded as a common mode current source.

  In order to deal with such a problem, in the present embodiment, as shown in FIG. 1, the switching power supply 10 further includes a first capacitor pair 34, a second capacitor pair 38, and a bypass path 36. The first capacitor pair 34 is provided in an electrical path that connects the output side of the full-wave rectifier circuit 18 and the smoothing capacitor 26. The capacitances of the capacitors constituting the first capacitor pair 34 are set to the same value. The second capacitor pair 38 is provided in an electrical path connecting the common mode choke coil 14 and the input side of the booster circuit 16. The capacitances of the capacitors constituting the second capacitor pair 38 are set to the same value. The neutral point of the first capacitor pair 34 and the neutral point of the second capacitor pair 38 are short-circuited by the bypass path 36 without passing through the ground portion GND. Thereby, the common mode electric current which flows into the earthing | grounding site | part GND can be suppressed.

  Further, in the present embodiment, the installation position of the common mode choke coil 14 is an electrical path that connects the p and n side input terminals Tpin and Tnin and the second capacitor pair 38. Thereby, the suppression effect of the common mode current flowing out to the outside is further improved. Hereinafter, the effects of the present embodiment will be described in comparison with the comparative technique.

  First, the comparison technique will be described with reference to FIG. In FIG. 3, the same members as those shown in FIG. 1 are denoted by the same reference numerals for convenience. As shown in the figure, in the comparative technique, the common mode choke coil 14 is provided in an electrical path connecting the second capacitor pair 38 and the input side of the booster circuit 16.

  FIG. 4 shows an equivalent circuit of a common mode current distribution path according to the comparative technique. Here, FIG. 4 shows an example in which the fourth diode D4 is the common mode current source 40. When the bypass path 36 is provided, the common mode current output from the full-wave rectifier circuit 18 is divided into the path including the p and n side parasitic capacitors 80 p and 80 n and the power source side parasitic capacitor 30 and the bypass path 36. The Here, the common mode current I flowing through the external power supply 12, that is, the power supply side parasitic capacitor 30, is expressed by the following equation (eq1).

上式（ｅｑ１）において、「ＺＰ」は各寄生コンデンサ８０ｐ，８０ｎ，３０の合成インピーダンスを示し、「ＺＢ」は各コンデンサ対３４，３８を含むバイパス経路３６の合成インピーダンスを示す。

In the above equation (eq1), “ZP” indicates the combined impedance of the parasitic capacitors 80p, 80n, and 30, and “ZB” indicates the combined impedance of the bypass path 36 including the capacitor pairs 34 and 38.

  Next, FIG. 5 shows the equivalent circuit according to the present embodiment. Here, an example in which the fourth diode D4 is the common mode current source 40 is also shown in FIG. In the present embodiment, the common mode current I flowing through the external power supply 12 is expressed by the following equation (eq2).

上式（ｅｑ２）において、「ＺＬ」はコモンモードチョークコイル１４のインピーダンス示す。ここで、図４及び図５において、各コンデンサ対３４，３８を含むバイパス経路３６の合成インピーダンスＺＢは、各寄生コンデンサ８０ｐ，８０ｎ，３０の合成インピーダンスＺＰよりも低く設定されている。この設定により、コモンモード電流をバイパス経路３６側に多く流すようにしている。しかしながら、こうした設定を採用する比較技術であっても、上式（ｅｑ１），（ｅｑ２）から、外部電源１２に流れるコモンモード電流の抑制効果が本実施形態よりも低いことがわかる。これは、比較技術では、コモンモード電流に対して高インピーダンスであるコモンモードチョークコイル１４を、第２コンデンサ対３８よりも出力端子Ｔｐｏｕｔ，Ｔｎｏｕｔ側に設けているためである。つまり、比較技術では、全波整流回路１８の出力側から流入するコモンモード電流が、低インピーダンスのバイパス経路３６を介して外部電源１２へと導かれることとなる。このように、比較技術では、バイパス経路３６の設置がかえって外部電源１２に流れるコモンモード電流を増大させることとなる。

In the above equation (eq2), “ZL” indicates the impedance of the common mode choke coil 14. 4 and 5, the combined impedance ZB of the bypass path 36 including the capacitor pairs 34 and 38 is set lower than the combined impedance ZP of the parasitic capacitors 80p, 80n, and 30. With this setting, a large amount of common mode current flows to the bypass path 36 side. However, even with a comparative technique that employs such a setting, it can be seen from the above equations (eq1) and (eq2) that the effect of suppressing the common mode current flowing through the external power supply 12 is lower than that of the present embodiment. This is because in the comparative technique, the common mode choke coil 14 having a high impedance with respect to the common mode current is provided on the output terminals Tpout and Tnout side of the second capacitor pair 38. That is, in the comparative technique, the common mode current flowing from the output side of the full-wave rectifier circuit 18 is guided to the external power source 12 through the low impedance bypass path 36. As described above, in the comparative technique, the common mode current flowing through the external power supply 12 is increased instead of the installation of the bypass path 36.

  In contrast, in this embodiment, the common mode choke coil 14 is shown in FIG. 1 in order to increase the impedance of the flow path of the common mode current flowing from the second capacitor pair 38 side to the external power supply 12 side. Provided in position. Thereby, the suppression effect of the common mode current flowing in the external power supply 12 can be improved. In particular, since the relationship of “ZL >> ZB” is generally established, in this embodiment, the effect of suppressing the common mode current flowing through the external power supply 12 is large.

  Next, the effect of suppressing the common mode current flowing through the external power supply 12 will be described using the experimental data shown in FIG. Here, FIG. 6A corresponds to the present embodiment, and FIG. 6B corresponds to the comparative technique. FIG. 6C corresponds to a configuration in which the bypass path 36 and the capacitor pairs 34 and 38 are removed from the comparative technique. Even in the comparative technique shown in FIG. 6B, the effect of suppressing the common mode current can be obtained in a part of the frequency band as compared with the configuration shown in FIG. On the other hand, according to the present embodiment shown in FIG. 6A, the effect of suppressing the common mode current can be obtained in the entire frequency band as compared with the configuration shown in FIG.

  Thus, according to the present embodiment, it is possible to suitably suppress the common mode current output from the full-wave rectifier circuit 18 from flowing out via the external power supply 12. In addition, according to the present embodiment, it is possible to suppress the common mode current flowing into the output terminals Tpout and Tnout from the outside of the switching power supply 10 from flowing out again through the external power supply 12.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIG. 7 with a focus on differences from the first embodiment. In the present embodiment, the resistor 42 and the reactor 46 are provided in the bypass path 36. In FIG. 7, the same members as those shown in FIG. 1 are denoted by the same reference numerals for the sake of convenience.

  First, the installation effect of the resistor 42 will be described. The parasitic inductance 44 in the bypass path 36 and the parasitic capacitance of the parasitic capacitor (for example, the p-side parasitic capacitor 80p) formed in the switching power supply 10 may cause resonance in the common mode current distribution path. Here, according to the resistor 42, the current in the vicinity of the resonance frequency of the path can be greatly reduced.

  Then, the installation effect of the reactor 46 is demonstrated. The installation of the bypass path 36 reduces the impedance in the high frequency region. For this reason, an unintended high-frequency common mode current may flow through the bypass path 36 and have an adverse effect. Here, according to the reactor 46, an impedance can be given to a high frequency region, and a common mode current having only a desired frequency can be bypassed.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to FIG. 8 with a focus on differences from the first embodiment. In FIG. 8, the same members as those shown in FIG. 1 are given the same reference numerals for the sake of convenience.

  As shown in the figure, in the present embodiment, an electrical path (for example, a wiring pattern) from the second end of the p-side reactor 22p to the connection point of the first and third diodes D1 and D3 and the grounding part GND is provided. The first parasitic capacitor 48p is formed. In addition, a second parasitic capacitor 48n is formed between the electrical path (for example, a wiring pattern) from the second end of the n-side reactor 22n to the connection point of the second and fourth diodes D2 and D4 and the ground part GND. Has been.

  Here, when the p-side switching element 24p and the n-side switching element 24n are turned on and off at high speed, the applied voltage between the source and drain of the switching elements 24p and 24n varies. When the applied voltage fluctuates, each of the parasitic capacitors 48p and 48n is charged and discharged, and from the drain side electrical path of the p-side switching element 24p and the drain side electrical path of the n-side switching element 24n via the parasitic capacitors 48p and 48n. As a result, a common mode current flows to the ground portion GND. If the common mode current flows to the outside through the grounding portion GND, there is a possibility that other electronic devices may be damaged.

  In order to cope with such a problem, in this embodiment, the inductance Lp of the p-side reactor 22p and the inductance Ln of the n-side reactor 22n are set to the same value. According to such setting, the potential on the drain side of the p-side switching element 24p with respect to the ground portion GND and the potential on the drain side of the n-side switching element 24n with respect to the ground portion GND are each set with reference to the common mode voltage (0V). , And can be changed complementarily while keeping the absolute values equal.

  On the premise of such a configuration, the parasitic capacitance Cp of the first parasitic capacitor 48p and the parasitic capacitance Cn of the second parasitic capacitor 48n are further set to the same value. According to such setting, the current flowing from the drain side of the p-side switching element 24p to the ground part GND through the first parasitic capacitor 48p in accordance with the on / off operation of the switching elements 24p and 24n is the second parasitic capacitor 48n. Flow into. Further, the current that flows from the drain side of the n-side switching element 24n to the ground part GND via the second parasitic capacitor 48n flows into the first parasitic capacitor 48p. Thereby, the common mode current flowing from the grounded portion GND to the outside can theoretically be set to “0”. Therefore, according to this embodiment, the effect of suppressing the common mode current flowing out can be further improved.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIG. 9 focusing on differences from the first embodiment. In the present embodiment, the power converter is embodied as a three-phase ACDC converter. In FIG. 9, the same members as those shown in FIG. 1 are given the same reference numerals for the sake of convenience.

  As illustrated, the switching power supply 10a includes a common mode choke coil 14a, a chopper booster circuit 16a, a full-wave rectifier circuit 18a, and a control device 20.

  The input side of the booster circuit 16a is connected to the A, B, C phase input terminals Ta, Tb, Tc which are the main input terminals of the switching power supply 10 through the common mode choke coil 14a. The booster circuit 16a includes A, B, and C phase reactors 50a, 50b, and 50c, and first, second, and third switching elements 52a, 52b, and 52c. In this embodiment, IGBT is used as each switching element 52a, 52b, 52c. Each switching element 52a, 52b, 52c is turned on and off by the control device 20. Moreover, the phase of the line voltage of each phase is shifted by 120 degrees from each other. For this reason, in this embodiment, two reactors arbitrarily selected among each phase reactor 50a-50c are corresponded to a "1st, 2nd reactor."

  A, B, and C phase input terminals Ta, Tb, and Tc are connected to the first end of the A, B, and C phase reactor 50a through a common mode choke coil 14, respectively. The collector of the first switching element 52a is connected to the second end of the A-phase reactor 50a, and the second end of the B-phase reactor 50b is connected to the emitter of the first switching element 52a. The collector of the second switching element 52b is connected to the second end of the B-phase reactor 50b, and the second end of the C-phase reactor 50c is connected to the emitter of the second switching element 52b. The collector of the third switching element 52c is connected to the second end of the A-phase reactor 50a, and the second end of the C-phase reactor 50c is connected to the emitter of the third switching element 52c.

  The input side of the full-wave rectifier circuit 18a is connected to the output side of the booster circuit 16a. The full-wave rectifier circuit 18a is a three-phase bridge type and includes three series-connected bodies of a pair of diodes. Specifically, the second end of the A-phase reactor 50a is connected to the connection point between the anode of the first diode D1 and the cathode of the fourth diode D4. A second end of the B-phase reactor 50b is connected to a connection point between the anode of the second diode D2 and the cathode of the fifth diode D5. A second end of the C-phase reactor 50c is connected to a connection point between the anode of the third diode D3 and the cathode of the sixth diode D6.

  A first capacitor pair 34 is connected to the output side of the full-wave rectifier circuit 18a. The neutral point of the second capacitor pair 34 is connected to the common mode choke coil 14a and the first ends of the reactors 50a, 50b, 50c via the bypass path 36a and the second capacitor pairs 38a, 38b, 38c. The electrical path to be connected is connected.

  According to the present embodiment described above, in the three-phase ACDC converter, it is possible to suppress the common mode current output from the full-wave rectifier circuit 18a and the common mode current flowing from the outside.

(Fifth embodiment)
Hereinafter, the fifth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In the present embodiment, the power conversion device is embodied as the device shown in FIG. In FIG. 10, the same members as those shown in FIG. 1 are denoted by the same reference numerals for the sake of convenience.

  The logic circuit 10 b includes a buffer 60, an inverter 62, a common mode choke coil 14 b, and first and second power supplies 66 and 68. The buffer 60 and the inverter 62 are composed of a P-channel MOSFET and an N-channel MOSFET arranged in CMOS. In the present embodiment, the logic circuit 10b corresponds to a “conversion circuit”.

  A signal source 64 that outputs a complementary signal composed of logic H and L is connected to an input terminal Tin (corresponding to a “main input terminal”) of the logic circuit 10b. The input terminal Tin is connected to the input terminals of the buffer 60 and the inverter 62. A first power supply 66 having a terminal voltage “Vcc” is connected to the p-side power supply input terminal of the buffer 60. A second power supply 68 having a terminal voltage of “−Vcc” is connected to the n-side power input terminal of the inverter 62. A ground portion GND is connected to each of the n-side power input terminal of the buffer 60 and the p-side power input terminal of the inverter 62.

  The signal transmission target 70 is connected to the output terminals of the buffer 60 and the inverter 62 via the common mode choke coil 14b and the output terminals Tpout and Tnout of the logic circuit 10b.

  In the present embodiment, a p-side parasitic capacitor 80p is formed between the electrical path that connects the p-side output terminal Tpout and the signal transmission target 70 and the ground part GND. In addition, an n-side parasitic capacitor 80n is formed between the electrical path connecting the n-side output terminal Tnout and the signal transmission target 70 and the ground portion GND.

  The logic circuit 10b further includes a first capacitor pair 72, a second capacitor pair 74, and a bypass path 36b. The first capacitor pair 72 is provided in an electrical path that connects the output terminals of the buffer 60 and the inverter 62 and the common mode choke coil 14b. The neutral point of the first capacitor pair 72 includes an electrical path connecting the p-side power input terminal of the buffer 60 and the first power supply 66 via the bypass path 36b, an n-side power input terminal of the inverter 62, and a second An electrical path connecting the power source 68 is connected. Hereinafter, the effects of the present embodiment will be described in comparison with a comparative technique.

  First, the comparison technique will be described with reference to FIG. In FIG. 11, the same members as those shown in FIG. 10 are given the same reference numerals for the sake of convenience. As illustrated, in the comparison technique, the first and second capacitor pairs 72 and 74 and the bypass path 36b are removed.

  FIG. 12 shows an operation mode of the logic circuit 10b. In FIG. 12, “VA” indicates the output voltage of the buffer 60, and “VB” indicates the output voltage of the inverter 62.

  As shown in the figure, the output voltages VA and VB fluctuate in a complementary manner with reference to the potential (0 V) of the ground portion GND. However, as shown in FIG. 13, a delay time t may occur in the switching time between the buffer 60 and the inverter 62. FIG. 13 shows an example in which the delay time t occurs in the buffer 60. In this case, in this period t, the transistor constituting the buffer 60 can be regarded as a common mode current source. As a result, in the configuration shown in FIG. 11, the common mode current may flow from the buffer 60 to the ground portion GND via the common mode choke coil 14b and the p-side parasitic capacitor 80p. As a result, the p-side parasitic capacitor 80p is charged, and the voltage on the electrical path connecting the output terminals Tpout and Tnout and the signal transmission target 70 may fluctuate.

  In order to cope with such a problem, in this embodiment, as shown in FIG. 10, the first and second capacitor pairs 72 and 74 and the bypass path 36b are provided. In the present embodiment, the capacitances of the capacitors constituting the capacitor pairs 72 and 74 are set to the same value. Further, the common mode choke coil 14b is provided in the electrical path connecting the first capacitor pair 72 and the output terminals Tpout and Tnout. According to such a configuration, the common mode current output from the output terminals of the buffer 60 and the inverter 62 can be returned to the respective power input terminal sides of the buffer 60 and the inverter 62. Thereby, the suppression effect of the common mode current flowing out to the outside can be improved.

(Sixth embodiment)
Hereinafter, the sixth embodiment will be described with reference to FIG. 14 with a focus on differences from the first embodiment. In the present embodiment, the power conversion device is embodied as a DCDC converter. In FIG. 14, the same members as those shown in FIG. 1 are given the same reference numerals for the sake of convenience.

  As shown in the figure, a switching power supply 10 c as a DCDC converter includes a common mode choke coil 14 c, a chopper type booster circuit 90, and a control device 20. A DC power supply 92 (corresponding to “external power supply”) is connected to the p-side input terminal Tpin and the n-side input terminal Tnin of the switching power supply 10c. In the switching power supply 10c, the input side of the booster circuit 90 is connected to the p-side input terminal Tpin and the n-side input terminal Tnin via the common mode choke coil 14c. The booster circuit 90 includes p and n side reactors 94p and 94n, a switching element 96, and p and n side diodes 98p and 98n. In this embodiment, an N-channel MOSFET is used as the switching element 96. The switching element 96 is turned on and off by the control device 20.

  A p-side input terminal Tpin is connected to the first end of the p-side reactor 94p via a common mode choke coil 14c. An n-side input terminal Tnin is connected to the first end of the n-side reactor 94n via a common mode choke coil 14c. The drain of the switching element 96 is connected to the second end of the p-side reactor 94p, and the second end of the n-side reactor 94n is connected to the source of the switching element 96.

  The anode of the p-side diode 98p is connected to the second end of the p-side reactor 94p. A p-side output terminal Tpout is connected to the cathode of the p-side diode 98p. The cathode of the n-side diode 98p is connected to the second end of the n-side reactor 94n. An n-side output terminal Tnout is connected to the anode of the n-side diode 98n. In the switching power supply 10c, the p-side output terminal Tpout and the n-side output terminal Tnout are connected by a smoothing capacitor 100.

  Here, in this embodiment, in addition to the p and n side parasitic capacitors 80p and 80n, p and n side power source parasitic capacitors 82p and 82n are formed. The p-side power supply parasitic capacitor 82p is formed between the positive electrode side of the DC power supply 92 and the ground part GND. The n-side power supply parasitic capacitor 82n is formed between the negative electrode side of the DC power supply 92 and the ground part GND.

  Here, when the switching element 96 is switched from the off operation to the on operation, a reverse voltage is applied to the p and n side diodes 98p and 98n. In this case, a recovery current flows through the p and n side diodes 98p and 98n. Here, due to variations in the recovery characteristics of the p and n side diodes 98p and 98n, the completion of recovery of one of the p and n side diodes 98p and 98n may be delayed with respect to the other. For example, it is assumed that the completion of the recovery of the n-side diode 98n is delayed with respect to the completion of the recovery of the p-side diode 98p. In this case, the n-side diode 98n can be regarded as a common mode current source that outputs a common mode current in a direction from the cathode toward the anode. For example, the common mode current flows to the ground portion GND via the smoothing capacitor 100 and the p-side parasitic capacitor 80p, and then flows to the DC power source 92 via the p-side power parasitic capacitor 82p. In this case, other electronic devices connected to the DC power source 92 may be damaged.

  In order to cope with such a problem, in the present embodiment, the switching power supply 10 c further includes a first capacitor pair 102, a second capacitor pair 104, and a bypass path 106. The first capacitor pair 102 is provided in an electrical path that connects the p and n-side diodes 98 p and 98 n and the smoothing capacitor 100. The capacitances of the capacitors constituting the first capacitor pair 102 are set to the same value. The second capacitor pair 104 is provided in an electrical path that connects the common mode choke coil 14 c and the input side of the booster circuit 90. The capacitances of the capacitors constituting the second capacitor pair 104 are set to the same value. The neutral point of the first capacitor pair 102 and the neutral point of the second capacitor pair 104 are short-circuited by the bypass path 106 without passing through the ground portion GND. Thereby, the common mode electric current which flows into the earthing | grounding site | part GND can be suppressed.

  Furthermore, in the present embodiment, the installation position of the common mode choke coil 14c is set as an electrical path connecting the p and n side input terminals Tpin and Tnin and the second capacitor pair 104, as in the first embodiment. Yes. Thereby, the suppression effect of the common mode current flowing out to the outside can be further improved. In the present embodiment, as in the third embodiment, the inductance Lp of the p-side reactor 94p and the inductance Ln of the n-side reactor 94n are set to the same value, and the parasitic of the first parasitic capacitor 48p is set. The capacitance Cp and the parasitic capacitance Cn of the second parasitic capacitor 48n are set to the same value.

(Seventh embodiment)
Hereinafter, the seventh embodiment will be described with reference to FIG. 15 focusing on the differences from the first embodiment. In the present embodiment, the power conversion device is embodied as a three-phase inverter device. In FIG. 15, the same members as those shown in FIG. 14 are given the same reference numerals for the sake of convenience.

  As shown in the figure, the inverter device 10d includes a common mode choke coil 14d, a smoothing capacitor 108, and a $ phase high side and low side switch S \ p, S \ n (\ = U, V, W) constituting the inverter circuit IV. And a control device 20. In the present embodiment, an IGBT is used as each switch S ¥ # (# = p, n). Although not shown, a free wheel diode is connected in antiparallel to each switch S ¥ #.

  The $ -phase high-side switch S \ p and the $ -phase low-side switch S \ n are connected in series. The $ phase output terminal T \ of the inverter device 10d is connected to the connection point of the $ phase switches S \ p, S \ n. The ¥ phase of a load 110 (for example, a motor generator) is connected to the ¥ phase output terminal T ¥. The $ phase high side switch S \ p and the $ phase low side switch S \ n are alternately turned on by the control device 20. For example, the control device 20 alternately turns on the $ -phase high-side switch S \ p and the $ -phase low-side switch S \ n so as to flow sine-wave currents that are 120 degrees out of phase with each other in electrical phase. .

  Here, in the present embodiment, in addition to the p and n side power source parasitic capacitors 82p and 82n, a parasitic capacitor is formed between the motor generator 110 and the ground portion GND. In FIG. 15, the parasitic capacitor is indicated by “84, 86” between the load 110 and the grounding portion GND.

  Here, each switch S ¥ # constituting the inverter device 10d can be a common mode current source. Specifically, for example, of the U-phase high-side switch SUp and the V-phase low-side switch SVn, the one with delayed off timing can be a common mode current source. In this case, for example, after flowing to the ground portion GND via the parasitic capacitor 84, it flows to the DC power source 92 via the p-side power parasitic capacitor 82p.

  In order to deal with such a problem, in the present embodiment, the inverter device 10d further includes a first capacitor pair 112U, 112V, 112W, a second capacitor pair 114, and a bypass path 116. The first capacitor pair 112 ¥ is provided in an electrical path that connects the connection point of each of the ¥ phase switches S ¥ p, S ¥ n and the ¥ phase output terminal T ¥. The capacitances of the capacitors constituting the first capacitor pair 112U, 112V, 112W are set to the same value. The second capacitor pair 114 is provided in an electrical path connecting the common mode choke coil 14d and the smoothing capacitor 108. The capacitances of the capacitors constituting the second capacitor pair 114 are set to the same value. The neutral point of the first capacitor pair 112U, 112V, 112W and the neutral point of the second capacitor pair 114 are short-circuited by the bypass path 116 without passing through the ground portion GND. Thereby, the common mode electric current which flows into the earthing | grounding site | part GND can be suppressed.

  Furthermore, in the present embodiment, the installation position of the common mode choke coil 14d is an electric path that connects the p and n side input terminals Tpin and Tnin and the second capacitor pair 114, as in the sixth embodiment. Yes. Thereby, the suppression effect of the common mode current flowing out to the outside can be further improved.

(Eighth embodiment)
Hereinafter, the eighth embodiment will be described with reference to FIG. 16 focusing on the differences from the first embodiment. In the present embodiment, as shown in FIG. 16, a pair of resistors is used instead of the capacitor pair. In FIG. 16, the same members as those shown in FIG. 1 are given the same reference numerals for the sake of convenience.

  As illustrated, the switching power supply 10 further includes a pair of first resistors 118 and a pair of second resistors 120. The resistance values of the pair of first resistors 118 are set to the same value. The resistance values of the pair of second resistors 120 are set to the same value. The connection point of the pair of first resistors 118 and the connection point of the pair of second resistors 120 are short-circuited by the bypass path 36 without passing through the grounding portion GND. Thereby, the common mode electric current which flows into the earthing | grounding site | part GND can be suppressed.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  In the first embodiment, a pair of reactors as passive elements may be used instead of the common mode choke coil 14. In this case, a reactor is provided in the electrical path connecting the p-side input terminal Tpin and the first end of the p-side reactor 22p, and the reactor is connected to the electrical path connecting the n-side input terminal Tnin and the first end of the n-side reactor 22n. May be provided. Further, instead of the common mode choke coil 14, a pair of resistors may be used.

  The setting of the parasitic capacitance of the parasitic capacitor and the inductance of each reactor described in the third embodiment may be applied to the configuration illustrated in FIG. 9 of the fourth embodiment. Moreover, you may provide at least one among the reactor and resistor which were demonstrated in the said 2nd Embodiment in the structure shown in FIG.9, FIG.10, FIG.14 to FIG. 16 of the said 4th-8th embodiment.

  -In the said 2nd Embodiment, it is not necessary to provide either a resistor or a reactor.

  -In the said 1st Embodiment, you may use the full wave rectifier circuit by which two sets of series connection bodies of a pair of switching element (for example, MOSFET) were connected in parallel as a full wave rectifier circuit. In this case, synchronous rectification is performed in the full-wave rectifier circuit. In synchronous rectification, two sets of switching elements are alternately turned on. Here, when focusing on one set of switching elements, switching of one switching element in the one set of switching elements is delayed from switching off of the other switching element due to variations in switching characteristics. In this case, the switching element whose switching to OFF is delayed can be a common mode current source.

  In the first embodiment, if the relationship of “Lp × Cp = Ln × Cn” is satisfied, the inductance Lp of the p-side reactor 22p and the inductance Ln of the n-side reactor 22n, or the capacitance of the first parasitic capacitor 48p The electrostatic capacitances Cn of Cp and the second parasitic capacitor 48n may not be the same, and these parameters Lp, Ln, Cp, Cn may be set to arbitrary values.

  In the eighth embodiment, any one of the pair of first resistors 118 and the pair of second resistors 120 may be the capacitor pair described in the first embodiment. In the second to seventh embodiments, at least one of the first capacitor pair and the second capacitor pair may be a series connection body of the pair of resistors described in the eighth embodiment.

  DESCRIPTION OF SYMBOLS 14 ... Common mode choke coil, 16 ... Booster circuit, 18 ... Full wave rectifier circuit, 34 ... 1st capacitor pair, 36 ... Bypass path, 38 ... 2nd capacitor pair.

Claims (10)

Main input terminals (Tpin, Tnin; Ta, Tb, Tc; Tin) and main output terminals (Tpout, Tnout; TU to TW);
A switching element (24p, 24n; 52a to 52c; 96; SUp to SWn), which converts a voltage signal input from the main input terminal into a predetermined value by an on / off operation of the switching element and outputs the voltage signal from the main output terminal A conversion circuit (16, 18; 16a, 18a; 60, 62, 66, 68; 90; IV),
A bypass path (36; 36a; 36b; 106; 116) that is connected to at least one electrical path constituting the power converter and shunts a common mode current flowing through the electrical path;
Among the electric paths constituting the power converter, an electric path connected to the outflow side of the common mode current of the bypass path, wherein the impedance with respect to the common mode current is set to be relatively high and (14d 14; 14a; 14b; ; 14c),
A pair of first resistors (118) provided in a first electrical path connecting the output side of the converter circuit and the main output terminal, and connected in series;
A pair of second resistors (120) provided in a second electrical path on the main input terminal side than the output side of the conversion circuit and connected in series;
The bypass path connects a connection point of the pair of first resistors and a connection point of the pair of second resistors,
The high impedance path is the main input terminal side of the second electrical path than the series connection of the second resistor, or the series connection of the first resistor of the first electrical path. An electric power converter comprising an impedance member provided on a main output terminal side and having an impedance higher than that of the first electric path and the second electric path with respect to the common mode current .   The power converter according to claim 1, wherein the bypass path is not directly connected to a grounded portion of the power converter. The main input terminal (Tpin, Tnin; Ta, Tb, Tc) is connected to an external power source (12) that outputs an alternating voltage,
The conversion circuit includes:
Reactors (22p, 24p, 24n; 52a to 52c) are provided so as to store electrical energy input from the main input terminal by turning on the switching elements (24p, 24n; 52a to 52c) and to release stored energy by turning off the switching elements. 22n; 50a-50c) as a component, and a booster circuit (16; 16a) for boosting and outputting an AC voltage input from the main input terminal;
Power of claim 1 or 2 wherein has a; (18a 18), said converts the AC voltage outputted from the booster circuit to a DC voltage main output terminal (Tpout, Tnout) full-wave rectification circuit for outputting to the Conversion device. An external power source (92) that outputs a DC voltage is connected to the main input terminals (Tpin, Tnin),
The conversion circuit accumulates electric energy input from the main input terminal when the switching element (96) is turned on, and is provided with a reactor (94p, 94n) capable of discharging the stored energy when the switching element is turned off. ) and the component, the main boosts a DC voltage input from the input terminal said main output terminal (TPOUT, power converter according to claim 1 or 2, wherein with a step-up circuit (90) for outputting to Tnout) . An external power source (92) that outputs a DC voltage is connected to the main input terminals (Tpin, Tnin),
The switching element includes a high side switching element (SUp to SWp) and a low side switching element (SUn to SWn) connected in series to the high side switching element,
The conversion circuit converts a DC voltage input from the main input terminal into an AC voltage by alternating on operation of the high-side switching element and the low-side switching element to the main output terminal (TU to TW). power converter according to claim 1 or 2, wherein an inverter circuit (IV) for outputting a. The reactor includes a first reactor (22p; 50a to 50c; 94p) connected to a first end of the switching element and a second reactor (22n; 50a to 50c) connected to a second end of the switching element. 94n), and
The power conversion device according to claim 4 , wherein the switching element is provided so as to be able to step up an input voltage by intermittently flowing current through the first reactor and the second reactor. A first parasitic capacitor (48p) is formed between the electrical path on the first end side of the switching element with respect to the first reactor and a ground member (GND) having a reference potential of the power converter,
A second parasitic capacitor (48n) is formed between the electrical path on the second end side of the switching element with respect to the second reactor and the ground member,
When the parasitic capacitance of the first parasitic capacitor is Cp, the parasitic capacitance of the second parasitic capacitor is Cn, the inductance of the first reactor is Lp, and the inductance of the second reactor is Ln, the parasitic capacitances and the inductances Is a power conversion device according to claim 6, which is set so as to satisfy a relationship of Lp × Cp = Ln × Cn. The power converter according to any one of claims 1 to 7 , further comprising a reactor (46) provided in the bypass path. The power converter according to any one of claims 1 to 8 , further comprising a resistor (42) provided in the bypass path. Said impedance element, the power conversion device according to any one of claims 1 to 9 is a common mode choke coil.

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