JP2012125055A - Inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter that can compactly and inexpensively reduce leakage current.SOLUTION: The inverter for AC-converting power of a DC power supply 1 for interconnection to a three-phase power system with one phase grounded includes: two sets of arms 20, 21 having a plurality of switching elements for outputting PWM power to the two phases other than the grounded phase; a first capacitor pair 22a, 22b connected in series in an interphase fashion on a DC power line and having a neutral point directly connected with the grounded phase; a sinusoidal filter comprising two normal mode reactors 23a, 23b connected to respective inverter output lines of the two sets of arms corresponding to the two phases other than the grounded phase and two interphase capacitors 24a, 24b connected between the grounded phase and the two phases; a bypass line 26 connecting the grounded phase of sinusoidal filter output to the neutral point of the first capacitor pair; and a first common mode choke coil 25 connected on the power line sandwiched by the bypass line.

Description

  Embodiments described herein relate generally to an inverter, and more particularly to a technique for reducing the leakage current of the inverter.

  In a grid-connected inverter system that converts a DC power source such as a photovoltaic power generation or a fuel cell into an AC and links it to a grid, voltage fluctuation occurs due to a switching operation of a semiconductor element. This becomes a noise source and noise is transmitted to the system, and a part thereof becomes a leakage current flowing through the ground via the stray capacitance of a DC power source such as a solar battery panel.

  Since leakage current may have adverse effects such as electric shock to the human body and malfunction of other devices, suppression of leakage current is an essential issue. In general, the solution is to isolate the input and output inside the inverter using a high-frequency transformer, or to insulate by inserting a transformer between the inverter and the system to cut off the path of leakage current. There is a method (Non-patent document 1, Patent document 1) or a method (Non-patent document 2) to take measures with a noise filter composed of a grounding capacitor, a common mode choke coil or the like.

  FIG. 14 shows a conventional countermeasure example using an insulating transformer. As for the direct current from the direct current power source 1, a PWM voltage waveform is output by the switching operation of the semiconductor elements 2a, 2b, 3a, 3b, 4a and 4b constituting each phase. The current from this inverter is output as a sine wave by a sine wave filter 7 constituted by reactors 5a, 5b, 5c and interphase capacitors 6a, 6b, 6c.

JP-A-8-256435

Sharp Technical Report No. 77, August 2000 “Technical Report of the Institute of Electrical Engineers of Japan, No. 545, Electromagnetic Noise of Power Electronics Equipment” P22, 2.34

  A part of the high-frequency component included in the output current flows as a leakage current from the ground phase of the system 8 to the ground through a route passing through the floating capacitors 9a and 9b of the DC power supply 1. The insulation transformer 9 suppresses the leakage current by blocking this route. This measure is very effective in suppressing leakage current, but the insulation transformer 9 is large and heavy, so that the entire inverter system is increased in size, weight, and cost. In addition, since power loss occurs in the insulating transformer 9, there is also a problem that the power conversion efficiency of the entire system is lowered.

  On the other hand, FIG. 15 shows a countermeasure circuit using the noise filter 11. Combining high-impedance common mode choke coils 12, 13 with low-impedance interphase capacitors 14a, 14b, 14c and grounding capacitor 15 against high-frequency common-mode currents that cause leakage current prevents leakage to the power supply. is doing.

  However, when the system 8 is one-phase grounding, a voltage change of the power supply frequency occurs at the neutral point of the three interphase capacitors 14a, 14b, and 14c. The capacity of 15 cannot be increased, and sufficient filter performance cannot be obtained. In addition, when the wiring between the inverter and the system 8 is long, the neutral point of the interphase capacitors 14a, 14b, and 14c fluctuates at a high frequency with respect to the ground due to the inductance of the wiring. appear.

  The problem to be solved by the present invention is to provide an inverter that can reduce a leakage current and can be reduced in size and cost.

  In order to solve the above-described problem, according to the inverter according to the embodiment, the power of the DC power source is converted to AC, and the inverter connected to the three-phase power system in which one phase is grounded, the ground phase is excluded. Two sets of arms having a plurality of switching elements for outputting PWM voltage to two phases and a series connection between the phases of the line of the DC power source, and the ground phase is directly connected to the neutral point thereof One normal capacitor and two normal mode reactors connected to the inverter output lines of the two arms corresponding to the two phases excluding the ground phase, and connected between the ground phase and the two phases. A sine wave filter composed of two interphase capacitors, a bypass path connecting a ground phase of the sine wave filter output and a neutral point of the first capacitor pair, and the bypass path And having a first common mode choke coil connected to a power supply line that is sandwiched.

It is a circuit diagram showing an inverter of a 1st embodiment of the present invention. It is a circuit diagram which shows the inverter of the 2nd Embodiment of this invention. It is a circuit diagram which shows the inverter of the 3rd Embodiment of this invention. It is a circuit diagram which shows the inverter of the 4th Embodiment of this invention. It is a circuit diagram which shows the inverter of the 5th Embodiment of this invention. It is a circuit diagram which shows the inverter of the 6th Embodiment of this invention. It is a U-phase / W-phase output voltage command value and carrier, U-phase / W-phase output voltage, and leakage current simulation waveforms for explaining a conventional inverter. It is a U-phase / W-phase output voltage command value and carrier, U-phase / W-phase output voltage, and a simulation waveform of leakage current, illustrating an inverter according to a sixth embodiment of the present invention. It is a circuit diagram which shows the inverter of the 7th Embodiment of this invention. It is a circuit diagram which shows the detail of the control circuit in the conventional inverter. It is a circuit diagram which shows the detail of the control circuit in the inverter of the 7th Embodiment of this invention. FIG. 11 is a simulation waveform of U-phase / W-phase output voltage command values and carriers, U-phase / W-phase output voltages, and leakage current, illustrating the conventional inverter shown in FIG. 10. It is a U-phase / W-phase output voltage command value and carrier, U-phase / W-phase output voltage, and leakage current simulation waveforms for explaining the inverter of the seventh embodiment of the present invention. It is a circuit diagram which shows an example of the conventional inverter. It is a circuit diagram which shows another example of the conventional inverter.

(First embodiment)
FIG. 1 is a circuit diagram showing an inverter according to a first embodiment of the present invention. The three-phase output inverter shown in FIG. 1 includes a DC power source 1, capacitors 22a, 22b, 24a, 24b, a U-phase arm 20, a W-phase arm 21, reactors 23a, 23b, a common mode choke coil 25, and a solar cell. The DC power source 1 from the DC power source 1 is converted into an alternating current. At both ends of the DC power source 1, a U-phase arm 20, a W-phase arm 21, and DC capacitors 22a and 22b connected in series (first capacitor pair) ) Is connected. Each of the U-phase arm 20 and the W-phase arm 21 has a plurality of switching elements, and outputs a PWM signal by turning on and off the plurality of switching elements. The remaining V phase is the ground phase of the power supply, and this ground phase is connected to the neutral point of the capacitors 22a and 22b.

 Reactors 23a and 23b (normal mode reactors) are connected to the output lines of the U-phase arm 20 and the W-phase arm 21, and capacitors 24a and 24b (interphase capacitors) are connected to the ground phase and the remaining two phases. Yes. Reactors 23a and 23b and capacitors 24a and 24b constitute a sine wave filter that smoothes the output waveform from the inverter.

 At this time, the reactor is not connected to the ground phase, and the wiring inductance is kept as small as possible. This is because, if the impedance of the ground phase is high, a potential difference is generated between the ground phase of the power source due to a high-frequency current flowing in the ground phase, and the neutral point of the inverter fluctuates, increasing noise and leakage current.

 A common mode choke coil 25 (first common mode choke coil) is connected to the system side of the sine wave filter, and the neutral point B of the system side ground phase A and capacitors 22a and 22b so as to sandwich the common mode choke coil 25 therebetween. Are connected by a bypass 26.

 According to such a configuration, a high-frequency common mode current from the inverter that becomes a leakage current is suppressed by the common mode choke coil 25 that has a high impedance. Further, since the common mode current flows through the bypass circuit 26 having a low impedance with respect to the leakage current path configured via the stray capacitors 9a and 9b on the DC power supply 1 side, the leakage current to the outside is greatly reduced. .

 Although FIG. 1 shows a state in which the reactors 23a and 23b are individually connected to the respective phases, a normal mode reactor configured by winding two windings 23a and 23b around one core may be used. good.

(Second Embodiment)
FIG. 2 is a circuit diagram showing an inverter according to the second embodiment of the present invention. The inverter shown in FIG. 2 includes two capacitors 27a and 27b (second capacitor pair) connected in series at both ends of the DC power source 1, and includes a neutral point of the capacitors 27a and 27b and a ground phase of the sine wave filter output. And a bypass path 26 is formed.

 Although electrolytic capacitors are generally used for the capacitors 22a and 22b, there are cases where a sufficient leakage current suppressing effect cannot be obtained because the equivalent series resistance is relatively large. On the other hand, a further effect can be obtained by connecting the bypass path 26 using a capacitor having a small equivalent series resistance such as a film capacitor.

 1 illustrates the example in which the common mode choke coil 25 is provided on the output side of the inverter. However, as illustrated in FIG. 2, the common mode choke coil is interposed between the DC power source 1 and the capacitors 22a and 22b. Even if 28 is arranged, the same effect as the leakage current suppressing effect of the first embodiment can be obtained. In addition, since the common mode choke coil 28 has a single phase, the number of windings can be reduced and the size can be reduced.

(Third embodiment)
FIG. 3 is a circuit diagram showing an inverter according to the third embodiment of the present invention. The inverter shown in FIG. 3 is obtained by adding a step-up chopper composed of a chopper reactor 29, a diode 30, and a switching element 31 between the common mode choke coil 28 and the capacitors 22a and 22b to the inverter shown in FIG. It is characterized by.

  When the step-up chopper circuit is also sandwiched by the bypass path 26, the leakage current newly generated by the step-up operation of the step-up chopper can obtain the same effect as the effect of suppressing the leakage current from the inverter.

(Fourth embodiment)
FIG. 4 is a circuit diagram showing an inverter according to the fourth embodiment of the present invention. The inverter shown in FIG. 4 is common to the inverter shown in FIG. 3 on at least one of the DC power supply side and the system side of the remaining power supply lines excluding the power supply line connecting the bypass path 26, that is, in the system 8. A choke coil 32 is connected, and a common mode choke coil 33 is connected to the DC power source 1.

  Since the impedances of the stray capacitances 9a and 9b are inversely proportional to the frequency, the impedance becomes small with respect to the high frequency, and the leakage current easily flows. On the other hand, since the common mode choke coils 32 and 33 act as a large impedance with respect to the high-frequency leakage current, the reduction effect can be further enhanced.

(Fifth embodiment)
FIG. 5 is a circuit diagram showing an inverter according to a fifth embodiment of the present invention. The inverter shown in FIG. 5 is connected to the inverter shown in FIG. 4 by connecting one capacitor 34 instead of the series capacitors 27a and 27b connected to the bypass path 26 on the DC power supply 1 side. , And is connected to one of the phases via another capacitor 35. Even with such a configuration, the same function and effect as those of the fourth embodiment can be obtained.

(Sixth embodiment)
FIG. 6 is a circuit diagram showing an inverter according to a sixth embodiment of the present invention. FIG. 7 is a simulation waveform of U-phase / W-phase output voltage command values and carriers, U-phase / W-phase output voltage, and leakage current for explaining a conventional inverter. FIG. 8 is a simulation waveform of U-phase / W-phase output voltage command values and carriers, U-phase / W-phase output voltage, and leakage current, illustrating an inverter according to a sixth embodiment of the present invention.

  The U-phase arm 20 of the inverter shown in FIG. 6 includes upper and lower switching elements 20a and 20b, and the W-phase arm 21 includes upper and lower switching elements 21a and 21b. The control circuit 10 includes a carrier generator CAR, comparators CMP1 and CMP2, and inverters INV1 to INV3.

  The carrier generator CAR generates a carrier signal composed of a triangular wave signal. The comparator CMP1 compares the carrier signal from the carrier generator CAR with the U-phase output voltage command value (hereinafter referred to as U-phase command value) UIN. When the U-phase command value UIN is equal to or higher than the carrier signal CAR, the comparator CMP1 When the U-phase command value UIN is less than the carrier signal CAR, the L level is output to the switching element 20a. The inverter INV1 inverts the output of the comparator CMP1 and outputs it to the switching element 20b.

  The inverter INV2 outputs the carrier signal from the carrier generator CAR to the inverting input terminal of the comparator CMP2. The comparator CMP2 compares the inverted carrier signal from the inverter INV2 with the W-phase output voltage command value (hereinafter referred to as W-phase command value) WIN. When the W-phase command value WIN is equal to or greater than the inverted carrier signal, the comparator CMP2 Is output to the switching element 21a, and when the W-phase command value WIN is less than the inverted carrier signal, the L level is output to the switching element 21a. The inverter INV3 inverts the output of the comparator CMP1 and outputs it to the switching element 21b.

  7A and 8A show the phase voltages of the U-phase arm 20 and the W-phase arm 21, that is, the U-phase command value UIN and the W-phase command value WIN. FIGS. 7B and 8B and FIGS. 7C and 8C are obtained by enlarging the time axis with respect to FIGS. 7A and 8A, respectively. The phase command value, the W phase command value, and the carrier signal CAR are shown.

  FIGS. 7D and 8D show simulation waveforms of U-phase and W-phase output voltages. The phase of the carrier signal in FIG. 8C is shifted by 180 ° with respect to the phase of the carrier signal shown in FIG.

  When the U-phase command value and the W-phase command value are larger than the carrier signal, the upper switching elements 20a and 21a are turned on. In the opposite case, the switching elements 20b and 21b are turned on. The negative pulse voltage is output.

  In the region where the polarities of the sine waves output from the U phase and the W phase are reversed, the phase of the carrier signal is shifted by 180 ° as in the sixth embodiment shown in FIG. The ratio of the polarity of the voltage output from the W phase is increased. In that case, the two output voltages of the U phase and the W phase are canceled out, and the fluctuation of the voltage causing the leakage current is reduced. As shown in FIG. Get smaller.

(Seventh embodiment)
FIG. 9 is a circuit diagram showing an inverter according to the seventh embodiment of the present invention. The U-phase arm 20 of the inverter shown in FIG. 9 includes four switching elements 20c, 20d, 20e, and 20f connected in series. The W-phase arm 21 includes four switching elements 21c, 21d, 21e and 21f.

  FIG. 10 is a circuit diagram showing details of a control circuit in a conventional inverter. The control circuit shown in FIG. 10 includes comparators CMP1 to CMP4 and inverters INV1 to INV4. The comparator CMP1 compares the U-phase command value UIN with the upper carrier signal CARU, and outputs an H level to the switching element 20c when the U-phase command value UIN is equal to or higher than the upper carrier signal CARU. Is less than the upper carrier signal CARU, the L level is output to the switching element 20c. The inverter INV1 inverts the output of the comparator CMP1 and outputs it to the switching element 20e.

  The comparator CMP2 compares the U-phase command value UIN and the lower carrier signal CARD, and outputs an H level to the switching element 20d when the U-phase command value UIN is equal to or higher than the lower carrier signal CARD. Is less than the lower carrier signal CARD, the L level is output to the switching element 20d. The inverter INV2 inverts the output of the comparator CMP2 and outputs it to the switching element 20f.

  The comparator CMP3 compares the W-phase command value WIN and the upper carrier signal CARU, and outputs an H level to the switching element 21c when the W-phase command value WIN is equal to or higher than the upper carrier signal CARU, and the W-phase command value WIN Is less than the upper carrier signal CARU, the L level is output to the switching element 21c. The inverter INV3 inverts the output of the comparator CMP3 and outputs it to the switching element 21e.

  The comparator CMP4 compares the W-phase command value WIN and the lower carrier signal CARD, and outputs the H level to the switching element 21d when the W-phase command value WIN is equal to or higher than the lower carrier signal CARD, and the W-phase command value WIN. Is less than the lower carrier signal CARD, the L level is output to the switching element 21d. The inverter INV4 inverts the output of the comparator CMP4 and outputs it to the switching element 21f.

  FIG. 11 is a circuit diagram showing details of the control circuit in the inverter according to the seventh embodiment of the present invention. The control circuit of the seventh embodiment shown in FIG. 11 is characterized by further comprising inverters INV5 and INV6 in addition to the conventional control circuit shown in FIG. The inverter INV5 inverts the upper carrier signal CARU and outputs it to the inverting input terminal of the comparator CMP3. The inverter INV6 inverts the lower carrier signal CARD and outputs it to the inverting input terminal of the comparator CMP4.

  FIG. 12 is a simulation waveform of U-phase / W-phase output voltage command values and carriers, U-phase / W-phase output voltages, and leakage current for explaining the conventional inverter shown in FIG. FIG. 13 is a simulation waveform of U-phase / W-phase output voltage command values and carriers, U-phase / W-phase output voltages, and leakage current, illustrating an inverter according to a seventh embodiment of the present invention.

  12A and 13A show the phase voltages of the U-phase arm 20 and the W-phase arm 21, that is, the U-phase command value UIN and the W-phase command value WIN. FIGS. 12B and 13B and FIGS. 12C and 13C are obtained by enlarging the time axis with respect to FIGS. 12A and 13A, respectively. A phase command value, a W phase command value, and two carrier signals CARU and CARD are shown.

  FIGS. 12D and 13D show simulation waveforms of output voltages of the U phase and the W phase. The phases of the carrier signals CARU and CARD of each phase in FIG. 13C are shifted by 180 ° with respect to the phases of the carrier signals CARU and CARD of each phase shown in FIG. FIG. 12E and FIG. 13E show simulation waveforms of leakage current.

  Similarly to the sixth embodiment, in the seventh embodiment, by shifting the carrier signals of the U phase and the W phase by 180 °, the period in which the voltages output from the respective phases cancel each other becomes longer, and the leakage current Can be reduced.

  As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2a-4b ... Switching element, 5a-5c ... Reactor, 6a-6c ... Capacitor, 7 ... Sine wave filter, 8 ... System | strain, 9a, 9b ... Stray capacitance, 9 ... Insulation transformer 10, 10a ... Control circuit, 11 ... Noise filter, 12, 13 ... Reactor, 14a-14c ... Interphase capacitor, 15 ... Grounding capacitor, 20 ... U phase arm, 21 ... W phase arm, 20a-20f, 21a-21f ... Switching element, 22a , 22b ... capacitor, 23a, 23b ... reactor, 24a, 24b ... capacitor, 25 ... common mode choke coil, 26 ... bypass path, 27a, 27b ... capacitor, 28 ... common mode choke coil, 29 ... reactor, 30 ... diode, 31 ... Switching element, 32, 33 ... Common mode choke carp , CMP1~CMP4 ... comparator, INV1~INV6 ... inverter.

Claims (7)

In an inverter connected to a three-phase power system in which the power of the DC power source is converted to AC and one phase is grounded,
Two sets of arms having a plurality of switching elements for outputting PWM voltage to two phases excluding the ground phase;
A first capacitor pair connected in series between the phases of the line of the DC power supply, the ground phase being directly connected to a neutral point thereof;
Two normal mode reactors connected to inverter output lines of the two sets of arms corresponding to two phases excluding the ground phase, and two interphase capacitors connected between the ground phase and the two phases A sine wave filter comprising:
A bypass path connecting the ground phase of the sine wave filter output and the neutral point of the first capacitor pair;
A first common mode choke coil connected to a power line sandwiched between the bypass paths;
An inverter characterized by comprising: In an inverter connected to a three-phase power system in which the power of the DC power source is converted to AC and one phase is grounded,
Two sets of arms having a plurality of switching elements for outputting PWM voltage to two phases excluding the ground phase;
A first capacitor pair connected in series between the phases of the line of the DC power supply, the ground phase being directly connected to a neutral point thereof;
Two normal mode reactors connected to inverter output lines of the two sets of arms corresponding to two phases excluding the ground phase, and two interphase capacitors connected between the ground phase and the two phases A sine wave filter comprising:
A second capacitor pair connected in series to the DC power supply line;
A bypass path connecting the ground phase of the sine wave filter output and the neutral point of the second capacitor pair;
A first common mode choke coil connected to a power line sandwiched between the bypass paths;
An inverter characterized by comprising:   A series circuit of a reactor and a diode connected to one line of the DC power source between the first capacitor pair and the second capacitor pair, a connection point of the reactor and the diode, and the other of the DC power source The inverter according to claim 1, further comprising a step-up chopper having a first switching element connected to the first line.   4. A second common mode choke coil connected to at least one of the DC power supply side and the system side of the remaining power supply lines excluding the power supply line sandwiched between the bypass paths. The inverter according to claim 1.   Instead of the second capacitor pair, a first capacitor connected between the phases of the DC power supply line, and a second capacitor connecting one of the DC power supply lines and the ground phase of the sine wave filter output. The inverter according to any one of claims 2 to 4, wherein the inverter is provided. Each of the two sets of arms that output the PWM voltage has two switching elements,
And a control circuit for PWM-switching the two switching elements in each of the two sets of arms,
The control circuit switches the two switching elements in one of the two phases using a first carrier signal, and uses the second carrier signal shifted by 180 ° from the first carrier signal. The inverter according to any one of claims 1 to 5, wherein two switching elements of the other phase are switched. Each of the two sets of arms that output the PWM voltage has an upper first and second switching elements and a lower third and fourth switching elements,
And a control circuit for PWM-switching the first and second switching elements in the upper stage and the third and fourth switching elements in the lower stage, which are provided in each of the two sets of arms,
The control circuit switches the first and third switching elements of one of the two phases using an upper carrier signal, and uses the carrier signal shifted by 180 ° from the upper carrier signal. The first and third switching elements of the other phase of the two phases are switched, the second and fourth switching elements of one of the two phases are switched using the lower carrier signal, and the lower stage is used. The inverter according to any one of claims 1 to 5, wherein the second and fourth switching elements of the other phase of the two phases are switched using a carrier signal that is shifted from the carrier signal by 180 °. .

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