WO2021229632A1

WO2021229632A1 - Power conversion device

Info

Publication number: WO2021229632A1
Application number: PCT/JP2020/018783
Authority: WO
Inventors: 将幸大石; 友一坂下
Original assignee: 三菱電機株式会社
Priority date: 2020-05-11
Filing date: 2020-05-11
Publication date: 2021-11-18
Also published as: JP7241970B2; JPWO2021229632A1

Abstract

A compensation voltage generator (10) generates a common mode compensation voltage for canceling a common mode voltage included in AC voltage on the AC side of a power conversion circuit (1) for performing power conversion between DC and AC. The compensation voltage generator (10) is configured so as to obtain, before a timing at which the power device is switched to on, drive information including information by which the on-state of a power device of the power conversion circuit (1) can be acknowledged and calculate and generate the common mode compensation voltage using the obtained drive information and at least one of a phase correction amount for correcting a phase and an amplitude correction amount for correcting an amplitude. The compensation voltage generator (10) is further configured so as to update at least one of the phase correction amount and the amplitude correction amount so that the detected common mode voltage decreases each time when the drive information changes.

Description

Power converter

This application relates to a power conversion device.

In recent years, in the power conversion circuit used in a power conversion device, a method of generating an arbitrary waveform by switching on and off a self-extinguishing power device and controlling the average value of the output voltage is generally used. ing. In the power conversion circuit, the common mode voltage defined by the average value of each output end voltage fluctuates due to the switching of the power device. Further, due to the fluctuation of the common mode voltage, the common mode current flows in the common mode path formed by the power conversion circuit and the loop of stray capacitance to ground. In the induction machine drive system, the common mode voltage causes bearing electrolytic corrosion that shortens the life of the device, and the common mode current causes induction failure that causes the peripheral electronic circuits to malfunction.

In order to improve the problem caused by this common mode voltage, the common mode voltage generated by the power conversion circuit is detected, and the compensation voltage is calculated by the arithmetic circuit composed of active elements such as operational amplifiers and bipolar transistors to obtain the common mode voltage. On the other hand, a common mode filter circuit has been proposed in which a voltage having a compensation waveform of opposite phase is injected and canceled. For example, in Non-Patent Document 1, a capacitor dividing circuit is used to extract and detect a common mode voltage from a three-phase power line, an amplifier circuit using a bipolar transistor amplifies the detected voltage, and a transformer with an injection auxiliary winding is used. A method of injecting a voltage of the opposite phase to the common mode voltage has been proposed. In principle, the common mode voltage can be completely canceled by injecting a voltage having a compensation waveform that is out of phase and has the same amplitude with respect to the common mode voltage generated by the power conversion circuit.

However, since a phase delay occurs in the input and output due to the influence of the parasitic component determined by the unique frequency characteristics existing in the components constituting the detection circuit, injection circuit, and amplifier circuit or the mounting condition of the circuit, it is used in the common mode filter circuit. Cannot inject a perfect reverse phase component, the common mode voltage remains, and the common mode voltage in a certain frequency band is amplified. Furthermore, in addition to the resistance and capacitance that make up the arithmetic circuit, the characteristics of the magnetic material of the transformer of the injection circuit change due to temperature changes, component variations, etc., so the desired gain cannot be obtained and the common mode voltage remains. Was an issue.

The present application discloses a technique for solving the above-mentioned problems, and an object thereof is to obtain a common mode filter circuit in which the residual common mode voltage is small even if the environment changes or the component characteristics vary. do.

The power conversion device disclosed in the present application is included in a power conversion circuit that converts power between DC and AC by switching the power device on and off, and an AC voltage on the AC side of this power conversion circuit. A compensating voltage generator that generates a common mode compensating voltage for canceling the common mode voltage, a compensating voltage injector that superimposes the common mode compensating voltage generated by the compensating voltage generator on the AC voltage, and the common. A power conversion device including a voltage detector for detecting a common mode voltage included in the AC voltage on which a mode compensation voltage is superimposed, and a common mode filter circuit having the mode compensation voltage generator. Drive information including information that can recognize the on state of the power device constituting the conversion circuit is acquired before the timing at which the power device is switched on, and the acquired drive information and the phase correction amount for correcting the phase are obtained. And at least one of the amplitude correction amounts for correcting the amplitude, is configured to calculate and generate the common mode compensation voltage, and further, each time the drive information changes, it is detected by the voltage detector. It is configured to calculate the common mode compensation voltage by updating at least one of the phase correction amount and the amplitude correction amount so that the common mode voltage is reduced.

According to the power conversion device disclosed in the present application, a power conversion device having a small residual common mode voltage can be obtained even if the environment changes or the component characteristics vary.

It is a block diagram which shows the structure of the power conversion apparatus by Embodiment 1. FIG. It is a circuit diagram for demonstrating the generation principle of the common mode voltage of a power conversion circuit 1. It is a figure which shows the equivalent circuit of a common mode path. It is a diagram for demonstrating the common mode voltage when a phase delay occurs. It is a diagram for demonstrating the common mode voltage when an amplitude error occurs. It is a diagram for demonstrating the operation of the power conversion apparatus according to Embodiment 1. FIG. It is a block diagram which shows an example of the structure of the common mode filter circuit of the power conversion apparatus according to Embodiment 1. FIG. It is a block diagram which shows the structure of the power conversion apparatus by Embodiment 2. FIG. It is a figure for demonstrating the operation of the power conversion apparatus by Embodiment 2. FIG. It is a figure for demonstrating another operation of the power conversion apparatus according to Embodiment 2. FIG. It is a circuit diagram which shows an example of the structure of the power conversion circuit of the power conversion apparatus according to Embodiment 3. It is a circuit diagram which shows another example of the structure of the power conversion circuit of the power conversion apparatus according to Embodiment 3.

Hereinafter, the power conversion device according to each embodiment will be described with reference to the drawings. In the drawings, those having the same reference numerals are the same or equivalent thereof, and are common to all the texts of the embodiments described below.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a power conversion device according to the first embodiment. The power conversion device 100 includes a power conversion circuit 1 that converts direct current into alternating current, and a common mode filter circuit 3 that provides a common mode compensation voltage for canceling the common mode voltage. The power conversion circuit 1 includes a capacitance component such as a DC capacitor and a power device which is a switching element. The power conversion device 100 supplies power to the compensation target 2 such as a power system or a load (for example, a motor). Alternatively, it receives power from the compensation target 2. The common mode filter circuit 3 includes a compensation voltage generator 10 that generates a common mode compensation voltage, a compensation voltage injector 104 that injects a common mode compensation voltage and superimposes it on an AC voltage output from the power conversion circuit 1, and a common mode. A voltage detector 101 for detecting a voltage is provided. The compensation voltage generator 10 has a control circuit 102 and an amplifier circuit 103. The power conversion circuit 1 is configured to convert a DC voltage on the input side into an AC voltage and output it by switching the power device on and off. The control circuit 102 acquires the drive information 105 that can recognize the on state of the power device of the power conversion circuit 1. In the following, the voltage detector 101 is a method of detecting a common mode voltage using a capacitor voltage divider circuit, and the compensation voltage injector 104 is a method of injecting a common mode compensation voltage via a three-phase transformer with an auxiliary winding. This method will be described as an example.

FIG. 2 is a circuit diagram for explaining the generation principle of the common mode voltage of the power conversion circuit 1 which is a noise source. Here, the power conversion circuit 1 is a three-phase full bridge conversion circuit in which three connections in which the upper arm and the lower arm are connected in series are connected in parallel to a DC power supply, and are used as an AC voltage to be output. The case of three phases will be described as an example. Each arm is composed of a power device T in which a switching element and a diode are connected in antiparallel. Further, for simplification of the explanation, in FIG. 2, the neutral point of the DC capacitor on the input side of the power conversion circuit 1 is set as the ground point. Since the common mode voltage included in the AC voltage output by the three-phase inverter that is the power conversion circuit 1 is obtained by the average value of each phase output voltage, the DC capacitor voltage is Vdc and the number of on-elements of the power device of the upper arm is N. ,, The common mode voltage is expressed as (N / 3-1 / 2) × Vdc. Therefore, by sending information on the number of on elements N of the upper arm and the DC capacitor voltage Vdc as drive information from the power conversion circuit 1 to the control circuit 102, the control circuit 102 cancels the common mode voltage by the common mode filter circuit 3 The common mode compensation voltage to be injected can be calculated immediately.

Specifically, the common mode voltage (N / 3-1 / 2) × Vdc is calculated in the control circuit 102, the calculation result is output from the amplifier circuit 103, and the auxiliary winding of the transformer of the compensation voltage injector 104 is performed. It is applied to the wire, and a common mode compensating voltage (also simply referred to as a compensating voltage) having the same polarity and amplitude as the common mode voltage is injected into each phase. The reverse polarity of the waveform can be realized by arithmetic processing by the arithmetic circuit 103 or by applying a polarizing transformer to the compensating voltage injector 104. Further, by setting the gain product determined by the calculated gain of the arithmetic circuit 103 and the turns ratio of the auxiliary winding of the transformer of the compensating voltage injector 104 and the power wire to 1, a compensating voltage having the same amplitude can be output with respect to the common mode voltage. .. In principle, the above compensation completely cancels the common mode voltage generated by the power conversion circuit 1. However, since an inverting amplifier circuit using an operational amplifier, a non-inverting amplifier circuit, an emitter follower circuit using a bipolar transistor, or the like is used for the amplifier circuit 103, the gain characteristics and phase characteristics of the input / output are practically component-specific. There is frequency dependence. In addition, the gain or phase characteristics may change in the operating state due to variations in peripheral components of the amplifier circuit 103 and changes in temperature. Further, the transformer of the compensation voltage injector 104 is affected by the leakage inductance, and the amplitude of the output voltage is lowered with respect to the theoretical value obtained by the turns ratio. Due to these factors, the voltage injected by the compensating voltage injector 104 has a deviation from the common mode voltage generated by the power conversion circuit 1, so that the common mode voltage remains.

FIG. 3 is a diagram showing a common mode path by an equivalent circuit. As shown in FIG. 3, the common mode path can be simulated by an LC series resonant circuit having a voltage source, wiring inductance, and stray capacitance to ground between the power conversion circuit 1 and the common mode filter circuit 3. The common mode voltage included in the output voltage of the power conversion circuit 1 is Vnoise, and the compensation voltage injected by the common mode filter circuit 3 is Vfilt. If the common mode filter circuit 3 has no amplitude error or phase delay with respect to the desired compensation voltage, Vnoise + Vfilt = 0, and the common mode voltage of the compensation target 2 is completely canceled. However, when a phase delay occurs, Vnoise + Vfilt does not become zero, and a step voltage with an amplitude of 1/3 Vdc is generated each time switching is performed.

FIG. 4 schematically illustrates Vnoise,-Vfilt, and Vnoise + Vfilt when a phase delay occurs. The larger the phase delay amount t1 = Tph_delay, the wider the time width of the step voltage of Vnoise + Vfilt, and the larger the effective value of the remaining common mode voltage. As a result, the voltage vibration amplitude generated in the LC series resonant circuit shown in FIG. 3 becomes large. The width of the voltage step generated by the phase delay is sufficiently small for the carrier period and increases only the common mode voltage of the high frequency component with respect to the carrier frequency.

FIG. 5 schematically shows Vnoise, -Vfilt, and Vnoise + Vfilt when an amplitude error occurs. The sum of the voltages of the power conversion circuit 1 and the common mode filter circuit 3 Vnoise + Vfilt does not become zero, has a time width from the change of the common mode voltage to the next change, and is determined by the amount of amplitude error. A step voltage of voltage amplitude is generated. Since this step voltage includes low frequency components such as carrier frequency components, it becomes a residual factor of not only high frequency but also low frequency common mode voltage. In the following, a method of independently suppressing the common mode voltage of the high frequency component and the low frequency component by dynamically switching the phase and amplitude of the common mode compensation voltage and suppressing the influence of changes in the surrounding environment will be described.

A specific method for reducing the common mode voltage will be described with reference to FIG. The output voltage command of the common mode filter circuit 3 is given by KN × Kp × Vdc. The value of KN is (N / 3-1 / 2) described above, and is changed step by step at the timing when the N value changes, that is, at the timing when the common mode voltage changes. Kp is an amplitude error correction term (also referred to as an amplitude correction amount). First, phase correction will be described. Adjust the timing to change the KN so that the timing of the change in the common mode compensation voltage actually injected matches the change timing of the common mode voltage included in the AC voltage output from the power conversion circuit 1, that is, phase correction. do. Based on the drive information 105, the control circuit 102 actually switches the N value in the power conversion circuit 1, that is, the timing tbefore (≧ 0s) before the time when the on state of the power device constituting the power conversion circuit 1 is switched. Get N value = Nf1 with. Arbitrary delay can be given by setting Nf2 to the N value that changes with a delay of the phase correction amount T delay that is arbitrarily set for the change of the acquired N value of Nf1, and the phase can be adjusted freely. It is possible. Here, by giving KN = (Nf2) / 3-1 / 2, it is possible to match the timing of the change of KN and the change of common mode voltage.

Specifically, as shown in FIG. 6, Nf1 acquired at the timing before tbefore is delayed by the arbitrarily set Tdelay, and Nf2 is set to set KN. Next, the output voltage command KN × Kp × Vdc, which is the compensation voltage injected by the compensation voltage injector 104, is calculated, this compensation voltage is injected from the compensation voltage injector 104, and the compensation voltage is output from the power conversion circuit 1. Superimpose on voltage. When the common mode voltage on which the compensation voltage is superimposed is detected by the voltage detector 101, a waveform as shown in the lowermost stage of FIG. 6 is detected. That is, voltage vibration occurs when KN changes. When the Tdelay is changed, the voltage vibration amplitude detected by the voltage detector 101 changes. Therefore, the optimum T delay can be obtained by searching for a T delay in which the voltage vibration amplitude detected by the voltage detector 101 is minimized while changing the phase correction amount T delay. By optimizing the Tdelay, the phase delay amount Tph_delay from the common mode voltage generated in the power conversion circuit 1 of the common mode compensation voltage injected by the compensation voltage injector 104 is minimized to the compensation target 2. It is possible to suppress the high frequency common mode voltage in the supplied AC voltage.

Here, the mountain climbing method can be used as an example of the method for determining T delay. For example, the maximum value Vpp_t0 of the voltage vibration amplitude detected by the voltage detector 101 when the N value changes at time t0 and the common mode voltage changes, and then the N value changes at time t1 and the common mode voltage Compare the maximum value Vpp_t1 of the voltage vibration amplitude when is changed, and update the T delay by increasing or decreasing the value ΔT delay smaller than the T delay so that the maximum value of the voltage vibration amplitude continues to decrease. If the maximum value of the voltage vibration amplitude decreases due to the update of Tdelay, the Tdelay is changed by ΔTdelay with the same polarity as the previous time, and if the maximum value of the voltage vibration amplitude increases, the Tdelay is changed by ΔTdelay with the opposite polarity from the previous time. In this way, every time the N value changes, that is, every time the drive information changes and the common mode voltage changes, the T delay is updated and continuously changing, so that the T delay value settles near the optimum value. Become. The value of ΔT delay does not have to be a fixed value, and the value may be changed according to the situation of the optimum value search. In this way, by continuing to search for the optimum value of Tdelay each time the N value changes and the common mode voltage changes, the phase delay amount is minimized even if the optimum phase correction amount changes due to changes in the surrounding environment. Can be transformed into. As a result, it becomes possible to reduce the residual amount of the high frequency component of the common mode voltage.

In the above, the T delay is always changed by ΔT delay, but if the maximum value of the voltage vibration amplitude after updating the T delay becomes the predetermined value Vppmin or less, the T delay may be fixed. In this case, it is determined whether the maximum value of the voltage vibration amplitude is Vppmin or less each time the N value changes, and if it becomes larger than Vppmin, the T delay is changed again by ΔT delay so that the maximum value of the voltage vibration amplitude becomes Vppmin or less. It should be.

Next, the method of reducing the amplitude error will be explained. Kp is an amplitude correction amount for correcting the amplitude error of the common mode compensation voltage, and is also referred to as gain Kp. As described above, when the gain of the amplifier circuit 103 changes and an amplitude error of the common mode compensation voltage occurs, as shown in the diagram at the bottom of FIG. 6, the N value changes to cause the common mode. The amplitude deviation remains even after the voltage vibration convergence that occurs when the voltage changes. Therefore, the gain Kp is updated to update the amplitude of the compensation voltage so as to reduce the amplitude deviation after the voltage vibration converges. Specifically, for example, the common mode voltage value V_t3 immediately before the N value changes from 0 to 1 and the common mode voltage changes, and then immediately before the N value changes from 1 to 2 and the common mode voltage changes. Compare the common mode voltage value V_t4 of, and increase or decrease Kp by ΔKp so that the common mode voltage value at the latest time continues to decrease. If the common mode voltage value decreases due to the update of Kp, Kp is changed by ΔKp with the same polarity as the previous time, and if the common mode voltage value increases due to the update of Kp, Kp is changed by ΔKp with the opposite polarity from the previous time. The value of ΔKp does not have to be a fixed value, and may be switched depending on the situation of the optimum value search. Even if the optimum gain (amplitude correction amount) changes due to the influence of the surrounding environment, the optimum value can be updated in real time. As a result, it becomes possible to suppress the low frequency component of the common mode voltage.

Above, we have explained how to optimize Kp using an algorithm that reduces the deviation that occurs when the common mode voltage fluctuates. If the gain Kp can be optimized, the step fluctuation of the common mode voltage can be completely canceled, so that it is effective not only in suppressing the low frequency component but also in suppressing the high frequency component generated by the step fluctuation. Therefore, for the optimization of Kp, the algorithm used for the optimization of T delay described above, which reduces the maximum value of the voltage vibration amplitude generated when the common mode voltage fluctuates, may be used.

As explained above, by improving the phase correction amount and the amplitude correction amount, it is possible to improve the common mode voltage compensation characteristics for both the low frequency component and the high frequency component. In this control method, the compensation voltage is calculated in advance by acquiring the switching drive information from the power conversion circuit 1 in advance and restoring the common mode voltage by the compensation voltage generator 10 in the common mode filter circuit 3. can. Therefore, it can be expected that the characteristics of the high frequency compensation characteristics will be improved as compared with the conventional method in which the compensation voltage is calculated after the common mode voltage is detected. In the above, Kp and Tdelay were optimized using the mountain climbing method, but the optimization method is not limited to this, and a constant optimization method using machine learning represented by a neural network can be applied.

Here, the case where both the amplitude and the phase of the common mode voltage are corrected has been described, but if necessary, only one of them may be used. Further, if the residual amount of the common mode voltage is within a desired range, the amplitude and phase update algorithm may be stopped for a certain period of time.

FIG. 7 can be considered as an example of the control circuit 102. The control circuit 102 includes an AD converter 201, a digital arithmetic unit 202, and a DA converter 203. The AD converter 201 converts the analog signal obtained from the voltage detector 101 into a digital signal, performs arithmetic processing of the compensation waveform with the digital arithmetic apparatus 202 incorporating the amplitude correction and phase correction algorithms described above, and performs DA conversion. The compensation waveform is output to the amplifier circuit 103 by the device 203. Kp and Tdelay can be easily realized by updating the values of variables in the digital arithmetic unit 202, and can be implemented without increasing the circuit scale. It is desirable to use FPGA (Field Program Gate Array) or ASIC (Application Specific Integrated Circuit), which can perform high-speed arithmetic processing by parallel processing, for the digital arithmetic unit 202, but sequentially according to the required compensation band. A DSP (Digital Signal Processor) or a microcomputer, which is a processing control device, may be used. The control circuit 102 can switch the gain (amplitude correction amount) and the phase correction amount, and holds the gain (amplitude correction amount), the phase correction amount, the voltage vibration amplitude of the common mode voltage, and the steady value after the vibration convergence. If there is a function to compare with the value, it may be mounted only in the analog circuit or in combination with the digital circuit and the analog circuit.

Further, the communication signal of the drive information 105 from the power conversion circuit 1 to the control circuit 102 may be an analog signal or a digital signal. This signal includes the number of on elements N of the upper arm of the power conversion circuit as drive information 105. The number N of on-elements of the upper arm here means that the gate of the switching element as a power device in the power conversion circuit is on, and the feedback diode as a power device is currented during the dead time period. Including the state of flowing. Whether the current flows through the elements of the upper arm or the lower arm during the dead time is determined by the polarity of the output current. Therefore, the drive information 105 may include the number of gate-on signals, the dead time, and the current polarity of each phase, and N may be calculated in the control circuit 102. That is, the drive information 105 needs to include at least information that can recognize the on state of the power device constituting the power conversion circuit 1. The amplifier circuit 103 is assumed to be an inverting amplifier circuit and a non-inverting amplifier circuit using an operational amplifier, an emitter follower circuit using a bipolar transistor, or a circuit in which both are combined according to the compensation band and the injection power. This is not the case if there is a function to amplify the signal. It is desirable that the drive information 105 also includes a Vdc signal from the viewpoint of initial responsiveness, but by updating the gain constant, it is possible to create a pseudo state in which Vdc is reflected in the gain value. Therefore, it may be omitted.

The control circuit 102 shown in FIG. 1 is assumed to be designed exclusively for the common mode filter circuit 3, but is not limited to the control circuit 102, and is not limited to the control circuit 102. The control circuit 102 of the circuit 3 may be built in.

Embodiment 2.
FIG. 8 is a block diagram showing the configuration of the power conversion device 100 according to the second embodiment. In the second embodiment, a method for improving the common mode voltage compensation characteristic in all frequency ranges by freely setting the amplitude correction amount and the phase correction amount in an arbitrary frequency band will be described. In the common mode filter circuit 3, the optimum gain Kp and the optimum phase correction amount T delay differ depending on the frequency band. When an operational amplifier is used, the gain and phase delay amount in the low frequency region and the high frequency region are generally very different. Therefore, the frequency band that compensates for the common mode voltage is divided into n, and Kp and T delay suitable for each frequency band are set and controlled.

As an example, the gain characteristics and the phase characteristics when the frequency band to be compensated is divided into three and the Kp optimization processing is not performed and the optimization processing is performed will be described with reference to FIGS. 8 and 9. Similar to the first embodiment, in the control circuit 102, the common mode voltage KN × Kp × Vdc is restored by using the drive information 105 obtained from the power conversion circuit 1. The restored common mode voltage is divided into each of the three frequency bands as the common mode voltage in the frequency bands f1 to f4 to be compensated. Therefore, the restored common mode voltage KN × Kp × Vdc is divided by applying the filters Filt1, Filt2, and Filt3 limited to the frequency bands f1 to f2, f2 to f3, and f3 to f4, respectively, in the output filter 302. Restore as KN1 x Kp1 x Vdc, KN2 x Kp2 x Vdc, KN3 x Kp3 x Vdc for each frequency band. Although f1, f2, f3, and f4 can be set arbitrarily, it is desirable to provide them at a point where the phase or gain characteristics change by a certain amount. In FIG. 8, the output filter 302 is arranged between the control circuit 102 and the amplifier circuit 103, but the output filter 302 may be arranged in the control circuit 102 or between the amplifier circuit 103 and the compensation voltage injector 104. good. For each frequency band, the Tdelay and Kp update algorithms described in Embodiment 1 are executed to update Tdelay1 and Kp1, Tdelay2 and Kp2, and Tdelay3 and Kp3. By synthesizing the compensation waveforms for each frequency band, the waveform of the common mode compensation voltage can be obtained.

The detection waveform is also divided into three frequency bands f1 to f2, f2 to f3, and f3 to f4 by using an input filter 301 that limits the frequency band with respect to the voltage waveform detected by the voltage detector 101. The detection waveform of each frequency band is obtained. In FIG. 8, the input filter 301 is arranged between the voltage detector 101 and the control circuit 102, but the input filter 301 may be arranged in the control circuit 102. In the first embodiment, the common mode voltage of each frequency band is described so as to minimize the voltage vibration amplitude or the deviation of the amplitude when the N value changes and the common mode voltage changes in each frequency band. Execute the updated Tdelay and Kp update algorithms to update Tdelay1 and Kp1, Tdelay2 and Kp2, and Tdelay3 and Kp3. This makes it possible to optimize T delay and Kp in each frequency band component of the common mode compensation voltage. In this way, the influence of changes in the frequency characteristics of the operational amplifier and components is suppressed, and the compensation voltage waveform with the same amplitude from low frequency to high frequency and the opposite phase is output with respect to the common mode voltage generated by the power conversion circuit 1. It becomes possible to do.

It can be assumed that the common mode voltage of multiple frequency bands is selectively reduced. For example, when the power source of the power conversion circuit 1 is a three-phase diode rectifier circuit, the negative potential of the power conversion circuit fluctuates with a frequency component three times the system frequency (150 Hz or 180 Hz), so that the carrier A low frequency common mode voltage is generated with respect to the frequency. However, in order to compensate for the common mode voltage of the low frequency component, it becomes a problem to increase the capacity of the amplifier circuit 103 or the size of the transformer in order to magnetize the transformer of the compensation voltage injector 104. Further, regarding the component three times the system frequency, since it has a large impedance due to the stray capacitance on the common mode path, it is difficult to contribute to the increase of the common mode current, and it may be excluded from the compensation target.

Therefore, a method for selectively compensating for a specific frequency range will be explained. As an example, a case where the frequency band is divided into f1 to f2, f2 to f3, and f3 to f4 in order from the lowest frequency will be described with reference to FIG. The frequency bands f2 to f3 and f3 to f4 are compensated, and the frequency bands f1 to f2 including frequencies three times the system frequency (150 Hz or 180 Hz) do not compensate for Kp1 as 0, that is, the amplitude of the compensation voltage as 0. For f1 to f2, for example, even in the frequency bands f2 to f3 and f3 to f4 compensated here, if it is not necessary to completely reduce the common mode voltage, the deviation amount of the target common mode voltage should be completely reduced to zero. Allow a certain amount of width and lower the gain by freely selecting the compensation level. As a result, for example, the amplifier circuit 103, the compensating voltage injector 104, and the voltage detector 101 do not need the characteristics in the low frequency region, so that the size of the common mode filter circuit 3 can be prevented from increasing.

For convenience of explanation, the number of divisions of the frequency band shown in FIGS. 9 and 10 is set to 3, but the number of divisions is not limited to this, and a plurality of divisions (n ≧ 2) can be freely set. Further, the phase and gain division frequency ranges may be set individually.

Embodiment 3.
In the first embodiment and the second embodiment, as the power conversion circuit 1, the power conversion circuit that outputs three-phase alternating current by the three-phase full bridge conversion circuit having the upper and lower arms shown in FIG. 2 has been described as an example. However, the technique disclosed in the present application is not limited to this, as long as it is a power conversion circuit in which a common mode voltage is generated in a power conversion circuit that converts a DC voltage into an AC voltage by switching the power device on and off. It is applicable not only to a full bridge circuit or a power conversion circuit that outputs a three-phase alternating current. In the third embodiment, a method of compensating for the common mode voltage when the power conversion circuit 1 is not a three-phase full bridge conversion circuit will be described.

First, as the power conversion circuit 1, consider an N_phase phase conversion circuit in which N_phase (N_phase is an integer of 2 or more) upper and lower arm pairs are connected to a common capacitor shown in FIG. The common mode voltage is calculated by the average value of each phase output terminal voltage and can be described as (N / N_phase-1 / 2) × Vdc. Note that N indicates the number of on elements of the upper arm, and the relational expression of 0 ≦ N ≦ N_phase is established. By setting KN = (N / N_phase-1 / 2) and performing phase correction or gain Kp correction on KN according to the change in N, the common mode is performed by the same algorithm as in the first and second embodiments. The residual amount of voltage can be reduced. Therefore, the technique disclosed in the present application can be applied to a full bridge conversion circuit having a single-phase, three-phase, or more phase number.

Here, consider a multi-level conversion circuit capable of outputting a plurality of step voltages to the power conversion circuit 1. As an example, a diode clamp type three-phase three-level conversion circuit shown in FIG. 12 will be described. Output terminal of three step voltage The N_phase three-level conversion circuit that outputs the voltage connects two DC capacitors in which N_phase (N_phase is an integer of 2 or more) three-level converters are commonly connected by a power device. By switching, the output terminal voltage of each phase is controlled. For the sake of simplicity, consider a one-phase output three-level conversion circuit in which the N_phase phase in FIG. 12 is one phase. The output terminal voltage of + 1 / 2Vdc is obtained by turning on the power devices T1 and T2, 0 by turning on the power devices T2 and T3, and -1 / 2Vdc by turning on the power devices T3 and T4. Therefore, the output terminal voltage can be calculated using the gate signal information. The output terminal voltage of any 1-phase 3-level conversion circuit _{can be calculated by (N 1} / 2-1 / 2) × Vdc. Here, N _l is an integer of 0 ≤ N _l ≤ 2, and is determined by the switching pattern of the conversion circuit. Therefore, it is obtained by giving the gate information to the control device 102. Also, the common mode voltage is

It can be calculated with. Similarly, an arbitrary one-phase M-level conversion circuit is assumed. The M-level conversion circuit is equipped with M-1 DC capacitors and controls the output terminal voltage by turning on the desired power device. The output terminal voltage _{can be calculated as (N 1} / (M-1) -1 / 2) × Vdc. At this time, the common mode voltage is

It can be calculated with. Since the common mode voltage changes at the timing when _{N l of} any one phase changes,

By performing phase correction or gain correction (amplitude correction) for KN according to the change in N _l , the residual amount of common mode voltage can be reduced by the same algorithm as in the first and second embodiments. ..

As described above, the technique disclosed in the present application can be applied to a multi-level conversion circuit having a single-phase, three-phase, and more phase number. In the above, the diode clamp type multi-level conversion circuit has been shown and described, but this is not the case as long as the common mode voltage can be calculated from the drive information. For example, a multi-level conversion circuit in which a full-bridge conversion circuit and a unit conversion circuit having a DC capacitor are connected in multiple series, a multi-level conversion circuit in which a half-bridge conversion circuit and a unit conversion circuit having a DC capacitor are connected in multiple series, and a multi-level conversion circuit having different capacities. The technique disclosed in the present application can also be applied to a multi-level conversion circuit using a gradation method in which conversion circuits are connected in multiple series.

Further, in each of the above embodiments, the power conversion circuit 1 has been described with the operation of using the DC side as an input and the AC side as an output, but the operation of converting AC to DC is also disclosed in the present application. The technology is applicable.

That is, the compensating voltage generator acquires the drive information including the information that can recognize the on state of the power device constituting the power conversion circuit before the timing when the power device is switched on, and the acquired drive information and the acquired drive information. It is configured to calculate and generate a common mode compensation voltage using at least one of the phase correction amount that corrects the phase and the amplitude correction amount that corrects the amplitude, and further, the voltage is generated each time the drive information changes. If at least one of the phase correction amount and the amplitude correction amount is configured to be updated so that the common mode voltage detected by the detector is reduced, the effects described in the first and second embodiments can be obtained. be able to.

Although various exemplary embodiments and examples are described in the present application, the various features, embodiments, and functions described in one or more embodiments are of particular embodiments. It is not limited to application, but can be applied to embodiments alone or in various combinations. Therefore, innumerable variations not exemplified are envisioned within the scope of the techniques disclosed herein. For example, it is assumed that at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components of other embodiments.

1 Power conversion circuit, 3 Common mode filter circuit, 10 Compensated voltage generator, 101 Voltage detector, 104 Compensated voltage injector, 105 Drive information, T, T1, T2, T3, T4 Power device

Claims

A power conversion circuit that converts power between DC and AC by switching the power device on and off, and a common mode for canceling the common mode voltage included in the AC voltage on the AC side of this power conversion circuit. A compensation voltage generator that generates a compensation voltage, a compensation voltage injector that superimposes the common mode compensation voltage generated by the compensation voltage generator on the AC voltage, and the AC voltage on which the common mode compensation voltage is superimposed. A power converter comprising a voltage detector for detecting a common mode voltage included in the above and a common mode filter circuit having.
The compensation voltage generator is
Drive information including information that can recognize the on state of the power device constituting the power conversion circuit is acquired before the timing at which the power device is switched on, and the acquired drive information and the phase for correcting the phase are obtained. It is configured to calculate and generate the common mode compensation voltage using at least one of the correction amount and the amplitude correction amount for correcting the amplitude.
Further, at least one of the phase correction amount and the amplitude correction amount is updated to reduce the common mode compensation voltage so that the common mode voltage detected by the voltage detector decreases each time the drive information changes. A power converter configured to compute.
The power conversion device according to claim 1, wherein the power conversion circuit is a three-phase full bridge conversion circuit or a three-phase three-level conversion circuit.
The compensation voltage generator according to claim 1 or 2, wherein the compensating voltage generator updates at least one of the phase correction amount and the amplitude correction amount so that the common mode voltage detected by the voltage detector is reduced by using a mountain climbing method. Power converter.
The claimed voltage generator is configured to use machine learning to update at least one of the phase correction amount and the amplitude correction amount so that the common mode voltage detected by the voltage detector is reduced. The power conversion device according to 1 or 2.
The compensation voltage generator is configured to divide the generated common mode compensation voltage into a plurality of frequency bands and update at least one of the phase correction amount and the amplitude correction amount for each divided frequency band. The power conversion device according to any one of claims 1 to 4.
The power conversion device according to claim 5, wherein the compensation voltage generator has an amplitude of the common mode compensation voltage of a part of the plurality of frequency bands as 0.
The compensation voltage generator is configured to update at least one of the phase correction amount and the amplitude correction amount only when the common mode voltage detected by the voltage detector is equal to or higher than a predetermined value. The power conversion device according to any one of claims 1 to 6.