WO2020068022A2

WO2020068022A2 - A single phase inverter for photovoltaic panels

Info

Publication number: WO2020068022A2
Application number: PCT/TR2019/050792
Authority: WO
Inventors: Eyup AKPINAR; Abdül BALIKÇI; Buket TURAN AZİZOĞLU; Enes DURBABA
Original assignee: Dokuz Eylül Üni̇versi̇tesi̇ Rektörlüğü
Priority date: 2018-09-29
Filing date: 2019-09-25
Publication date: 2020-04-02
Also published as: WO2020068022A3

Abstract

This invention is related to a single phase inverter which enables converting the direct current voltage to alternating current voltage, allowing the energy obtained from photovoltaic (PV) panels to be transferred to the voltage of the grid, connecting to the grid voltage without using a transformer, keeping the leakage current below the standards and keeping the efficiency (ratio between output and input powers) at the rated power value up to 96 %.

Description

A SINGLE PHASE INVERTER FOR PHOTOVOLTAIC PANELS

Technical Field

This invention is related to a single phase inverter which enables converting the direct current voltage to alternating current voltage, allowing the energy obtained from photovoltaic (PV) panels to be transferred to the voltage of the grid, connecting to the grid voltage without using a transformer, keeping the leakage current below the standards and keeping the efficiency (ratio between output and input power) at the rated power value up to 96%.

State of the Art

Single phase inverters are used to produce alternating current voltage from direct current voltage. One of these uses is to transmit the direct current voltage obtained from photovoltaic panels to the grid as an alternating current voltage. If the transformer is not used between the grid and the inverter, the leakage current flows between the panels and the ground of the grid must be controlled. Today, H5 and H6 inverter structures that offer transformerless use are widely used. Figure 1 shows H6 inverter, Figure 2 shows H5 inverter, Figure 3 shows optimized H5 (oH5) inverter and Figure 4 shows improved H6 inverter circuit diagrams of structures.

In order to connect the photovoltaic panels directly to the grid, the connecting inverters must meet the grid connection standards. In Figure 5, the circuit diagram of the conventional bridge inverter structure and in Figure 6, the circuit diagram of the common mode model of the conventional bridge inverter structures is shown. When the inverter structures shown in Figure 5 and Figure 6 are examined, it is stated in the VDE0126-1-1 standards that in order not to decrease the reliability and the efficiency of the system, the magnitude of the leakage current (icm) which flows through the parasitic capacitors (Cp) and formed between the photovoltaic panel and the ground does not exceed 300mA (rms). A transformer can be used between the inverter and the grid to prevent leakage current formation. However, the usage of transformers not only increases the cost, volume and weight of the system, but also decreases efficiency of the system. When the inverter is connected to the grid without using the transformer, the voltage on the parasitic capacitor (Cp) must be set to zero or kept constant to prevent leakage current. The voltage on the parasitic capacitor (V_on)is achieved using Thevenin's equivalent and superposition methods, as in equation 1.

(Equation 1)

In this equation, V_cm ((VAO+ VBO)/2) common mode voltage, V_dm (VAO-VBO)) inverter output (differential mode) voltage, V_gCm grid common mode voltage and V_gdm expresses the voltage of the electrical network differential mode.

Since the common mode (V_gcm) and difference mode voltages (V_gdm) resulting from the grid are low frequency (50Hz-60Hz), the effects of these voltages on leakage current can be neglected. In addition, inductances (L1 , L2) used for current control between the inverter and the grid can be equally selected to eliminate the effect of differential mode. Therefore, in order to prevent leakage current formation, the common mode voltage (V_cm) should be kept at a constant value at all levels of inverter output voltage.

H6 and optimized H5 topologies shown in Figure 1 and Figure 3, in order to keep the common mode voltage constant at all levels of the inverter output voltage, the capacitor (Cdd and Cdc2) voltages used on the DC link must be equal. Therefore, the capacitor voltages can be kept equally by using capacitor voltage balancing algorithms. However, these algorithms will bring extra load to system control algorithms and need extra circuit elements (voltage sensors, resistance, diode, etc.) to read capacitor voltages. Another method to keep the capacitor voltages equal is the voltage divider resistance connected to each capacitor in parallel; however, this adversely affects the efficiency of the system.

Improved H6 structure shown in Figure 4 utilizes capacitors (IGBT collector - emitter junction capacitors) in the internal structure of semiconductor materials used in circuit topology in order to keep the common mode voltage constant at all levels of the inverter output voltage. Since the values of the capacitors in the internal structure of the semiconductor material can vary according to the working conditions, control of the common mode voltage and therefore the leakage current is difficult. In addition, the resonance that occurs during the operation of the system oscillates the common mode voltage. Although H5 inverter given in Figure 2 uses a single capacitor, the common mode voltage carries uncertainty at zero levels of output voltage and can only control the leakage current in this inverter when the power factor of load is one. These restrictions limit the usage of this inverter structure.

The patent application document No KR101514803 in the literature describes the SPWM-based single phase inverter used in a distributed power supply connected to the renewable energy grid.

The patent application document No CN 108023498 in the literature describes the hybrid H6 photovoltaic single phase inverter structure. While the hybrid H6 single phase photovoltaic inverter works, pulse width modulation performs according to two different modulation strategies.

The patent application document No US10038393 in the literature describes the new single phase, non-insulated inverter with reactive power capability. The inverter in question contains eight switching structures.

In the patent application document No US2009316458 in the literature, a structure is presented for converting direct current electrical energy into alternative current electrical energy. The feature of this structure is that it is simple, highly efficient and minimizes the problem of electromagnetic compatibility.

The patent application document No CN 107834888 in the literature describes the single-phase photovoltaic inverter of the type without transformers. The inverter in question has up to 98% conversion efficiency.

The inverters described in the above documents have different properties and none of these have the same circuit structure as the single phase inverter subject to the invention.

Consequently, due to the aforementioned deficiencies, the electrical network, which converts the direct current voltage to alternating current voltage, allows the energy obtained from photovoltaic (PV) panels to be transferred to the voltage of the grid inverter structures that are connected to the voltage without using the transformers, keep the leakage current below the standards and operate at a high conversion efficiency using a single capacitor at the panel output are needed.

The Aim of the Invention

The invention aims to solve the disadvantages mentioned about the existing circuit structures. ³ The main aim of this invention is to realize the single phase inverter, which converts direct current voltage into alternating current voltage, allowing the energy obtained from photovoltaic (PV) panels to be transferred to the voltage of the grid.

Another aim of this invention is to realize the single phase inverter that connects the voltage of the grid without the use of a transformer.

Another aim of this invention is to realize the single-phase inverter that keeps the leakage current below the standards.

Another aim of this invention is to realize the efficiency of the single phase inverter between the input and output forces at 96% under rated power conditions.

Another aim of this invention is to keep the total cost of production low.

Figure Clarifying the Invention

The structural and characteristic features of the invention and all the advantages it offers are more clearly understood in the following ways and detailed explanations.

The circuit structures of the single phase inverter developed with the current invention and the single phase inverters in the prior art are shown in attached shapes and in which;

Figure 1 is the circuit diagram of the H6 inverter of the prior art.

Figure 2 is the circuit diagram of the H5 inverter of the prior art.

Figure 3 is the circuit diagram of the optimized H5 (oH5) inverter of the prior art.

Figure 4 is the circuit diagram of the improved inverter of the prior art.

Figure 5 is a circuit diagram of the conventional bridge inverter structure of the prior art.

Figure 6 is a circuit diagram of the common mode model of the traditional bridge inverter structure of the prior art.

Figure 7 is a circuit diagram of the inventive inverter.

Figure 8 is the circuit diagram of the active current mode during the positive cycle of the inventive inverter.

Figure 9 is a circuit diagram of the freewheeling mode during the positive cycle of the inventive inverter.

Figure 10 is a circuit diagram of the active current mode during the negative cycle of the inventive inverter.

Figure 11 is a circuit diagram of the inverter's freewheeling mode during the negative cycle of the inventive inverter.

Figure 12 is the active circuit structure for snubber analysis of the inventive inverter. The circuit elements and variables in the figures are defined individually and the equivalents of these variables are given below.

1. Inverter

Vdc. DC line voltage

Idc. DC line current

Cdd . Decoupling capacitor

51 First semiconductor switch

52 Second semiconductor switch

53 Third semiconductor switch

54 Fourth semiconductor switch

55 Fifth semiconductor switch

56 Sixth semiconductor switch

57 Seventh semiconductor switch

Rs. Snubber resistance

Cs. Snubber capacitor

Is (t). Snubber Current

VCE,S7. Collector-absorber voltage of the seventh semiconductor switch

Is7. Snubber current of the seventh semiconductor switch

0. Local common ground

Cp. Parasitic capacitor

Von. Parasitic capacitor voltage

L1. First inductance

L2. Second inductance

Vg. Electrical network voltage

Ig. Electrical network current

Ls Runaway inductance

Es Snubber voltage

Detailed Description of the Invention

In this detailed description, the analysis of the single-phase inverter (1) subject to the invention, the results recorded in operation and the preferred configurations are given only for a better understanding of the subject.

This invention is related to a single phase inverter (1) which enables converting the direct current voltage to alternating current voltage, allowing the energy obtained from photovoltaic (PV) panels to be transferred to the voltage of the grid, connecting to the grid voltage (Vg) without using a transformer, keeping the leakage current below the standards and keeping the efficiency (ratio between output and input powers) at the rated power value up to 96%.

The inverter (1) according to the invention, whose circuit diagram is given in Figure 7, is in the most basic form, comprises the following; a DC connection decoupling capacitor (Cdd), which is connected in parallel to the DC line voltage (Vdc) obtained from the photovoltaic panel, thus preventing the need for voltage compensation, keeping the common mode voltage (Vgcm) constant and keeping the leakage current below the specified value in the standards,

- two snubber circuits formed as a result of the series connection of the snubber resistance (Rs), which limits the DC line current (Idc), and the snubber capacitor (Cs) that keeps the common mode voltage (Vgcm) constant by charging up to half of the DC line voltage (Vdc), a fifth semiconductor switch (S5), which is connected to the port of the decoupling capacitor (Cdd) with the positive (+) terminal of the DC line voltage (Vdc), is parallel to the first snubber circuit, has reduced switching losses due to said snubber circuit, is IGBT or semiconductors with similar switching characteristics, a sixth semiconductor switch (S6), which is connected to the port of the decoupling capacitor (Cdd) with the negative (-) terminal of the DC line voltage (Vdc), is parallel to the second snubber circuit, has reduced switching losses due to said snubber circuit, is IGBT or semiconductors with similar switching characteristics. a seventh semi-conductor (S7) which is located between the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6), is used for active clamping, freewheeling when turned on to maintain common mode voltage (Vgcm) constant flowing over a snubber current (Is7) with low average and effective values, at turn off the collector-emitter voltage (VCE, S7) is equal to the DC line voltage (Vdc), is IGBT or semiconductors with similar switching characteristics,

- the first semiconductor switch (S1) and the third semiconductor switch (S3), which are semiconductors with IGBT or similar switching properties, are connected to each other in a serial manner and parallel to the seventh semiconductor switch (S7),

- the second semiconductor switch (S2) and the fourth semiconductor switch (S4), which are semiconductors with IGBT or similar switching properties, are connected to each other in a serial manner and parallel to the seventh semiconductor switch (S7),

(Cp) which is between the negative (-) terminal of the DC line voltage (Vdc) and the neutral point of the grid voltage (Vg) and represents the parasitic capacitor of the PV panel, a first inductance (L1) which is located between the common end that is between the first semiconductor switch (S1) and the third semiconductor switch (S3) and the grid voltage (Vg) and is used for controlling the mains current (Ig) passes through the grid voltage (Vg) and a second inductance (L2) which is located between the common end between the second semiconductor switch (S2) and the fourth semiconductor switch (S4) and the grid voltage (Vg) and is used for controlling the mains current (Ig) that passes through the grid voltage (Vg).

Voltage balancing is not required due to the use of a single capacitor (Cdd) in the inverter (1) structure of the invention subject. Although the common mode voltages (Vgcm) of H6 and optimized H5 topologies are constant, capacitor voltage balancing is required due to the use of two capacitors in these inverter structures. In the improved H6 inverter structure, the resonance problem based on the use of the internal capacitors (junction capacitors) of semiconductors and the associated common mode voltage (Vgcm) oscillations have been eliminated by the proposed inverter (1) structure. While the common mode voltage (Vgcm) remains constant in the inverter (1) in the inventor's case, the leakage current is kept below the specified value in the standards. In addition, with the proposed inverter (1) structure, oscillations caused by diode clamp circuit and diode reverse recovery current are eliminated. The efficiency of the inverter (1) is around 96% at the rated power value.

The structure of the active clamped snubber-based inverter (1) was created using seven semiconductor switches (S1 , S2, S3, S4, S5, S6 and S7), as shown in Figure 7. The seventh semiconductor switch (S7) used for active clamping is only turned on to keep the common mode voltage constant at the moment of freewheeling, so a low average and effective snubber current LLT^,! switch (S7). When the seventh semiconductor switch (S7) is not conduction, the collector- emitter voltage (VQE S7) of this switch (VCE, S7) is equal to the DC line voltage (Vdc). The Snubber circuit capacitor (C_s ) keeps the common mode voltage constant by filling up to half the DC line voltage (Vdc). In addition, snubber circuits reduce the switching losses of the fifth and sixth switches (S5 and S6). The parasitic capacitor (Cp) of the photovoltaic panel is located between the negative terminal of the DC line voltage (Vd_C) and the neutral point of the grid voltage (Vg).

During a period of grid voltage (Vg), there are four different working modes of the topology of the inventor (1) of the invention subject. The modes in question include; active current mode during the positive cycle, freewheeling mode during the positive cycle, active current mode during the negative cycle and freewheeling mode during the negative cycle. The gate signals of the seven semiconductor switches (S1 , S2, S3, S4, S5, S6 and S7) that cause these modes to occur are shown in Figure 1.

Graph 1 - Switching signals (1) for the unipolar switching method for the proposed inverter. For this proposed inverter (1) topology, the gate signals of the seven semiconductor switches (S1 , S2, S3, S4, S5, S6 and S7) supplied in Graph 1 are fully compatible with the PWM ports of the digital signal processors required by the standard unipolar switching method.

The common mode voltage (Vgcm) of the inverter of the subject of invention (1) is written in VAO and VBO according to the local common point (0) in the negative terminal of the DC line voltage (Vdc). The common mode voltage in question (Vgcm) is shown in equation 2. VAO is the voltage difference between the VA terminal and the local common point (0) of the inverter (1). VBO is the voltage difference between the (1) VB terminal and the local common point (0) of the inverter.

(Equation 2)

Differential mode voltage (Vdm) in the inverter's (1) VA and VB output terminals can be written in VAO and VBO, as shown in equation 3;

(Equation 3)

Vdm-VAO-VBO

VAO; the voltage difference between the VA terminal between the first semiconductor switch (S1) and the third semiconductor switch (S3) and the dc line voltage (Vdc) negative (-) terminal and the local common point (0) at the decoupling capacitor (Odd) port is noted. VBO; the voltage difference between the VB terminal between the second semiconductor switch (S2) and the fourth semiconductor switch (S4) and the dc line voltage (Vdc) negative (-) terminal and the local common point (0) at the decoupling capacitor (Cdd) port is noted.

The switching signals for the proposed inverter (1) for sinusoidal pulse width modulation are included in Graph 1. The fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) are running simultaneously, and the seventh semiconductor switch (S7) is switched in the complementary to these switches (S5 and S6). In this case, it is clearly observed from Graph 1 that the first semiconductor switch (S1), the second semiconductor switch (S2), the third semiconductor switch (S3) and the fourth semiconductor switch (S4) are operated with a unipolar switching form.

Common mode voltage (Vgcm) can be analyzed in two intervals corresponding to a positive half-cycle of reference sinusoidal signal and a negative half-cycle. As shown in Figure 8, the first semiconductor switch (S1) is in a continuous conduction position during the positive semi-cycle of the reference sinusoidal signal, while the third semiconductor switch (S3) is in an off position.

The transmission of these two switches (S1 and S3) varies alternately. The fourth semiconductor switch (S4), the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) and the second semiconductor switch (S2) are operated at the frequency of the carrier wave (switch frequency) complementary with each other. The value of the common mode voltage (Vgcm) in the meantime is obtained as shown in equation 4.

(Equation 4)

During the positive half cycle of the reference sinusoidal signal, the fourth semiconductor switch (S4) is opened to obtain the freewheeling path, the second semiconductor switch (S2) is turned on and the inverter (1) output voltage is zero. In addition, the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) are turned off and the seventh semiconductor switch (S7), the active clamping switch, is simultaneously turned on to keep the common mode voltage (Vgcm) constant.

During the transmission of the seventh semiconductor switch (S7), the current Is (t) flows through the snubber circuit, as shown in Figure 9, until the voltage value of the snubber capacitor (Cs) reaches half of the DC line voltage (Vdc). The value of the common mode voltage (Vgcm) in the meantime is obtained as shown in equation 5.

(Equation 5)

During the negative semi-cycle of the reference sinusoidal signal, the active current path is shown in Figure 10. In this case, the second semiconductor switch (S2) is in continuous conduction and the fourth semiconductor switch (S4) is off state. The second switch (S2) and the fourth semiconductor switch (S4) are commuted alternately. In this mode, the value of common mode voltage (Vgcm) is obtained as shown in equation 6.

(Equation 6)

v (0+Vdc) Vdc

V^cm 2 2

In freewheeling mode during the negative semi-cycle of the reference sinusoidal signal, the constant common mode voltage is achieved as shown in Figure 11. Since the two snubber circuits are equivalent, the voltage value on each is equal to half of the DC line voltage (Vdc). Therefore, in this mode, the value of the common mode voltage (Vgcm) is obtained as shown in equation 7.

(Equation 7)

(¾ ¾) _v<k

^{V cm} 2 2

In all operating modes of unipolar switching, the common mode voltage (Vgcm) is constant and equals half of the DC line voltage (Vdc) ( v_cm= ^Vdc/₂)_·

The snubber circuit allows the inverter (1) to keep constant common mode voltage (Vgcm) without oscillations during freewheeling periods. The voltages on the Snubber circuits are shared equally half value through the DC line voltage (Vdc) level, ensuring that the seventh semiconductor switch (S7) is turned on. If the seventh semiconductor switch (S7) switch had not been turned on, no current (Is (t)) would flow through the snubber circuits at the time of freewheeling, so the snubber capacitors (Cs) would not be charged.

The active circuit structure for Snubber analysis is shown in Figure 12. Snubber resistance (Rs), snubber condenser (Cs) and stray inductance (Ls) circuit on the DC line side form a circuit. Differential equations analyzing this circuit are shown in equations 8 and equation 9.

(Equation

(D

(Equation 9)

Here D = d/dt and snubber voltage is es. Damping Coefficient

Resonance frequency, w₀ = 1 /^/L_SC_S

The snubber current t_s(t) for the (underdamped) is (0 < x < 1)

(Equation 10)

Here w =

current wave forms, Rs = 1 ohm and Rs = 5 Ohm is recorded at two different snubber resistance value, snubber capacitor (Cs) at 22 nF and when inverter (1) is running at nominal load (1 kW output power).

When these snubber parameters are used, underdamped response has been observed in recorded snubber current waveforms. The mathematical expression of the Snubber current waveform is given in equation 10. The stray inductance is calculated as

0.7 mH using the resonant frequency in the missing underdamped response mode of Ls. The snubber resistance is then fixed to 10 ohm snubber resistance to achieve a critically damped response that causes minimal effect on the icm of the leakage current. The mathematical expression of the snubber current for critically damped response is given in equation 1 1. The results measured through the snubber circuit designed for the critically damped state are shown in Graph 2 when the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) are turned off. The initial value of the Snubber current is zero and has two critically damped waves in each turning off. The first wave occurs after the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) are simultaneously turned off. The second current wave appears when the seventh semiconductor switch (S7) is turned on after the 1.3 micro second dead time period between the seventh semiconductor switch (S7) and the sixth semiconductor switch (S6). For a critically damped response ( x =

1) state, the snubber current is like t_s(t) in equation 1 1.

(Equation 11)

The initial value of the Snubber current ( t_s(0)) equals to zero. Therefore

Stored energy in snubber capacitor (Cs) can be calculated as follows;

Here, f_sw is the switching frequency of IGBTs.

Graph 2 contains results measured through the snubber circuit when the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) are out of transmission. In Graph 2, a) section of the snubber circuit voltage of the sixth semiconductor switch (S6) of the sixth semiconductor switch (S6), b) section of the snubber circuit current (Is) of the sixth semiconductor switch (S6) of section B, c) section of the snubber circuit voltage of the fifth semiconductor switch (S5) of the c section (Es) d) section of the collector-absorber voltage (VCE, S7) of the sevenll® semiconductor switch (S7) is specified.

Graph 3 contains the results measured through the snubber circuit during turn on of the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6).

Graph 3 a) section of the snubber circuit voltage of the sixth semiconductor switch (S6), b) section of the snubber circuit current of the sixth semiconductor switch (S6), the c) section of the seventh semiconductor switch (S7) collector-emitter voltage (VCE,S7) and d) section of the seventh semiconductor switch (S7) the collector-emitter current (Is7) is indicated.

Graph 4 includes simulation of the proposed inverter (1) and experimental results (below) of the proposed inverter (1) in Graph 5. In Graph 4 and Graph 5, a) section of inverter (1) output voltage (Vg) and output current (Ig) (by network), b) section of VAO, c) section of VBO and d) section of (2x common mode voltage (Vgcm)) refers to VAO + VBO.

Graph 2- Results measured over the snubber circuit during turn off interval of the

fifth semiconductor switch (S5) and the sixth semiconductor switch (S6)

Graph 3 - Results measured over the snubber circuit during turn on interval of the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6)

Graph 4 - Simulation of the proposed inverter (1)

Graph 5 - Experimental results of the proposed inverter (1)

Claims

1. A single phase inverter which enables converting the direct current voltage to alternating current voltage, allowing the energy obtained from photovoltaic (PV) panels to be transferred to the voltage of the grid, connecting to the grid voltage without using a transformer, keeping the leakage current below the standards and keeping the efficiency ratio between output and input powers (efficiency) at the rated power value up to 96%, characterized in that it comprises the following;.

- A DC connection decoupling capacitor (Cdd), which is connected in parallel to the DC line voltage (Vdc) obtained from the photovoltaic panel, thus preventing the need for voltage compensation, keeping the common mode voltage (Vgcm) constant and keeping the leakage current below the specified value in the standards,

Two snubber circuits formed as a result of the series connection of the snubber resistance (Rs), which limits the DC line current (Idc), and the snubber capacitor

(Cs), that keeps the common mode voltage (Vgcm) constant by filling up to half of the DC line voltage (Vdc),

- A Fifth semiconductor switch (S5), which is connected to the port of the decoupling capacitor (Cdd) with the positive (+) terminal of the DC line voltage (Vdc), is parallel to the first snubber circuit, has reduced switching losses due to said snubber circuit, isIGBT or semiconductors with similar switching characteristics,

- A sixth semiconductor switch (S6), which is connected to the port of the decoupling capacitor (Cdd) with the negative (-) terminal of the DC line voltage (Vdc), is parallel to the second snubber circuit, has reduced switching losses due to said snubber circuit, is IGBT or semiconductors with similar switching characteristics.

- A seventh semi-conductor (S7) which is located between the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) area, is used for active clamping only freewheeling when turned on to maintain common mode voltage (Vgcm) constant, flowing over a snubber current (Is7) with low average and effective values, at non conducting state the collector-emitter voltage (VCE, S7) is equal to the DC line voltage (Vdc), is IGBT or semiconductors with similar switching characteristics,

- the first semiconductor switch (S1) and the third semiconductor switch (S3), which are IGBT or semiconductors with IGBT or similar switching properties, are connected to each other in a serial manner and parallel to the seventh semiconductor switch (S7), the second semiconductor switch (S2) and the fourth semiconductor switch (S4), which are IGBT or semiconductors with IGBT or similar switching properties, are connected to each other in a serial manner and parallel to the seventh semiconductor switch (S7),

(Cp) which is between the negative (-) terminal of the DC line voltage (Vdc) and the neutral point of the grid voltage (Vg) and represents the parasitic capacitor of the PV panel, the first inductance (L1) which is located between the common end that is between the first semiconductor switch (S1) and the third semiconductor switch (S3) and the grid voltage (Vg) and is used for controlling the mains current (Ig) passes through the electrical network voltage (Vg) and the second inductance (L2) which is located between the common end between the second semiconductor switch (S2) and the fourth semiconductor switch (S4) and the grid voltage (Vg) and is used for controlling the mains current (Ig) that passes through the electrical network voltage (Vg).

2. An inverter (1) according to claim 1 , characterized in that; in case VA0 states the voltage difference between the VA terminal located between the first semiconductor switch (S1) and the third semiconductor switch (S3) and the negative (-) terminal of the DC line voltage (Vdc) and the local common point (0) at the connection point of the decoupling capacitor (Cdd) and VB0 states the voltage difference between VB terminal between the second semiconductor switch (S2) and the fourth semiconductor switch (S4) and the DC line voltage (Vdc) negative (-) terminal and the local common point (0) at the connection point of the decoupling capacitor (Cdd), the common mode voltage is the value obtained from the equation V_Cm=(VAo⁺V_Bo)/2 and the differential mode voltage (Vdm) at the VA and VB output terminals is the value obtained from Vdm=V_Ao-V_Bo·

3. An inverter (1) according to claim 1, characterized in that; it comprises for the sinusoidal pulse width modulation, a fifth semiconductor switch (S5) which operates simultaneously and a sixth semiconductor switch (S6),a seventh semiconductor switch (S7) which is switched in complementary to these switches (S5 and S6), a first semiconductor switch (S1), the second semiconductor switch (S2), third semiconductor switch (S3) and fourth semiconductor switch (S4) which are operated with a unipolar switching form.

4. An inverter (1) according to claim 1, characterized in that; it comprises seven semiconductor switches (S1 , S2, S3, S4, S5, S6 and S7) which form during the period of grid voltage (Vg), four different operating modes as the active current mode during the positive cycle, freewheeling mode during the positive cycle, active current mode during negative cycle and freewheeling mode during negative cycle and which are t are fully compatible with the PWM ports of the digital signal processors which are required by the standard unipolar switching method of the gate signals.

5. An inverter (1) according to claim 4, characterized in that; during the positive semi-cycle of the reference sinusoidal signal, it comprises the first semiconductor switch (S1), whose transmissions change alternately, i.e. one in a conduction position at all time, the other in an off position and third semiconductor switch (S3), the fourth semiconductor switch

(54), which is operated complementary with the second semiconductor switch (S2) and at the frequency of the carrier wave (switching frequency), fifth semiconductor switch

(55) and sixth semiconductor switch (S6) and the value of common mode voltage

(Vgcm) is derived from the V_cm

= -y equation as a result of the work carried out

in this way.

6. An inverter (1) according to claim 4, characterized in that; to obtain the freewheeling path during the positive half-cycle of the reference sinusoidal signal, the second semiconductor switch (S2), which is in the conduction position while the fourth semiconductor switch (S4) is off and thus ensures that the output voltage is zero, the fifth semiconductor switch (S5) and the sixth semiconductor switch (S6) which are off state, the seventh semiconductor switch (S7), which is clamping switch, simultaneously turned on and as a result of this work, the current Is (t) flows through the snubber circuit until the voltage value of the snubber capacitor (Cs) reaches half of the DC line voltage (Vdc) flow and the value of the

(Vdcj Jdcj )

common mode voltage (Vgcm) is the value derived from the V_cm = -— -— - ^l equation.

7. An inverter (1) according to claim 4, characterized in that; during the negative half-cycle of the reference sinusoidal signal, it comprises second semiconductor switch (S2) which is alternately transmitted and a fourth semiconductor switch (S4) and as a result of this work, the value of the common mode voltage (Vgcm) is the value obtained from the V_cm

equation.

8. An inverter (1) according to claim 4, characterized in that; in freewheeling mode during the negative half-cycle of the reference sinusoidal signal, the value of common mode voltage (Vgcm) is the value derived from the V_r,

equation because the voltage value per-second is

2 2

equal to half of the DC line voltage (Vdc), as the two snubber circuits are equivalent

9. An inverter (1) according to claim 1 , characterized in that; during the freewheeling periods, it comprises seventh semiconductor switch (S7) which ensures that the voltages on the snubber circuits that remain at constant common mode voltage (Vgcm) without fluctuations, are shared equally by half of the DC line voltage (Vdc) level and allows current (Is (t)) to flow through the snubber circuits and charge from the snubber capacitors (Cs).