WO2017157271A1

WO2017157271A1 - Multilevel inverters

Info

Publication number: WO2017157271A1
Application number: PCT/CN2017/076559
Authority: WO
Inventors: Ka Wai Eric Cheng; Raghu Raman SEKHAR; Yuanmao YE
Original assignee: The Hong Kong Polytechnic University
Priority date: 2016-03-14
Filing date: 2017-03-14
Publication date: 2017-09-21

Abstract

A multilevel inverter is disclosed. The multilevel inverter may include: a switched capacitor inverter configured to output a unipolar sequence of DC voltages; and a full bridge inverter configured to receive the unipolar sequence of DC voltages and to output a bipolar sequence of DC voltages.

Description

MULTILEVEL INVERTERS

PRIORITY CLAIMS

The present application claims priority to United States of America provisional patent application number 62,307,590. The present application furthermore claims priority to United States of America provisional patent application number 62,307,591.

TECHNICAL FIELD

The following discloses a multilevel inverter. In particular, a multilevel inverter with a switched-capacitor inverter and a full bridge inverter may be provided.

BACKGROUND ART

Power distribution systems with frequencies above utility frequency (50 Hz or 60 Hz) are traditionally referred to as high frequency AC (alternating current) power distribution systems. High frequency AC power distribution systems find application for example in aerospace, telecommunication, lighting, computer power supply, micro-grids and auxiliary power supply units for automotive. High frequency AC power distribution systems offer significant advantages over conventional direct current (DC) power distribution systems and low frequency alternating current power distribution systems.

However, presently used systems suffer for example from the requirement of a high number of components. Thus, there is a want for improved systems.

Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.

SUMMARY OF INVENTION

According to an aspect of the invention, multilevel inverter is disclosed. The multilevel inverter may include: a switched capacitor inverter configured to output a unipolar sequence of DC voltages； and a full bridge inverter configured to receive the unipolar sequence of DC voltages and to output a bipolar sequence of DC voltages.

According to various embodiments, the unipolar sequence may include or may be a periodic sequence. According to various embodiments, the unipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence. According to various embodiments, the bipolar sequence may include or may be a periodic sequence. According to various embodiments, the bipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.

According to various embodiments, the switched capacitor inverter may include or may be a charge pump. According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source. According to various embodiments, the switched capacitor inverter may be configured to be connected to a plurality of voltage sources.

According to various embodiments, the full bridge inverter may be configured to selectively pass through the DC voltages of the unipolar sequence or to negate the DC voltages of the unipolar sequence.

According to various embodiments, the switched capacitor inverter may be configured to be connected to a first voltage source and to a second voltage source. According to various embodiments, the switched capacitor inverter may include a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a first diode, a second diode and a capacitor.

According to various embodiments, the first switched capacitor inverter switch may be connected to the second voltage source, the second diode, and the second switched capacitor inverter switch； the second switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second diode, the capacitor, and the third switched capacitor inverter switch； the third switched capacitor inverter switch may be connected to the first voltage source, the second voltage source, the second switched capacitor inverter switch, the capacitor, and the full bridge inverter； the first diode may be connected to the first voltage source and the second diode； the second diode may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the first diode, and the capacitor； and the capacitor may be connected to the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first diode, the second diode, and the full bridge inverter.

According to various embodiments, the unipolar sequence may include or may be DC voltages of four different levels corresponding to a zero voltage, a voltage of the first voltage source, a voltage of the second voltage source, and a sum of the voltage of the first voltage source and the voltage of the second voltage source. According to various embodiments, the bipolar sequence may include or may be DC voltages of seven different levels corresponding to a zero voltage, the voltage of the first voltage source, the voltage of the second voltage source, the sum of the voltage of the first voltage source and the voltage of the second voltage source, an inverted voltage of the first voltage source, an inverted voltage of the second voltage source, and an inverted sum of the voltage of the first voltage source and the voltage of the second voltage source.

According to various embodiments, the switched capacitor inverter may be configured to output a voltage of the first voltage source to the full bridge inverter if the third switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an off state. According to various embodiments, the switched capacitor inverter may be configured to output a voltage of the second voltage source to the full bridge inverter if the first switched capacitor inverter switch is in an on state and the second switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state. According to various embodiments, the switched capacitor inverter may be configured to output a voltage corresponding to a sum of the voltage of the first voltage source and the voltage of the second voltage source to the full bridge inverter if the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an on state and the third switched capacitor inverter switch is in an off state.

According to various embodiments, the switched capacitor inverter may include or may be a voltage increaser configured to selectively increase a voltage of at least one of the first voltage source or the second voltage source. According to various embodiments, the switched capacitor inverter may include or may be a voltage doubler configured to selectively double a voltage of at least one of the first voltage source or the second voltage source. According to various embodiments, the switched capacitor inverter may include or may be a voltage reducer configured to selectively reduce a voltage of at least one of the first voltage source or the second voltage source. According to various embodiments, the switched capacitor inverter may include or may be a voltage reducer configured to selectively half a voltage of at least one of the first voltage source or the second voltage source.

According to various embodiments, the unipolar sequence may include or may be DC voltages of five different levels； and the bipolar sequence may include or may be DC voltages of nine different levels.

According to various embodiments, the switched capacitor inverter may be configured to be connected to at least three voltage sources； and the switched capacitor inverter may be configured to selectively output voltages corresponding to combinations of voltages of the three voltage sources to the full bridge inverter.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a relay. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a transistor. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a bipolar junction transistor. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.

According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source； and the switched capacitor inverter may include or may be a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a fourth switched capacitor inverter switch, a first diode, a second diode, a first capacitor, and a second capacitor.

According to various embodiments, the first switched capacitor inverter switch may be connected to the voltage source, the first diode, the first capacitor, the second switched capacitor inverter switch, and the fourth switched capacitor inverter switch； the second switched capacitor inverter switch may be connected to the voltage source, to the first switched capacitor inverter switch, to the first capacitor, to the fourth switched capacitor inverter switch, and to the full bridge inverter； the third switched capacitor inverter switch may be connected to the fourth switched capacitor inverter switch, the first diode, the second diode, the first capacitor, and the second capacitor； the fourth switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first capacitor, and the second capacitor； the first diode may be connected to the voltage source, the first switched capacitor inverter switch, the third switched capacitor inverter switch, and the second diode； the second diode may be connected to the third switched capacitor inverter switch, the first diode, the first capacitor, the second capacitor, and the full bridge inverter； the first capacitor may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the fourth switched capacitor inverter switch, the first diode, and the second diode； and the second capacitor may be connected to the third switched capacitor inverter switch, the fourth switched capacitor inverter switch, the second diode, and the full bridge inverter.

According to various embodiments, the unipolar sequence may include or may be DC voltages of four different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source； and the bipolar sequence may include or may be DC voltages of seven different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source, an inverted voltage of the voltage source, an inverted doubled voltage of the voltage source, and an inverted tripled voltage of the voltage source.

According to various embodiments, the switched capacitor inverter may be configured to output a voltage of the voltage source to the full bridge inverter if the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an on state and the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state. According to various embodiments, the switched capacitor inverter may be configured to output a doubled voltage of the voltage source to the full bridge inverter if the first switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch are in an off state. According to various embodiments, the switched capacitor inverter may be configured to output a tripled voltage of the voltage source to the full bridge inverter if the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an on state and the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an off state.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a relay.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a transistor. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a bipolar junction transistor. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor. According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.

According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source； and the switched capacitor inverter may include or may be a plurality of voltage increasers configured to selectively increase a voltage of the voltage source.

According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source； and the switched capacitor inverter may include or may be a plurality of voltage doublers configured to selectively double a voltage of the voltage source.

According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source； and the switched capacitor inverter may include or may be a plurality of voltage reducers configured to selectively reduce a voltage of the voltage source.

According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source； and the switched capacitor inverter may include or may be a plurality of voltage reducers configured to selectively half a voltage of the voltage source.

According to various embodiments, the full bridge inverter may include a first full bridge inverter switch, a second full bridge inverter switch, a third full bridge inverter switch, and a fourth full bridge inverter switch.

According to various embodiments, the first full bridge inverter switch may be connected to the switched capacitor inverter the second full bridge inverter switch, the fourth full bridge inverter switch, and an output of the full bridge inverter； the second full bridge inverter switch may be connected to the switched capacitor inverter, the first full bridge inverter switch, the third full bridge inverter switch, and the output； the third full bridge inverter switch may be connected to the switched capacitor inverter, the second full bridge inverter switch, the fourth full bridge inverter switch, and the output； and the fourth full bridge inverter switch may be connected to the switched capacitor inverter, the first full bridge inverter switch, the third full bridge inverter switch, and the output.

According to various embodiments, the full bridge inverter may be configured to output a voltage received from the switched capacitor inverter if the first full bridge inverter switch and the third full bridge inverter switch are in an on state and the second full bridge inverter switch and the fourth full bridge inverter switch are in an off state.

According to various embodiments, the full bridge inverter may be configured to invert a voltage received from the switched capacitor inverter and output the inverted voltage if the second full bridge inverter switch and the fourth full bridge inverter switch are in an on state and the first full bridge inverter switch and the third full bridge inverter switch are in an off state.

According to various embodiments, the full bridge inverter may be configured to output a zero voltage after having output a positive voltage with the first full bridge inverter switch in an on state and the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch in an off state.

According to various embodiments, a body diode associated with the second full bridge inverter switch may be configured to provide freewheeling.

According to various embodiments, the full bridge inverter may be configured to output a zero voltage after having output a negative voltage with the fourth full bridge inverter switch in an on state and the first full bridge inverter switch, the second full bridge inverter switch, and the third full bridge inverter switch in an off state.

According to various embodiments, a body diode associated with the fourth full bridge inverter switch may be configured to provide freewheeling.

According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a relay.

According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a transistor. According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a bipolar junction transistor. According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be an insulated-gate bipolar transistor. According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to illustrate various embodiments, by way of example only, and to explain various principles and advantages in accordance with a present embodiment.

Figure 1 shows a multilevel inverter in accordance with an embodiment of the invention.

Figure 2 shows a topology of a high frequency multilevel inverter according to various embodiments.

Figure 3A to Figure 3H show topological stages of a seven level switched-capacitor multilevel inverter according to various embodiments.

igure 4 shows a simulation model according to various embodiments.

Figure 5 shows a diagram illustrating a 50 kHz multilevel (seven) staircase output voltage of an inverter according to various embodiments.

Figure 6 shows a nine level switched–capacitor based multilevel inverter (MLI) according to various embodiments.

Figure 7 shows a nine level switched–capacitor based MLI according to various embodiments.

Figure 8 shows an illustration of a generalized topology for a switched capacitor based multilevel inverter (SCMLI) according to various embodiments.

Figure 9 shows a topology of a high frequency multilevel inverter according to various embodiments.

Figure 10A to Figure 10H show illustrations of topological stages of a seven level switched–capacitor multilevel inverter according to various embodiments.

Figure 11 shows a simulation model according to various embodiments.

Figure 12 shows a diagram illustrating a 50 kHz multilevel (seven) staircase output voltage of an inverter according to various embodiments.

Figure 13A shows a nine level switched–capacitor based MLI according to various embodiments.

Figure 13B and Figure 13C show higher level switched-capacitor multilevel inverters according to various embodiments.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been depicted to scale. For example, the dimensions of some of the elements in the block diagrams or steps in the flowcharts may be exaggerated in respect to other elements to help improve understanding of the present embodiment.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description. It is the intent of the preferred embodiments to disclose a method and system which is able to efficiently generate AC (alternating current) voltages.

Power distribution systems with frequencies above utility frequency (50 Hz or 60 Hz) are traditionally referred to as high frequency AC power distribution systems (HFAC PDS) . HFAC PDS find application for example in aerospace, telecommunication, lighting, computer power supply, micro-grids and auxiliary power supply units for automotive. HFAC PDS offer significant advantages over conventional direct current (DC) PDS and low frequency alternating current PDS. An advantage of HFAC PDS over DC PDS is that HFAC PDS eliminate the need for a rectifier stage in the front end power supply system, and the need for an inverter in the point of load power supply. Advantageously, this reduction in the number of power conversion stages translates to fewer components, higher efficacy/efficiency, lower cost and better reliability.

Multilevel inverters (MLIs) are used in the power industry owing to benefits they present. With MLIs, it is easier to produce a high power, high voltage AC output with a multilevel topology as the voltage stress on the individual device is controlled. Advantageously, it is furthermore possible to obtain higher voltages with low harmonics without employing transformers. The harmonic content may be mitigated by increasing the number of voltage levels in the AC output. Multilevel inverters are generally classified into diode–clamped, flying–capacitors (also called capacitor–clamped) and cascaded types. Popular PWM (pulse width modulation) strategies include space vector modulation, multilevel selective harmonic elimination and multilevel sinusoidal pulse width modulation.

Switched–capacitor converters have drawn attention due to their simplicity, low weight and low cost features. They employ switches and capacitors to achieve voltage conversion. Since they eliminate the need for bulky inductors, they are usually small in size and extremely lighter. These features allow switched–capacitor converters to be also fabricated into ICs (integrated circuits) .

According to various embodiments, a switched–capacitor converter (in other words: a switched-capacitor inverter) may be provided in a multilevel inverter to realize a circuitry that outputs a staircase high frequency AC waveform. According to various embodiments, a switched–capacitor based front end DC level shifter may enable a system to obtain multiple voltage levels to realize a multilevel inverter.

Advantageously, according to various embodiments, an inverter is provided which uses a reasonable number of capacitors, and can be operated without relying on PWM (pulse width modulation) , in contrast to commonly used inverters which use a high number of switches and which use complex PWM techniques.

According to various embodiments, a topology of multilevel inverters for high frequency AC applications may be provided. The multilevel inverters according to various embodiments may employ a switched–capacitor technique. Advantageously, the multilevel inverters according to various embodiments may include an inverter front end including a switched–capacitor based DC (direct current) level shifter that produces multiple DC levels at the DC bus of the inverter. Advantageously, the multilevel inverters according to various embodiments may further include a full bridge inverter which obtains different voltage levels at the output.

Figure 1 shows a multilevel inverter 100 according to various embodiments. The multilevel inverter 100 may include a switched capacitor inverter 102 configured to output a unipolar sequence of DC voltages. The multilevel inverter 100 may further include a full bridge inverter 104 configured to receive the unipolar sequence of DC voltages and to output a bipolar sequence of DC voltages. The switched capacitor inverter 102 and the full bridge inverter 104 may be connected, like illustrated by line 106, for example electrically connected.

In other words, advantageously, the full bridge inverter 104 of the multilevel inverter 100 receives a sequence of DC voltages of a single polarity from the switched capacitor inverter 102, and generates a sequence of DC voltages of two different polarities based on (in other words: from) the received sequence of DC voltages of the single polarity. In other words, the full bridge inverter 104 of the multilevel inverter 100 converts a sequence of DC voltages of a single polarity received from the switched capacitor inverter 102 into a sequence of DC voltages of two different polarities.

According to various embodiments, the unipolar sequence may include or may be a periodic sequence.

According to various embodiments, the unipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.

According to various embodiments, the unipolar sequence may include or may be DC voltages of a single pre-determined polarity.

According to various embodiments, the bipolar sequence may include or may be a periodic sequence.

According to various embodiments, the bipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.

According to various embodiments, the bipolar sequence may include or may be DC voltages of two different polarities.

According to various embodiments, the switched capacitor inverter 102 may include or may be a charge pump.

According to various embodiments, the switched capacitor inverter 102 may include a plurality of capacitors.

According to various embodiments, the switched capacitor inverter 102 may be free from inductors.

According to various embodiments, the unipolar sequence may be free from pulse width modulation signals.

According to various embodiments, the bipolar sequence may be free from pulse width modulation signals.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a single voltage source. Advantageously, generating the multilevel voltages from a single voltage source reduces complexity of the input to the multilevel inverter

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a plurality of voltage sources.

According to various embodiments, the full bridge inverter 104 may be configured to selectively pass through the DC voltages of the unipolar sequence or to negate the DC voltages of the unipolar sequence.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a first voltage source and to a second voltage source. According to various embodiments, the switched capacitor inverter 102 may include a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a first diode, a second diode and a capacitor.

According to various embodiments, the first switched capacitor inverter switch may be connected to the second voltage source, the second diode, and the second switched capacitor inverter switch； the second switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second diode, the capacitor, and the third switched capacitor inverter switch； the third switched capacitor inverter switch may be connected to the first voltage source, the second voltage source, the second switched capacitor inverter switch, the capacitor, and the full bridge inverter 104； the first diode may be connected to the first voltage source and the second diode； the second diode may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the first diode, and the capacitor； and the capacitor may be connected to the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first diode, the second diode, and the full bridge inverter 104.

According to various embodiments, the switched capacitor inverter 102 may be configured to output a voltage of the first voltage source to the full bridge inverter 104 if the third switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an off state.

According to various embodiments, the switched capacitor inverter 102 may be configured to output a voltage of the second voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch is in an on state and the second switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.

According to various embodiments, the switched capacitor inverter 102 may be configured to output a voltage corresponding to a sum of the voltage of the first voltage source and the voltage of the second voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an on state and the third switched capacitor inverter switch is in an off state.

According to various embodiments, the switched capacitor inverter 102 may include or may be a voltage increaser configured to selectively increase a voltage of at least one of the first voltage source or the second voltage source.

According to various embodiments, the switched capacitor inverter 102 may include or may be a voltage doubler configured to selectively double a voltage of at least one of the first voltage source or the second voltage source.

According to various embodiments, the switched capacitor inverter 102 may include or may be a voltage reducer configured to selectively reduce a voltage of at least one of the first voltage source or the second voltage source.

According to various embodiments, the switched capacitor inverter 102 may include or may be a voltage reducer configured to selectively half a voltage of at least one of the first voltage source or the second voltage source.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to at least three voltage sources； and the switched capacitor inverter 102 may be configured to selectively output voltages corresponding to combinations of voltages of the three voltage sources to the full bridge inverter 104.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a relay.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a transistor.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a bipolar junction transistor.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a single voltage source； and the switched capacitor inverter 102 may include or may be a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a fourth switched capacitor inverter switch, a first diode, a second diode, a first capacitor, and a second capacitor.

According to various embodiments, the first switched capacitor inverter switch may be connected to the voltage source, the first diode, the first capacitor, the second switched capacitor inverter switch, and the fourth switched capacitor inverter switch； the second switched capacitor inverter switch may be connected to the voltage source, to the first switched capacitor inverter switch, to the first capacitor, to the fourth switched capacitor inverter switch, and to the full bridge inverter 104； the third switched capacitor inverter switch may be connected to the fourth switched capacitor inverter switch, the first diode, the second diode, the first capacitor, and the second capacitor； the fourth switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first capacitor, and the second capacitor； the first diode may be connected to the voltage source, the first switched capacitor inverter switch, the third switched capacitor inverter switch, and the second diode； the second diode may be connected to the third switched capacitor inverter switch, the first diode, the first capacitor, the second capacitor, and the full bridge inverter 104； the first capacitor may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the fourth switched capacitor inverter switch, the first diode, and the second diode； and the second capacitor may be connected to the third switched capacitor inverter switch, the fourth switched capacitor inverter switch, the second diode, and the full bridge inverter 104.

According to various embodiments, the switched capacitor inverter 102 may be configured to output a voltage of the voltage source to the full bridge inverter 104 if the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an on state and the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.

According to various embodiments, the switched capacitor inverter 102 may be configured to output a doubled voltage of the voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch are in an off state.

According to various embodiments, the switched capacitor inverter 102 may be configured to output a tripled voltage of the voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an on state and the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an off state.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a transistor.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a bipolar junction transistor.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor.

According to various embodiments, one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a single voltage source； and the switched capacitor inverter 102 may include or may be a plurality of voltage increasers configured to selectively increase a voltage of the voltage source.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a single voltage source； and the switched capacitor inverter 102 may include or may be a plurality of voltage doublers configured to selectively double a voltage of the voltage source.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a single voltage source； and the switched capacitor inverter 102 may include or may be a plurality of voltage reducers configured to selectively reduce a voltage of the voltage source.

According to various embodiments, the switched capacitor inverter 102 may be configured to be connected to a single voltage source； and the switched capacitor inverter 102 may include or may be a plurality of voltage reducers configured to selectively half a voltage of the voltage source.

According to various embodiments, the full bridge inverter 104 may include a first full bridge inverter switch, a second full bridge inverter switch, a third full bridge inverter switch, and a fourth full bridge inverter switch.

According to various embodiments, the first full bridge inverter switch may be connected to the switched capacitor inverter 102, the second full bridge inverter switch, the fourth full bridge inverter switch, and an output of the full bridge inverter； the second full bridge inverter switch may be connected to the switched capacitor inverter 102, the first full bridge inverter switch, the third full bridge inverter switch, and the output； the third full bridge inverter switch may be connected to the switched capacitor inverter 102, the second full bridge inverter switch, the fourth full bridge inverter switch, and the output； and the fourth full bridge inverter switch may be connected to the switched capacitor inverter 102, the first full bridge inverter switch, the third full bridge inverter switch, and the output.

According to various embodiments, the full bridge inverter 104 may be configured to output a voltage received from the switched capacitor inverter 102 if the first full bridge inverter switch and the third full bridge inverter switch are in an on state and the second full bridge inverter switch and the fourth full bridge inverter switch are in an off state.

According to various embodiments, the full bridge inverter 104 may be configured to invert a voltage received from the switched capacitor inverter 102 and output the inverted voltage if the second full bridge inverter switch and the fourth full bridge inverter switch are in an on state and the first full bridge inverter switch and the third full bridge inverter switch are in an off state.

According to various embodiments, the full bridge inverter 104 may be configured to output a zero voltage after having output a positive voltage with the first full bridge inverter switch in an on state and the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch in an off state.

According to various embodiments, the full bridge inverter 104 may be configured to output a zero voltage after having output a negative voltage with the fourth full bridge inverter switch in an on state and the first full bridge inverter switch, the second full bridge inverter switch, and the third full bridge inverter switch in an off state.

According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a transistor.

According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a bipolar junction transistor.

According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be an insulated-gate bipolar transistor.

According to various embodiments, one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.

According to various embodiments, a switched capacitor based multilevel inverter for high frequency AC power distribution systems may be provided. According to various embodiments, a dual input switched capacitor based multilevel inverter for high frequency AC power distribution systems may be provided.

According to various embodiments, a front end DC level shifter with two (voltage) sources, three transistors, two diodes and a capacitor may be provided. Advantageously, providing to voltage sources reduces complexity of the circuit of the multilevel inverter.

According to various embodiments, a front end DC level shifter with a single voltage source, four transistors, two diodes and two capacitors may be provided.

According to various embodiments, a family of circuits may be provided. Each circuit of the family of circuits may use a low (for example a minimum) number of switches to obtain multiple DC voltage levels.

According to various embodiments, a multilevel inverter (or a topology of multilevel inverters) , for example a multilevel inverter circuit, for high frequency AC applications may employ a switched–capacitor technique. The inverter front end may include a switched–capacitor based DC to DC converter (for example a DC level shifter) that produces multiple DC levels at the DC bus of the inverter. A full bridge inverter may receive the multiple DC levels and may obtain different voltage levels at the output.

For example, a multilevel inverter (which may use a plurality of DC input sources, or which may use a single DC input source and) may output for example a seven level (for example three positive levels, three negative levels and a zero level) staircase voltage waveform. Utilizing a switched–capacitor technique according to various embodiments, the need to use heavy magnetic components, which may also occupy large space, may be eliminated. Thus, an inverter according to various embodiments may be lighter, may be smaller in size and/or may be cheaper.

According to various embodiments, a multilevel inverter may include a front end multi-level generator, which is realized by a switched-capacitor DC level shifter, and an H-bridge converter.

According to various embodiments, the front end switched–capacitor converter may be configured to produce multiple DC levels at the DC bus of the inverter. The front end converter may employ two voltage sources, two diodes, three transistors and one capacitor for voltage conversion.

Figure 2 shows an illustration 200 of a high frequency multilevel inverter (HF MLI) according to various embodiments, which may output a seven level staircase voltage waveform (three positive, zero and three negative) . The HF MLI may include two cascaded stages: a switched capacitor based front end DC level shifter 202 and a full bridge inverter 204. The front end switched capacitor DC level shifter 202 may include (or employ) three (switched capacitor inverter) switches (for example MOSFETs) : a first switch S ₁ 214, a second switch S ₂ 216 and a third switch S ₃ 220. The front end switched capacitor DC level shifter 202 may furthermore include two diodes: a first diode D ₁ 208 and a second diode D ₂ 210. The front end switched capacitor DC level shifter 202 may furthermore include two voltage sources: a first voltage source V _IN1 206 and a second voltage source V _IN2 218. The front end switched capacitor DC level shifter 202 may furthermore include a capacitor C 212. The different DC levels obtained at the V _DCbus 230 include V_IN1, V_IN2 and V_IN1 + V_IN2. The full bridge inverter 204 employs four MOSFETs Q ₁ 222, Q ₂ 224, Q ₃ 226 and Q ₄ 228. Full bridge inverter operation effectively produces seven levels, i.e., 0, ±V_IN1, ±V_IN2 and ± (V_IN1 + V_IN2) , which for example are available to a load 232. For analysis, it may be assumed that the size of the capacitor 212 is large enough for the voltage ripple to be negligible, and that the switching devices (the

MOSFETS

214, 216, 220, 222, 224, 226, and 228, and the diodes 208, 210) and the

input voltage sources

206, 218 are ideal. The working states will be explained in more detail with reference to Figure 3A to Figure 3H.

Figure 3A shows an equivalent circuit 300 of the multilevel inverter according to various embodiments for V₀ ＝ +V_IN1. Figure 3B shows an equivalent circuit 302 of the multilevel inverter according to various embodiments and V₀ ＝ –V_IN1. For a V₀ ＝ ±V_IN1 state (which may be understood as to be a short form of a state in which V₀ ＝ +V_IN1 or V₀ ＝ -V_IN1) , the capacitor C 212 is charged to V _IN1 206 through the first diode D ₁ 208 and by turning ON S ₃ 220, while S ₁ 214 and S ₂ 216 remain turned OFF, in the front end DC level shifter 202. In the full bridge inverter 204, to obtain +V_IN1 across the load 232, Q ₁ 222 and Q ₃ 226 are turned ON, while Q ₂ 224 and Q ₄ 228 remain turned OFF. To obtain –V_IN1 across the load 232, Q ₂ 224 and Q ₄ 228 are turned ON, while Q ₁ 222 and Q ₃ 226 remain turned OFF. D ₂ 210 remains turned OFF for both the states (+V_IN1 across the load 232 and –V_IN1 across the load 232) . V _IN2 218 is blocked from appearing at the output by turning OFF S ₁ 214 and S ₂ 216.

Figure 3C shows an equivalent circuit 304 of the multilevel inverter according to various embodiments for V₀ ＝ +V_IN2. Figure 3D shows an equivalent circuit 306 of the multilevel inverter according to various embodiments for and V₀ ＝ –V_IN2. According to various embodiments, for normal operation, i.e., to produce a seven level staircase output, an input voltage condition V_IN2 > V_IN1 may be provided. For a V₀ ＝ ±V_IN2 state, in the frontend DC level shifter 202, when S ₁ 214 is turned ON, while S ₂ 216 and S ₃ 220 remain turned OFF, D ₂ 210 is forward biased by V _IN2 218, and D ₁ 208 is reverse biased (V_IN2 > V_IN1) . Under this condition, V _IN2 218 is directly connected to the V _DCbus 230. In the full bridge inverter 204, to obtain +V_IN2 across the load 232, Q ₁ 222 and Q ₃ 226 are turned ON, while Q ₂ 224 and Q ₄ 228 remain turned OFF. To obtain –V_IN2 across the load 232, Q ₂ 224 and Q ₄ 228 are turned ON, while Q ₁ 222 and Q ₃ 226 remain turned OFF. Voltage across the capacitor C 212 still remains at V_IN1.

Figure 3E and shows an equivalent circuit 308 of the multilevel inverter according to various embodiments for V₀ ＝ + (V_IN1 + V_IN2) . Figure 3F shows an equivalent circuit 310 of the multilevel inverter according to various embodiments for V₀ ＝ – (V_IN1 + V_IN2) . For a V₀ ＝± (V_IN1 + V_IN2) state, the voltage across the capacitor C 212 remains at V_IN1. In the frontend DC level shifter 202, when S ₁ 214 and S ₂ 216 are turned ON, while S ₃ 220 remains turned OFF, D ₁ 208 and D ₂ 210 are reverse biased. Under this condition, the capacitor C 212 is connected in series to V _IN2 218. This connection ensures V₀ ＝ V_IN1 + V_IN2. In the full bridge inverter 204, to obtain + (V_IN1 + V_IN2) across the load 232, Q ₁ 222 and Q ₃ 226 are turned ON, while Q ₂ 224 and Q ₄ 228 remain turned OFF. To obtain – (V_IN1 + V_IN2) across the load 232, Q ₂ 224 and Q ₄ 228 are turned ON, while Q ₁ 222 and Q ₃ 226 remain turned OFF.

Figure 3G shows an equivalent circuit 312 of the multilevel inverter according to various embodiments for generating a zero level after a positive half cycle. Figure 3H shows an equivalent circuit 316 of the multilevel inverter according to various embodiments for generating a zero level after a negative half cycle. For a V₀ ＝ 0 state, to obtain zero volt at the output (V₀) 232 after a positive half cycle, only Q ₁ 222 is turned ON, while all the other switches in the full bridge inverter 204 remain turned OFF, and the body diode D_Q2 314 (of the switch Q₂ 224) is employed for freewheeling. To obtain zero volt at the output (V₀) 232 after the negative half cycle, only Q ₄ 224 is turned ON, while all the other switches in the full bridge inverter remain turned OFF, and the body diode D_Q3 318 (of the switch Q₃ 226) is employed for freewheeling. The switches in the front end DC level shifter 202 remain in their previous states.

Table 1 shows a summary of the working states logic as described with reference to Figure 3A to Figure 3H for the multilevel inverter according to various embodiments.

S₁	S₂	S₃	Q₁	Q₂	Q₃	Q₄	V₀
1	1	0	1	0	1	0	V₁+V ₂
1	0	0	1	0	1	0	V ₂
0	0	1	1	0	1	0	V ₁
0	0	1	1	0	0	0	0
0	0	1	0	1	0	1	-V ₁
1	0	0	0	1	0	1	-V ₂
1	1	0	0	1	0	1	- (V₁+V₂)
0	0	1	0	0	0	1	0

Table 1.

As described above, and as illustrated in Table 1, by turning on different transistors at different instants may result in obtaining different DC levels. In the front–end converter, turning ON only S1 and S2 provides VIN1 + VIN2 at the DC bus, turning ON only S1 provides VIN2 at the DC bus and turning ON only S3 provides VIN1 at the DC bus. As described above, the H-bridge converter (which may include or may consist of four transistors) may provide a bipolar waveform from a unipolar waveform at the DC bus. Figures 3A to 3H and Table 1 explain in detail and show the seven levels, i.e., 0, ±VIN1, ±VIN2 and ± (VIN1 + VIN2) . For example, turning ON Q1 and Q3, a positive cycle of AC is obtained at the output. Turning ON, Q2 and Q4, a negative cycle of AC is obtained at the output.

Figure 4 shows an illustration 400 of a simulation model of a multilevel inverter (for example the multilevel inverter 200 of Figure 2) according to various embodiments. A circuitry 402 for controlling the switches may be provided.

Figure 5 shows an illustration 500 of an output of the inverter (for example of the simulation model of Figure 4) , for example a 50 kHz multilevel (for example seven-level) staircase output voltage) .

Figure 6 shows a nine level inverter 600 according to various embodiments, and based on the seven level circuit of Figure 2, so that the same reference signs may be used, and some reference signs may be omitted for ease of readability of Figure 6. The nine level inverter 600 may employ a voltage doubler 604 (for double the voltage V_IN1 of the voltage source 206) as one of the voltage inputs to the front end DC level shifter 602. Therefore, the inverter 600 may output ±V_IN1, ±2V_IN1 ±V_IN2 and ± (V_IN1 + V_IN2) . The voltage double 604 may include switches S₁ 610 and S ₂ 612, a diode 606, and a capacitor 608.

Figure 7 shows a nine level inverter 700 according to various embodiments, and based on the seven level circuit of Figure 2, so that the same reference signs may be used, and some reference signs may be omitted for ease of readability of Figure 7. The nine level inverter 700 may employ a circuit 704 which reduces the input voltage V_IN1 of the voltage source 206 by half as one of the voltage inputs to the front end DC level shifter 702. This enables the inverter 700 to output ± (V_IN1/2) , ±V_IN1, ±V_IN2 and ± (V_IN1/2 + V_IN2) . The circuit 704 may include switches S₁ 712 and S₂ 714, a capacitor C 706, and diodes D₁ 708 and D ₂ 710.

Figure 8 shows an illustration 800 of a switched–capacitor based multilevel inverter (SCMLI) according to various embodiments. The switched–capacitor based multilevel inverter may be based on the seven level circuit of Figure 2, so that the same reference signs may be used, and some reference signs may be omitted for ease of readability of Figure 8. The dotted lines 804 illustrate portions where further circuit elements may be provided for a higher level inverter based on a basic cell 812 of the switched-capacitor based front end DC level shifter 802 (in which the basic cell 812 (in other words: single unit) corresponds to the switched capacitor based front end DC level shifter 202 of the seven level circuit 200 of Figure 2) . For an integer number i independent

input voltage sources

806, 808, 810, the number of levels may be n ＝ 2 ⁽ⁱ⁺¹⁾ –1. Table 2 shows a switching logic for the generalized topology of the SCMLI.

S₁	S₂	S₃	S₄	S_i+2	V_DCbus
0	0	1	0	1	V ₃
0	0	1	0	0	V ₂
1	0	0	0	0	V ₁
0	0	1	1	0	V₃+V ₂
1	0	0	1	0	V₁+V ₃
1	1	0	0	0	V₂+V ₁
1	1	0	1	0	V₁+V₂+V₃

Table 2.

According to various embodiments, a multilevel converter may be provided with a front end converter which include one voltage sources, two diodes, four transistors and two capacitors for voltage conversion.

Figure 9 shows a high frequency multilevel inverter (HF MLI) 900 according to various embodiments. The high frequency multilevel inverter (HF MLI) 900 may output a seven level staircase voltage waveform (for example three positive, one zero and three negative voltages) . The high frequency multilevel inverter (HF MLI) 900 may include (or consist of) two cascaded stages: a switched capacitor based front end DC to DC converter 902 and a full bridge inverter 904. The switched capacitor based front end DC to DC converter 902 may be a front end switched capacitor DC level shifter, and may include four (switched-capacitor) switches (a first switch G ₁ 916, a second switch G ₂ 918, a third switch G ₃ 920 and fourth switch G₄ 922) , which may for example be MOSFETs, two diodes (a first diode D ₁ 908 and a second diode D₂ 910) , a voltage sources V _IN 906, and two capacitors (a first capacitor C ₁ 910 and a second capacitor C₂ 914) . The different DC levels obtained at the V _DCbus 924 may include V_IN, 2V_IN and 3V_IN. The full bridge inverter 904 may include switches S₁ 926, S ₂ 928, S ₃ 930, S ₄ 932, and may produce seven levels of voltages V₀, for example, 0, ±V_IN, ±2V_IN and ±3V_IN, which for example may be output or provided to a load 934. For analysis, it may be assumed that the size of the

capacitors

912, 914 is large enough for the voltage ripple to be negligible, and that the switching

devices

916, 918, 920, 922, 926, 928, 930, 932 and the input voltage sources 906 are ideal. The working states of the HF MLI 900 will be described in more detail with reference to Figure 10A to Figure 10H. It will be understood that the numbering of the switches S_i (in other words: the index i in the switch name S_i) in the full bridge inverter 904 shown in Figure 9 may be different from the numbering of the switches Q_i in the full bridge inverter 204 shown in Figure 2； for example, while the first (full bridge inverter) switch is Q₁ in Figure 2 and S₁ in Figure 9 (i.e. same index 1) , the second (full bridge inverter) switch is Q₂ in Figure 2 and S₃ in Figure 9 (i.e. different indexes 2 and 3, respectively) ； likewise, the third (full bridge inverter) switch is Q₃ in Figure 2 and S₄ in Figure 9； and the fourth (full bridge inverter) switch is Q₄ in Figure 2 and S₂ in Figure 9.

Figure 10A shows an equivalent circuit 1000 of the multilevel inverter according to various embodiments for V₀ ＝ +V_IN1. Figure 10B shows an equivalent circuit 1002 of the multilevel inverter according to various embodiments for V₀ ＝ –V_IN1. For the V₀ ＝ ±V_IN state, the capacitor C ₁ 912 and C ₂ 914 may be charged to V_IN through the diodes D ₁ 908 and D ₂ 910, respectively, by turning ON the switches G ₂ 918 and G ₄ 922, while the switches G ₁ 918 and G ₃ 920 remain turned OFF, in the front end DC level shifter 902. In the full bridge inverter 904, to obtain +V_IN1 across the load 934, switches S ₁ 926 and S ₄ 932 may be turned ON, while switches S₂ 928 and S ₃ 930 remain turned OFF. To obtain –V_IN1 across the load 934, switches S ₂ 928 and S ₃ 930 may be turned ON, while switches S₁ 926 and S₄r932 remain turned OFF.

Figure 10C shows an equivalent circuit 1004 of the multilevel inverter according to various embodiments for V₀ ＝ +V_IN2. Figure 10D shows an equivalent circuit 1006 of the multilevel inverter according to various embodiments for V₀ ＝ –V_IN2 respectively. For the V₀ ＝ ±2V_IN state, in the frontend DC level shifter 902, when the switch G ₁ 916 is turned ON, while switches G ₂ 918, G ₃ 920 and G ₄ 930 remain turned OFF, diode D ₂ 910 is forward biased, and diode D ₁ 908 is reverse biased. Under this condition, the voltage source V _IN 906 is in series with capacitor C₁ 912 (which is charged to V_IN) and is directly connected to the V _DCbus 924. In the full bridge inverter 904, to obtain +2V_IN across the load 934, switches S ₁ 926 and S ₄ 932 may be are turned ON, while switches S₂ 928 and S ₃ 930 remain turned OFF. To obtain –2V_IN across the load 934, switches S ₂ 928 and S ₃ 930 are turned ON, while switches S₁ 926 and S ₄ 932 remain turned OFF. The voltage across both

capacitors

912, 914 may remain at V_IN.

Figure 10E shows an equivalent circuit 1008 of the multilevel inverter according to various embodiments for V₀ ＝ +3V_IN1. Figure 10F shows an equivalent circuit 1010 of the multilevel inverter according to various embodiments for V₀ ＝ –3V_IN1. For the V₀ ＝ ±3V_IN state, a voltage across both

capacitors

912, 914 may remain at V_IN. In the frontend switched– capacitor DC level shifter 902, when switches G ₁ 916 and G ₃ 920 are turned ON, while switches G ₂ 918 and G ₄ 922 remain turned OFF, diodes D ₁ 908 and D ₂ 910 may be reverse biased. Under this condition, both the

capacitors

912, 914 are connected in series to V _IN 906. This connection may provide that V_DCbus ＝ 3V_IN1. In the full bridge inverter 904, to obtain +3V_IN across the load 934, switches S ₁ 926 and S ₄ 932 may be turned ON, while switches S₂ 928 and S ₃ 930 may remain turned OFF. To obtain –3V_IN across the load 934, switches S ₂ 928 and S ₃ 930 may be turned ON, while switches S₁ 926 and S ₄ 932 may remain turned OFF.

Figure 10G shows an equivalent circuit 1012 of the multilevel inverter according to various embodiments for generating the zero level after a positive half cycle. Figure 10H shows an equivalent circuit 1016 of the multilevel inverter according to various embodiments for generating the zero level after a negative half cycle. For the V₀ ＝ ‘0’s tate, to obtain zero volt at the output V₀ after the positive half cycle, only the switch S ₁ 926 may be turned ON, while all the

other switches

928, 930, 932 in the full bridge inverter 904 remain turned OFF, and a body diode D _S3 1014 associated with the switch S ₃ 930 is employed for freewheeling. To obtain zero volt at the output V₀ after the negative half cycle, only the switch S ₂ 928 is turned ON, while all the

other switches

926, 930, 932 in the full bridge inverter 904 may remain turned OFF, and a body diode D _S4 1018 associated with the switch S ₄ 932 is employed for freewheeling. The

switches

916, 918, 920, 922 in the front end DC level shifter 902 may remain in their previous states.

Table 3 shows a summary of the working states logic for the multilevel inverter like described with reference to Figure 10A to Figure 10H above.

G₁	G₂	G₃	G₄	S₁	S₂	S₃	S₄	V₀
1	0	1	0	1	0	0	1	3V ₁
1	0	0	0	1	0	0	1	2V1
0	1	0	1	1	0	0	1	V1
0	1	0	1	1	0	0	0	0
0	1	0	1	0	1	1	0	-V1
1	0	0	0	0	1	1	0	-2V1
1	0	1	0	0	1	1	0	-3V1
0	1	0	1	0	1	0	0	0

Table 3.

As described above, the voltage levels at the DC bus 924 of the inverter 902 may include V_IN, 2V_IN and 3V_IN. As highlighted in Figures 10A to 10H and Table 3, turning on

different transistors

916, 918, 920, 922 at different instants may provide obtaining the mentioned DC levels. In the front–end converter 902, turning ON only G ₁ 916 and G ₂ 918 may provide 3V_IN at the DC bus 924. Turning ON only G ₁ 916 may provide 2V_IN at the DC bus 924. Turning ON only G ₂ 918 and G ₄ 922 provides V_IN at the DC bus 924. Figure 10A to Figure 10H above describe in more detail how seven levels, i.e., 0, ±V_IN1, ±2V_IN and ±3V_IN., are obtained. Turning ON switch S ₁ 926 and S ₄ 932, a positive cycle of AC (for example a sequence of piecewise DC voltages) may be obtained at the output 934. Turning ON switch S ₂ 928 and S ₃ 930, a negative cycle of AC may be obtained at the output 934.

Figure 11 shows an illustration 1100 of a simulation model of a multilevel inverter (for example the multilevel inverter 900 of Figure 9) according to various embodiments. A circuitry 1102 for controlling the switches may be provided.

Figure 12 shows an illustration 1200 of the states of the switches of the multilevel inverter 900 of Figure 9 (wherein for example Vs1 indicates the state of the switch S ₁ 926, wherein a higher value (i.e. a line closer to the top of the diagram) indicates an ‘on’s tate, and a lower value (i.e. a line closer to the bottom of the diagram) indicates an ‘off’s tate) in a sub-diagram 1202, and the resulting voltage V₀ in a sub-diagram 1204.

Figure 13A shows a nine level inverter 1300, which is based on the five level inverter shown in Figure 9 (including the switched capacitor inverter 902 and the full bridge inverter 904) , with additional two switches 1308, 1310 (for example transistors) , an additional diode 1304, and an additional capacitor 1306. The additional two

switches

1308, 1310, the additional diode 1304, and the additional capacitor 1306 may form a (further) voltage doubler 1302, so that the following voltages may be provided to the load 934: 0, ±V_IN, ±2V_IN, ±3V_IN., and ±4V_IN. (in other words: -4V_IN, -3V_IN, -2V_IN., -V_IN, 0, V_IN, 2V_IN, 3V_IN., and 4V_IN) .

Figure 13B shows a multilevel inverter 1310, which includes a plurality of voltage doublers 1302. Like indicated by lines 1312, further voltage doublers may be added.

Figure 13C shows a multilevel inverter 1314. Like indicated by lines 1316, further voltage doublers may be added.

It will be understood that in the various front end DC level shifters described herein, one or more voltage sources may or may not be a part of the front end DC level shifter. According to various embodiments, the front end DC level shifter may include one or more voltage sources. According to various embodiments, the front end DC level shifter may be connected to one or more voltage sources.

The multilevel inverters according to various embodiments may be configured to provide either a high frequency AC output, for example 400 Hz, or 50 kHz, or a low frequency AC output, for example 50 Hz or 60 Hz.

According to various embodiments, a lower number of switches (for example compared to commonly used inverters) may be used.

According to various embodiments, different topologies may be provided based on a basic topology (for example based on one of the topologies described above) .

According to various embodiments, a small capacitor size may be sufficient for high frequency applications (or high frequency operation) .

According to various embodiments, an intelligent placement of switches may be provided.

According to various embodiments, a modular design may be provided which may ensure extension of the topologies (for example extension to a higher number of voltage levels in the multilevel output) .

Various embodiments may solve (in other words: overcome； in other words: eliminate) the need to use excessive devices, power sources and passive components. Various embodiments may eliminate the need to employ bulky inductors.

Various embodiments may provide a multilevel output which may reduce harmonic content.

Various embodiments may be applied in aerospace industry, telecommunications industry, lighting industry, and automotive industry.

It will be understood that a switched capacitor inverter switch is a switch, and that a full bridge inverter switch is a switch, and that the terms ‘switched capacitor inverter’ switch and ‘full bridge inverter’ switch are merely used to describe where the respective switch is provided, without necessarily requiring any specific property of the switch.

It will be understood that the name of a voltage source and the voltage it provides may be denoted with the same reference. For example, ‘V’ may refer to a voltage source as a circuit element, and at the same time, ‘V’ may refer to the voltage that the voltage source ‘V’ provides.

According to various embodiments, a switch may be illustrated in the drawings as a transistor and a diode, and may be provided as a transistor and a diode accordingly.

According to various embodiments, transistors provided in the multilevel inverter may be any controllable switch, such as bipolar junction transistor, IGBT (Insulated-gate bipolar transistor) , MOSFET (metal–oxide–semiconductor field-effect transistor) or a relay.

While exemplary embodiments have been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist.

It should further be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, operation, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements and method of operation described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims.

Claims

A multilevel inverter comprising:

a switched capacitor inverter configured to output a unipolar sequence of DC voltages； and

a full bridge inverter configured to receive the unipolar sequence of DC voltages and to output a bipolar sequence of DC voltages.
The multilevel inverter of claim 1,

wherein the unipolar sequence comprises a periodic sequence.
The multilevel inverter of claim 2,

wherein the bipolar sequence comprises a periodic sequence.
The multilevel inverter of any one of claims 1 to 3,

wherein the unipolar sequence comprises a rising sub-sequence and a falling sub-sequence.
The multilevel inverter of claim 4,

wherein the bipolar sequence comprises a rising sub-sequence and a falling sub-sequence.
The multilevel inverter of any one of claims 1 to 5,

wherein the switched capacitor inverter comprises a charge pump.
The multilevel inverter of any one of claims 1 to 6,

wherein the switched capacitor inverter is configured to be connected to a single voltage source.
The multilevel inverter of any one of claims 1 to 6,

wherein the switched capacitor inverter is configured to be connected to a plurality of voltage sources.
The multilevel inverter of any one of claims 1 to 8,

wherein the full bridge inverter is configured to selectively pass through the DC voltages of the unipolar sequence or to negate the DC voltages of the unipolar sequence.
The multilevel inverter of any one of claims 1 to 9,

wherein the switched capacitor inverter is configured to be connected to a first voltage source and to a second voltage source； and

wherein the switched capacitor inverter comprises a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a first diode, a second diode and a capacitor.
The multilevel inverter of claim 10,

wherein the first switched capacitor inverter switched capacitor inverter switch is connected to the second voltage source, the second diode, and the second switched capacitor inverter switch；

wherein the second switched capacitor inverter switch is connected to the first switched capacitor inverter switch, the second diode, the capacitor, and the third switched capacitor inverter switch；

wherein the third switched capacitor inverter switch is connected to the first voltage source, the second voltage source, the second switched capacitor inverter switch, the capacitor, and the full bridge inverter；

wherein the first diode is connected to the first voltage source and the second diode；

wherein the second diode is connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the first diode, and the capacitor； and

wherein the capacitor is connected to the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first diode, the second diode, and the full bridge inverter.
The multilevel inverter of any one of claims 10 to 11,

wherein the unipolar sequence comprises DC voltages of four different levels corresponding to a zero voltage, a voltage of the first voltage source, a voltage of the second voltage source, and a sum of the voltage of the first voltage source and the voltage of the second voltage source； and

wherein the bipolar sequence comprises DC voltages of seven different levels corresponding to a zero voltage, the voltage of the first voltage source, the voltage of the second voltage source, the sum of the voltage of the first voltage source and the voltage of the second voltage source, an inverted voltage of the first voltage source, an inverted voltage of the second voltage source, and an inverted sum of the voltage of the first voltage source and the voltage of the second voltage source.
The multilevel inverter of any one of claims 10 to 12,

wherein the switched capacitor inverter is configured to output a voltage of the first voltage source to the full bridge inverter if the third switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an off state.
The multilevel inverter of any one of claims 10 to 13,

wherein the switched capacitor inverter is configured to output a voltage of the second voltage source to the full bridge inverter if the first switched capacitor inverter switch is in an on state and the second switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.
The multilevel inverter of any one of claims 10 to 14,

wherein the switched capacitor inverter is configured to output a voltage corresponding to a sum of the voltage of the first voltage source and the voltage of the second voltage source to the full bridge inverter if the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an on state and the third switched capacitor inverter switch is in an off state.
The multilevel inverter of any one of claims 10 to 15,

wherein the switched capacitor inverter comprises a voltage increaser configured to selectively increase a voltage of at least one of the first voltage source or the second voltage source.
The multilevel inverter of any one of claims 10 to 16,

wherein the switched capacitor inverter comprises a voltage doubler configured to selectively double a voltage of at least one of the first voltage source or the second voltage source.
The multilevel inverter of any one of claims 10 to 17,

wherein the switched capacitor inverter comprises a voltage reducer configured to selectively reduce a voltage of at least one of the first voltage source or the second voltage source.
The multilevel inverter of any one of claims 10 to 18,

wherein the switched capacitor inverter comprises a voltage reducer configured to selectively half a voltage of at least one of the first voltage source or the second voltage source.
The multilevel inverter of any one of claims 16 to 19,

wherein the unipolar sequence comprises DC voltages of five different levels； and

wherein the bipolar sequence comprises DC voltages of nine different levels.
The multilevel inverter of any one of claims 1 to 20,

wherein the switched capacitor inverter is configured to be connected to at least three voltage sources；

wherein the switched capacitor inverter is configured to selectively output voltages corresponding to combinations of voltages of the three voltage sources to the full bridge inverter.
The multilevel inverter of any one of claims 10 to 21,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch comprises a relay.
The multilevel inverter of any one of claims 10 to 22,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch comprises a transistor.
The multilevel inverter of claim 23,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch comprises a bipolar junction transistor.
The multilevel inverter of any one of claims 23 to 24,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch comprises an insulated-gate bipolar transistor.
The multilevel inverter of any one of claims 23 to 25,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch comprises a metal–oxide–semiconductor field-effect transistor.
The multilevel inverter of any one of claims 1 to 9,

wherein the switched capacitor inverter is configured to be connected to a single voltage source； and

wherein the switched capacitor inverter comprises a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a fourth switched capacitor inverter switch, a first diode, a second diode, a first capacitor, and a second capacitor.
The multilevel inverter of claim 27,

wherein the first switched capacitor inverter switch is connected to the voltage source, the first diode, the first capacitor, the second switched capacitor inverter switch, and the fourth switched capacitor inverter switch；

wherein the second switched capacitor inverter switch is connected to the voltage source, to the first switched capacitor inverter switch, to the first capacitor, to the fourth switched capacitor inverter switch, and to the full bridge inverter；

wherein the third switched capacitor inverter switch is connected to the fourth switched capacitor inverter switch, the first diode, the second diode, the first capacitor, and the second capacitor；

wherein the fourth switched capacitor inverter switch is connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first capacitor, and the second capacitor；

wherein the first diode is connected to the voltage source, the first switched capacitor inverter switch, the third switched capacitor inverter switch, and the second diode；

wherein the second diode is connected to the third switched capacitor inverter switch, the first diode, the first capacitor, the second capacitor, and the full bridge inverter；

wherein the first capacitor is connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the fourth switched capacitor inverter switch, the first diode, and the second diode； and

wherein the second capacitor is connected to the third switched capacitor inverter switch, the fourth switched capacitor inverter switch, the second diode, and the full bridge inverter.
The multilevel inverter of any one of claims 27 to 28,

wherein the unipolar sequence comprises DC voltages of four different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source； and

wherein the bipolar sequence comprises DC voltages of seven different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source, an inverted voltage of the voltage source, an inverted doubled voltage of the voltage source, and an inverted tripled voltage of the voltage source.
The multilevel inverter of any one of claims 27 to 29,

wherein the switched capacitor inverter is configured to output a voltage of the voltage source to the full bridge inverter if the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an on state and the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.
The multilevel inverter of any one of claims 27 to 30,

wherein the switched capacitor inverter is configured to output a doubled voltage of the voltage source to the full bridge inverter if the first switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch are in an off state.
The multilevel inverter of any one of claims 27 to 31,

wherein the switched capacitor inverter is configured to output a tripled voltage of the voltage source to the full bridge inverter if the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an on state and the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an off state.
The multilevel inverter of any one of claims 27 to 32,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch comprises a relay.
The multilevel inverter of any one of claims 27 to 33,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch comprises a transistor.
The multilevel inverter of claim 34,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch comprises a bipolar junction transistor.
The multilevel inverter of any one of claims 34 to 35,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch comprises an insulated-gate bipolar transistor.
The multilevel inverter of any one of claims 34 to 36,

wherein at least one of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch comprises a metal–oxide–semiconductor field-effect transistor.
The multilevel inverter of any one of claims 1 to 37,

wherein the switched capacitor inverter is configured to be connected to a single voltage source； and

wherein the switched capacitor inverter comprises a plurality of voltage increasers configured to selectively increase a voltage of the voltage source.
The multilevel inverter of any one of claims 1 to 38,

wherein the switched capacitor inverter is configured to be connected to a single voltage source； and

wherein the switched capacitor inverter comprises a plurality of voltage doublers configured to selectively double a voltage of the voltage source.
The multilevel inverter of any one of claims 1 to 39,

wherein the switched capacitor inverter is configured to be connected to a single voltage source； and

wherein the switched capacitor inverter comprises a plurality of voltage reducers configured to selectively reduce a voltage of the voltage source.
The multilevel inverter of any one of claims 1 to 40,

wherein the switched capacitor inverter is configured to be connected to a single voltage source； and

wherein the switched capacitor inverter comprises a plurality of voltage reducers configured to selectively half a voltage of the voltage source.
The multilevel inverter of any one of claims 1 to 41,

wherein the full bridge inverter comprises a first full bridge inverter switch, a second full bridge inverter switch, a third full bridge inverter switch, and a fourth full bridge inverter switch.
The multilevel inverter of claim 42,

wherein the first full bridge inverter switch is connected to the switched capacitor inverter, the second full bridge inverter switch, the fourth full bridge inverter switch, and an output of the full bridge inverter；

wherein the second full bridge inverter switch is connected to the switched capacitor inverter, the first full bridge inverter switch, the third full bridge inverter switch, and the output；

wherein the third full bridge inverter switch is connected to the switched capacitor inverter, the second full bridge inverter switch, the fourth full bridge inverter switch, and the output； and

wherein the fourth full bridge inverter switch is connected to the switched capacitor inverter, the first full bridge inverter switch, the third full bridge inverter switch, and the output.
The multilevel inverter of any one of claims 42 to 43,

wherein the full bridge inverter is configured to output a voltage received from the switched capacitor inverter if the first full bridge inverter switch and the third full bridge inverter switch are in an on state and the second full bridge inverter switch and the fourth full bridge inverter switch are in an off state.
The multilevel inverter of any one of claims 42 to 44,

wherein the full bridge inverter is configured to invert a voltage received from the switched capacitor inverter and output the inverted voltage if the second full bridge inverter switch and the fourth full bridge inverter switch are in an on state and the first full bridge inverter switch and the third full bridge inverter switch are in an off state.
The multilevel inverter of any one of claims 42 to 45,

wherein the full bridge inverter is configured to output a zero voltage after having output a positive voltage with the first full bridge inverter switch in an on state and the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch in an off state.
The multilevel inverter of claim 46,

wherein a body diode associated with the second full bridge inverter switch is configured to provide freewheeling.
The multilevel inverter of any one of claims 42 to 47,

wherein the full bridge inverter is configured to output a zero voltage after having output a negative voltage with the fourth full bridge inverter switch in an on state and the first full bridge inverter switch, the second full bridge inverter switch, and the third full bridge inverter switch in an off state.
The multilevel inverter of claim 48,

wherein a body diode associated with the fourth full bridge inverter switch is configured to provide freewheeling.
The multilevel inverter of any one of claims 42 to 49,

wherein at least one of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch comprises a relay.
The multilevel inverter of any one of claims 42 to 50,

wherein at least one of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch comprises a transistor.
The multilevel inverter of claim 51,

wherein at least one of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch comprises a bipolar junction transistor.
The multilevel inverter of any one of claims 51 to 52,

wherein at least one of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch comprises an insulated-gate bipolar transistor.
The multilevel inverter of any one of claims 51 to 52,

wherein at least one of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch comprises a metal–oxide–semiconductor field-effect transistor.