WO2012168533A1

WO2012168533A1 - Apparatus for glitchless clock divider with fast clock change and method thereof

Info

Publication number: WO2012168533A1
Application number: PCT/FI2011/050538
Authority: WO
Inventors: Ari Hatula; Jussi Pennala
Original assignee: Nokia Corporation
Priority date: 2011-06-09
Filing date: 2011-06-09
Publication date: 2012-12-13
Also published as: EP2718780A4; EP2718780A1

Abstract

An apparatus comprising a clock shaper (510) configured to derive a frequency of a reference clock signal (501) into a plurality of n frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1,..., Clock n-1 (571-0, 571-1,..., 571-n-1), and configured to generate a plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m), where n is a number of the gated clocks and m corresponds to a divisor; a plurality of n coupled clock selection and gating units (550-0, 550-1,..., 550-n-1) receiving the reference clock (501) and the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m), and configured to select one of the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m) and to gate to an output clock (571-0, 571-1,..., 571-n-1); and a phase decoding unit (530) configured to decode the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m) based on a plurality of received division value per clock signals, and configured to generate a plurality of n clock selection signals (531-0, 531-1,..., 531-n-1), wherein one of the plurality of n clock selection signals (531-0, 531-1 531 -n-1) corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks (571-1, 571-2,..., 571-n-1); wherein the plurality of n coupled clock selection and gating units (550-0, 550-1 550-n-1) are responsive to the plurality of n clock selection signals (531-0, 531-1 531 -n-1) to generate the output clock (571-0, 571-1,..., 571 -n-1) with the selected frequency.

Description

APPARATUS FOR GLITCHLESS CLOCK DIVIDER WITH FAST CLOCK CHANGE AND METHOD THEREOF

TECHNICAL FIELD

[0001] The present application relates generally to data communication and more particularly to apparatuses and methods for glitchless clock divider with fast clock change.

BACKGROUND

[0002] A clock signal is used in digital electronic to control the operations of different electrical or electronic circuits. Therefore, for devices that operate with multiple clock sources, a clock selection circuit which selects between two or more frequencies and phase locked sources can produce output transients. The clock selection circuit which controls different clock sources can create glitches and intermediate clock behavior on the output clock.

[0003] US2006/0091928 describes a clock scaling circuit for scaling and switching in a glitch free manner. Two phase clocks are generated from a master clock, wherein the two phase clocks do not transition at substantially the same time. One of the two phase clocks may be in phase with the master clock but the other of the two phase clocks may be 180 degrees out of phase with the master clock such that they do not transition at the same time. In particular, the clock scaling circuit utilizes 4 clocks with a 180 degrees phase shift wherein two phase clocks are needed and wherein a Flip Flop divider is implemented and which has undesirable outcome.

[0004] US2004/0267848 describes a circuit for clock division with dynamic divide-by value change capability. The clock divider is conventional except for the logic that handles the dynamic divide-by value change. The divider generates a clock signal corresponding to the new divide-by value. Although the circuit provides low area and low latency, the changing of the division value during runtime causes a blank period at switching point and this may cause unwanted effects if the clock is used for processing in a multiclock design.

[0005] Therefore, these techniques cannot guarantee a glitch free clock switch without a blank period since they don't support or support poorly the clock change during run time.

SUMMARY [0006] Various aspects of examples of the invention are set out in the claims.

[0007] According to a first aspect of the present invention, an apparatus comprises:

- a clock shaper configured to derive a frequency of a reference clock signal into a plurality of frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1...

Clock n -1, and configured to generate a plurality of m clock enable signals, where n is a number of gated clocks and m corresponds to a divisor;

- a plurality of n coupled clock selection and gating units receiving the reference clock and the plurality of m clock enable signals, and configured to select one of the plurality of m clock enable signals and to gate to an output clock; and

- a phase decoding unit configured to decode the plurality of m clock enable signals based on a plurality of received division value per clock signals, and configured to generate a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1... Clock n - 1 ;

wherein the plurality of n coupled clock selection and gating units are responsive to the plurality of n clock selection signals to generate the output clock with the selected frequency.

[0008] According to a second aspect of the present invention, an apparatus comprises:

- means for gating a reference clock signal to produce plurality of frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1, ..., Clock n -1 and for shaping a plurality of m clock enable signals, where n is a number of gated clocks and m

corresponds to a divisor;

- means for decoding the plurality of m clock enable signals based on a plurality of received division value per clock signals, and for generating a plurality of clock selection signals, wherein one of the plurality of clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks, Clock 0, Clock 1, Clock n -1; and

- means for selecting one of the plurality of m clock enable signals per a gated clock based on the plurality of n clock selection signals, and for gating the reference clock by the selected clock enable signal associated to a selected frequency to generate an output clock with the selected frequency.

[0009] According to a third aspect of the present invention, a method, comprises: - receiving a reference clock signal with a frequency in a clock shaper;

- gating the frequency of the reference clock signal to produce a plurality of frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1, ..., Clock n -l, where n is a number of gated clocks;

- shaping a plurality of m clock enable signals from the clock shaper where m corresponds to a divisor;

- decoding the plurality of m clock enable signals based on a plurality of received division value per clock signals in a phase decoding unit;

- generating a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1, ..., Clock n -l;

- selecting one of the plurality of m clock enable signals with a selected frequency based on the plurality of n clock selection signals; and

- gating the reference clock signal by the selected clock enable signal to generate an output clock with the selected frequency.

[0010] According to a fourth aspect of the present invention, an apparatus comprises:

a processor configured to:

- receive a reference clock signal with a frequency in a clock shaper;

- gate the frequency of the reference clock (501) to produce a plurality of frequencies associated to a plurality of n gated clocks, clocks Clock 0, Clock 1, ..., Clock n -1, where n is a number of gated clocks;

- shaping a plurality of m clock enable signals from the clock shaper, where m corresponds to a divisor;

- decode the plurality of m clock enable signals based on a plurality of received division value per clock signals in a phase decoding unit;

- generate a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1, ..., Clock n -l;

- select one of the plurality of m clock enable signals with a selected frequency based on the plurality of n clock selection signals; and

- gate the reference clock signal by the selected clock enable signal to generate an output clock with the selected frequency.

[0011] According to fifth aspect of the invention, an apparatus comprises: at least one processor; and

at least one memory including computer program code

the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following: - receive a reference clock signal with a frequency in a clock shaper;

- gate the frequency of the reference clock to produce a plurality of frequencies associated to a plurality of n clocks, Clock 0, Clock 1, ..., Clock n -1, where n is a number of gated clocks;

- shape a plurality of m clock enable signals from the clock shaper, where m corresponds to a divisor;

- generate a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1... Clock n -1;

- select one of the plurality of m clock enable signals with a selected frequency based on the plurality of n clock selection signals, and

[0012] According to sixth aspect of the present invention, a computer program comprises:

- code for receiving a reference clock signal with a frequency in a clock shaper or with a frequency of a plurality of n gated clocks Clock 0, Clock 1, ..., Clock n -1;

- code for gating the frequency of the reference clock to produce a plurality of frequencies associated to the plurality of n gated clocks, Clock 0, Clock 1, ..., Clock n -l, where n is a number of gated clocks;

- code for shaping a plurality of m clock enable signals from the clock shaper, where m corresponds to a divisor;

- code for decoding the plurality of m clock enable signals based on a plurality of received division value per clock signals in a phase decoding unit;

- code for generating a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1, ..., Clock n -l; - code for selecting one of the plurality of m clock enable signals with a selected frequency based on the plurality of n clock selection signals; and

- code for gating the reference clock signal by the selected clock enable signal to generate an output clock with the selected frequency;

when the computer program is run on a processor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of example embodiments of the present invention, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:

[0014] FIG. l illustrates a conventional flip flop divider with a bypass

multiplexer.

[0015] FIG.2 illustrates a conventional flip flop divider with a bypass control unit.

[0016] FIG.3 illustrates timing diagram of a conventional flip flop divider during a clock change.

[0017] FIG.4 illustrates a principle of a gating divider.

[0018] FIG.5 illustrates in detail a glitchless clock divider with n number of clock signals.

[0019] FIG.6 illustrates a time diagram of a gating divider with a division up to 4.

[0020] FIG.7 illustrates a programmable clock divider using an enable selection multiplexer for n number of clocks combined with a clock gating component.

[0021] FIG.8 illustrates a phase decoding switch for n number of clocks.

[0022] FIG.9 illustrates a timing diagram of a phase decoding with new and old clock edges aligned.

[0023] FIG.10 illustrates a timing diagram of a phase decoding with all clocks aligned.

[0024] FIG.11 illustrates a timing diagram with no phase decoding nor edge alignment.

[0025] FIG.12 illustrates a timing diagram with fast alignment to closest phase.

[0026] FIG.13 illustrates a clock gate consisting of a latch and an AND-gate (gate-to-low).

DETAILED DESCRIPTON OF THE DRAWINGS [0027] Example embodiments of the present invention and their potential advantages are understood by referring to FIG.1 through FIG.13 of the drawings.

[0028] Conventional circuits for glitcheless clock divider with fast clock change are presented using a Flip Flop divider with one multiplexer or a plurality of multiplexers with an output clock which may use in case of a division by 1. The multiplexers can be implemented in different ways. However, the designs have to be improved so that they can switch an output clock without a blank period. This improvement can be achieved by using for instance a gating divider instead of the flip flop FF divider.

[0029] This invention may be implemented in an environment using a digital ASIC/SoC clock generation. Modern low power ASICs/SoCs, such as wireless baseband modems or CPUs, are typically multi-clock designs having several clock domains running at different frequencies and having aggressive control to disable the clocks whenever possible. Many practical solutions of today contain selectable clocks, e.g. low frequency clock for low-active modes and high frequency clock for high-active modes. Those clocks may be derived from the same clock source in practice.

[0030] Multi-clock design (i.e. IC/IP with several different reference clocks) typically contains frequency synthesizers (e.g. PLLs or DLLs), clock selectors and clock dividers. Selecting an appropriate clock can be done either by configuring the frequency synthesizer which is typically a very slow procedure or by programming a digital divider which is a very fast procedure. This present invention is dedicated to the second option wherein the Glitchless Clock Divider is to be used with a fast clock switching.

[0031] In the state of the art of multi-clock ASICs/SOCs, there is a need to generate multiple reference clocks with different frequencies. Moreover, each or some of the reference clocks needs be configurable (i.e. low frequency for low processing load and high frequency high processing load). Clocks can be generated using a programmable frequency synthesizers and dividers which can also be programmable. The frequency synthesizers are relatively complex and they change the output frequency relatively slowly. The dividers are simple components to divide basic frequency clocks as well as

synthesized and/or high frequency clocks. And the dividers can change the output frequency relatively fast. Therefore, dividers are preferably choosen to handle a number of different clocks rather than a number of frequency synthesizers.

[0032] The clock frequencies and the number of selectable clocks are both continuosly increasing in the state of the art designs. Therefore, creating a clock divider circuit is no longer a simple task but requires a lot of attention. The issue is: "How to generate clocks without worsening the jitter/skew/slew/variation of the clock signals?". This present invention illustrates a scalable solution with minimal/no effect on the clock signals.

[0033] A simpliest clock divider, from theoretical aspect, is the "well-known" flip-flop (FF) divider as previously referred, which is commonly utilized in digital circuits and shown in Fig.1. The issue with the conventional FF divider is the selectivity: a multiplexer is to be used in order to switch between the divided clock and the source clock (division by 1 clock).

[0034] As is shown in Fig. l , the principle of a conventional flip flop divider consists of a bypass multiplexer 120 and a flip flop divider 1 10. The bypass multiplexer 120 has two inputs. A first input pin 0 receives a clock signal divided by 2, Clk 12 signal referred as 1 14. The second input pinl receives the clock signal Clk 101. The multiplexer 120 also receives a clock selection signal ClkSel 1 19 on a third input. The ClkSel signal 1 19 value determines which one of the two input pins of the multiplexer is selected as an output pin signal 121 referred as OutClk. When ClkSel = 1 , the multiplexer output OutClk receives Clk / 2 signal, the divided clock; and when ClkSel = 0, the OutClk receives Clk signal; no clock division.

[0035] The flip flop divider 1 10 has two inputs. A first input receives a clock signal Clk 101 which is the clock for a sampling. The second input receives an inverted output 1 1 1 of the flip flop divider. The flip flop divider 1 10 has also two outputs. A first output generates an output signal 1 14 which takes the state of the input signal 1 1 1 at a positive edge of the clock signal 101. The second output generates an output signal 1 1 1 takes the inverted state of the input 1 1 1 at the positive edge of the clock signal 101.

[0036] In such case, the FF divider circuit ClkSel 1 19 needs to be synchronous with the clock input Clk 101 and it has very short, restricted, timing requirement which may not be fulfilled if the frequency is high. In a practice, this means that the conventional and simpliest clock divider can become very complex to implement even though the principle is simple.

[0037] An example of a real implementation (conventional circuit) is shown in Fig 2. It illustrates a conventional flip flop divider 200 consisting of a Bypass Control 230, Divided Clock Generation 210, a flip flop clock as FFClk 270, a multiplexer MUX 280, a shift register ShiftRegs 250, and a Clock Select signal 290. The flip flop divider 200 has eight inputs. A first input 201 (which is also referred as a bypass path signal 221), receives a clock signal Clkln. Clkln is the reference clock to a divided clock process 220, FFClk 270, MUX 280, and ClockSelect 290. A second input 202 receives a test mode signal, referred as TestMode which is only used in a production testing. The production testing is supported by the flip flop divider but not described in this context. A 3^rd input 203 is a Resets signal 203 which is also an input signal 208 for the Bypass Control 230. The Resets signal is a synchronous reset of the flip flop divider. It operates also a system reset. The Divided Clock Generation 210 also uses a 4^th input signal Count 204, a 5^th input signal Divider 205, and a 6^th input signal EN 206 for the clock division. A 7^th input signal Divider Bypass 207 bypasses the flip flop divider; wherein the clock is divided by 1. A 9^th input signal ActiveResetSrc 209 controls the Divider 200 to a known state during a system reset.

[0038] Divided Clock Generation 210 generates a divided clock through a functional path 222 based on the Count signal 204, the Divider signal 205 and the En signal 206. The generated divided clock is connected to the flip flop Clk 270. The flip flop Clk 270 transmits a FF divided clock signal 271. The FF divided clock 271 is transmitted to a bypass multiplexer 280; the FF divided clock 271 is then mapped through the multiplexer 280 for furher processing when the Divider Bypass signal 207 is Ί ', otherwise the Clkln signal 201 is mapped for further processing. An output of the bypass multiplexer 280 is a functional clock 282 in case of clock division.

[0039] The Divider 200 has an Output Clock which is referred as ClkOut signal 291. When the Divider Bypass 207 is high Ί ', the Clkln signal 201 is as the output clock, otherwise the output clock is as the functional clock signal 282. The ClockSelect uses the Select signal 251 and Alive signal 252 for the clock change so that the glitches are avoided during the clock change. The ShiftRegs 250 decodes the clock changes by decoding a Bypass signal 231 through an inverter 260. The current frequency is taken into account inside the ShiftRegs through the functional clock signal 282. The clock changes are synchronized by a CS Ctrl P 240. The output clock ClkOut 291 has to stop in order to guarantee a glitch free clock switch inside the FF divider 200, see Fig 3. In general, stopping the clock for frequency change prevents runtime utilization of the clock selection. Hence, it is desired to change the clock on-the-fly, i.e. during runtime. A clock change on- the-fly, runtime, is an issue in the FF divider. As a matter of fact, the clock change requires a blank period and if a data transfer is on going to another clock domain, a system malfunction may occur. Fig.3 illustrates a blank period in a FF divider during a clock change such that the divider control logic stops the output clock automatically for the time the divider configuration is changed (divider ratio change). [0040] Fig.3 shows a timing diagram of the conventional flip flop divider. It illustrates the waveforms of lofical value (low/high: 0/1) of each inputs and output as a function of time. Time is shown in on an axis 310. When the clock frequency is changed, the output clocks stop for a while. In this exemplary embodiment, the timing diagram shows the divider input clock signal L1HF SOURCECLK 301. The output clocks of the divider are: LI PROCESSOR CLK signal 302, L 1 _S YSTEM CLK signal 303, and LI SLOW SYSTEM CLK signal 304. The output clocks are divided from the

L1HF SOURCECLK signal. In the beginning, the clocks are divided as follows in the timing diagram: the LI PROCESSOR CKL signal is divided by 1, the

L 1 _S YSTEM CLK is divided by 2, and the LI SLOW SYSTEM CLK signal is divided by 4. When the change of clock frequencies causes latency to the output clocks; the clocks are stopped. Latency takes a while when the divider decodes the frequency change. Once the frequency change is finished, the output clocks are released with new frequencies by the divider. The frequencies are as follows: the LI PROCESSOR CKL signal is divided by 2, the L 1 _S YSTEM CLK is divided by 8, and the LI SLOW SYSTEM CLK signal is divided by 16.

[0041] On a general level, the following assumption pertaining to the FF divider can be used:

The FF divider needs components such as for instance multiplexers and the sequential cells as shown in the figures, to a clock line. The mentioned components in the clock line have to avoid; the components complicates a BE implementation on all level; for instance in a clock tree synthesis and a clock balancing.

The FF divider is "ok" if a divider is fixed; a programmable divider should be implemented by a gating divider instead of a FF divider.

[0042] As previously mentioned, the present invention is a glitchless clock divider for a fast clock swithing capability without blank period that generates n derived clocks based on one input clock source. In this embodiment, the derived clocks are enabled, changed and disabled without a glitch. Besides, the clock switch is guaranteed in a minimum period from a system perspective. Furthermore, the clock enable, divider value and disable can be controlled either by Hardware or by Software.

[0043] The idea is very simple - a gating divider is implemented with the free running clock enables. The clock enables are generated with a Clock Shaper; the Clock Shaper derives the clock enables from a RefClk. The Clock Shaper generates an enable pulse per a divider value on every n -th clock cycle, where n means a divider value. The width of the clock enable is a RefClk clock period. A division by 1 is implemented by setting a clock enable to Ί '. The principle of Gating Divider is shown in Fig.4 whereby the Clock Shaper selects if the input clock cycle is passed through to determine the clock output frequency. Note that any clock shaping does not affect the clock path (i.e. a vast number of selectable frequencies causes no deterioration to the clock path). It should also be kept in mind that a clock splitter can also replace the Clock Shaper 501.

[0044] Fig.4 shows a gating divider with two inputs and one output. The first input is an enabling sequence signal 411 which is generated by a Clock Shaper 410. While enabling sequence is Ί ', a divided clock signal 421 which is generated as an output of the gating divider is enabled by a clock gate 420. One exemplary embodiment of the clock gate is shown in FIG.13 which is a gate-to-low clock gate, meaning that when the enable sequence is '0' the output value is low (or 0) - clock is disabled. The second input InClk 401 receives an input clock "RefClk" which is the reference clock input for the clock gate 420.

[0045] The number of x divided clocks can be derived by one Clock Shaper. As for the output clocks, several dedicated Clock Shapers are not needed per division. The number x is roughly a feasible integer value from 1 to 200. The generated clocks enables are mapped to the clock gates based on a divider value per generated output clock. By replicating a Clock Shaper and a clock gate, the sophisticated clocking schemes can be implemented systematically in a robust way.

[0046] A fast clock change is implemented by decoding at the same time the phases of the clock enables, and the old and new divider values.

[0047] The present invention can be implemented for all kind of designs that do not require 50/50 duty cycle, wherein the 50/50 duty cycle is created only in case of division by 1. A pulse width of the divided clock is the same as the pulse width of the input reference clock signal RefClk 401.

[0048] The present invention utilizes the gating division technique which means that clock is divided by enabling/disabling the clock signal with an appropriate sequence using the Gating Divider principle is depicted in Fig. 4 and as previously mentioned.

[0049] A glitchless Clock Divider, which is shown in an exemplary embodiment of Fig.5, can be divided into four sub-modules: a Clock Shaper 510, an Enable Selection

Multiplexer 560, a Phase Decoding 530 and a Clock Gating 570. In an exemplary embodiment, the phase decoding 530 is coupled to a control interface 520. [0050] In an exemplary embodiment as shown in Fig.5, n identical Clock

Selection and n Gating branches are connected to receive each a reference clock RefClk 501, a clock selection signal 531 and a clock enable signal 561, where n defines the numbers of the generated clocks; Clock 0, Clock 1... Clock n -1. Each branch has its own configuration and is configured through a Control interface 520.

[0051] At a first branch receiving Clock 0: Clock Selection and Gating 550-0 comprises a Clock Gating 570-0 that receives the reference clock 501 and a clock enable 561-0, and an Enable Selection Mux 560-0 that receives a Selection signal 531-0 and the clock enables per a divided clock 511 - 1 , 511 -2, 511 -3 , 511 -4, ... , and 511 -m, where m corresponds to a divisor. The Clock Gating 570-0 generates an output clock signal 571-0.

[0052] Conversely, at a second branch receiving Clock 1 : Clock Selection and Gating 550-1 comprises a Clock Gating 570-1 that receives the reference clock 501 and a clock enable 561-1, and an Enable Selection Mux 560-1 that receives a Selection signal 531-1 and the clock enables per a divided clock 511-1, 511-2, 511-3, 511-4, and 511- m, where m corresponds to a divisor. The Clock Gating 570-1 generates an output clock signal 571-1. In the same way, other output clocks, n > 2, can be derived as illustrated herein.

[0053] The latest Clock Selection and Gating branch is 550-n-l which is configured to receive a selection signal 531 -n-1 - the clock enables are mapped

respectively from the Clock Shaper 510. In this exemplary embodiment, the Clock Shaper 510 generates the clock enables DivBylEn 511-1, DivBy2En 511-2, DivBy3En 511-3, DivBy4En 511-4, and DivBymEn 511-m, where m determines a divisorfor the clock enables. The Control interface 520 determines a divider value for the output clocks. A Clock 0 Divider Value 512-0 determines a clock division for an output clock 571-0.

Conversely, a Clock 1 Divider Value 512-1 determines a clock division for an output clock 571-1, and a Clock n-1 Divider Value 512-n-l determines a clock division respectively for the latest output clock. All Aligned Enabled defines how the clock enables are aligned in the clock change. The clock change and a function of the Phase Decoding 530 are described in Fig.9, Fig.10, Fig.11, and Fig.12.

[0054] In more general terms, the functions and implementation of the four sub- modules of the glitchless clock divider can be as follows: the Clock Gating is coupled to a Clock Selection and it may comprise a set of n Clock Gating 570-0 to 570-n-l . Conversely, the Enable Selection Multiplexer 560 may comprise a set of n Enable Selection Mux 560-0 to 560-n-l . The set of n Clock Gating 570-0 to 570-n-l and the set of n Enable Selection Mux 560-0 to 560-n-l are coupled to the Clock Shaper 510 and the Phase Decoding 530.

[0055] The Clock Shaper 510 generates the clock enables 511 from the RefClk 501. The Clock Shaper can be implemented for instance by utilizing a linear feedback shift register, LFSR, or a counter - where different options are available. The clock enables 511 are free running, that is, the enable sequencing is a continuous process. The functionality of the Clock Shaper 510 is presented on the left in an exemplary Fig.6 where the output sequences are listed and presented with the timing diagram. In the timing diagram of an exemplary gating divider shown in Fig.6, the Clock Shaper 510 generates the clock enable pulses - where the division by 1, 2, 3 and 4 are presented. Other division values above 4 can be derived in the same way. For instance for m division values, the clock enables 511 are mapped into a set of n Enable Selection Multiplexers 560-0 to 560-n-l and also into the Phase Decoding 530.

[0056] The Enable Selection Multiplexer 560 selects the output clock frequency by selecting one of the clock enable input sequences (=programmed clock division value with a phase alignment) for a clock gating component. A mth selection of the Enable Selection Multiplexer sets the clock enable to 'Ο'; the output clock is disabled. The Enable Selection Multiplexer is shown more in detail in Fig.7.

[0057] The Phase Decoding 530 guarantees that a clock enable within the Enable Selection Multiplexer 560 is set at a correct time; once the new division has been set. A top diagram of the Phase Decoding is described in more detail in Fig.8. The division and all aligned values can be set by either by Software or Hardware or both. Four possible implementation for the phase decoding are listed as follows:

d. Phase decoding with fast alignment to closest phase (as illustrated in detail in Fig. 12).

[0058] The Clock Gating 570 gates RefClk 501 with a clock enable 561. The simpliest clock gate implementation is an AND-gate which can be used in the present invention but it might present some restricted timing constraints. Modern novelty recognizes several different clock gating techniques and this invention can utilize any clock gating that gates the clock to low when disabled. Typical and preferred clock gate is shown in an exemplary embodiment in Fig.13.

[0059] One of the many advantages of the present invention is that it enables changing the clock synchronously and fast without blank periods to guarantee glitchless output. The output frequency can be selected by HW or SW on-the-fly and is always glitch free. The clock change is effective with a minimum latency of the clocks or no

implementation latencies at all. The implementation of the invention is very simple and general - also from elaboration and physical synthesis point of view. This implementation may be on a silicon, meaning that the Design-For-Test, DFT, structures have been implemented in a simple way. The glitchless clock change can even be programmed to support the required clocking scheme in the DFT mode.

[0060] The present invention is particularly suited for low power designs. The lower power techniques, for instance a dynamic clock gating, are supported by default and clock gating can be merged to Clock Gating input.

[0061] The present invention becomes even more usefull in future designs as the technology scales down and frequencies increase. One of the advantages is the fact that the present invention does not actually "touch" the critical clock lines. The clock gates are always needed and the present invention can be merged together with normal clock control (as has been already done and proved in silicon). Unlike many other clock generators, the present invention has minimal affect on the clock line parameters such as the jitter, slew, skew, propagation delay, on-chip variation, etc.

[0062] The scenario of 50/50 duty cycle occurs in case of division by 1.

However, most of the designs do not need the 50/50 duty cycle.

[0063] The following tables represent the advantages/disadvanteges of the flip flop dividers and the gating dividers from the front-end and back-end point of views.

Conventional circuit design has been used as an example.

Table 1: Disadvantages/ Advantages of FF and gating dividers presented from a front-end point of view.

Fast Clock Change No Yes

50/50 Duty Cycle Yes Only in case of division by

1.

Simple implementation No (Division by 1 is Yes

problem) Dynamic clock change No (Division by 1 is Yes

problem)

Aligned Clock Change No Yes

One output clock per Yes; this isn't a good design No; plenty of clocks can be divider practice derived from one Clock

Shaper.

Table 2: Disadvantages/ Advantages of FF and gating dividers presented from a back-end point of view.

[0064] Fig.6 illustrates a functionality of the gating divider. The enables are generated per a divisor value - a Clock Shaper generates those pulses. In this example the dividers are supporting division by 1, 2, 3 and 4 as an example. Other division values can be derived the same way. All enables occur at the same time within a blue oval - the phases are aligned. A timing diagram of a gating divider is shown in more detail as it illustrates the waveforms of logical value (low/high: 0/1) of each input and output of a Clock Shaper and the clock gates of Fig.13. In this exemplary embodiment, the timing diagram shows an input clock signal of the Clock Shaper, RefClk 601. The outputs of the Clock Shaper are the clock enables 612-1, 612-2, 612-3 and 612-4. The clock enables are mapped for the clock gates as the inputs. The clock gates derive the gated outputs clocks 611-1, 611-2, 611-3 and 611-4 from the RefClk. A blue circle illustrates the aligned enables, also the derived clock are aligned. In this exemplary embodiment are used as an example the divider values 1, 2, 3, and 4.

[0065] Fig.7 shows how the Clock Enable Multiplexer maps the selected enable for a clock gating component wherein m means number of divisors. It illustrates a programmable clock divider. In this exemplary embodiment, it consists of an enable selection multiplexer 700, an enable selector 720, and a clock gate 730. The programmable clock divider has two inputs. A first input 701 receives a clock signal RefClk. The second input 719 receives a selection signal for the clock enables. The selection signal 719 value determines which one of the mth clock enables are selected as an output pin 721 for the clock gate, where m means an input selection of the enable selector 720 . The clock gate 730 controls an output clock 731 by using the clock enable 721 and a RefClk signal 701. FIG. 13 describes functionality of the clock gate. The Clock Shaper 710 has m outputs, where m means the number of the divisors. The outputs of the Clock Shaper are the clock enables 711-1, 711-2, 711-3, 711-4, and 711-m, where m means the number of the divisors. The clock enable 711-1 means a clock division by 1, the clock enable 711-2 means a clock division by 2, the clock enables 711-3, 711-4 and 711-m mean a clock division respectively by 3, 4 and m.

[0066] Fig.8 shows how a phase decoding switches the selected frequency with a correct time to transmit to the Enable Selection Multiplexer based on the division and all aligned enable values. These values can be set by HW and SW or both. In this exemplary embodiment, n means the number of clocks. The phase decoding has three inputs. A first input 801 receives a clock signal RefClk. RefClk is a reference clock for a Clock Shaper 810. The Clock Shaper 810 has m outputs, where m determines the divisors. The outputs of the Clock Shaper are the clock enables 811-1, 811-2, 811-3, 811-4, and 811-m, where m corresponds to a divisor. The clock enable 811-1 means a clock division by 1, the clock enable 811-2 means a clock division by 2, the clock enables 811-3, 811-4, and 811-m mean a clock division respectively 3,4.., and m. The second input 818 is a Division Value per Clock signal. The Division Value per Clock signal determines which on of the clock enables are mapped for further processing. The third input is an All Aligned Enable signal 819. The Division Value per Clock and All Aligned Enable signals determine which one of the mth clock enables is selected for a clock enable 821. The phase decoding 820 decodes the clock enables 811-1, 811-2, 811-3, and 811-m based on the Division Value per Clock and All Aligned Enable values. The All Aligned Enables signals determine which one of the four clock selections mode is used for the clock enables.

[0067] The timing diagrams of the clock enable schemes are described in the Fig.9, Fig.10, Fig.11, and Fig.12. When All Aligned Enable = 0, the phase decoding uses the clock enable scheme described in Fig.9. When All Aligned Enable = 1, the phase decoding uses the clock enable scheme described in Fig.10. When All Aligned Enable = 2, the phase decoding uses the clock enable scheme described in Fig.11. When All Aligned

Enable = 3, the phase decoding uses the clock enable scheme described in Fig.12. The clock enable 821 is mapped for an enable selection multiplexer. The principle of the enable selection multiplexer was previously described in Fig.7.

[0068] Fig.9 shows a case of Phase decoding with new and old clock edges aligned. 'Phase decoding' observerves the clock shape of new and old 'Clock Shaper' sequences and writes the new selection value to 'Enable selection multiplier' when the new and old values are both high. This is a fast way to apply the new frequency.

[0069] More specifically, Fig.9 shows a timing diagram of a clock change; the clock change takes place when the clock enables of the current and former clock configuration are aligned. The clock frequency, the clock change, is configured with an input signal ModClkSel 912. The figure illustrates the waveforms of logical value

(low/high: 0/1) of the input and output signals as a function of time. In this exemplary embodiment, the timing diagram shows the input clock signal, RefClk signal 901. The clock enables are as the inputs derived from the input clock signal RefClk 901. A Clock Shaper generates clock enables 911-1, 911-2, 911-3, 911-4, and 911-8 which change their states on a positive edge of the input clock 901. The clock enable 911-1 is tied to high; division by 1. The clock enable 911-2 changes its state every second positive edge of the input clock; division by 2. The clock enable 911-3 changes its state every third positive edge of the input clock; division by 3. The clock enable 911-4 changes its state every 4^th positive edge of the input clock; division by 4. The clock enable 911-8 changes its state every 8^th positive edge of the input clock; division by 8. When ModClkSel 912 changes its state from Div2 to Div3; the clock division is changed from division by 2 to division by 3. In the present case, a frequency of the divided clock ModClk 913 is the input clock divided by 2; the clock enable DivBy2En 911-2 is mapped to a clock gate - the ModClk signal is an output. An exemplary embodiment of a clock gate is presented in Fig.13. A phase decoding logic decodes a change of the ModClkSel signal; the state was changed from Div2 to Div3. The phase decoding logic decodes the clock enables DivBy2En and

DivBy3En now. The clock change takes place when both of signals are high; the

DivBy3En signal is mapped to the clock gate instead of the DivBy2En signal; the clock change was taken place now.

[0070] Fig.10 shows a case of Phase decoding with all clock edges aligned.

'Phase decoding' observers a phase of all 'Clock Shaper' sequences and selects the new selection value to 'Enable selection multiplier' when all clock enables are high. In case of several division values, this becomes a slow way to apply the new frequency. However, this is useful if there are several clock outputs whose frequencies are dynamically changed on-the-fly, as in typical multi-clock designs, based on a system load - all output clocks are in the same phase.

[0071] More specifically, Fig.10 shows a timing diagram of a clock change; the clock change takes place when all clock enables are in the same phase; the clock enables are aligned. The clock frequency, the clock change, is configured with an input signal ModClkSel 1012. The figure illustrates the waveforms of logical value (low/high: 0/1) of the input and output signals as a function of time. In this exemplary embodiment, the timing diagram shows the input clock signal, RefClk signal 1001. The clock enables are as the inputs derived from the input clock signal 1001. A Clock Shaper has generated the clock enables 1011-1, 1011-2, 1011-3, 1011-4, and 1011-8. The clock enables changes their states on a positive edge of the input clock. The clock enable 1011-1 is tied to high; division by 1. The clock enable 1011-2 changes a state every second positive edge of the input clock; division by 2. The clock enable 1011-3 changes a state every third positive edge of the input clock; division by 3. The clock enable 1011-4 changes a state every 4^th positive edge of the input clock; division by 4. The clock enable 1011-8 changes a state every 8^th positive edge of the input clock; division by 8. ModClkSel changes its state from Div2 to Div3; the clock division is changed from division by 2 to division by 3. In the present case, a frequency of the divided clock ModClk 1013 is the input clock divided by 2; the clock enable DivBy2En 1011-2 is mapped to a clock gate - the ModClk signal is an output. The clock gate is presented in Fig.13. A phase decoding logic decodes a change of the ModClkSel signal; the state was changed from Div2 to Div3. The phase decoding logic decodes all clock enables now. The clock change takes place when all clock enables are high; the DivBy3En signal is mapped to the clock gate instead of the DivBy2En signal; the clock change was taken place now.

[0072] Fig.11 shows a case of No phase decoding nor edge alignment. High intermediate frequency passed through during clock change. This can cause a fatal malfunction for example in a low operating mode (with lower voltage/reduced

performance) where timing is not met with the highest frequency.

[0073] More specifically, Fig.l 1 shows a timing diagram of a clock change; the clock change takes place immediately - neither phase decoding nor edge alignment. The clock frequency, the clock change, is configured with an input signal ModClkSel 1112.

The figure illustrates the waveforms of logical value (low/high: 0/1) of the input and output signals as a function of time. In this exemplary embodiment, the timing diagram shows the input clock signal, RefClk signal 1101. The clock enables are as the inputs derived from the input clock signal 1101. A Clock Shaper generates the clock enables 1111-1, 1111-2, 1111-3, 1111-4, and 1111-8. The clock enables changes their states on a positive edge of the input clock. The clock enable 1111-1 is tied to high; division by 1. The clock enable 1111-2 changes a state every second positive edge of the input clock; division by 2. The clock enable 1111-3 changes a state every third positive edge of the input clock; division by 3. The clock enable 1111-4 changes a state every 4^th positive edge of the input clock; division by 4. The clock enable 1111-8 changes a state every 8^th positive edge of the input clock; division by 8. ModClkSel changes its state from Div8 to Div3; the clock division is changed from division by 8 to division by 3.

[0074] In the present case, a frequency of the divided clock ModClk 1113 is the input clock divided by 8; the clock enable DivBy8En 1111-8 is mapped to a clock gate - the ModClk signal is an output. The clock gate is presented in Fig.13. A phase decoding logic decodes a change of the ModClkSel signal; the state was changed from Div8 to Div3. The phase decoding logic decodes the DivBy3En signal now. The clock change takes place when the DivBy3En is high; the DivBy3En signal is mapped to the clock gate instead of the DivBy8En signal; the clock change was taken place now.

[0Θ75] Fig.12 shows a case of Phase decoding with fast alignment to the closest phase. There are several different phases for different clock frequencies. The phase decoding decodes the alignments of the phases of the old and new clock selections by applying to closest new frequency phase. This is extremely fast but may introduce phase difference between different clock outputs even though they run at the same frequency.

[0076] More specifically, Fig.12 shows a timing diagram of a clock change; the clock change takes place immediately - neither phase decoding nor edge alignment. This is the fastest way to change the clock frequency; the clock enables per a divided clock are generated for all phases. In the figure is presented the phases of the clock enables for a division by 3 as an example.

[0077] The clock frequency, the clock change, is configured with an input signal ModClkSel 1212. The figure illustrates the waveforms of logical value (low/high: 0/1) of the input and output signals as a function of time. In this exemplary embodiment, the timing diagram shows the input clock signal, RefClk signal 1201. The clock enables are as the inputs derived from the input clock signal 1201.

[0078] A Clock Shaper generates the clock enables 1211-1, 1211-2, 1211-4, and

1211-8. The clock enables changes their states on a positive edge of the input clock. The clock enable 1211-1 is tied to high; division by 1. The clock enable 1211-2 changes a stage every second positive edge of the input clock; division by 2. The clock enable 1211-4 changes a stage every 4^th positive edge of the input clock; division by 4. The clock enable 1211-8 changes a stage every 8^th positive edge of the input clock; division by 8. The clock enables 1211-31, 1211-31, and 1211-33 are generated for all phases; those signals change their state every third positive edge of the input clock; division by 3 - the signals change the state with their dedicated phases. In this examplery embodiment is described the phase enables for the clock divided by 3. All phase enables per the clock enables are generated but not shown in the figure. ModClkSel changes its state from Div2 to Div3; the clock division is changed from division by 2 to division by 3. In the present case, a frequency of the divided clock ModClk 1213 is the input clock divided by 2; the clock enable

DivBy2En 1211-2 is mapped to a clock gate - the ModClk signal is an output. The clock gate is presented in Fig.13. A phase decoding logic decodes a change of the ModClkSel signal; the state was changed from Div2 to Div3. The phase decoding logic decodes the phases of the DivBy3En signal now. The clock change takes place when one of the three phases is high; the phase signal, a DivBy3EnP2 clock enable, is mapped to the clock gate instead of the DivBy2En signal; the clock change was taken place now.

[0079] Fig.13 illustrates an example of a state of the art clock gate (gate-to-low). Typical clock gate consists of a latch and an AND-gate. Instead of using only an AND-gate 1320, it contains also a latch 1310 that allows ClkEn to be passed through only when InClk is low. When InClk is low, the OutClk is low. Hence, the OutClk contains no glitches because of ClkEn cannot be gated to low when InClk is high. The latch 1310 has two inputs EN and D and one output Q. The first input EN receives an input clock InClk 1301 which is the reference clock input. The second input D receives a clock enable signal ClkEn 1302. When the ClkEn signal is high, the clock is enabled (OutClk = InClk). When the ClkEn signal is low, the OutClk clock is low. When the input EN is high Q = D and when the input EN is low Q holds its value. Note that EN is inverted from InClk which is denoted by a small circle in front of the EN pin in Fig.13. Hence, when InClk is low Q = ClkEn value. The output 1311 of the latch can change its value only when InClk is low (EN is high). The AND-gate 1320 receives the output 1311 of latch 1310. When the latch output 1311 is high OutClk = InClk. When the latch output 1311 is low, OutClk = low.

Note: that when InClk is high, the latch output 1311 cannot change the state (prevents gating glitches) because the latch 1310 is disabled (InClk is high).

[0080] Embodiments of the present invention may be implemented as a computer program in the apparatus as previously described. The computer program implemented in the apparatus may carry out, but is not limited to, the functions as described in the appended Figures.

[0081] The computer program may be stored on a computer program distribution medium readable by a computer or a processor. The computer program medium may be, for example but not limited to, an electric, magnetic, optical, infrared or semiconductor system, device or transmission medium. The computer program medium may include at least one of the following media: a computer readable medium, a program storage medium, a record medium, a computer readable memory, a random access memory, an erasable programmable read-only memory, a computer readable software distribution package, a computer readable signal, a computer readable telecommunications signal, computer readable printed matter, and a computer readable compressed software package.

[0082] If desired, the different functions discussed herein may be performed in a different order and/or concurrently with each other. Furthermore, if desired, one or more of the above-described functions may be optional or may be combined.

[0083] Although various aspects of the invention are set out in the independent claims, other aspects of the invention comprise other combinations of features from the described embodiments and/or the dependent claims with the features of the independent claims, and not solely the combinations explicitly set out in the claims.

[0084] It is also noted herein that while the above describes example

embodiments of the invention, these descriptions should not be viewed in a limiting sense. Rather, there are several variations and modifications which may be made without departing from the scope of the present invention as defined in the appended claims.

Claims

CLAIMS:

1. An apparatus, comprising:

- a clock shaper configured to derive a frequency of a reference clock signal into a plurality of frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1... Clock n -1, and configured to generate a plurality of m clock enable signals, where n is a number of gated clocks and m corresponds to a divisor;

- a phase decoding unit configured to decode the plurality of m clock enable signals based on a plurality of received division value per clock signals, and configured to generate a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1... Clock n -1;

2. The apparatus of claim 1 wherein the phase decoding unit is coupled to a control interface for determing the selection of division value per clock signals.

3. The apparatus of claim 1 or 2 wherein each of the n coupled clock selection and gating units is configured through the control interface.

4. The apparatus of any of the preceding claims wherein:

- each of the plurality of n coupled clock selection and gating units comprises a plurality of n enable selection multiplexer units coupled to a plurality of n clock gating units; and

- each of the plurality of n clock gating units receives a clock enable signal from a corresponding enable selection multiplexer unit and the reference clock signal.

5. The apparatus of any one of the preceding claims wherein the phase decoding unit switches the selected frequency with a correct time to transmit an enable selection signal to the plurality of n enable selection multiplexer units.

6. The apparatus of any one of the preceding claims wherein the phase decoding unit implements a process or combination of any one of:

- phase decoding with new and old clock edges aligned;

- phase decoding with all clock edges aligned;

- no phase decoding and no edge alignment; and

- phase decoding with fast alignment to a closest phase.

7. The apparatus of any one of the preceding claims wherein the clock shaper uses a linear feedback shift register or a counter register or an equal clock enable sequence generator.

8. An apparatus comprising:

- means for gating a reference clock signal to produce plurality of frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1, ..., Clock n -1 and for shaping a plurality of m clock enable signals, where n is a number of gated clocks and m corresponds to a divisor;

9. The apparatus of claim 8 wherein the decoding means is coupled to a controlling means for determing the selection of received division value per clock signals.

10. The apparatus of claims 8 or 9 wherein the selecting means is configured through a control interface.

11. The apparatus of claims 8, 9, or 10 wherein: - the selecting means comprises a plurality of n enable selection multiplexer units coupled to a plurality of n clock gating units; and

12. A method, comprising:

- receiving a reference clock signal with a frequency in a clock shaper;

13. The method of claim 12 wherein the gating is associated with the plurality of received division value per clock signals whereby the reference clock signal is gated by enabling/disabling the selected clock enable signal with the selected frequency

corresponding to the output clock frequency.

14. The method of claims 12 or 13 wherein the plurality of m clock enable signals are generated on every m -th clock cycle, where m corresponds to a divisor value.

15. The method of any one of claims 12 to 14 wherein a phase decoding process of the phase decoding unit is any one or any combination of:

- phase decoding with new and old clock edges aligned;

- phase decoding with all clock edges aligned; - no phase decoding and no edge alignment; and

- phase decoding with fast alignment to a closest phase.

16. An apparatus, comprising :

a processor configured to:

- receive a reference clock signal with a frequency in a clock shaper;

17. An apparatus, comprising :

at least one processor; and

at least one memory including computer program code

the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following:

- receive a reference clock signal with a frequency in a clock shaper;

- gate the frequency of the reference clock to produce a plurality of frequencies associated to a plurality of n clocks, Clock 0, Clock 1, ..., Clock n -l, where n is a number of gated clocks;

- decode the plurality of m clock enable signals based on a plurality of received division value per clock signals in a phase decoding unit; - generate a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1... Clock n -1;

18. A computer program, comprising:

- code for generating a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks Clock 0, Clock 1, ..., Clock n -l;

- code for selecting one of the plurality of m clock enable signals with a selected frequency based on the plurality of n clock selection signals; and

when the computer program is run on a processor.

19. The computer program according to claim 18, wherein the computer program is a computer program product comprising a computer-readable medium bearing computer program code embodied therein for use with a computer.