JP2003216268A - Circuit and method for selecting clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for quickly switching a synchronous clock that is now outputted to a selected clock without generating clock switching noise. <P>SOLUTION: A clock selection circuit has an output selection signal generation circuit 3 and an output selection circuit 4. Respective signal lines are connected such that a basic clock signal CK1, frequency division clock signals CK2 to CK4 generated by a frequency dividing circuit 2 and a clock selection signal SEL are inputted to the output selection signal generation circuit 3. In an output port of the output selection signal generation circuit 3, a signal line (2-bit) of an output selection signal OUTSEL is connected to an input port of the output selection circuit 4, and the basic clock CK1 and the frequency division clocks CK2, CK3 and CK4 are respectively inputted to the other input ports. If a value of the clock selection signal SEL changes, the output clock selection signal OUTSEL is changed when phases of frequency division clocks selected on the basis of the current output clock and clock selection signal are uniform. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock selection circuit and a clock selection method, and more particularly to a clock selection circuit and a clock selection circuit which have an improved switching speed when switching from a divided clock currently being output to a clock selected by a selection signal. Regarding the method.

[0002]

2. Description of the Related Art In recent years, with the progress of miniaturization technology of semiconductor elements, LSIs made up of the semiconductor elements have become large in scale. In particular, various microcomputers incorporating a RAM in which these elements are integrated have been developed, and portable devices incorporating these microcomputers are remarkably spread. Since these devices use a battery as a power source, it is required to lower the operating frequency in order to prolong the operating time of the battery.

An example for responding to this request is Japanese Patent Laid-Open No.
No. 00-293261. In the operation clock frequency switching circuit described in the publication, there is proposed a technology for dynamically switching the operation clock frequency of the microcomputer while avoiding generation of noise.

That is, referring also to FIG. 10 showing a circuit diagram of the operation clock frequency switching circuit described in the publication and FIG. 11 showing a timing chart for explaining the operation thereof, the selection signal S is a halved clock. When the selection is instructed, the value of the selection signal S is decoded by the decoding device 201, and only the decode signal o1 becomes active. Here, the decoded signal o1 represents the least significant bit among the 3 bits, o2 represents the second bit, o3 represents the third bit,
001 is a divided clock by 2, 010 is a divided clock by 4, 1
00 designates a clock divided by eight.

The decode signal o1 is the operation clock signal CO
Latched in synchronism with, the decode signal p1 becomes active. In the selection circuit 202, one of the outputs of FF204 to FF206 corresponding to the decoded signals p1 to p3 is selected and output as the signal r1. The signal r1 is inverted by the inverting circuit 203 and output as the signal r2.

That is, when the divided-by-2 clock is selected (S = 0
In 1), a change in the signal level of the inverted signal r2 is output as a high level of a logic level in one clock period and a low level of a logic level in one clock period. When the select signal S selects the clock divided by 4 (S = 10), the inverted signal r
Since the signal level of 2 changes every 2 clocks, 4
The divided clock is output.

As another known technique, there has been proposed a technique for dynamically switching the operating clock frequency of a microcomputer while avoiding the generation of noise.

FIG. 12 showing a block diagram of another conventional example of the clock selection circuit, FIG. 13 showing a circuit diagram of the output selection signal generating circuit in the block diagram and a timing chart for explaining the operation of the clock selection circuit. Referring also to FIG. 14 shown, when all phases of the divided clocks CK2 to CK4 divided by the divider circuit 306 are in the low level period, the NOR circuit 31 in the output signal selection circuit 307.
The switching enable signal CHTRG output from 0 becomes active, and the clock selection signal S held in the FF 311
EL is selected by the selector 312 and propagated to the output clock selection signal OUTSEL via the FF 313. Then, an output clock is selected by the decode circuit 308 and AND circuits 301 to 304 by the output clock selection signal OUTSEL, and output from the OR circuit 305.

[0009]

However, the above-mentioned conventional technique has the following problems. For example, when the frequency division is switched from 2 frequency division to 6 frequency division (the switching stage is skipped), if the direct switching is performed, the result is as shown in FIG. 15, and the clock cannot be switched. That is, in FIG. 12, the effective signal of the output signal of the latch circuit 207 is p.
When switching from 1 to p3, FF204 output q1
To select the in-phase FF206 output q3, that is, because the output signal r1 cannot extend the signal width of the same level after the output signal of the latch circuit 207 is switched as shown in FIG. It is not possible to switch the clock.

Therefore, it is necessary to switch the clocks one by one, such as switching from the divided-by-2 clock to the divided-by-4 clock and switching from the divided-by-4 clock to the divided-by-6 clock.

As a result, the clock must be changed step by step until the maximum divided clock is switched to the minimum divided clock. Therefore, the larger the number of divided stages, the more time is required for the clock switching. There is a drawback that it will end up.

On the other hand, the other conventional examples described above have the following problems.

Since the output selection signal is switched when all phases of the divided clock are aligned, there is a drawback that the cycle for switching the clock depends on the maximum divided clock.

Specifically, in the case of the selection circuit for switching the divided clocks from 2 to 32, the switching timing is generated only every 32 clocks. With this, the reaction of the clock switching becomes worse, such as when switching from 2 division to 4 division.

As described above, the conventional technique has a drawback that the response time from switching the clock selection signal to switching the output clock is slow. For this reason, it is not possible to deal with the enhancement of the time responsiveness in which the low power consumption and the low power consumption state in the standby state are quickly shifted to the high speed processing.

The object of the present invention has been made in view of the above-mentioned conventional drawbacks, and when the synchronous clock is switched, it is selected by the selection signal from the present output clock promptly and without generating clock switching noise. It is to provide a circuit for switching to a different clock.

[0017]

A clock selection circuit according to the present invention comprises a basic clock, a frequency dividing means for generating a plurality of frequency-divided clocks synchronized with the basic clock, the basic clock and a plurality of the frequency-divided clocks. A clock selecting means for selectively outputting an arbitrary clock from, the selecting means monitors only the divided clock to be selected and switched by the divided clock and a selection signal being output,
It is characterized in that it has a function of outputting the clock selected by the lock selecting means instead of the clock being output when the results of phase comparison of the two clocks being monitored match.

Another feature of the clock selection circuit of the present invention is that
A plurality of bits of selection signals respectively corresponding to different divided clock groups are held by holding means, and the divided clocks and the selection signals newly selected before the combination of the plurality of bits of the selection signals are changed. The phase comparison is performed only for the two divided clocks with the selected divided clock after the switching, and the selection signal is generated in response to the switching valid signal that becomes active when the phases of these two divided clocks are aligned. Is provided with clock selection means for selecting and outputting the clock corresponding to the value instructed from the basic clock and the divided clock group.

Further, the basic clock is included in the clocks to be selected in the clock selecting means having the function of phase comparison.

Further, the clock selection means having the function of phase comparison also has a function of selecting the basic clock with a value obtained by decoding the value indicated by the selection signal held by the holding means. .

Furthermore, it is possible to have a function of selectively outputting from the basic clock and the divided clock group only when the values of the selection signal held by the holding means and the switching valid signal are not equal. .

Another feature of the clock selection circuit of the present invention is that a basic clock, a frequency dividing means for generating a plurality of frequency-divided clocks synchronized with the basic clock, and the basic clock and a plurality of the frequency-divided clocks. A clock selecting means for selectively outputting an arbitrary clock, wherein the clock selecting means inputs the basic clock and the clock selecting signal, and outputs the divided clock and the divided clock instructed by the clock selecting signal. Output selection signal generating means for generating a switching valid signal for notifying that the phases match, and a clock corresponding to the value instructed by the clock selection signal in response to the switching valid signal, the basic clock and And output selection means for selectively outputting from the divided clock.

The output selection signal generating means corresponds to the first storage means for latching the clock selection signal at the rising edge of the basic clock and the clock specified by the clock selection signal among the plurality of divided clocks. The first decoding means and the second decoding means for activating one of the divided clocks or deactivating all the divided clocks, and the first decoding means and the second decoding means. A logical sum means for a signal that activates the clock specified by the clock selection signal and one corresponding divided clock based on the active signal among the outputs of the logical sum means are made effective, and all the effective divided clocks are Phase matching means for outputting the switching enable signal that becomes active when the logical level is low, and the switching Selector means for selecting a value latched in the first storage means when a valid signal is active, and a signal selected by the selector means at the falling timing of the basic clock and output as an output clock selection signal. It can be configured with the second storage means.

Further, the first decoding means decodes the value latched by the first storage means and activates only one signal corresponding to any of the plurality of divided clocks. And a configuration for generating a plurality of decode signals in which all are inactive, wherein the second decoding means decodes the output clock selection signal,
It is possible to have a configuration in which only one signal corresponding to any of the plurality of divided clocks is activated or a plurality of decoded signals in which all are inactive are generated.

Furthermore, the output selecting means is composed of a third decoding means and a combinational circuit composed of a plurality of logical product means and one logical sum means, and the third decoding means outputs the output clock selection signal. Decodes to generate a plurality of decode signals corresponding to one of the basic clock and the plurality of divided clocks, and the logical product means receives the basic clock and the plurality of divided clocks, respectively, The plurality of decode signals are also input.

Also, one basic clock and n-
The output selection signal generating means circuit of the clock selection means corresponding to n synchronization clocks composed of 1 (n is an integer) of the divided clocks, and the clock selection signal and the output clock selection signal are n pieces. Has an arbitrary bit width capable of being decoded, each of the first decoding means and the second decoding means outputs n-1 decode signals, and the decode OR means outputs n-1 outputs. A signal is output, and the phase matching means is provided with a configuration for inputting n-1 frequency-divided clocks and the output signal of the decode logical sum means, and may have a function corresponding to n-1 frequency-divided clocks. it can.

Further, the clock selecting means activates the switching enable signal when the second and fourth divided clocks of the divided clocks are both in the high level period of the logic level, and the switching enable signal is It has a function of switching clocks in the active period and at the falling timing of the basic clock.

Furthermore, the phase matching means is a plurality of two-input exclusive inputs for inputting a plurality of logical product means for inputting a plurality of outputs of the decoding logical sum means and a plurality of divided clocks for each pair of the divided clocks. A negative OR means and a plurality of the two corresponding to the outputs of the plurality of AND means, respectively.
It can be constituted by a plurality of logical product means having the outputs of the input exclusive-NOR means as inputs and a logical sum means having the outputs of the plurality of logical product means as inputs.

Further, the clock selecting means has a function of activating the switching enable signal when the phase of the comparison target clock is in either the high level period or the low level period.

The clock selection method of the present invention comprises a basic clock, a frequency dividing means for generating a plurality of frequency divided clocks synchronized with the basic clock, and a clock selecting means for selecting an arbitrary clock from the frequency dividing means. The clock selection means monitors only the frequency-divided clock being output and the frequency-divided clock to be selected and switched by the selection signal, and when the results of phase comparison of the two frequency-divided clocks being monitored match. , The divided clock selected by the lock selection means is output instead of the divided clock being output.

Another feature of the clock selection method of the present invention is that
A plurality of bits of selection signals respectively corresponding to different divided clock groups are held by holding means, and the divided clocks and the selection signals newly selected before the combination of the plurality of bits of the selection signals are changed. Phase comparison is performed on the two divided clocks with the selected divided clock after switching, and the basic clock and the divided clock are generated by a switching valid signal that becomes active when the phases of these two divided clocks are aligned. It is to select and output an arbitrary clock from the clock group by the selecting means.

Further, it is possible to selectively output from the basic clock and the divided clock group only when the values of the selection signal held by the holding means and the switching valid signal are not equal.

Further, the clock selecting means having the function of phase comparison can select the basic clock as one of the selection target clocks.

Furthermore, the basic clock can be selected by a value obtained by decoding the value indicated by the selection signal held by the holding means by the clock selecting means having the function of phase comparison. it can.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the present invention will be described.
When selecting one clock from a plurality of synchronous clocks in a microcomputer, paying attention to the phases of two clocks, the currently output clock and the clock to be selected next when the selection signal changes, the phases are aligned. A feature is that a circuit for generating a clock switching signal is provided at times.

That is, referring to FIG. 1 showing a block diagram of the clock selection circuit in the first embodiment of the present invention and FIG. 2 showing a circuit diagram of the output selection signal generation circuit thereof, for example, the clock selection signal SEL (\ 2 on the signal line
The numerical value shown by means the bit width)
The clock selection signal SEL is latched in the flip-flop FF5 at the rising edge of the basic clock CK1.

The signal latched by FF5 is decoded by the first decoding circuit 8, and the divided clocks CK2 to CK4 are decoded.
One of the decode signals b1 to b3 corresponding to is active or all are inactive.

The output clock selection signal OUTSEL
Is decoded by the second decoding circuit 9, and one of the decode signals c1 to c3 corresponding to the divided clocks CK2 to CK4 becomes active or all become inactive.

Decode signal b1 of the first decode circuit 8
To b3 and the decode signals c1 to c of the second decode circuit 9
Reference numeral 3 denotes a decode logical sum (OR) circuit 10 which takes the logical sum of the respective decode signals corresponding to the divided clocks CK2 to CK4 and outputs signals d1 to d3.

The phase matching circuit 11 compares the phases of the active clocks among the divided clocks corresponding to the output signals d1 to d3 of the decode OR circuit 10.

That is, the phase comparison is performed on the two clocks, the divided clock that was selected before the selection signal SEL was switched and the divided clock that was newly selected by the selection signal SEL. Then, when the phases of the two clocks are aligned, the switching valid signal CHTRG becomes active, and the selector 7 selects the signal latched by the FF 5.

When the fall of the basic clock CK1 occurs while the switching enable signal CHTRG is active, FF6
Thus, the output of the selector 7 is latched and output as the output clock selection signal OUTSEL.

The output selection circuit 4 shown in FIG.
A clock corresponding to the value of the output clock selection signal OUTSEL among the K1 and the divided clocks CK2 to CK4 is output as the output clock CLKOUT.

Therefore, since the clocks are switched when the phases of the clock before the switching of the clock selection signal and the clock after the switching coincide with each other, the divided clocks can be switched step by step or the clock switching timing can be changed as in the conventional case. Since it does not depend on the maximum frequency-divided clock, the clock can be switched swiftly and suppressing generation of noise.

Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, the clock selection circuit 1 has an output selection signal generation circuit 3 and an output selection circuit 4 according to the present invention.

The basic clock signal CK1, the divided clock signals CK2 to CK4 generated by the frequency dividing circuit 2 and the clock selection signal SEL are connected to respective signal lines so as to be input to the output selection signal generation circuit 4. .

At the output end of the output selection signal generation circuit 4, the signal line (2 bits) of the output selection signal OUTSEL is connected to the input end of the output selection circuit 4, and at the other input end, the basic clock CK1 and the divided clock. CK2, CK3 and CK4 are input respectively.

When the value of the clock selection signal SEL changes, the output clock selection signal OUTSEL is changed when the phases of the current output clock and the divided clock selected by the clock selection signal are aligned.

The output of the output selection signal generation circuit 3 is given to the clock selection circuit 4, and the output clock selection signal OUTS is output.
The basic clock CK1 or the divided clocks CK2 to CK4 are output to the output clock signal CLKOUT according to the value of EL.

On the other hand, referring to FIG. 2, the output selection signal generation circuit 3 in FIG. 1 includes an FF5 that latches the clock selection signal SEL at the rising edge of the basic clock CK1, and an F
The clock selection signal SEL is input from F5 and one signal corresponding to the designated clock of the nucleus is activated, or the first decoding circuit 8 that deactivates all the signals and the output clock selection signal OUTSEL described later are input. , A second decoding circuit 9 which activates one signal corresponding to the designated clock in the core output or makes all of the signals inactive, and the core designated clocks b1 to b3 of the first decode circuit 8. An OR10 that takes the logical sum of two signals corresponding to the core designated clocks c1 to c3 of the second decoding circuit 9 when active, for example, the logical sum of b1 and c1.
OR 102, b3 and c3 that take the logical sum of 1, b2 and c2
A decoding OR circuit 10 each having an OR 103 that takes the logical sum of AND, an AND 111 that takes the logical product of the output d1 of the decoding OR circuit 10 and the clock CK2, and an output d2
AND112 which takes the logical product of the clock CK3 and AND113 which takes the logical product of the output d3 and the clock CK4
And N taking the NOR of these AND111-113
A phase matching circuit 11 that has an OR 114 and that makes the divided clock valid based on an active signal of d1 to d3, and that outputs a switching valid signal CHTRG that becomes active when all the effective divided clocks are at a low level; A selector 7 that selects the signal latched by the FF 5 when the switching enable signal CHTRG is active, and an FF 6 that latches the signal selected by the selector 7 at the falling edge of the basic clock CK1 and outputs the above-described output clock selection signal. It is composed of.

In the above-mentioned structure, the first decoding circuit 8 decodes the signal latched by the FF5 and outputs one signal corresponding to any one of the frequency-divided clock CK2, the frequency-divided clock CK3, and the frequency-divided clock CK4. Three decode signals b1 to b3 are generated in which only the signals are active or all are inactive.

The second decoding circuit 9 decodes the output clock selection signal OUTSEL, and divides it by two to generate a clock CK.
Three decoded signals c1 to 1 that make only one signal corresponding to any of the 2/4 clock CK3 and the 8 clock CK4 active or all inactive
Generate c3.

These decode signals b1 to b3 and c1 to
c3 is input to the decode OR circuit 10. Decode O
The R circuit 10 ORs the decode signals b1 to b3 and c1 to c3 of the decode circuits 8 and 9 with a one-to-one relationship.
The signals are input to the circuit and the signals d1 to d3 are output.

The phase matching circuit 11 activates the phase matching signal CHTRG signal when the phases of the divided clocks CK2 to CK4 selected by the signals d1 to d3 are aligned. The signal latched by the clock FF5 is selected by the selector 7 when the phase matching signal CHTRG is active, and is latched by the FF6 at the falling edge of the basic clock CK1. Output clock selection signal OU of the output of FF6
TSEL is input to the output selection circuit 4.

Referring to FIG. 3, which shows a circuit diagram of the output selection circuit 4 of FIG. 1, a third decoding circuit 46 and four A's are provided.
It is composed of ND circuits 41 to 44 and one OR circuit 45. The decode circuit 46 outputs the output clock selection signal O
UTSEL is decoded and decoded signals e1 to e4 corresponding to any one of the basic clock CK1, the divided clock CK2, the divided clock CK3, the divided clock CK4
To generate.

A basic clock C is applied to the AND circuits 41 to 44.
K1 and the three divided clocks CK2 to CK4 are input, respectively, and the decode signals e1 to e4 are also input.

That is, the decode signal e1 is input to the AND circuit 41 together with the basic clock CK1. Also,
The AND circuit 42 receives the decode signal e2 together with the divide-by-2 clock CK2, and the AND circuit 43 receives the decode signal e3 together with the divide-by-four clock CK3.

Further, the decode signal e4 is input to the AND circuit 44 together with the divided-by-8 clock CK4. Then, the outputs of the AND circuits 41 to 44 are input to the OR circuit 45. The output of the OR circuit 45 is the output clock signal CL
It becomes KOUT.

The decoding circuits 8 and 9 of FIG. 2 and the decoding circuit 46 of FIG. 3 are well known to those skilled in the art, and since they are not directly related to the present invention, a detailed configuration thereof will be omitted here.

The operation of this embodiment will be described below. First, the operation when switching from the divided-by-2 clock to the divided-by-8 clock will be described. Referring to FIG. 4, which shows a timing chart for explaining the operation of the first embodiment, at the time T0 in the initial state, the clock selection signal SEL is “01” indicating the frequency division number “2”. Therefore, in both the first decoding circuit 8 and the second decoding circuit 9, the signals b1 and c1 corresponding to the divided-by-two clock are active.
In this case as well, the clock selection signal SEL indicates 01 for 4 frequency division, 10 for 4 frequency division, and 11 for 8 frequency division.

The signals b1 and c1 are active, the other decode signals are inactive, and the switching enable signal CHTR
G becomes active when the divided-by-2 clock is in the low level period.

At this time, when the latch signal of the FF 5 and the value of the output clock selection signal OUTSEL are equal to each other, clock switching does not occur.

At time T1, the clock selection signal SEL is switched to "11" indicating the frequency division number "8".
At this point, the output clock CLKOUT is still a frequency-divided clock.

At time T2, the clock selection signal SEL is latched by the FF5 at the rise of the basic clock CK1 and the output of the first decoding circuit 8 changes.

That is, b1 becomes inactive and b3
Becomes active. Further, in the second decoding circuit 9, the signal corresponding to the divided-by-2 clock, that is, c1 remains active. Then, the decode OR circuit 10 activates d1 and d3, that is, 2 in the phase matching circuit.
The divided clock CK2 and the divided-by-8 clock CK4 are targets for phase comparison. Even at this time, the output clock is still a divide-by-2 clock.

When the signal levels of the divided-by-2 clock CK2 and the divided-by-8 clock CK4 both become low at time T3, the switching valid signal CHTRG becomes active and the selector 7 selects the signal latched by the FF6.

Then, at time T4, the switching effective signal CHT
At the fall of the basic clock CK1 during the active period of RG, it is latched by the FF6, and the output clock selection signal OUTSEL is switched from "01" indicating the frequency division "2" to "11" indicating the frequency division "8". In the output selection circuit 4, since the output selection signal is the frequency division "8", the frequency-divided clock CK4
Is selected, and the basic clock divided by 8 is output from the output clock.

In the above-described first embodiment, the phase comparison circuit compares the phases of only the clocks selected by the current output clock and the clock selection signal and switches the clocks. The output clock can be switched immediately when the phases of the two clocks match, regardless of the external clock.

Therefore, the response speed of clock switching can be improved.

Furthermore, in this embodiment, not only the frequency-divided signal but also the basic clock can be used as the output clock, so that the operating frequency of the microcomputer can be widely used.

Next, a second embodiment of the present invention will be described. Referring to FIG. 5 showing the block diagram of the second embodiment, one basic clock CK1 is the same as that of the first embodiment, but n−1 (n is an integer) frequency-divided clocks. The present embodiment differs from the first embodiment in having an output selection signal generation circuit of a clock selection circuit corresponding to a total of n synchronous clocks.

The clock selection signal SEL and the output clock selection signal OUTSEL have an arbitrary bit width capable of being decoded into n pieces, and the first decoding circuit 80 and the second decoding circuit 90 have n-1 decoding signals b1 to b1. bn-1 and c
1 to cn-1 and the decode OR circuit 100 outputs n-1
The book output signals d1 to dn-1 are output.

Further, the phase matching circuit 110 outputs n-1 divided clocks and the output signals d1 to d1 of the decode OR circuit 100.
Enter dn-1. With such a configuration, it is possible to support many divided clocks.

To explain the operation, referring also to FIGS. 1 to 5, here again, at the time T0 in the initial state, the clock selection signal SEL is selected to be "01" indicating the frequency division number "2", In both the first decoding circuit 8 and the second decoding circuit 9, the signals b1 and c1 corresponding to the divided-by-2 clock are active.

The signals b1 and c1 are active, the other decode signals b2 to bn-1 and c2 to cn-1 are inactive, and the switching valid signal CHTRG becomes active when the divide-by-2 clock is in the low level period. Becomes

Also here, when the latch signal of the FF 5 and the value of the output clock selection signal OUTSEL are equal, the clock switching does not occur.

At time T1, the clock selection signal SEL switches to "11" indicating the frequency division number "8".
At this point, the output clock CLKOUT is still a frequency-divided clock.

At time T2, the clock selection signal SEL is latched by the FF5 at the rise of the basic clock CK1 and the output b1 of the first decoding circuit 80 changes.

That is, b1 becomes inactive and b3
Becomes active. In the second decoding circuit 90, the signal corresponding to the divided-by-two clock, that is, c1 remains active. Then, the decode OR circuit 100 activates d1 and d3, and the other d2 and d4 ...
dn-1 is inactive. That is, in the phase matching circuit 110, the divided-by-2 clock CK2 and the divided-by-8 clock CK
4 is the target of phase comparison. Even at this time, the output clock is still a divide-by-2 clock.

When the signal levels of the divided-by-2 clock CK2 and the divided-by-8 clock CK4 both become low level at time T3, the switching valid signal CHTRG becomes active and the selector 7 selects the signal latched by the FF6.

Then, at time T4, the switching effective signal CHT
At the fall of the basic clock CK1 during the active period of RG, it is latched by the FF6, and the output clock selection signal OUTSEL is switched from "01" indicating the frequency division "2" to "11" indicating the frequency division "8". In the output selection circuit 4, since the output selection signal is the frequency division "8", the frequency-divided clock CK4
Is selected, and the basic clock divided by 8 is output from the output clock.

In the above description, the decode signals of the first decode circuit 80 are b1 and b3, the decode signals c1 and c3 of the second decode circuit, and the output signals d1 and d3 of the decode OR circuit 100 are examples. ~ Bn-1, c1
The same applies to the signals corresponding to .about.cn-1 and d1 to dn-1.

Also in the above-described second embodiment, since the phase comparison of only the clocks selected by the current output clock and the clock selection signal in the phase comparison circuit is performed and the clocks are switched, the comparison target is made. The output clock can be switched immediately when the phases of the two clocks match, regardless of the external clock, and the response speed of clock switching can be improved.

Furthermore, since not only the frequency-divided signal but also the basic clock can be used as the output clock, the operating frequency of the microcomputer can be widely used.

Next, a third embodiment will be described. Third
Referring to FIG. 6 showing the circuit diagram of the phase matching circuit of the embodiment of the present invention and FIG. 7 showing the timing chart for explaining the operation of the third embodiment using the phase matching circuit 12, In the embodiment, when the comparison target clocks are all in the high level period in the phase matching circuit, the switching effective signal C
It shows that the HTRG can be configured to be active.

The phase matching circuit 12 outputs signals d1 to d3.
INV circuits 121 to 123 and signals d1 to
The OR circuits 124 to 126 which receive the polarity inversion signal of d3 and the divided clocks CK2 to CK4, respectively.
AND with the outputs of the OR circuits 124 to 126 as inputs
And a circuit 127.

Referring also to FIGS. 1 to 3 and 6 and FIG. 7 showing a timing chart for explaining the operation of the third embodiment, the clock selection signal SEL is also the frequency division number at the initial state. "01" indicating "2" is selected, and the signals b1 and c1 corresponding to the divided-by-2 clock are active in both the first decoding circuit 8 and the second decoding circuit 9.

The signals b1 and c1 are active, the other decode signals are inactive, and the switching enable signal CHTR
G becomes active when the divided-by-2 clock is in the high level period.

As described above, when the latch signal of the FF5 and the value of the output clock selection signal OUTSEL are equal, the clock switching does not occur.

At the time when the clock selection signal SEL is switched from "2" to "8", the output clock CL is still present.
A clock divided by two is output to KOUT.

At the next rise of the basic clock CK1 at the time when the clock selection signal SEL switches from "2" to "8", the clock selection signal SEL is latched by the FF5 and the output of the first decoding circuit 8 changes.

That is, b1 becomes inactive and b3
Becomes active. Further, in the second decoding circuit 9, the signal corresponding to the divided-by-2 clock, that is, c1 remains active. Then, the decode OR circuit 10 activates d1 and d3, that is, 2 in the phase matching circuit.
The divided clock CK2 and the divided-by-8 clock CK4 are targets for phase comparison. Even at this time, the output clock is still a divide-by-2 clock.

At T5, when the signal levels of the divided-by-2 clock CK2 and the divided-by-8 clock CK4 both become high level, the switching valid signal CHTRG becomes active and the selector 7 selects the signal latched by the FF6.

As shown in FIG. 7, when the divided clocks CK2 and CK4 are both in the high level period, the switching valid signal CHTRG becomes active, and the selector 7 selects the signal latched by the FF6. Clock switching is performed at time T5 when the switching valid signal CHTRG is the fall of the basic clock CK1 in the active period.

That is, the switching enable signal CHTRG is latched by the FF6 at the time T5 when the basic clock CK1 falls during the active period, and the output clock selection signal OUTSEL is divided from "01" indicating "2" to "8". Is switched to "11" indicating "." In the output selection circuit 4, since the output selection signal is the frequency division "8", the frequency-divided clock CK4
Is selected, and the basic clock divided by 8 is output from the output clock.

Also in the third embodiment described above, the phase comparison is performed in the phase comparison circuit only for the clocks selected by the current output clock and the clock selection signal, and the clocks are switched. The output clock can be switched immediately when the phases of the two clocks match, regardless of the external clock, and the response speed of clock switching can be improved.

Furthermore, since not only the frequency-divided signal but also the basic clock can be used as the output clock, the operating frequency of the microcomputer can be widely used.

Next, a fourth embodiment will be described.

Phase matching circuit 1 in the fourth embodiment
Referring to FIG. 13 showing the circuit diagram of FIG. 3 and FIG. 9 showing the timing chart for explaining the operation of the fourth embodiment using the phase matching circuit 13, in the present embodiment, the phase matching circuit is shown. 13 shows a configuration in which the switching enable signal CHTRG becomes active when the phases of the comparison target clocks are aligned in either the high level period or the low level period.

In FIG. 8, the phase matching circuit 13 includes AND circuits 131 to 133 which receive signals d1 and d2, d2 and d3, d3 and d1, respectively, and a divided clock CK2.
And CK3, CK3 and CK4, CK4 and CK2 as inputs, and EX-NOR circuits 135 to 137, and AN
Outputs of D circuits 131 to 133 and EX-NOR circuit 135
AND circuits 138 to 14 which receive the outputs of
0 and the inputs of the outputs of the AND circuits 138 to 140
And an R circuit 141.

Referring also to FIGS. 1 to 3 and 8 and FIG. 9 showing a timing chart for explaining the operation of the fourth embodiment, the clock selection signal SEL is the frequency division number also in the initial state. "01" indicating "2" is selected, and the signals b1 and c1 corresponding to the divided-by-2 clock are active in both the first decoding circuit 8 and the second decoding circuit 9.

The signals b1 and c1 are active, the other decode signals are inactive, and the switching enable signal CHTR
G becomes active when the divided-by-2 clock is in the low level period.

As described above, when the latch signal of FF5 and the value of the output clock selection signal OUTSEL are equal, the clock switching does not occur.

Then, when the clock selection signal SEL is switched from the frequency division number "2" to "11" indicating "8", the output clock CLKOUT is still the frequency-divided clock 2.

When the clock selection signal SEL switches from "2" to "8", the clock selection signal SEL is latched by the FF5 at the rise of the basic clock CK1.
The output of the first decoding circuit 8 changes.

That is, b1 becomes inactive and b3
Becomes active. Further, in the second decoding circuit 9, the signal corresponding to the divided-by-2 clock, that is, c1 remains active. Then, the decode OR circuit 10 activates d1 and d3, that is, 2 in the phase matching circuit.
The divided clock CK2 and the divided-by-8 clock CK4 are targets for phase comparison. Even at this time, the output clock is still a divide-by-2 clock.

When the signal levels of the divided-by-2 clock CK2 and the divided-by-8 clock CK4 both become low at time T6, the switching valid signal CHTRG becomes active and the selector 7 selects the signal latched by the FF6.

When the phases of the divided clocks CK2 and CK4 are aligned, the divided clocks are low level and the signal levels match at time T6 in FIG. 9, and the clocks are switched at time T7.

That is, the switching enable signal CHTRG is latched by the FF6 at the time T7 when the basic clock CK1 falls during the active period, and the output clock selection signal OUTSEL changes from "01" indicating the frequency division "2" to "8". Is switched to "11" indicating "." In the output selection circuit 4, since the output selection signal is the frequency division "8", the frequency-divided clock CK4
Is selected and the basic clock divided by 8 is output from the output clock CLKOUT.

Also in the above-described fourth embodiment, since the phase comparison of only the clocks selected by the current output clock and the clock selection signal in the phase comparison circuit is performed and the clocks are switched, the comparison target is made. The output clock can be switched immediately when the phases of the two clocks match, regardless of the external clock, and the response speed of clock switching can be improved.

Furthermore, since not only the frequency-divided signal but also the basic clock can be used as the output clock, the operating frequency of the microcomputer can be widely used.

[0113]

As described above, according to the clock selection circuit and the clock selection method of the present invention, the phase comparison circuit performs the phase comparison only between the current output clock and the clock selected by the clock selection signal, and switches the clock. Since the output clock is switched, the output clock can be switched immediately when the phases of the two clocks match each other regardless of the clocks that are not compared, so that the response speed of clock switching can be improved.

Since the basic clock can also be used as the output clock, the operating frequency of the microcomputer can be widely used.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output selection signal generation circuit 3 of FIG.

3 is a circuit diagram of an output selection circuit 4 of FIG.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a block diagram of a second embodiment.

FIG. 6 is a circuit diagram of a phase matching circuit 12 according to a third embodiment.

FIG. 7 is a timing chart for explaining the operation of the third embodiment.

FIG. 8 is a circuit diagram of a phase matching circuit 13 according to a fourth embodiment.

FIG. 9 is a timing chart for explaining the operation of the fourth embodiment.

FIG. 10 is a circuit diagram of a conventional operation clock frequency switching circuit.

11 is a timing chart for explaining the operation of FIG.

FIG. 12 is a block diagram of another conventional example of a clock selection circuit.

13 is a circuit diagram of the output selection signal generation circuit of FIG.

14 is a timing chart for explaining the operation of the clock selection circuit of FIG.

FIG. 15 is a timing chart when switching from 2 division to 6 division in the conventional example of FIG.

[Explanation of symbols]

1 selection circuit 2, 306 frequency division circuit 3, 307 output selection signal generation circuit 4 output selection circuit 5, 6, 204, 205, 206, 311, 313
FF7 Selector 8, 80 First decoding circuit 9, 90 Second decoding circuit 10, 100 Decoding OR circuit 11, 12, 13, 110 Phase matching circuit 121, 122, 123 INV circuit 124, 125, 126, 141, 305 OR circuits 127, 131, 132, 133, 138, 139, 1
40, 301, 302, 303, 304 AND circuits 135, 136, 137 EX-NOR circuits 201, 308 Decoding circuit 202 Selection circuit 207 Latch circuit 310 NOR circuit

Claims (18)

[Claims] 1. A basic clock, a frequency dividing means for generating a plurality of frequency-divided clocks synchronized with the basic clock, and a clock selecting means for selectively outputting an arbitrary clock from the basic clock and the plurality of frequency-divided clocks. The clock selection means monitors only the divided clock that is being output and the divided clock that should be selected and switched by the selection signal, and the results of phase comparison of the two clocks that are being monitored match. Sometimes, a clock selection circuit having a function of outputting the clock selected by the lock selection means instead of the clock being output. 2. A plurality of bits of selection signals respectively corresponding to different divided clock groups are held by holding means, and the divided clocks selected before the combination of the plurality of bits of the selection signals are switched and the divided clocks. Phase comparison is performed only for the two divided clocks with the divided clock after switching, which is newly selected by the selection signal, and responds to the switching valid signal that becomes active when the phases of these two divided clocks are aligned. The clock selection circuit further comprises clock selection means for selectively outputting the clock corresponding to the value indicated by the selection signal from the basic clock and the divided clock group. 3. The clock selection circuit according to claim 1, wherein the selection target clock in the clock selection means having the phase comparison function includes the basic clock. 4. The clock selecting means having the function of phase comparison also has a function of selecting the basic clock with a value obtained by decoding a value indicated by the selection signal held by the holding means. The clock selection circuit according to claim 2. 5. Only when the values of the selection signal and the switching valid signal held by the holding means are not equal to each other,
4. The clock selection circuit according to claim 3, which has a function of selectively outputting from the basic clock and the divided clock group. 6. A basic clock, frequency dividing means for generating a plurality of divided clocks synchronized with the basic clock, and clock selecting means for selecting and outputting an arbitrary clock from the basic clock and the plurality of divided clocks. The clock selection means inputs the basic clock and the clock selection signal and notifies that the phases of the divided clock being output and the divided clock instructed by the clock selection signal match when they match. Output selection signal generating means for generating a switching valid signal, and output selecting means for selectively outputting a clock corresponding to a value indicated by the clock selection signal from the basic clock and the divided clock in response to the switching valid signal. And a clock selection circuit. 7. The output selection signal generation means corresponds to a first storage means for latching the clock selection signal at a rising edge of a basic clock and a clock designated by the clock selection signal among a plurality of the divided clocks. A first decoding means and a second decoding means for activating one of the divided clocks or deactivating all of the divided clocks, and the first decoding means and the second decoding means. AND means of the signal that activates the clock specified by the clock selection signal,
A phase matching circuit that validates a corresponding one of the divided clocks based on an active signal among the outputs of the logical sum means, and outputs the switching valid signal that becomes active when all the valid divided clocks are at the low level of the logical level. Means and selector means for selecting the value latched in the first storage means when the switching enable signal is active;
7. The clock selection circuit according to claim 6, further comprising: second storage means for latching the signal selected by the selector means at the falling timing of the basic clock and outputting it as an output clock selection signal. 8. The first decoding means decodes the value latched by the first storage means and activates only one signal corresponding to any one of the plurality of divided clocks, The second decoding means decodes the output clock selection signal and outputs one signal corresponding to any one of the plurality of divided clocks. 8. The clock selection circuit according to claim 7, wherein the clock selection circuit is configured to generate a plurality of decode signals in which only all of them are active or all of them are inactive. 9. The output selection means is composed of a third decoding means and a combinational circuit composed of a plurality of logical product means and one logical sum means, and the third decoding means decodes the output clock selection signal. A plurality of decode signals corresponding to the basic clock and a plurality of the divided clocks are generated, and the logical product means receives the basic clock and the plurality of divided clocks, respectively, and 8. The clock selection circuit according to claim 7, having a configuration in which a plurality of decode signals are also input. 10. One said basic clock and n-1.
(N is an integer) The output selection signal generating means circuit of the clock selection means corresponding to n synchronous clocks composed of the divided clocks, and the clock selection signal and the output clock selection signal are n. The first decoding means and the second decoding means each output n-1 decoded signals, and the decoding logical sum means has n-1 output signals. 7. The phase matching means is configured to input n-1 frequency-divided clocks and the output signal of the decoding logical sum means, and has a function corresponding to n-1 frequency-divided clocks. The described clock selection circuit. 11. The clock selecting means activates the switching valid signal when both the second and fourth divided clocks of the divided clock are in a high level period of a logical level, and the switching valid signal is 11. The clock selection circuit according to claim 10, which has a function of switching clocks during an active period and at a falling timing of the basic clock. 12. The phase matching means inputs a plurality of logical product means for inputting a plurality of outputs of the decoding logical sum means and a plurality of two-input exclusive negations for inputting the plurality of divided clocks in a combination of two sets each. A logical sum means, a plurality of logical product means having inputs of outputs of the plurality of two-input exclusive-NOR means corresponding to outputs of the plurality of logical product means, and outputs of the plurality of logical product means. 8. The clock selection circuit according to claim 7, which is configured by a logical sum means for inputting. 13. The clock selection device according to claim 12, wherein the clock selection means has a function of activating the switching enable signal when the phase of the comparison target clock is aligned in either a high level period or a low level period. circuit. 14. A clock selecting means comprising: a basic clock; a frequency dividing means for generating a plurality of frequency-divided clocks synchronized with the basic clock; and a clock selecting means for selecting an arbitrary clock from the frequency dividing means. Monitor only the frequency-divided clock being output and the frequency-divided clock that should be selected and switched by the selection signal. A clock selection method, wherein the divided clock selected by the lock selection means is output instead of the divided clock. 15. A holding unit holds a selection signal of a plurality of bits respectively corresponding to different divided clock groups, and the divided clock selected before the combination of the plurality of bits of the selection signal is switched and the divided clock. Phase comparison is performed on the two divided clocks with the divided clock after the switching newly selected by the selection signal, and the switching effective signal that becomes active when the phases of these two divided clocks are aligned causes the above-mentioned basic A clock selecting method characterized in that an arbitrary clock is selected and output from a clock and the divided clock group by a selecting means. 16. The clock selection according to claim 15, wherein the basic clock and the divided clock group are selectively output only when the selection signal held by the holding means and the switching valid signal are not equal in value. Method. 17. The clock selection method according to claim 14, wherein the clock selection means having the function of phase comparison also selects the basic clock as one of the selection target clocks. 18. The basic clock is selected by a value obtained by decoding a value designated by the selection signal held by the holding means by the clock selecting means having the function of phase comparison. The clock selection method described.