WO2010050097A1 - Clock division circuit, clock distribution circuit, clock division method, and clock distribution method - Google Patents

Abstract

Provided is a clock division circuit which generates a clock signal enabling execution or a correct communication expected in the communication with a circuit operating at a different frequency clock.  The clock division circuits (10a, b) reduce S clock pulses in the input clock signal by S – N clock pulses in accordance with the division ratio defined by the N/S so as to generate an output clock signal obtained by N/S-dividing the input clock signal.  The clock division circuits (10a, b) generates a control signal which reduces with a higher priority, the clock pulses other  than those at the communication timing of the data communication performed by a target circuit using the output clock signal among the S clock pulses of the input clock signal.  Furthermore, the clock pulses of the input clock signal are reduced in accordance with the generated control signal, thereby generating an output clock signal.

Description

Clock dividing circuit, clock distributing circuit, clock dividing method and clock distributing method

The present invention relates to a clock dividing circuit, a clock distributing circuit, a clock dividing method, and a clock distributing method, and more particularly, a clock dividing circuit and a clock distributing circuit that generate and distribute clock signals having different frequencies to each of a plurality of functional blocks. The present invention relates to a clock dividing method and a clock distributing method.

As a method of distributing clock signals with different frequencies to each of a plurality of circuits (functional blocks) integrated in a semiconductor device, a clock signal with a lower frequency is divided from a clock signal with a certain frequency for each functional block. A method of generating and distributing to each functional block has been proposed.

In a clock frequency dividing circuit that divides a clock signal having a lower frequency from a clock signal having a certain frequency, the frequency division ratio, that is, the ratio of the frequency of the clock signal before frequency division to the frequency of the clock signal after frequency division is 1 /. A frequency dividing circuit (integer frequency dividing circuit) of M (M is an integer) can be easily realized by using a counter circuit.

On the other hand, a frequency dividing circuit (rational number frequency dividing circuit) capable of frequency division even when the frequency dividing ratio is N / M (N and M are integers) has been proposed (for example, Patent Document 1 and Patent Document). 2). According to these background arts, first, a value for setting the numerator of the division ratio (the value of N in the division ratio N / M) is cumulatively added for each cycle of the input clock signal. Next, when the addition result becomes larger than a value for setting the denominator of the division ratio (the value of M in the division ratio N / M), M is subtracted from the addition result. By performing these operations and referring to the result of the addition, the rational pulse division is realized by appropriately masking (thinning out) the clock pulses of the input clock signal.

Also, as the semiconductor device becomes larger and its operating frequency increases, a relative phase shift between clock signals distributed on the semiconductor device, so-called clock skew, becomes a big problem. When the clock skew becomes large, the upper limit of the operating frequency of the synchronous circuit is limited, so that the performance is degraded.

As a technique for reducing clock skew, a clock tree circuit in which a clock buffer and clock wiring are configured in a tree shape is known. This clock tree circuit uses a clock buffer in each hierarchy of the clock tree. Furthermore, the delay of the clock propagation path from the input end of the clock tree to each output end is made the same by performing the design layout so that the load capacitance and the wiring resistance are the same. Therefore, the phase difference of the clock signal between the output terminals becomes relatively small, and it can be expected that the clock skew is reduced.

Referring to FIG. 8 and FIG. 9, a specific example of a problem in the clock divider circuit and the clock distribution circuit according to the background art will be described.

FIG. 8 shows a circuit Ai (i is an integer satisfying 1 ≦ i ≦ 64) operating with a clock Ai (i is an integer satisfying 1 ≦ i ≦ 64), a communication circuit N operating with a clock N, a clock tree circuit 20, and a plurality of 2 is an example of a semiconductor integrated circuit including a clock frequency dividing circuit 100. FIG. The circuits Ai are connected to the communication circuit N and communicate with each other through the communication circuit N. A clock frequency divider circuit 100 is connected to each output terminal of the clock tree circuit 20 to constitute a clock distribution circuit composed of the clock tree circuit 20 and a plurality of clock frequency divider circuits 100.

The clock tree circuit 20 uses the clock buffer 22 in each hierarchy of the clock tree and performs a design layout so that the load capacitance and wiring resistance are the same. Thereby, the clock skew of the clock S and the clock Ai is reduced. Further, the clock N is also distributed by a clock tree circuit (not shown), so that the distribution delays of the clock N and the clock S are the same. As a result, the clock skew of the clock N, the clock S, and the clock Ai is reduced, and the circuit Ai and the communication circuit N communicate with each other synchronously.

The background clock division circuit 100 generates a clock Ai by rationally dividing the clock S distributed by the clock tree circuit 20 based on the input division ratio setting.

The clock frequency dividing circuit 100 according to the background art realizes frequency division by selectively masking the clock pulse of the input clock signal. However, communication with the communication circuit N that operates with clocks having different frequencies is not considered. Therefore, when communicating with the communication circuit N, there is a problem that a special clock change circuit and a special timing design are required. Further, as a result, there is a problem that communication performance deteriorates. Further, when the frequency division ratio is changed, there is a problem that the timing of communication with the communication circuit N needs to be changed accordingly.

FIG. 9 is a timing diagram showing an example of clock division by the clock divider circuit 100 according to the background art. A clock Ai generated by dividing the clock S by a frequency division ratio of 11/12 to 4/12 is shown. The clock Ai can be generated by appropriately masking the clock pulse of the input clock S. For example, a clock Ai with a division ratio of 9/12 masks three clock pulses at timings T3, T8, and T11 among twelve clock pulses at timings T0 to T11 of the clock S. It is generated with.

Here, it is assumed that the frequency of the clock N is 1/3 of the clock S. That is, the frequency division ratio of the clock N to the clock S is 1/3 (= 4/12). At this time, the phase relationship between the clock N and the clock Ai circulates in 12 cycles of the clock S. The timing of 12 cycles in which this phase relationship makes a round is indicated by T0 to T11.

Here, it is assumed that the circuit Ai and the communication circuit N communicate at timings T0, T3, T6, and T9, which are all rising timings of the clock N. More specifically, the circuit Ai outputs a signal to the communication circuit N and inputs a signal from the communication circuit N at timings T0, T3, T6, and T9. Similarly, at timings T0, T3, T6, and T9, the communication circuit N outputs a signal to the circuit Ai and inputs a signal from the circuit Ai.

However, the clock frequency dividing circuit 100 according to the background art does not consider communication with clocks having different frequencies. Therefore, even at the timing of this communication, the clock Ai may be generated by masking the clock pulse of the clock S.

In the case of the example of FIG. 9, the clock Ai may be generated by masking the clock pulse of the clock S at T3, T6, and T9 among the communication timings. Specifically, at timing T3, the clock pulse is masked when the frequency division ratio is 9/12 (110a), 6/12 (110b), and 5/12 (110c). Similarly, at timing T6, the clock pulse is masked in the case of 5/12 (110d). Similarly, at timing T9, the clock pulse is masked when the frequency division ratio is 7/12 (110e), 6/12 (110f), and 5/12 (110g).

When the clock Ai is generated by masking the clock pulse of the clock S at the timing of communication as in the above case, the signal output from the communication circuit N operating at the clock N is transferred to the circuit Ai operating at the clock Ai. It will not be possible to input at the expected timing. Similarly, the circuit Ai operating with the clock Ai cannot output a signal at the timing expected by the communication circuit N operating with the clock N.

Therefore, the clock divider circuit according to the background art requires a special clock transfer circuit and a special timing design in order to realize the expected correct communication operation in communication with a circuit operating with a clock of a different frequency. There is a problem of becoming. As a result, there is a problem that communication performance is degraded. Furthermore, when the frequency division ratio is changed, there is a problem that the timing of communication with a clock having a different frequency needs to be changed accordingly.
Further, in the clock distribution circuit in which the clock divider circuit 100 is connected to each output terminal of the clock tree circuit 20 shown in FIG. 8, the clock S distributed by the clock tree circuit 20 has a frequency that is not always divided. High clock signal. Therefore, there is a problem that the power consumption of the clock tree circuit 20 is large.

JP 2005-45507 A JP 2006-148807 A

As described above, the clock frequency dividing circuit and the clock distribution circuit according to the background art cause the first problem that it is difficult to perform a correct communication operation expected in communication with a circuit operating with a clock having a different frequency. .
In addition, a second problem occurs that the power consumption of the clock tree circuit is large.

An object of the present invention is invented in view of the first problem, and generates a clock signal that enables a correct communication operation expected in communication with a circuit operating with a clock of a different frequency. It is an object of the present invention to provide a clock frequency divider circuit, a clock distribution circuit, a clock frequency division method, and a clock distribution method.
Another object of the present invention according to another aspect is to provide a clock divider circuit, a clock distribution circuit, a clock division method, and a clock distribution method that can reduce the power consumption of the clock tree circuit in order to solve the second problem. It is in.

The clock frequency dividing circuit according to the present invention is based on a frequency dividing ratio defined by N / S (N is a positive integer, S is a positive integer larger than N), out of S clock pulses of the input clock signal. , (S−N) clock divider circuits for generating an output clock signal obtained by dividing the input clock signal by N / S by reducing the number of clock pulses. A control circuit for generating a control signal for preferentially reducing clock pulses other than the communication timing of data communication performed by the target circuit using the output clock signal, and the control generated by the control circuit A processing circuit is provided for generating the output clock signal by reducing clock pulses of the input clock signal in response to the signal.

The clock distribution circuit according to the present invention includes a clock tree circuit, a first clock frequency dividing circuit that performs first frequency division on the input clock signal and outputs the clock signal to the clock tree circuit, and the clock signal. A plurality of clock signals output from the tree circuit, a second frequency dividing circuit for each of the clock signals, and a second clock frequency dividing circuit for outputting to the plurality of target circuits. .

The clock frequency dividing method according to the present invention is based on a frequency dividing ratio defined by N / S (N is a positive integer, S is a positive integer larger than N), out of S clock pulses of an input clock signal. , A clock dividing method for generating an output clock signal obtained by dividing the input clock signal by N / S by reducing S−N clock pulses, the S clocks of the input clock signal being Among the pulses, a clock pulse other than the communication timing of data communication performed in the target circuit using the output clock signal is determined, and the output clock signal is generated by decreasing the determined clock pulse.

In the clock distribution method according to the present invention, the first frequency division is performed on the input clock signal, the clock signal on which the first frequency division is performed is divided into a plurality, and the second clock signal is distributed to the distributed clock signal. Is divided and output to a plurality of circuits.

According to the present invention, a clock frequency dividing circuit, a clock distribution circuit, a clock frequency dividing method, and a clock for generating a clock signal that enable a correct communication operation expected in communication with a circuit operating with a clock having a different frequency. A distribution method can be provided.
In addition, according to another aspect of the present invention, it is possible to provide a clock divider circuit, a clock distribution circuit, a clock division method, and a clock distribution method that can reduce the power consumption of the clock tree circuit.

It is a block diagram of the semiconductor integrated circuit in this invention. 1 is a configuration diagram of a clock frequency dividing circuit according to a first embodiment of the invention; It is a timing diagram which shows the example of a clock frequency division concerning Embodiment 1 of invention. It is a timing diagram which shows the example of a clock frequency division concerning Embodiment 1 of invention. It is a block diagram of the clock frequency divider circuit concerning Embodiment 2 of invention. It is a timing diagram which shows operation | movement of the clock frequency divider circuit concerning Embodiment 2 of invention. It is a timing diagram which shows operation | movement of the clock frequency divider circuit concerning Embodiment 2 of invention. It is a block diagram of the semiconductor integrated circuit by background art. It is a timing diagram which shows the example of clock division by background art.

Embodiment 1 of the Invention
First, the clock distribution circuit according to the first exemplary embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a circuit Ai (i is an integer satisfying 1 ≦ i ≦ 64) operating with a clock Ai (i is an integer satisfying 1 ≦ i ≦ 64), a communication circuit N operating with a clock N, a clock tree circuit 20, and a clock component. This is an example of a semiconductor integrated circuit including peripheral circuits 10a and 10b. The same components as those in the example of the semiconductor integrated circuit according to the background art shown in FIG.

The circuits Ai are connected to the communication circuit N and communicate with each other through the communication circuit N. A clock frequency divider circuit 10a is connected to each output terminal of the clock tree circuit 20, and a clock frequency divider circuit 10b is connected to an input terminal of the clock tree circuit 20 to constitute a clock distribution circuit.

The clock tree circuit 20 reduces the clock skew of the clock S by using the clock buffer 22 in each hierarchy of the clock tree and performing the design layout so that the load capacitance and the wiring resistance are the same. Further, the clock N is also distributed by a clock tree circuit (not shown), so that the distribution delays of the clock N and the clock S are the same. As a result, the clock skew of the clock N, the clock S, and the clock Ai is reduced, and the circuit Ai and the communication circuit N communicate with each other synchronously.

FIG. 2 is a configuration diagram showing the configuration of the clock frequency dividing circuit 10 in the present embodiment. The clock frequency dividing circuit 10 is given by a frequency dividing ratio defined by N / M (N is a positive integer, M is a positive integer larger than N) given by the frequency dividing ratio setting 35 and input clock frequency dividing ratio information 61. Of the S clock pulses of the clock IN (input clock signal) consecutively based on the frequency division ratio information of the clock IN defined by S / M (S is a positive integer, M is a positive integer larger than S). Of these, (S−N) clock pulses are masked. As a result, the clock frequency dividing circuit 10 generates a clock OUT (output clock signal) obtained by dividing the clock IN by a rational number with a frequency division ratio of N / S.

Here, the clock IN is a clock divided by S / M. Therefore, the clock frequency dividing circuit 10 generates the clock OUT divided by the N / M frequency dividing ratio with respect to the clock signal that has not been frequency-divided. In other words, the clock frequency dividing circuit 10 is input based on the frequency division ratio S / M given by the input clock frequency division ratio information 61 based on the frequency division ratio N / M given by the frequency division ratio setting 35. The clock signal is divided by a rational number with a frequency division ratio of N / S. As a result, the clock frequency dividing circuit 10 outputs an output clock corresponding to a clock signal obtained by dividing the clock signal that has not been divided by a frequency dividing ratio of N / M (= (S / M) × (N / S)). Generate a signal.

In addition to the above-described frequency division ratio setting 35 and input clock frequency division ratio information 61, the clock frequency dividing circuit 10 further receives communication timing information 36 indicating the timing at which a circuit operating with the clock OUT performs communication. Based on the above, a clock OUT is generated in consideration of the communication timing.

The clock frequency dividing circuit 10 includes a mask circuit 50 and a mask control circuit 30 as main circuits.
The mask circuit 50 is a processing circuit having a function of generating and outputting the clock OUT by masking the clock pulse of the clock IN in accordance with the input mask signal 39.

The mask control circuit 30 is a control circuit having a function of outputting a mask signal 39 to the mask circuit 50 based on communication timing information 36 indicating a timing at which a circuit operating with the clock OUT performs communication. The mask signal 39 is a number (S−N) that is a difference between S and N with respect to other timings except for the communication timing at which the communication is performed, among the timings of S clock pulses that are continuous. This is a signal to which a mask timing for masking the minute clock pulse is assigned.

Further, the mask control circuit 30 has a larger division ratio (N / M) than the timing to which the mask timing is assigned when the division ratio is small (the value of N / M or N / S is large). Even when the value of M or N / S is small), the mask signal 39 to which the mask timing is assigned is always output to the mask circuit 50.

In the present embodiment shown in FIG. 1, the clock frequency dividing circuits 10 a and 10 b are clock frequency dividing circuits having the same configuration as the clock frequency dividing circuit 10. The clock frequency dividing circuit 10a rationally divides the clock S ′ distributed by the clock tree circuit 20 based on the input frequency division ratio setting 35, the communication timing information 36, and the input clock frequency division ratio information 61. A clock Ai is generated. The clock frequency dividing circuit 10b divides the clock S by a rational number based on the input frequency division ratio setting 35, communication timing information 36, and input clock frequency division ratio information 61, thereby distributing the clock S distributed by the clock tree circuit 20. Generate '.

All the circuits Ai communicate with the communication circuit N at the same timing, for example, the timing of all rising edges of the clock N. Accordingly, all the clock frequency dividing circuits 10a and 10b are supplied with the same communication timing information 36 indicating the timing.

On the other hand, each circuit Ai may have a different operating frequency. Accordingly, each clock frequency dividing circuit 10a may be supplied with a frequency division ratio setting 35 having a different value. Further, in the frequency division ratio setting 35 of the clock frequency division circuit 10b, the frequency division ratio setting 35 in which the smallest frequency division ratio (the value of N / M is large) among all the clock frequency division circuits 10a is set. Is supplied with the same value.

Further, each clock frequency dividing circuit 10a is supplied with input clock frequency dividing ratio information 61 indicating the frequency of the clock S ′ that is the input clock of the clock frequency dividing circuit 10a. Similarly, input clock frequency division ratio information 61 indicating the frequency of the clock S that is the input clock of the clock frequency dividing circuit 10b is supplied to the clock frequency dividing circuit 10b.

The above-described frequency division ratio setting 35, communication timing information 36, and input clock frequency division ratio information 61 supplied to the clock frequency dividing circuits 10a and 10b may be supplied by an upper circuit (not shown) or the circuit Ai. Either of these may be supplied.

Next, the operation of the clock frequency dividing circuit according to the first exemplary embodiment of the present invention will be described with reference to FIG. 3 and FIG.

FIG. 3 is a timing chart showing the operation of the clock divider circuit 10b according to the first exemplary embodiment of the present invention. Here, the division ratio denominator M = 12, and the division ratio numerator N = 11-3. An example in which the clock S ′ is generated by dividing the clock S by a frequency division ratio of 11/12 to 3/12 will be described.

Also, the clock S that is the input clock signal is a clock signal that is not divided. Therefore, in the frequency division ratio S / M of the clock S given by the input clock frequency division ratio information 61, the input clock frequency division ratio numerator S = 12, and the input clock frequency division ratio denominator M = 12. Therefore, in this example, N / M = N / S.

In FIG. 3, the frequency of the clock N is 1/4 of the clock S. That is, the frequency division ratio of the clock N to the clock S is 1/4 (= 3/12), and the clock N is synchronized with the clock S. At this time, the phase relationship between the clock N and the clock S ′ circulates in 12 cycles of the clock S. In FIG. 3, T0 to T11 indicate the timings of 12 cycles in which this phase relationship makes a round. The circuit Ai performs data communication at timings T0, T4, and T8 corresponding to the rising timing of the clock N.

The difference between the clock divider circuit 10 according to the first embodiment of the present invention and the clock divider circuit 100 according to the background art is that the clock divider circuit 10 according to the first embodiment of the present invention indicates the timing of the communication. The timing information is input and rational number division is performed in consideration of the communication timing based on the timing information. Specifically, it is characterized in that rational frequency division is realized by masking clock pulses that are not in communication timing without masking clock pulses that are in communication timing at all times. Further, when the division ratio is small (the value of N / M or N / S is large), the division ratio is larger (N / M or N / S) than the timing at which the clock pulse is masked. Even when the value is small), rational number division is realized by always masking at this timing.

In the clock division example of FIG.
(1) At timings T0, T4, and T8, which are communication timings, clock pulses are not always masked, and timings T1, T2, T3, T5, T6, T7, T9, T10, which are not other communication timings, Mask the clock pulse at any of T11,
And,
(2) In contrast to the timing when the clock pulse is masked when the division ratio is small, the timing is always masked at the timing when the division ratio is large.
Thus, the clock S ′ is generated.

Therefore, the mask control circuit 30 masks SN clock pulses for any of the timings T1, T2, T3, T5, T6, T7, T9, T10, and T11 that are not the timing of the communication. At the timing when the clock pulse is masked when the frequency division ratio is small, a mask signal 39 to which a mask timing for masking is always assigned even when the frequency division ratio is large is generated.

Such a clock S ′ can be generated by additionally assigning the timing for masking the clock pulse from the case where the frequency division ratio is small.

For example, if a mask timing is assigned to timings other than T0, T4, T8, for example, timing T9 out of 12 clock pulses at timings T0 to T11 of clock S, a clock with a division ratio of 11/12 S ′ can be generated. Furthermore, if a mask timing is additionally assigned to T5, a clock S ′ having a frequency division ratio of 10/12 can be generated. Furthermore, by additionally assigning to T1, a clock S ′ having a frequency division ratio of 9/12 can be generated. Furthermore, if additional allocation is made for T7, a clock S ′ having a frequency division ratio of 8/12 can be generated.

Furthermore, if additional allocation is made to T11, a clock S ′ having a frequency division ratio of 7/12 can be generated. Furthermore, if additional allocation is performed for T3, a clock S ′ having a frequency division ratio of 6/12 can be generated. Furthermore, if additional allocation is performed for T2, a clock S ′ having a frequency division ratio of 5/12 can be generated. Furthermore, if additional allocation is performed for T10, a clock S ′ having a frequency division ratio of 4/12 can be generated. Furthermore, if additional allocation is made for T6, a clock S ′ having a frequency division ratio of 3/12 can be generated.

FIG. 4 is a timing chart showing the operation of the clock divider circuit 10a according to the first exemplary embodiment of the present invention. The operation of the clock frequency dividing circuit 10a is the same as that of the clock frequency dividing circuit 10b shown in FIG. 3 except that the input clock is a clock S ′ that may be frequency-divided by the clock frequency dividing circuit 10b. is there. The timing for masking the clock pulse with respect to the clock S is also the same.

Here, the case where the division ratio N / M given by the division ratio setting 35 is set to the division ratio denominator M = 12, and the division ratio numerator N = 9 to 3 will be described as an example. At this time, it is assumed that the clock S ′ as the input clock signal is a clock obtained by dividing the clock S by a division ratio of 9/12. Therefore, in the division ratio S / M that defines the division ratio of the clock S ′ given by the input clock division ratio information 61, the input clock division ratio numerator S = 9 and the input clock division ratio denominator M = 12. is there.

In other words, this is an example in which the clock Ai is generated by dividing the clock S ′ having the division ratio of 9/12 by the division ratio of 9/9 to 3/9. Accordingly, this is an example in which the clock Ai corresponding to the clock signal obtained by dividing the clock S by the frequency division ratio 9/12 to 3/12 is generated.

As described above, the frequency dividing ratio setting 35 of the clock frequency dividing circuit 10b is the frequency dividing ratio in which the smallest frequency dividing ratio (the value of N / M is large) among all the clock frequency dividing circuits 10a is set. The same value as the ratio setting 35 is supplied. Therefore, in this example, the clock frequency dividing circuit 10a generates the clock Ai divided by any of the frequency dividing ratios 9/12 to 3/12. FIG. 4 also shows the waveform of the clock Ai when the division ratio is 11/12 and 10/12 for comparison with FIG. 3, but in this example, those division ratios are set. There is no.

4, the frequency of the clock N is ¼ of the clock S, as in FIG. 3. That is, the frequency division ratio of the clock N to the clock S is 1/4 (= 3/12), and the clock N is synchronized with the clock S. The clock S ′ is generated by dividing the clock S by a frequency division ratio of 9/12. At this time, the phase relationship between the clock N and the clock S ′ or the clock Ai makes a round in 12 cycles of the clock S. In FIG. 4, the timing of 12 cycles in which this phase relationship makes a round is indicated by T0 to T11. The circuit Ai and the communication circuit N perform data communication at timings T0, T4, and T8 corresponding to the rising timing of the clock N.

Also in the clock division example of FIG.
(1) At timings T0, T4, and T8, which are communication timings, clock pulses are not always masked, and timings T1, T2, T3, T5, T6, T7, T9, T10, which are not other communication timings, Mask the clock pulse at any of T11,
And,
(2) In contrast to the timing when the clock pulse is masked when the division ratio is small, the timing is always masked at the timing when the division ratio is large.
As a result, the clock Ai is generated.

Therefore, the mask control circuit 30 masks SN clock pulses for any of timings T1, T2, T3, T5, T6, T7, T9, T10, and T11 that are not the timing of this communication. In addition, a mask signal 39 is generated in which a mask timing that is always masked at this timing is assigned to the timing at which the clock pulse is masked when the frequency division ratio is small, even when the frequency division ratio is large.

As described above, the clock distribution circuit according to the first embodiment uses the frequency division ratio S / G given by the input clock frequency division ratio information 61 based on the frequency division ratio N / M given by the frequency division ratio setting 35. The input clock signal divided by M is divided by a rational number at a division ratio of N / S, thereby corresponding to a clock signal obtained by dividing an undivided clock signal by a division ratio of N / M. An output clock signal is generated. Therefore, the frequency can be reduced by dividing the input clock signal in advance.

Further, the clock distribution circuit according to the first embodiment always generates a clock by masking the timing at which the clock pulse is masked when the frequency division ratio is small, even when the frequency division ratio is large. . Further, the frequency division ratio setting of the clock frequency dividing circuit 10b is the frequency division ratio in which the smallest frequency dividing ratio (the value of N / M or N / S is large) is set among all the clock frequency dividing circuits 10a. The same value as the setting is supplied. Therefore, the clock frequency dividing circuit 10a can generate a clock Ai having a frequency dividing ratio equal to or larger than the frequency dividing ratio of the clock S ′ from the clock S ′ divided by the clock frequency dividing circuit 10b. . This is because at the timing masked with the clock S ′, it is always masked even with the clock Ai, and at the timing not masked with the clock Ai, it is not masked with the clock S ′.

In other words, among all the clocks Ai, the clock S ′ can be divided by the same division ratio as the smallest division ratio (the value of N / M is large). For this reason, the frequency of the clock signal (clock S ′) distributed by the clock tree circuit 20 can be reduced. Therefore, the power consumption of the clock tree circuit 20 can be reduced.

On the other hand, as in the clock division example according to the background art shown in FIG. 9, in the clock distribution method that does not consider the division at the input end of the clock tree circuit, the smallest division among all the clocks Ai is not necessarily used. The clock S ′ cannot be divided by the same division ratio as the ratio.

For example, in the example of FIG. 9, there is no clock pulse at timings T3 and T8 in the clock S ′ having a frequency division ratio of 9/12. Therefore, a clock Ai having a division ratio of 8/12, 7/12, 6/12, 4/12, which requires a clock pulse at timing T3 or T8, is generated from the clock S ′ having a division ratio of 9/12. Can not do it. For this reason, even if the smallest dividing ratio among all the clocks Ai is 9/12, the clock S ′ cannot necessarily be divided by the dividing ratio of 9/12. Therefore, even if a clock divider circuit is connected to the input end of the clock tree, the power consumption of the clock tree circuit cannot be reduced sufficiently.

Further, in the first embodiment, the mask control circuit 30 generates the mask signal 39 and outputs it to the mask circuit 50. The mask signal 39 masks the clock pulse with respect to other timings excluding the communication timing at which the communication is performed based on the communication timing information 36 indicating the timing of the communication performed between the circuit Ai and the communication circuit N. This signal is assigned with mask timing. As a result, the clock pulse is masked from the clock S and the clock S ′ and the clock Ai are generated at other timings except the communication timing at which communication is performed between the circuit Ai and the communication circuit N.

Therefore, the clock pulse of the clock Ai is not masked at the communication timing, and the clock pulse is always output to the clock Ai at the communication timing. In response to this, the circuit Ai can receive the signal output from the communication circuit N at an expected timing. Similarly, the circuit Ai can output a signal at the timing expected by the communication circuit N.

Therefore, according to the clock frequency dividing circuit according to the first embodiment, communication performance is not deteriorated even with a communication partner circuit (communication circuit N) operating with a clock signal (clock N) having a different frequency. An output clock signal (clock Ai) capable of data communication can be generated. This eliminates the need for special timing design and special clock transfer circuit for communication with clock signals of different frequencies, and can divide the clock signal by a rational number with low power, low area, and low design cost. It becomes possible.

In the first embodiment, the mask control circuit 30 masks the clock pulse with respect to other timings excluding the communication timing at which communication is performed in the communication partner circuit in accordance with the frequency division ratio setting 35. Added mask timing. Therefore, for example, even when the division ratio N / M is changed to any one of 11/12 to 3/12, the clock pulses of the clocks S and S ′ are generated at timings other than the communication timings T0, T4, and T8. Can be masked. Therefore, even when the division ratio is changed, it is not necessary to change the clock N or communication timing of the communication circuit N, and it is possible to cope with the change of the division ratio extremely flexibly.

Embodiment 2 of the Invention
Next, with reference to FIG. 5, a clock divider circuit according to the second exemplary embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of a clock frequency divider circuit according to the second exemplary embodiment of the present invention. In the second embodiment of the present invention, specific examples of the mask circuit 50 and the mask control circuit 30 of the clock frequency dividing circuit 10 according to the first embodiment will be described.

In FIG. 5, a mask circuit 50 has a function of referring to an input mask signal 39 and selecting either masking the clock IN pulse or outputting it directly to the clock OUT without masking. ing. In the second embodiment, the mask circuit 50 includes a latch circuit 52 and a gate circuit 53.

The latch circuit 52 latches the mask signal 39 at the timing when the clock IN falls, thereby limiting the transition of the mask signal 39 input to the gate circuit 53 to the timing when the value of the clock IN is “0”. It has a function. The gate circuit 53 has a function of masking the clock IN based on the mask signal 39 latched by the latch circuit 52. When the value of the mask signal 39 is “0”, the clock IN is masked. When the value of the mask signal 39 is “1”, the clock IN is not masked.

By providing the latch circuit 52, it is possible to suppress the occurrence of a glitch in the clock OUT. Although there is an effect that the timing design is facilitated, the latch circuit 52 may be omitted when the occurrence of a glitch is avoided by strictly designing the timing. In FIG. 5, an AND circuit is used as the gate circuit 53 for masking the clock IN. However, the present invention is not limited to this. An OR circuit may be used, or a circuit having an equivalent function may be used.

The mask control circuit 30 counts clock pulses of the clock IN based on the frequency division ratio setting 35, the communication timing information 36, and the input clock frequency division ratio information 61. Thus, a counter value indicating the relative phase between the clock IN and the clock OUT is generated, and a mask signal 39 to which a mask timing is assigned based on the counter value is generated and output.

In the second embodiment, the mask control circuit 30 includes a counter 33 and a table circuit 31. The frequency division ratio setting 35 includes a frequency division ratio denominator M and a frequency division ratio numerator N composed of parallel data of a plurality of bits, and defines the frequency division ratio setting N / M.

The communication timing information 36 includes a timing selection signal 37 and a phase signal 38. The timing selection signal 37 is obtained from each timing in a period in which the phase relationship between the clock OUT (clock S ′ or clock Ai) and the clock signal (clock N) that drives the communication partner circuit operating on the clock OUT is completed. , A signal for selecting a communication timing. The timing selection signal 37 is composed of a plurality of bits of parallel data indicating a value specifying the communication timing, and the value does not change unless the communication timing is changed. The phase signal 38 is a signal indicating a relative phase relationship between the clock OUT and a clock signal (hereinafter, referred to as a communication partner clock signal) that drives a communication partner circuit of a circuit that operates on the clock OUT.

The input clock frequency division ratio information 61 is composed of a frequency division ratio numerator S composed of parallel data of a plurality of bits, and defines the frequency division ratio S / M of the input clock signal. The value of the denominator M is the same as the value in the frequency division ratio setting 35, and the input of the frequency division ratio denominator M constituting the frequency division ratio setting 35 is used, and redundant input is omitted.

The counter 33 counts the clock pulses of the clock IN, and resets the counter value in accordance with the timing of the phase signal 38 when the phase relationship between the clock OUT and the communication partner clock signal makes a round, and communicates with the clock OUT. It has a function of outputting a counter value 34 indicating a relative phase with the counterpart clock signal. As a result, the counter 33 outputs, as the counter value 34, the number of cycles in which the phase relationship between the clock OUT and the communication partner clock signal makes a round.

The table circuit 31 is a combination of a counter value 34, a division ratio denominator M and a division ratio numerator N that are division ratio settings 35, a division ratio numerator S that is input clock division ratio information 61, and a timing selection signal 37. Each has a function of preliminarily holding table data 32 indicating the necessity of masking in a table format and a function of selecting and outputting table data corresponding to a combination of these inputted values as a mask signal 39. Yes. Thus, the mask circuit 50 masks the clock pulse of the clock IN in accordance with the frequency division ratio denominator M, the frequency division ratio numerator N, the counter value 34, the frequency division ratio numerator S, and the timing selection signal 37 from the table circuit 31. A mask signal 39 for controlling whether or not to perform is output for each clock pulse of the clock IN.

Next, with reference to FIG. 6 and FIG. 7, the operation of the clock divider circuit according to the second exemplary embodiment of the present invention will be described.

FIG. 6 is a timing chart showing the operation of the clock divider circuit 10b according to the second exemplary embodiment of the present invention.

Here, a case where a clock S ′ having a frequency division ratio of 9/12 is generated from the clock S will be described. Note that the circuit Ai and the communication circuit N perform data communication at all rising timings of the clock N, and the clock N is synchronized with the clock S, and the frequency division ratio thereof is 1/4. . In other words, the circuit Ai and the communication circuit N communicate at timings T0, T4, and T8.

The timing selection signal 37 is a signal indicating that the timing of this communication is the timing T0, T4, T8, and the value does not change unless the communication timing is changed.

The phase signal 38 is a signal that becomes “1” in any one cycle of the rising timing of the clock N while the phase relationship between the clock S ′ and the clock N makes a round, and becomes “0” otherwise. In the case of FIG. 6, the phase relationship becomes “1” at the timing T <b> 0 that is one cycle of the 12 cycles of the clock S that makes a round.

The clock S that is an input clock signal is a clock signal that is not divided. Therefore, since the frequency division ratio is 1, that is, S / M = 12/12, a value 12 is set for the frequency division ratio numerator S.

The counter 33 resets the counter value at the timing when the phase signal 38 becomes “1”. Thereafter, the clock pulses of the clock S are counted by repeating 12 cycles in which the phase relationship between the clock S ′ and the clock N is completed. As a result, a counter value 34 indicating the relative phase relationship between the clock S ′ and the clock N is output from the counter 33.

In FIG. 6, the timing at which the counter value 34 takes a value from “0” to “11” corresponds to the timing T0 to T11. That is, the counter value 34 is “0” at timing T0, “1” at timing T1, and “11” at timing T11. Thereafter, it becomes “0” again at the timing T0.

The table data 32 of the table circuit 31 includes a pulse of the next cycle of the clock S for each combination of the division ratio denominator M, the division ratio numerator N, the counter value 34, the division ratio numerator S, and the timing selection signal 37. “0” is preset when masking, and “1” is preset when not masking. Therefore, the value of the table data 32 corresponding to the combination of the division ratio denominator M, the division ratio numerator N, the counter value 34, the division ratio numerator S, and the timing selection signal 37 input at each timing is the mask signal 39. Is output as

In the case of FIG. 6, the table circuit 31 includes combinations of timings T0 to T11 corresponding to other timings T1, T5, and T9 other than the communication timing of data communication performed between the circuit Ai and the communication circuit N. Table data 32 to which mask timing is assigned is set in advance. Further, non-mask timings are assigned to combinations corresponding to timings T0, T2, T3, T4, T6, T7, T8, T10, and T11 other than these.

Thus, for example, when the counter value is “1”, “5”, “9”, “0” indicating the mask timing as the table data 32, and “0” indicating the non-mask timing as the table data 32 otherwise. 1 ”is output from the table circuit 31 as the mask signal 39. The mask circuit 50 refers to the mask signal 39, masks the pulse of the clock S at timings T1, T5, and T9, and outputs it to the clock S ′ without masking the pulses at other timings.

Therefore, among the timings T0 to T11, at the communication timings T0, T4, and T8, the clock pulse of the clock S is not always masked and is output as the clock S ′. In addition, among the timings T0 to T11, clock pulses at other timings that are not communication timings, here, timings T1, T5, and T9 are masked and are not output as the clock S ′.

FIG. 6 shows a generation example in the case where the frequency division ratio of the clock S ′ is 9/12, the frequency of the clock N is 1/4 of the clock S, and communication is performed at all rising timings of the clock N. The same applies to other cases. The value of the table data 32 is appropriately set for each combination of the communication timing information 36, the division ratio setting 35, the input clock division ratio information 61, and the counter value 34 indicating the relative phase relationship between the clock S ′ and the clock N. By setting, it is possible to achieve any rational division by masking clock pulses that are not in communication timing without always masking clock pulses in communication timing.

In FIG. 6, the values of the frequency division ratio denominator M, the frequency division ratio numerator N, the frequency division ratio numerator S, etc., which are input to the mask control circuit 30 are constant. As long as it is within the range in which the table data 32 corresponding to is held, it can be appropriately changed during operation.

FIG. 7 is a timing chart showing the operation of the clock frequency dividing circuit 10a according to the second exemplary embodiment of the present invention.

Here, a case where a clock Ai having a frequency division ratio of 5/12 is generated from a clock S ′ having a frequency division ratio of 9/12 generated by the clock frequency dividing circuit 10b will be described. Note that the circuit Ai and the communication circuit N perform data communication at all rising timings of the clock N, and the clock N is synchronized with the clock S, and the frequency division ratio thereof is 1/4. . In other words, the circuit Ai and the communication circuit N communicate at timings T0, T4, and T8.

The timing selection signal 37 is a signal indicating that the timing of this communication is the timing T0, T4, T8, and the value does not change unless the communication timing is changed.

The phase signal 38 is a signal that becomes “1” in any one cycle of the rising timing of the clock N while the phase relationship between the clock Ai and the clock N completes, and becomes “0” otherwise. In the case of FIG. 7, the phase relationship becomes “1” at the timing T <b> 0, which is one cycle of the 12 cycles of the clock S.

Since the division ratio S / M of the clock S ′ that is the input clock signal is 9/12, the value 9 is set in the division ratio numerator S.

The counter 33 resets the counter value at the timing when the phase signal 38 becomes “1”, and then repeats the 12 cycles of the clock S and the 9 cycles of the clock S ′ in which the phase relationship between the clock Ai and the clock N goes around. To count the clock pulses of the clock S ′. As a result, a counter value 34 indicating the relative phase relationship between the clock Ai and the clock N is output from the counter 33. Since the counter 33 operates with the clock S ′, the counter value 34 takes values “0” to “8” corresponding to nine cycles of the clock S ′.

In FIG. 7, the timing at which the counter value 34 takes a value from “0” to “8” corresponds to the timing T0 to T11. That is, the counter value 34 is “0” at timing T0, “1” at timings T1 and T2, “2” at timing T3, “3” at timing T4, “4” at timings T5 and T6, and “4” at timing T7. 5 ”,“ 6 ”at timing T8,“ 7 ”at timings T9 and T10, and“ 8 ”at timing T11. Thereafter, it becomes “0” again at the timing T0.

The table data 32 of the table circuit 31 includes a pulse of the next cycle of the clock S ′ for each combination of the division ratio denominator M, the division ratio numerator N, the counter value 34, the division ratio numerator S, and the timing selection signal 37. “0” is set in advance when masking is set, and “1” is set when not masking. Therefore, the value of the table data 32 corresponding to the combination of the division ratio denominator M, the division ratio numerator N, the counter value 34, the division ratio numerator S, and the timing selection signal 37 input at each timing is the mask signal 39. Is output as

In the case of FIG. 7, the table circuit 31 includes other timings T1, T2, T3, T5, T7, T9 other than the communication timing of data communication performed between the circuit Ai and the communication circuit N among the timings T0 to T11. Table data 32 in which mask timings are assigned to combinations corresponding to T11 is set in advance. Further, non-mask timing is assigned to combinations corresponding to timings T0, T4, T6, T8, and T10 other than these.

Thus, for example, when the counter value is “1”, “2”, “5”, “8”, “0” indicating the mask timing as the table data 32, otherwise, the table data 32 is not masked. “1” indicating the timing is output as a mask signal 39 from the table circuit 31. The mask circuit 50 refers to the mask signal 39, masks the pulse of the clock S ′ at timings T1, T2, T3, T5, T7, T9, and T11, and does not mask the pulses at other timings. Output to clock Ai.

Therefore, among the timings T0 to T11, at the timings T0, T4, and T8 which are communication timings, the clock pulse of the clock S ′ is not always masked and is output as the clock Ai. In addition, among the timings T0 to T11, clock pulses at other timings that are not communication timings, here, timings T1, T2, T3, T5, T7, T9, and T11 are masked and are not output as the clock Ai.

In FIG. 7, the frequency division ratio of the clock S ′ is 9/12, the frequency division ratio of the clock Ai is 5/12, the frequency of the clock N is 1/4 of the clock S, and at every rising timing of the clock N. Although an example of generation in the case of performing communication is shown, the same applies to other cases. The value of the table data 32 is appropriately set for each combination of the communication timing information 36, the division ratio setting 35, the input clock division ratio information 61, and the counter value 34 indicating the relative phase relationship between the clock Ai and the clock N. By doing so, it is possible to realize arbitrary division of rational numbers by masking clock pulses that are not in communication timing without always masking clock pulses in communication timing.

In FIG. 7, the values of the frequency division ratio denominator M, the frequency division ratio numerator N, the frequency division ratio numerator S, and the like input to the mask control circuit 30 are constant. As long as it is within the range in which the table data 32 corresponding to is held, it can be changed appropriately during operation.

As described above, in the second embodiment, in the mask control circuit, the clock pulse of the input clock signal is counted by the counter, and the output clock signal and the circuit that is the communication partner of the circuit that operates on the output clock signal are driven. A count value that indicates the relative phase of communication timing with respect to the input clock signal is generated by resetting the count value when the phase relationship with the clock signal is completed, and a mask that is assigned a mask timing based on this count value Since the signal is generated, the relative phase of the communication timing with respect to the input clock signal can be derived with a very simple circuit configuration called a counter, and the mask timing can be accurately assigned from a timing other than the communication timing. .

In the second embodiment, in the mask control circuit, table data indicating whether or not masking is necessary for each combination of at least the communication timing information, the division ratio setting, the input clock division ratio information, and the count value is previously stored in the table circuit. The table data output from the table circuit according to these input combinations is output as a mask signal, so the input clock can be used from a timing other than the communication timing with a very simple circuit configuration called a table circuit. A desired mask timing according to the relative phase of the communication timing with respect to the signal can be accurately assigned.

In the second embodiment, in the mask control circuit, table data indicating whether or not masking is necessary for each combination of at least the communication timing information, the division ratio setting, the input clock division ratio information, and the count value is previously stored in the table circuit. The table data output from the table circuit is output as a mask signal in accordance with these input combinations, so that even if the input clock signal is a divided clock signal, other than the communication timing From the timing, a desired mask timing according to the relative phase of the communication timing with respect to the input clock signal can be accurately assigned.

In the second embodiment, the frequency division ratio setting 35 input by the mask control circuit 30 includes the frequency division ratio denominator M indicating the denominator value of the frequency division ratio and the frequency division indicating the numerator value of the frequency division ratio. Although it is composed of the specific numerator N, another form may be used as long as the division ratio can be set. Similarly, the communication timing information input by the mask control circuit 30 is composed of a timing selection signal 37 for selecting the communication timing, and a phase signal 38 indicating the phase relationship between the output clock signal and the communication partner clock signal. However, another format may be used as long as the communication timing can be designated. Further, signals unnecessary for setting the frequency division ratio and specifying the communication timing may be omitted as appropriate. For example, when the communication timing is only a specific timing, it is not necessary to prepare the table data 32 for each value of the timing selection signal 37, so that the timing selection signal 37 can be omitted.

Further, the clock divider circuit 10 according to the second embodiment is composed of only a digital logic circuit, and selects either whether or not the clock IN is masked to realize rational frequency division. The layout area is small. Further, since an analog circuit or a circuit that requires a dedicated design is not used, the design / verification cost is low.

This application claims priority based on Japanese Patent Application No. 2008-278497 filed on Oct. 29, 2008, the entire disclosure of which is incorporated herein.

The present invention can be widely applied to the field of semiconductor circuits that distribute clock signals having different frequencies to a plurality of circuit blocks, and electronic equipment using the same.

10, 10a, 10b Clock divider circuit 20 Clock tree circuit 22 Clock buffer 30 Mask control circuit 31 Table circuit 32 Table data 33 Counter 34 Counter value 35 Division ratio setting 36 Communication timing information 37 Timing selection signal 38 Phase signal 39 Mask signal 50 mask circuit 52 latch circuit 53 gate circuit 61 input clock division ratio information 100 clock division circuit

Claims (17)

1. Based on the frequency division ratio defined by N / S (N is a positive integer, S is a positive integer greater than N), (S−N) clocks out of S clock pulses of the input clock signal A clock frequency dividing circuit for generating an output clock signal obtained by dividing the input clock signal by N / S by reducing the pulse;
   A control circuit that generates a control signal that preferentially decreases clock pulses other than the communication timing of data communication performed by the target circuit using the output clock signal among S clock pulses of the input clock signal;
   And a processing circuit that generates the output clock signal by reducing clock pulses of the input clock signal in accordance with a control signal generated by the control circuit.
2. The processing circuit includes a processing circuit that generates the output clock signal by masking a part of a plurality of clock pulses included in the input clock signal according to the control signal. 2. The clock frequency dividing circuit according to claim 1, wherein:
3. 3. The clock circuit according to claim 2, wherein the control circuit includes a clock pulse that is a mask target when the frequency division ratio is small and that is included in the mask target when the frequency division ratio is larger than the clock pulse. Divider circuit.
4. The control circuit includes a table circuit that preliminarily stores table data indicating whether or not a mask is necessary for each combination of a frequency division ratio denominator S and a frequency division ratio numerator N that define the frequency division ratio. 3. The clock frequency dividing circuit according to claim 2, wherein the table data output from the table circuit is output as the control signal in response to.
5. The table circuit divides S / M (S is a positive integer, M is a positive integer larger than S) that defines the frequency division ratio of the input clock signal in the frequency division ratio denominator S and the frequency division ratio numerator N. 5. The clock frequency dividing circuit according to claim 4, wherein table data indicating whether or not a mask is necessary is held in advance for each combination to which a frequency ratio denominator M is added.
6. The control circuit counts clock pulses of the input clock signal with a counter, and resets the count value when the count value reaches the frequency division ratio denominator S, whereby the communication timing for the input clock signal is set. 6. The clock frequency dividing circuit according to claim 2, wherein a count value indicating a relative phase of the clock is generated, and the control signal is generated based on the count value.
7. The table circuit indicates whether or not a mask is necessary for each combination of the frequency division ratio denominator S, the frequency division ratio numerator N, and the frequency division ratio denominator M plus the information related to the communication timing and the count value. 5. The clock divider circuit according to claim 4, wherein the clock data is held in advance in a table circuit, and table data output from the table circuit is output as the control signal in accordance with the input combination.
8. The information on the communication timing further includes communication timing selection information for selecting a communication timing in the target circuit from each timing in a period in which the phase relationship between the clock signal used for the communication operation in the target circuit and the output clock signal goes around. 8. The clock divider circuit according to claim 1, further comprising a clock divider circuit.
9. A clock tree circuit;
   A first clock frequency dividing circuit for performing a first frequency division on the input clock signal and outputting to the clock tree circuit;
   A clock including a plurality of clock signals output from the clock tree circuit, a second frequency division for each of the clock signals, and a second clock frequency dividing circuit for outputting to the plurality of target circuits Distribution circuit.
10. The first clock frequency dividing circuit performs the first frequency division based on the same frequency division ratio as the smallest frequency division ratio among the second frequency divisions in the second clock frequency dividing circuit. The clock distribution circuit according to claim 9.
11. 11. The clock distribution according to claim 9, wherein the clock signal output from the second clock divider circuit includes all clock pulses corresponding to timings at which the plurality of target circuits perform data communication. circuit.
12. Based on the frequency division ratio defined by N / S (N is a positive integer, S is a positive integer greater than N), (S−N) clocks out of S clock pulses of the input clock signal A clock dividing method for generating an output clock signal obtained by dividing the input clock signal by N / S by reducing pulses;
    Of the S clock pulses of the input clock signal, determine a clock pulse other than the communication timing of data communication performed in the target circuit using the output clock signal,
    A clock frequency dividing method for generating the output clock signal by reducing the determined clock pulse.
13. 13. The output clock signal is generated by masking a part of a plurality of clock pulses included in the input clock signal when generating the output clock signal. Clock division method described.
14. 14. The clock frequency dividing method according to claim 13, wherein a clock pulse that is a mask target when the frequency division ratio is small is included in the mask target when the frequency division ratio is larger than that.
15. Performs first frequency division on the input clock signal,
    Distributing the clock signal having undergone the first frequency division to a plurality of times,
    A clock distribution method for performing a second frequency division on a distributed clock signal and outputting the result to a plurality of circuits.
16. 16. The first frequency division is performed based on a frequency division ratio that is the same as a smallest frequency division ratio among the second frequency divisions when performing the first frequency division. Clock distribution method.
17. 17. The clock distribution according to claim 15, wherein the clock signal output from the second clock divider circuit includes all clock pulses corresponding to timings at which the plurality of target circuits perform data communication. Method.

Images