JPH0946222A - Variable clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with a wide frequency band without enlarging a hardware scale and to prevent a processing from being occupied by the output control of a thinning pattern. SOLUTION: This circuit is provided with a pattern generation part 3' generating the thinning pattern for thinning a fixed frequency clock generated in a clock generation part 1, a memory 5 storing the thinning pattern, a data write part 4' writing the generated thinning pattern into the memory 5 and a data read part 4" which repetitively reads the thinning pattern and supplies it to a gate 6. The memory for storing thinning pattern 5 is provided for the external part of the pattern generation part 3'. Thus, a variable frequency range can be set wide. Furthermore, the write processing of the thinning pattern can be executed as a part of the initialization processing of a processor for device control by detaching the connection of the pattern generation part 3' and the memory 5 after the thinning pattern is written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable clock generation circuit capable of generating and outputting a frequency clock having an arbitrary value using a fixed frequency clock.
It is suitable for use in a data communication device having a control processor.

[0002]

2. Description of the Related Art In a conventional variable clock generation circuit, when a variable frequency clock signal is created using a fixed frequency clock signal, by thinning out the fixed frequency clock signal, that is, by stopping the operation for a certain period,
It was generating the target frequency clock signal.

In this case, when the variable frequency range is large and the target frequency is considerably smaller than the original fixed frequency, the effective period of the clock becomes short. At this time, if the effective period is concentrated at one place in the entire period, the clocks are generated in bursts.

For this reason, a mask pattern for evenly distributing the effective period of the clock in the entire period is stored in a ROM (read only memory), and the method is used by reading it and using a one-chip microcomputer. A method (for example, the method described in Japanese Patent Application Laid-Open No. 4-40116) for generating a thinning pattern has been adopted.

[0005]

As described above, in the conventional variable frequency clock generation circuit, 1) mask the clock as a mask pattern generation method for evenly distributing the effective period of the clock during the entire period. RO mask pattern for
Several kinds of data are stored in M, and an appropriate pattern is read out in synchronization with the clock. 2) A one-chip microcomputer is used to store and generate an appropriate thinning pattern on the internal memory. Etc. were used.

However, when the variable frequency range is large, the required types of thinning patterns increase. Therefore, the method 1) using the ROM requires a larger memory capacity. Also, a plurality of ROMs are required depending on the type of thinning pattern, and it is also necessary to provide an output selection control unit for selecting one of the ROMs. Therefore, there is a problem that the hardware scale becomes large.

In the method 2) using a one-chip microcomputer, unlike the method 1) using a ROM, the thinning pattern is generated by software. Therefore, the hardware scale can be small, but the built-in memory capacity is required. There is a problem that the maximum value of the original oscillation frequency is limited. Further, since the output control of the thinning pattern is also performed by the microcomputer itself, there is a problem that other processing cannot be performed during this period.

The present invention has been made to solve such a problem. The hardware scale is not large, a wide frequency band can be dealt with, and the processing is not occupied by the output control of the thinning pattern. It is an object of the present invention to provide a variable clock generation circuit that can achieve the following.

[0009]

A variable clock generation circuit of the present invention includes a clock generation means for generating a fixed frequency clock and a memory for storing a thinning pattern for thinning the fixed frequency clock generated by the clock generation means. A gate means for thinning and outputting a fixed frequency clock supplied from the clock generating means according to a thinning pattern supplied from the memory; a pattern generating means for generating the thinning pattern; and a pattern generating means generated by the pattern generating means. Data writing means for writing the thinning pattern to the memory, and data reading means for repeatedly reading the thinning pattern from the memory after writing the thinning pattern by the data writing means and supplying the thinning pattern to the gate means are provided.

Another feature of the present invention is that after the thinning pattern is written in the memory, the connection between the pattern generating means and the memory is disconnected.

Another feature of the present invention is a clock generating means for generating a fixed frequency clock, a memory for storing a thinning pattern for thinning the fixed frequency clock generated by the clock generating means, and the memory. Gate means for thinning and outputting the fixed frequency clock supplied from the clock generating means in accordance with the thinning pattern supplied from the pattern generating means, the pattern generating means for generating the thinning pattern, and the thinning pattern generated by the pattern generating means. Switching means for switching between writing to the memory and reading of the thinning pattern stored in the memory according to a predetermined switching signal, the switching means, when writing the thinning pattern to the memory, the pattern generating means. Is connected to the memory, and When reading pull pattern from said memory is characterized in that for connecting the said memory gate means.

Another feature of the present invention is a variable clock generation circuit used in an apparatus including a control processor, wherein the pattern generation means is included in the control processor. .

Another feature of the present invention is that the generation and writing process of the thinning pattern is performed as part of the initialization process of the control processor.

[0014]

According to the present invention constructed as described above, the thinning pattern is first generated by the pattern generating means, and the thinning pattern thus generated is written in the memory. The generation of the thinning pattern is performed, for example, as a part of the initialization processing of the control processor of the device including the variable clock generation circuit of the present invention (the pattern can be generated by the control processor. , It is also possible to provide an independent pattern generating means).

After writing the thinning pattern, the pattern generating means and the memory are separated from each other, and the thinning pattern written in the memory is repeatedly read by the data reading means and supplied to the gate means. The gate means thins out the fixed frequency clock supplied from the clock generating means in accordance with the read thinning pattern and outputs the thinned out pattern.

As described above, by having a memory for storing the thinning pattern outside the pattern generating means (control processor) for generating the thinning pattern, the memory can be made variable as compared with the conventional example having the memory inside. The frequency range can be widened, and the original oscillation frequency can be made higher.

Further, since the pattern generation means (control processor) and the memory are separated after the writing of the thinning pattern, the thinning pattern generation and writing processing is performed as a part of the initialization processing of the control processor, for example. Therefore, it is not necessary to provide a dedicated processor for generating the thinning pattern.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of one embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a variable clock generation circuit according to this embodiment. As shown in FIG. 1, the variable clock generating circuit of this embodiment includes a clock generating section 1, a pattern generating section 3 ', a data writing section 4', a data reading section 4 ", a memory 5 and a gate 6.
It consists of.

Here, the clock generator 1 generates a clock signal having a fixed frequency. The pattern generation unit 3'performs a process of generating a thinning pattern used when generating a variable frequency clock based on the fixed frequency clock generated by the clock generation unit 1.

The data writing section 4'writes the thinning pattern generated by the pattern generating section 3'in the memory 5. In addition, the data reading unit 4 ″ is
The thinning pattern stored in the memory 5 is read out and supplied to the gate 6. The memory 5 stores the thinning pattern generated by the pattern generator 3 '.

The gate 6 has a data reading section 4 ".
The variable frequency clock is generated and output by thinning out the fixed frequency clock generated by the clock generation unit 1 according to the thinning pattern read from the memory 5 by.

As is apparent from this configuration, in the present embodiment, an appropriate thinning pattern is generated by the pattern generating section 3 ', rather than a configuration in which an appropriate thinning pattern is generated using a ROM storing a plurality of types of thinning patterns. It is configured to generate. As a result, it is possible to prevent the inconvenience of the conventional example in which the hardware scale increases as the memory capacity of the ROM increases.

Further, in this embodiment, the memory 5 for storing the thinning pattern is provided outside the pattern generating section 3'for generating the thinning pattern. As a result, it is possible to prevent the inconvenience that the maximum value of the original oscillation frequency is limited by the capacity of the internal memory, as compared with the conventional example in which the memory is provided inside the one-chip microcomputer that generates the thinning pattern. It is possible to widen the variable frequency range.

Further, in this embodiment, when the thinning pattern is being written by the data writing section 4 ', the pattern generating section 3'and the memory 5 are connected via the data writing section 4'. After writing the thinning pattern, the memory 5 and the gate 6 are connected via the data reading unit 4 ″, and the pattern generating unit 3 ′ and the memory 5 are connected.
The connection with is disconnected.

As a result, the thinning pattern generation and writing process can be performed as part of the initialization process of the device control processor, for example, and it is not necessary to provide a dedicated processor for generating the thinning pattern. .

Next, another implementation example of the variable clock generation circuit to which the present invention is applied is shown in FIG. As shown in FIG. 2, the variable clock generation circuit of this embodiment is composed of a clock generation unit 1, a clock number counting unit 2, a processor 3, an address data switching unit 4, a memory 5 and a gate 6.

Here, the clock generator 1 generates a clock signal having a fixed frequency. The clock number counting unit 2 counts the number of clocks of the fixed frequency clock signal generated by the clock generating unit 1.

The processor 3 is, for example, a so-called one-chip microcomputer that controls the operation of the data communication device constructed by using the variable clock generation circuit of this embodiment. The processor 3 also performs a process of generating a thinning pattern used when generating a variable frequency clock from a fixed frequency clock.

The address data switching unit 4 switches between writing the thinning pattern generated by the processor 3 in the memory 5 and reading the thinning pattern stored in the memory 5. The memory 5 stores the thinning pattern generated by the processor 3.

The gate 6 thins out the fixed frequency clock generated by the clock generator 1 in accordance with the thinning pattern read from the memory 5 via the address data switching unit 4 to generate and output a variable frequency clock. To do.

A procedure for creating an appropriate clock thinning pattern for handling a variable frequency clock with the above-mentioned configuration will be described below. First, the processor 3 sends a switching signal 7 to the address data switching unit 4.
And the address signal 8 output from the processor 3
And data 9 of the thinning pattern are set to be input to the memory 5.

Next, the processor 3 calculates a thinning pattern so that the clock is thinned uniformly with respect to a target output frequency. Then, the calculated thinning pattern is written in the memory 5 as a part of the initialization processing of the apparatus. That is, the thinning pattern data 9 input to the data terminal is stored in the area indicated by the address signal 8 input to the address terminal of the memory 5.

The processor 3 outputs the switching signal 7 again to the address data switching unit 4 when the writing of all patterns is completed. As a result, the memory 5 enters the output mode. That is, the signal output from the clock number counting unit 2 is input to the address terminal, and the thinning pattern output from the data terminal of the memory 5 is input to the gate 6 according to the address.
As a result, the connection between the processor 3 and the memory 5 is disconnected.

By the way, the clock number counting unit 2
Generates an address signal by counting a fixed frequency clock signal output from the clock generator 1 for a certain period. In the output mode, the memory 5 inputs this address signal from the address terminal and outputs the thinning pattern written by the processor 3 from the data terminal.

The data of the thinning pattern output from the memory 5 and the fixed frequency clock signal output from the clock generator 1 are input to the gate 6. The gate 6 decimates the fixed frequency clock signal according to the inputted decimation pattern to generate and output a desired frequency clock signal.

As described above, also in the embodiment shown in FIG. 2, similar to the embodiment shown in FIG. 1, the ROM storing the thinning pattern is used to generate an appropriate thinning pattern. Since it does not exist, it is possible to prevent the inconvenience of the conventional example in which the hardware scale increases as the memory capacity of the ROM increases.

Further, in this embodiment, since the memory 5 for storing the thinning pattern is provided outside the processor 3 for generating the thinning pattern, the maximum value of the original oscillation frequency is limited by the capacity of the internal memory. The inconvenience of the conventional example can be prevented, and the variable frequency range can be widened.

Further, in this embodiment, the processor 3 and the memory 5 are separated after the thinning pattern is written, so that the processor 3 is separated after the separation is performed.
Can perform processing other than the output control of the thinning pattern, and the processing capacity of the processor 3 can be effectively used.

[0039]

As described above, according to the present invention, the memory for storing the clock thinning pattern is provided outside the pattern generating means (control processor), and the connection between the control processor and the memory is disconnected after writing the thinning pattern. It is characterized by As described above, by having the memory for storing the pattern outside the control processor, the variable frequency range can be widened, and the higher original oscillation frequency can be supported. . Furthermore, by disconnecting the connection between the control processor and the memory after writing the thinning pattern, it becomes possible to perform the thinning pattern generation and writing process as a part of the initialization process of the control processor. It is not necessary to have a dedicated processor for. Therefore, it is possible to realize a variable clock generation circuit in which the hardware scale is not large, a wide frequency band can be supported, and processing is not occupied by the output control of the thinning pattern.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a variable clock generation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a variable clock generation circuit according to another embodiment of the present invention.

[Explanation of symbols]

 1 clock generation unit 2 clock number counting unit 3 processor 3'pattern generation unit 4 address data switching unit 4'data writing unit 4 "data reading unit 5 memory 6 gate 7 switching signal 8 address signal 9 data

Claims (5)

[Claims] 1. A clock generating means for generating a fixed frequency clock, a memory for storing a thinning pattern for thinning the fixed frequency clock generated by the clock generating means, and the clock according to the thinning pattern supplied from the memory. Gate means for thinning and outputting a fixed frequency clock supplied from the generating means; pattern generating means for generating the thinning pattern; data writing means for writing the thinning pattern generated by the pattern generating means in the memory; A variable clock generation circuit comprising: a data reading unit that repeatedly reads the thinning pattern from the memory after writing the thinning pattern by the data writing unit and supplies the thinning pattern to the gate unit. 2. The variable clock generation circuit according to claim 1, wherein the connection between the pattern generation means and the memory is disconnected after the thinning pattern is written in the memory. 3. A clock generating means for generating a fixed frequency clock, a memory for storing a thinning pattern for thinning the fixed frequency clock generated by the clock generating means, and the clock according to the thinning pattern supplied from the memory. Gate means for thinning and outputting the fixed frequency clock supplied from the generating means, pattern generating means for generating the thinning pattern, and writing the thinning pattern generated by the pattern generating means in the memory or storing in the memory. Switching means for switching whether to read the thinned pattern according to a predetermined switching signal, the switching means, when writing the thinning pattern to the memory, connects the pattern generating means and the memory, Read thinning pattern from the memory Variable clock generation circuit, characterized in that for connecting the said memory gate means when issuing. 4. A variable clock generation circuit used in an apparatus including a control processor, wherein the pattern generation means is included in the control processor. A variable clock generation circuit according to item. 5. The variable clock generation circuit according to claim 4, wherein the generation and write processing of the thinning pattern is performed as a part of initialization processing of the control processor.